1bdcd8170SKalle Valo
2bdcd8170SKalle Valo /*
3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc.
41b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
5bdcd8170SKalle Valo *
6bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any
7bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above
8bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies.
9bdcd8170SKalle Valo *
10bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17bdcd8170SKalle Valo */
18bdcd8170SKalle Valo
19516304b0SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20516304b0SJoe Perches
21c6efe578SStephen Rothwell #include <linux/moduleparam.h>
22f7830202SSangwook Lee #include <linux/errno.h>
23d6a434d6SKalle Valo #include <linux/export.h>
2492ecbff4SSam Leffler #include <linux/of.h>
25bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h>
268437754cSVivek Natarajan #include <linux/vmalloc.h>
27d6a434d6SKalle Valo
28bdcd8170SKalle Valo #include "core.h"
29bdcd8170SKalle Valo #include "cfg80211.h"
30bdcd8170SKalle Valo #include "target.h"
31bdcd8170SKalle Valo #include "debug.h"
32bdcd8170SKalle Valo #include "hif-ops.h"
33e76ac2bfSKalle Valo #include "htc-ops.h"
34bdcd8170SKalle Valo
35856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = {
36856f4b31SKalle Valo {
370d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION,
38293badf4SKalle Valo .name = "ar6003 hw 2.0",
39856f4b31SKalle Valo .dataset_patch_addr = 0x57e884,
40856f4b31SKalle Valo .app_load_addr = 0x543180,
41856f4b31SKalle Valo .board_ext_data_addr = 0x57e500,
42856f4b31SKalle Valo .reserved_ram_size = 6912,
4339586bf2SRyan Hsu .refclk_hz = 26000000,
4439586bf2SRyan Hsu .uarttx_pin = 8,
45a2e1be33SMohammed Shafi Shajakhan .flags = ATH6KL_HW_SDIO_CRC_ERROR_WAR,
46856f4b31SKalle Valo
47856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */
48856f4b31SKalle Valo .app_start_override_addr = 0x944C00,
49d1a9421dSKalle Valo
50c0038972SKalle Valo .fw = {
51c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR,
52c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE,
53d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE,
54c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
55c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE,
56c0038972SKalle Valo },
57c0038972SKalle Valo
58d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
59d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
60856f4b31SKalle Valo },
61856f4b31SKalle Valo {
620d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION,
63293badf4SKalle Valo .name = "ar6003 hw 2.1.1",
64856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74,
65856f4b31SKalle Valo .app_load_addr = 0x1234,
66856f4b31SKalle Valo .board_ext_data_addr = 0x542330,
67856f4b31SKalle Valo .reserved_ram_size = 512,
6839586bf2SRyan Hsu .refclk_hz = 26000000,
6939586bf2SRyan Hsu .uarttx_pin = 8,
70cd23c1c9SAlex Yang .testscript_addr = 0x57ef74,
71a2e1be33SMohammed Shafi Shajakhan .flags = ATH6KL_HW_SDIO_CRC_ERROR_WAR,
72d1a9421dSKalle Valo
73c0038972SKalle Valo .fw = {
74c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR,
75c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE,
76d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
77c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
78c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE,
79cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
80cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
81c0038972SKalle Valo },
82c0038972SKalle Valo
83d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
84d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
85856f4b31SKalle Valo },
86856f4b31SKalle Valo {
870d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION,
88293badf4SKalle Valo .name = "ar6004 hw 1.0",
89856f4b31SKalle Valo .dataset_patch_addr = 0x57e884,
90856f4b31SKalle Valo .app_load_addr = 0x1234,
91856f4b31SKalle Valo .board_ext_data_addr = 0x437000,
92856f4b31SKalle Valo .reserved_ram_size = 19456,
930d4d72bfSKalle Valo .board_addr = 0x433900,
9439586bf2SRyan Hsu .refclk_hz = 26000000,
9539586bf2SRyan Hsu .uarttx_pin = 11,
96eba95bceSKalle Valo .flags = 0,
97d1a9421dSKalle Valo
98c0038972SKalle Valo .fw = {
99c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR,
100d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE,
101c0038972SKalle Valo },
102c0038972SKalle Valo
103d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
104d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
105856f4b31SKalle Valo },
106856f4b31SKalle Valo {
1070d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION,
108293badf4SKalle Valo .name = "ar6004 hw 1.1",
109856f4b31SKalle Valo .dataset_patch_addr = 0x57e884,
110856f4b31SKalle Valo .app_load_addr = 0x1234,
111856f4b31SKalle Valo .board_ext_data_addr = 0x437000,
112856f4b31SKalle Valo .reserved_ram_size = 11264,
1130d4d72bfSKalle Valo .board_addr = 0x43d400,
11439586bf2SRyan Hsu .refclk_hz = 40000000,
11539586bf2SRyan Hsu .uarttx_pin = 11,
116eba95bceSKalle Valo .flags = 0,
117c0038972SKalle Valo .fw = {
118c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR,
119d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE,
120c0038972SKalle Valo },
121c0038972SKalle Valo
122d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
123d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
124856f4b31SKalle Valo },
1256146ca69SRay Chen {
1266146ca69SRay Chen .id = AR6004_HW_1_2_VERSION,
1276146ca69SRay Chen .name = "ar6004 hw 1.2",
1286146ca69SRay Chen .dataset_patch_addr = 0x436ecc,
1296146ca69SRay Chen .app_load_addr = 0x1234,
1306146ca69SRay Chen .board_ext_data_addr = 0x437000,
1316146ca69SRay Chen .reserved_ram_size = 9216,
1326146ca69SRay Chen .board_addr = 0x435c00,
1336146ca69SRay Chen .refclk_hz = 40000000,
1346146ca69SRay Chen .uarttx_pin = 11,
135eba95bceSKalle Valo .flags = 0,
1366146ca69SRay Chen
1376146ca69SRay Chen .fw = {
1386146ca69SRay Chen .dir = AR6004_HW_1_2_FW_DIR,
1396146ca69SRay Chen .fw = AR6004_HW_1_2_FIRMWARE_FILE,
1406146ca69SRay Chen },
1416146ca69SRay Chen .fw_board = AR6004_HW_1_2_BOARD_DATA_FILE,
1426146ca69SRay Chen .fw_default_board = AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE,
1436146ca69SRay Chen },
144bf744f11SBala Shanmugam {
145bf744f11SBala Shanmugam .id = AR6004_HW_1_3_VERSION,
146bf744f11SBala Shanmugam .name = "ar6004 hw 1.3",
147bf744f11SBala Shanmugam .dataset_patch_addr = 0x437860,
148bf744f11SBala Shanmugam .app_load_addr = 0x1234,
149bf744f11SBala Shanmugam .board_ext_data_addr = 0x437000,
150bf744f11SBala Shanmugam .reserved_ram_size = 7168,
151bf744f11SBala Shanmugam .board_addr = 0x436400,
15278803770SJessica Wu .refclk_hz = 0,
153bf744f11SBala Shanmugam .uarttx_pin = 11,
154eba95bceSKalle Valo .flags = 0,
155bf744f11SBala Shanmugam
156bf744f11SBala Shanmugam .fw = {
157bf744f11SBala Shanmugam .dir = AR6004_HW_1_3_FW_DIR,
158bf744f11SBala Shanmugam .fw = AR6004_HW_1_3_FIRMWARE_FILE,
15978803770SJessica Wu .tcmd = AR6004_HW_1_3_TCMD_FIRMWARE_FILE,
16078803770SJessica Wu .utf = AR6004_HW_1_3_UTF_FIRMWARE_FILE,
16178803770SJessica Wu .testscript = AR6004_HW_1_3_TESTSCRIPT_FILE,
162bf744f11SBala Shanmugam },
163bf744f11SBala Shanmugam
164bf744f11SBala Shanmugam .fw_board = AR6004_HW_1_3_BOARD_DATA_FILE,
165bf744f11SBala Shanmugam .fw_default_board = AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE,
166bf744f11SBala Shanmugam },
16778803770SJessica Wu {
16878803770SJessica Wu .id = AR6004_HW_3_0_VERSION,
16978803770SJessica Wu .name = "ar6004 hw 3.0",
17078803770SJessica Wu .dataset_patch_addr = 0,
17178803770SJessica Wu .app_load_addr = 0x1234,
17278803770SJessica Wu .board_ext_data_addr = 0,
17378803770SJessica Wu .reserved_ram_size = 7168,
17478803770SJessica Wu .board_addr = 0x436400,
17578803770SJessica Wu .testscript_addr = 0,
176907ec43aSSteve deRosier .uarttx_pin = 11,
17778803770SJessica Wu .flags = 0,
17878803770SJessica Wu
17978803770SJessica Wu .fw = {
18078803770SJessica Wu .dir = AR6004_HW_3_0_FW_DIR,
18178803770SJessica Wu .fw = AR6004_HW_3_0_FIRMWARE_FILE,
18278803770SJessica Wu .tcmd = AR6004_HW_3_0_TCMD_FIRMWARE_FILE,
18378803770SJessica Wu .utf = AR6004_HW_3_0_UTF_FIRMWARE_FILE,
18478803770SJessica Wu .testscript = AR6004_HW_3_0_TESTSCRIPT_FILE,
18578803770SJessica Wu },
18678803770SJessica Wu
18778803770SJessica Wu .fw_board = AR6004_HW_3_0_BOARD_DATA_FILE,
18878803770SJessica Wu .fw_default_board = AR6004_HW_3_0_DEFAULT_BOARD_DATA_FILE,
18978803770SJessica Wu },
190856f4b31SKalle Valo };
191856f4b31SKalle Valo
192bdcd8170SKalle Valo /*
193bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module
194bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs,
195bdcd8170SKalle Valo * here.
196bdcd8170SKalle Valo */
197bdcd8170SKalle Valo
198bdcd8170SKalle Valo /*
199bdcd8170SKalle Valo * This configuration item enable/disable keepalive support.
200bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null
201bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association
202bdcd8170SKalle Valo * active. This configuration item defines the periodic interval.
203bdcd8170SKalle Valo * Use value of zero to disable keepalive support
204bdcd8170SKalle Valo * Default: 60 seconds
205bdcd8170SKalle Valo */
206bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
207bdcd8170SKalle Valo
208bdcd8170SKalle Valo /*
209bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout
210bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this
211bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP.
212bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout
213bdcd8170SKalle Valo * it sends a new connect event
214bdcd8170SKalle Valo */
215bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
216bdcd8170SKalle Valo
217bdcd8170SKalle Valo
218bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64
ath6kl_buf_alloc(int size)219bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size)
220bdcd8170SKalle Valo {
221bdcd8170SKalle Valo struct sk_buff *skb;
222bdcd8170SKalle Valo u16 reserved;
223bdcd8170SKalle Valo
224bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */
2256a3e4e06SMyoungje Kim reserved = roundup((2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
2266a3e4e06SMyoungje Kim sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES, 4);
227bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved);
228bdcd8170SKalle Valo
229bdcd8170SKalle Valo if (skb)
230bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES);
231bdcd8170SKalle Valo return skb;
232bdcd8170SKalle Valo }
233bdcd8170SKalle Valo
ath6kl_init_profile_info(struct ath6kl_vif * vif)234e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif)
235bdcd8170SKalle Valo {
2363450334fSVasanthakumar Thiagarajan vif->ssid_len = 0;
2373450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid));
2383450334fSVasanthakumar Thiagarajan
2393450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH;
2403450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH;
2413450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT;
2423450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0;
2433450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT;
2443450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0;
2456f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
2468c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
2478c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid));
248f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0;
249bdcd8170SKalle Valo }
250bdcd8170SKalle Valo
ath6kl_set_host_app_area(struct ath6kl * ar)251bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar)
252bdcd8170SKalle Valo {
253bdcd8170SKalle Valo u32 address, data;
254bdcd8170SKalle Valo struct host_app_area host_app_area;
255bdcd8170SKalle Valo
256bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s
257bdcd8170SKalle Valo * instance in the host interest area */
258bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
25931024d99SKevin Fang address = TARG_VTOP(ar->target_type, address);
260bdcd8170SKalle Valo
261addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data))
262bdcd8170SKalle Valo return -EIO;
263bdcd8170SKalle Valo
26431024d99SKevin Fang address = TARG_VTOP(ar->target_type, data);
265cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
266addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
267addb44beSKalle Valo sizeof(struct host_app_area)))
268bdcd8170SKalle Valo return -EIO;
269bdcd8170SKalle Valo
270bdcd8170SKalle Valo return 0;
271bdcd8170SKalle Valo }
272bdcd8170SKalle Valo
set_ac2_ep_map(struct ath6kl * ar,u8 ac,enum htc_endpoint_id ep)273bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar,
274bdcd8170SKalle Valo u8 ac,
275bdcd8170SKalle Valo enum htc_endpoint_id ep)
276bdcd8170SKalle Valo {
277bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep;
278bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac;
279bdcd8170SKalle Valo }
280bdcd8170SKalle Valo
281bdcd8170SKalle Valo /* connect to a service */
ath6kl_connectservice(struct ath6kl * ar,struct htc_service_connect_req * con_req,char * desc)282bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar,
283bdcd8170SKalle Valo struct htc_service_connect_req *con_req,
284bdcd8170SKalle Valo char *desc)
285bdcd8170SKalle Valo {
286bdcd8170SKalle Valo int status;
287bdcd8170SKalle Valo struct htc_service_connect_resp response;
288bdcd8170SKalle Valo
289bdcd8170SKalle Valo memset(&response, 0, sizeof(response));
290bdcd8170SKalle Valo
291ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
292bdcd8170SKalle Valo if (status) {
293bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n",
294bdcd8170SKalle Valo desc, status);
295bdcd8170SKalle Valo return status;
296bdcd8170SKalle Valo }
297bdcd8170SKalle Valo
298bdcd8170SKalle Valo switch (con_req->svc_id) {
299bdcd8170SKalle Valo case WMI_CONTROL_SVC:
300bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag))
301bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
302bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint;
303bdcd8170SKalle Valo break;
304bdcd8170SKalle Valo case WMI_DATA_BE_SVC:
305bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
306bdcd8170SKalle Valo break;
307bdcd8170SKalle Valo case WMI_DATA_BK_SVC:
308bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
309bdcd8170SKalle Valo break;
310bdcd8170SKalle Valo case WMI_DATA_VI_SVC:
311bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
312bdcd8170SKalle Valo break;
313bdcd8170SKalle Valo case WMI_DATA_VO_SVC:
314bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
315bdcd8170SKalle Valo break;
316bdcd8170SKalle Valo default:
317bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
318bdcd8170SKalle Valo return -EINVAL;
319bdcd8170SKalle Valo }
320bdcd8170SKalle Valo
321bdcd8170SKalle Valo return 0;
322bdcd8170SKalle Valo }
323bdcd8170SKalle Valo
ath6kl_init_service_ep(struct ath6kl * ar)324bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar)
325bdcd8170SKalle Valo {
326bdcd8170SKalle Valo struct htc_service_connect_req connect;
327bdcd8170SKalle Valo
328bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect));
329bdcd8170SKalle Valo
330bdcd8170SKalle Valo /* these fields are the same for all service endpoints */
331900d6b3fSKalle Valo connect.ep_cb.tx_comp_multi = ath6kl_tx_complete;
332bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx;
333bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill;
334bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full;
335bdcd8170SKalle Valo
336bdcd8170SKalle Valo /*
337bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler
338bdcd8170SKalle Valo * gets called.
339bdcd8170SKalle Valo */
340bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
341bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
342bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh)
343bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++;
344bdcd8170SKalle Valo
345bdcd8170SKalle Valo /* connect to control service */
346bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC;
347bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
348bdcd8170SKalle Valo return -EIO;
349bdcd8170SKalle Valo
350bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
351bdcd8170SKalle Valo
352bdcd8170SKalle Valo /*
353bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can
354bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized
355bdcd8170SKalle Valo * (802.3) frames on the send path.
356bdcd8170SKalle Valo */
357bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
358bdcd8170SKalle Valo
359bdcd8170SKalle Valo /*
360bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU
361bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger
362bdcd8170SKalle Valo * packets.
363bdcd8170SKalle Valo */
364bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
365bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
366bdcd8170SKalle Valo
367bdcd8170SKalle Valo /*
368bdcd8170SKalle Valo * For the remaining data services set the connection flag to
369bdcd8170SKalle Valo * reduce dribbling, if configured to do so.
370bdcd8170SKalle Valo */
371bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
372bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
373bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
374bdcd8170SKalle Valo
375bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC;
376bdcd8170SKalle Valo
377bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
378bdcd8170SKalle Valo return -EIO;
379bdcd8170SKalle Valo
380bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */
381bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC;
382bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
383bdcd8170SKalle Valo return -EIO;
384bdcd8170SKalle Valo
385171fe768SMohammed Shafi Shajakhan /* connect to Video service, map this to HI PRI */
386bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC;
387bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
388bdcd8170SKalle Valo return -EIO;
389bdcd8170SKalle Valo
390bdcd8170SKalle Valo /*
391bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI
392bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally
393bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when
394bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on
395bdcd8170SKalle Valo * mailboxes.
396bdcd8170SKalle Valo */
397bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC;
398bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
399bdcd8170SKalle Valo return -EIO;
400bdcd8170SKalle Valo
401bdcd8170SKalle Valo return 0;
402bdcd8170SKalle Valo }
403bdcd8170SKalle Valo
ath6kl_init_control_info(struct ath6kl_vif * vif)404e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif)
405bdcd8170SKalle Valo {
406e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif);
4073450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0;
4086f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
409f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0;
410bdcd8170SKalle Valo }
411bdcd8170SKalle Valo
412bdcd8170SKalle Valo /*
413bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the
414bdcd8170SKalle Valo * target is in the BMI phase.
415bdcd8170SKalle Valo */
ath6kl_set_htc_params(struct ath6kl * ar,u32 mbox_isr_yield_val,u8 htc_ctrl_buf)416bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
417bdcd8170SKalle Valo u8 htc_ctrl_buf)
418bdcd8170SKalle Valo {
419bdcd8170SKalle Valo int status;
420bdcd8170SKalle Valo u32 blk_size;
421bdcd8170SKalle Valo
422bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size;
423bdcd8170SKalle Valo
424bdcd8170SKalle Valo if (htc_ctrl_buf)
425bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16;
426bdcd8170SKalle Valo
427bdcd8170SKalle Valo /* set the host interest area for the block size */
42824fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
429bdcd8170SKalle Valo if (status) {
430bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n");
431bdcd8170SKalle Valo goto out;
432bdcd8170SKalle Valo }
433bdcd8170SKalle Valo
434bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
435bdcd8170SKalle Valo blk_size,
436bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
437bdcd8170SKalle Valo
438bdcd8170SKalle Valo if (mbox_isr_yield_val) {
439bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */
44024fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
44124fc32b3SKalle Valo mbox_isr_yield_val);
442bdcd8170SKalle Valo if (status) {
443bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n");
444bdcd8170SKalle Valo goto out;
445bdcd8170SKalle Valo }
446bdcd8170SKalle Valo }
447bdcd8170SKalle Valo
448bdcd8170SKalle Valo out:
449bdcd8170SKalle Valo return status;
450bdcd8170SKalle Valo }
451bdcd8170SKalle Valo
ath6kl_target_config_wlan_params(struct ath6kl * ar,int idx)4520ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
453bdcd8170SKalle Valo {
4544dea08e0SJouni Malinen int ret;
455bdcd8170SKalle Valo
456bdcd8170SKalle Valo /*
457bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the
458bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set
459bdcd8170SKalle Valo * RxMetaVersion to 2.
460bdcd8170SKalle Valo */
4611ca4d0b6SKalle Valo ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
4621ca4d0b6SKalle Valo ar->rx_meta_ver, 0, 0);
4631ca4d0b6SKalle Valo if (ret) {
4641ca4d0b6SKalle Valo ath6kl_err("unable to set the rx frame format: %d\n", ret);
4651ca4d0b6SKalle Valo return ret;
466bdcd8170SKalle Valo }
467bdcd8170SKalle Valo
4681ca4d0b6SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
4691ca4d0b6SKalle Valo ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
47005aab177SKalle Valo IGNORE_PS_FAIL_DURING_SCAN);
4711ca4d0b6SKalle Valo if (ret) {
4721ca4d0b6SKalle Valo ath6kl_err("unable to set power save fail event policy: %d\n",
4731ca4d0b6SKalle Valo ret);
4741ca4d0b6SKalle Valo return ret;
4751ca4d0b6SKalle Valo }
476bdcd8170SKalle Valo }
477bdcd8170SKalle Valo
4781ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
4791ca4d0b6SKalle Valo ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
48005aab177SKalle Valo WMI_FOLLOW_BARKER_IN_ERP);
4811ca4d0b6SKalle Valo if (ret) {
4821ca4d0b6SKalle Valo ath6kl_err("unable to set barker preamble policy: %d\n",
4831ca4d0b6SKalle Valo ret);
4841ca4d0b6SKalle Valo return ret;
4851ca4d0b6SKalle Valo }
486bdcd8170SKalle Valo }
487bdcd8170SKalle Valo
4881ca4d0b6SKalle Valo ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
4891ca4d0b6SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
4901ca4d0b6SKalle Valo if (ret) {
4911ca4d0b6SKalle Valo ath6kl_err("unable to set keep alive interval: %d\n", ret);
4921ca4d0b6SKalle Valo return ret;
493bdcd8170SKalle Valo }
494bdcd8170SKalle Valo
4951ca4d0b6SKalle Valo ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
4961ca4d0b6SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT);
4971ca4d0b6SKalle Valo if (ret) {
4981ca4d0b6SKalle Valo ath6kl_err("unable to set disconnect timeout: %d\n", ret);
4991ca4d0b6SKalle Valo return ret;
500bdcd8170SKalle Valo }
501bdcd8170SKalle Valo
5021ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
5031ca4d0b6SKalle Valo ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
5041ca4d0b6SKalle Valo if (ret) {
5051ca4d0b6SKalle Valo ath6kl_err("unable to set txop bursting: %d\n", ret);
5061ca4d0b6SKalle Valo return ret;
5071ca4d0b6SKalle Valo }
508bdcd8170SKalle Valo }
509bdcd8170SKalle Valo
510b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) {
5110ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
5126bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ |
5134dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ |
5144dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ);
5154dea08e0SJouni Malinen if (ret) {
516cdeb8602SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC,
517cdeb8602SKalle Valo "failed to request P2P capabilities (%d) - assuming P2P not supported\n",
518cdeb8602SKalle Valo ret);
5193db1cd5cSRusty Russell ar->p2p = false;
5206bbc7c35SJouni Malinen }
5216bbc7c35SJouni Malinen }
5226bbc7c35SJouni Malinen
523b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) {
5246bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */
5250ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
5266bbc7c35SJouni Malinen if (ret) {
527cdeb8602SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC,
528cdeb8602SKalle Valo "failed to enable Probe Request reporting (%d)\n",
529cdeb8602SKalle Valo ret);
5306bbc7c35SJouni Malinen }
5314dea08e0SJouni Malinen }
5324dea08e0SJouni Malinen
5331ca4d0b6SKalle Valo return ret;
534bdcd8170SKalle Valo }
535bdcd8170SKalle Valo
ath6kl_configure_target(struct ath6kl * ar)536bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar)
537bdcd8170SKalle Valo {
538bdcd8170SKalle Valo u32 param, ram_reserved_size;
5393226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0;
54039586bf2SRyan Hsu int i, status;
541bdcd8170SKalle Valo
542f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
54324fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
544a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n");
545a10e2f2fSVasanthakumar Thiagarajan return -EIO;
546a10e2f2fSVasanthakumar Thiagarajan }
547a10e2f2fSVasanthakumar Thiagarajan
5487b85832dSVasanthakumar Thiagarajan /*
5497b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is
5507b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can
5517b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode
5527b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But
5537b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is
5547b85832dSVasanthakumar Thiagarajan * configured for now.
5557b85832dSVasanthakumar Thiagarajan */
556dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
557bdcd8170SKalle Valo
55871f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++)
5597b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
5607b85832dSVasanthakumar Thiagarajan
5617b85832dSVasanthakumar Thiagarajan /*
5621e8d13b0SVasanthakumar Thiagarajan * Submodes when fw does not support dynamic interface
5631e8d13b0SVasanthakumar Thiagarajan * switching:
5643226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS
5657b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
5667b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
5671e8d13b0SVasanthakumar Thiagarajan * Otherwise, All the interface are initialized to p2p dev.
5687b85832dSVasanthakumar Thiagarajan */
5693226f68aSVasanthakumar Thiagarajan
5701e8d13b0SVasanthakumar Thiagarajan if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
5711e8d13b0SVasanthakumar Thiagarajan ar->fw_capabilities)) {
5721e8d13b0SVasanthakumar Thiagarajan for (i = 0; i < ar->vif_max; i++)
5731e8d13b0SVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
5741e8d13b0SVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS);
5751e8d13b0SVasanthakumar Thiagarajan } else {
5763226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++)
5773226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
5783226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS);
5793226f68aSVasanthakumar Thiagarajan
58071f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++)
5813226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
5823226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS);
5837b85832dSVasanthakumar Thiagarajan
584b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1)
5857b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
5861e8d13b0SVasanthakumar Thiagarajan }
5877b85832dSVasanthakumar Thiagarajan
58824fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
58924fc32b3SKalle Valo HTC_PROTOCOL_VERSION) != 0) {
590bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n");
591bdcd8170SKalle Valo return -EIO;
592bdcd8170SKalle Valo }
593bdcd8170SKalle Valo
594bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */
595bdcd8170SKalle Valo param = 0;
596bdcd8170SKalle Valo
59780fb2686SKalle Valo if (ath6kl_bmi_read_hi32(ar, hi_option_flag, ¶m) != 0) {
598bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n");
599bdcd8170SKalle Valo return -EIO;
600bdcd8170SKalle Valo }
601bdcd8170SKalle Valo
60271f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
6037b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
6047b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
6057b85832dSVasanthakumar Thiagarajan
606bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
607bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
608bdcd8170SKalle Valo
60924fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
610bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n");
611bdcd8170SKalle Valo return -EIO;
612bdcd8170SKalle Valo }
613bdcd8170SKalle Valo
614bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
615bdcd8170SKalle Valo
616bdcd8170SKalle Valo /*
617bdcd8170SKalle Valo * Hardcode the address use for the extended board data
618bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time
619bdcd8170SKalle Valo * But since it is a new feature and board data is loaded
620bdcd8170SKalle Valo * at init time, we have to workaround this from host.
621bdcd8170SKalle Valo * It is difficult to patch the firmware boot code,
622bdcd8170SKalle Valo * but possible in theory.
623bdcd8170SKalle Valo */
624bdcd8170SKalle Valo
62578803770SJessica Wu if ((ar->target_type == TARGET_TYPE_AR6003) ||
62678803770SJessica Wu (ar->version.target_ver == AR6004_HW_1_3_VERSION) ||
62778803770SJessica Wu (ar->version.target_ver == AR6004_HW_3_0_VERSION)) {
628991b27eaSKalle Valo param = ar->hw.board_ext_data_addr;
629991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size;
630bdcd8170SKalle Valo
63124fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
632bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
633bdcd8170SKalle Valo return -EIO;
634bdcd8170SKalle Valo }
635991b27eaSKalle Valo
63624fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
63724fc32b3SKalle Valo ram_reserved_size) != 0) {
638bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
639bdcd8170SKalle Valo return -EIO;
640bdcd8170SKalle Valo }
6416b42d308SKalle Valo }
642bdcd8170SKalle Valo
643bdcd8170SKalle Valo /* set the block size for the target */
644bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
645bdcd8170SKalle Valo /* use default number of control buffers */
646bdcd8170SKalle Valo return -EIO;
647bdcd8170SKalle Valo
64839586bf2SRyan Hsu /* Configure GPIO AR600x UART */
64924fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
65024fc32b3SKalle Valo ar->hw.uarttx_pin);
65139586bf2SRyan Hsu if (status)
65239586bf2SRyan Hsu return status;
65339586bf2SRyan Hsu
654f8a68c96SSteve deRosier /* Only set the baud rate if we're actually doing debug */
655f8a68c96SSteve deRosier if (ar->conf_flags & ATH6KL_CONF_UART_DEBUG) {
656f8a68c96SSteve deRosier status = ath6kl_bmi_write_hi32(ar, hi_desired_baud_rate,
657f8a68c96SSteve deRosier ar->hw.uarttx_rate);
658f8a68c96SSteve deRosier if (status)
659f8a68c96SSteve deRosier return status;
660f8a68c96SSteve deRosier }
661f8a68c96SSteve deRosier
66239586bf2SRyan Hsu /* Configure target refclk_hz */
663958e1be8SKalle Valo if (ar->hw.refclk_hz != 0) {
664958e1be8SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz,
665958e1be8SKalle Valo ar->hw.refclk_hz);
66639586bf2SRyan Hsu if (status)
66739586bf2SRyan Hsu return status;
668958e1be8SKalle Valo }
66939586bf2SRyan Hsu
670bdcd8170SKalle Valo return 0;
671bdcd8170SKalle Valo }
672bdcd8170SKalle Valo
673bdcd8170SKalle Valo /* firmware upload */
ath6kl_get_fw(struct ath6kl * ar,const char * filename,u8 ** fw,size_t * fw_len)674bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
675bdcd8170SKalle Valo u8 **fw, size_t *fw_len)
676bdcd8170SKalle Valo {
677bdcd8170SKalle Valo const struct firmware *fw_entry;
678bdcd8170SKalle Valo int ret;
679bdcd8170SKalle Valo
680bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev);
681bdcd8170SKalle Valo if (ret)
682bdcd8170SKalle Valo return ret;
683bdcd8170SKalle Valo
684bdcd8170SKalle Valo *fw_len = fw_entry->size;
685bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
686bdcd8170SKalle Valo
687bdcd8170SKalle Valo if (*fw == NULL)
688bdcd8170SKalle Valo ret = -ENOMEM;
689bdcd8170SKalle Valo
690bdcd8170SKalle Valo release_firmware(fw_entry);
691bdcd8170SKalle Valo
692bdcd8170SKalle Valo return ret;
693bdcd8170SKalle Valo }
694bdcd8170SKalle Valo
69592ecbff4SSam Leffler #ifdef CONFIG_OF
69692ecbff4SSam Leffler /*
69792ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct
69892ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a
69992ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the
70092ecbff4SSam Leffler * appropriate board-specific file.
70192ecbff4SSam Leffler */
check_device_tree(struct ath6kl * ar)70292ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar)
70392ecbff4SSam Leffler {
70492ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id";
70592ecbff4SSam Leffler struct device_node *node;
70692ecbff4SSam Leffler char board_filename[64];
70792ecbff4SSam Leffler const char *board_id;
70892ecbff4SSam Leffler int ret;
70992ecbff4SSam Leffler
71092ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") {
71192ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL);
71292ecbff4SSam Leffler if (board_id == NULL) {
713e12e643cSRob Herring ath6kl_warn("No \"%s\" property on %pOFn node.\n",
714e12e643cSRob Herring board_id_prop, node);
71592ecbff4SSam Leffler continue;
71692ecbff4SSam Leffler }
71792ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename),
718c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
71992ecbff4SSam Leffler
72092ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
72192ecbff4SSam Leffler &ar->fw_board_len);
72292ecbff4SSam Leffler if (ret) {
72392ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n",
72492ecbff4SSam Leffler board_filename, ret);
72592ecbff4SSam Leffler continue;
72692ecbff4SSam Leffler }
72781a57703SJulia Lawall of_node_put(node);
72892ecbff4SSam Leffler return true;
72992ecbff4SSam Leffler }
73092ecbff4SSam Leffler return false;
73192ecbff4SSam Leffler }
73292ecbff4SSam Leffler #else
check_device_tree(struct ath6kl * ar)73392ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar)
73492ecbff4SSam Leffler {
73592ecbff4SSam Leffler return false;
73692ecbff4SSam Leffler }
73792ecbff4SSam Leffler #endif /* CONFIG_OF */
73892ecbff4SSam Leffler
ath6kl_fetch_board_file(struct ath6kl * ar)739bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar)
740bdcd8170SKalle Valo {
741bdcd8170SKalle Valo const char *filename;
742bdcd8170SKalle Valo int ret;
743bdcd8170SKalle Valo
744772c31eeSKalle Valo if (ar->fw_board != NULL)
745772c31eeSKalle Valo return 0;
746772c31eeSKalle Valo
747d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL))
748d1a9421dSKalle Valo return -EINVAL;
749d1a9421dSKalle Valo
750d1a9421dSKalle Valo filename = ar->hw.fw_board;
751bdcd8170SKalle Valo
752bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
753bdcd8170SKalle Valo &ar->fw_board_len);
754bdcd8170SKalle Valo if (ret == 0) {
755bdcd8170SKalle Valo /* managed to get proper board file */
756bdcd8170SKalle Valo return 0;
757bdcd8170SKalle Valo }
758bdcd8170SKalle Valo
75992ecbff4SSam Leffler if (check_device_tree(ar)) {
76092ecbff4SSam Leffler /* got board file from device tree */
76192ecbff4SSam Leffler return 0;
76292ecbff4SSam Leffler }
76392ecbff4SSam Leffler
764bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */
765bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
766bdcd8170SKalle Valo filename, ret);
767bdcd8170SKalle Valo
768d1a9421dSKalle Valo filename = ar->hw.fw_default_board;
769bdcd8170SKalle Valo
770bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
771bdcd8170SKalle Valo &ar->fw_board_len);
772bdcd8170SKalle Valo if (ret) {
773bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n",
774bdcd8170SKalle Valo filename, ret);
775bdcd8170SKalle Valo return ret;
776bdcd8170SKalle Valo }
777bdcd8170SKalle Valo
778bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
779bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
780bdcd8170SKalle Valo
781bdcd8170SKalle Valo return 0;
782bdcd8170SKalle Valo }
783bdcd8170SKalle Valo
ath6kl_fetch_otp_file(struct ath6kl * ar)784772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar)
785772c31eeSKalle Valo {
786c0038972SKalle Valo char filename[100];
787772c31eeSKalle Valo int ret;
788772c31eeSKalle Valo
789772c31eeSKalle Valo if (ar->fw_otp != NULL)
790772c31eeSKalle Valo return 0;
791772c31eeSKalle Valo
792c0038972SKalle Valo if (ar->hw.fw.otp == NULL) {
793d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
794d1a9421dSKalle Valo "no OTP file configured for this hw\n");
795772c31eeSKalle Valo return 0;
796772c31eeSKalle Valo }
797772c31eeSKalle Valo
798c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s",
799c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp);
800d1a9421dSKalle Valo
801772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
802772c31eeSKalle Valo &ar->fw_otp_len);
803772c31eeSKalle Valo if (ret) {
804772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n",
805772c31eeSKalle Valo filename, ret);
806772c31eeSKalle Valo return ret;
807772c31eeSKalle Valo }
808772c31eeSKalle Valo
809772c31eeSKalle Valo return 0;
810772c31eeSKalle Valo }
811772c31eeSKalle Valo
ath6kl_fetch_testmode_file(struct ath6kl * ar)8125f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
813772c31eeSKalle Valo {
814c0038972SKalle Valo char filename[100];
815772c31eeSKalle Valo int ret;
816772c31eeSKalle Valo
8175f1127ffSKalle Valo if (ar->testmode == 0)
818772c31eeSKalle Valo return 0;
819772c31eeSKalle Valo
8205f1127ffSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
8215f1127ffSKalle Valo
8225f1127ffSKalle Valo if (ar->testmode == 2) {
823cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) {
824cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n");
825cd23c1c9SAlex Yang return -EOPNOTSUPP;
826cd23c1c9SAlex Yang }
827cd23c1c9SAlex Yang
828cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s",
829cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf);
830cd23c1c9SAlex Yang } else {
831c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) {
832cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n");
833772c31eeSKalle Valo return -EOPNOTSUPP;
834772c31eeSKalle Valo }
835772c31eeSKalle Valo
836c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s",
837c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd);
838cd23c1c9SAlex Yang }
8395f1127ffSKalle Valo
840772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag);
841772c31eeSKalle Valo
8425f1127ffSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
8435f1127ffSKalle Valo if (ret) {
8445f1127ffSKalle Valo ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
8455f1127ffSKalle Valo ar->testmode, filename, ret);
8465f1127ffSKalle Valo return ret;
847772c31eeSKalle Valo }
848772c31eeSKalle Valo
8495f1127ffSKalle Valo return 0;
8505f1127ffSKalle Valo }
8515f1127ffSKalle Valo
ath6kl_fetch_fw_file(struct ath6kl * ar)8525f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar)
8535f1127ffSKalle Valo {
8545f1127ffSKalle Valo char filename[100];
8555f1127ffSKalle Valo int ret;
8565f1127ffSKalle Valo
8575f1127ffSKalle Valo if (ar->fw != NULL)
8585f1127ffSKalle Valo return 0;
8595f1127ffSKalle Valo
860c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
861c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL))
862d1a9421dSKalle Valo return -EINVAL;
863d1a9421dSKalle Valo
864c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s",
865c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw);
866772c31eeSKalle Valo
867772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
868772c31eeSKalle Valo if (ret) {
869772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n",
870772c31eeSKalle Valo filename, ret);
871772c31eeSKalle Valo return ret;
872772c31eeSKalle Valo }
873772c31eeSKalle Valo
874772c31eeSKalle Valo return 0;
875772c31eeSKalle Valo }
876772c31eeSKalle Valo
ath6kl_fetch_patch_file(struct ath6kl * ar)877772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar)
878772c31eeSKalle Valo {
879c0038972SKalle Valo char filename[100];
880772c31eeSKalle Valo int ret;
881772c31eeSKalle Valo
882d1a9421dSKalle Valo if (ar->fw_patch != NULL)
883772c31eeSKalle Valo return 0;
884772c31eeSKalle Valo
885c0038972SKalle Valo if (ar->hw.fw.patch == NULL)
886d1a9421dSKalle Valo return 0;
887d1a9421dSKalle Valo
888c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s",
889c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch);
890d1a9421dSKalle Valo
891772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
892772c31eeSKalle Valo &ar->fw_patch_len);
893772c31eeSKalle Valo if (ret) {
894772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n",
895772c31eeSKalle Valo filename, ret);
896772c31eeSKalle Valo return ret;
897772c31eeSKalle Valo }
898772c31eeSKalle Valo
899772c31eeSKalle Valo return 0;
900772c31eeSKalle Valo }
901772c31eeSKalle Valo
ath6kl_fetch_testscript_file(struct ath6kl * ar)902cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
903cd23c1c9SAlex Yang {
904cd23c1c9SAlex Yang char filename[100];
905cd23c1c9SAlex Yang int ret;
906cd23c1c9SAlex Yang
9075f1127ffSKalle Valo if (ar->testmode != 2)
908cd23c1c9SAlex Yang return 0;
909cd23c1c9SAlex Yang
910cd23c1c9SAlex Yang if (ar->fw_testscript != NULL)
911cd23c1c9SAlex Yang return 0;
912cd23c1c9SAlex Yang
913cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL)
914cd23c1c9SAlex Yang return 0;
915cd23c1c9SAlex Yang
916cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s",
917cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript);
918cd23c1c9SAlex Yang
919cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
920cd23c1c9SAlex Yang &ar->fw_testscript_len);
921cd23c1c9SAlex Yang if (ret) {
922cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n",
923cd23c1c9SAlex Yang filename, ret);
924cd23c1c9SAlex Yang return ret;
925cd23c1c9SAlex Yang }
926cd23c1c9SAlex Yang
927cd23c1c9SAlex Yang return 0;
928cd23c1c9SAlex Yang }
929cd23c1c9SAlex Yang
ath6kl_fetch_fw_api1(struct ath6kl * ar)93050d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
931772c31eeSKalle Valo {
932772c31eeSKalle Valo int ret;
933772c31eeSKalle Valo
934772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar);
935772c31eeSKalle Valo if (ret)
936772c31eeSKalle Valo return ret;
937772c31eeSKalle Valo
938772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar);
939772c31eeSKalle Valo if (ret)
940772c31eeSKalle Valo return ret;
941772c31eeSKalle Valo
942772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar);
943772c31eeSKalle Valo if (ret)
944772c31eeSKalle Valo return ret;
945772c31eeSKalle Valo
946cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar);
947cd23c1c9SAlex Yang if (ret)
948cd23c1c9SAlex Yang return ret;
949cd23c1c9SAlex Yang
950772c31eeSKalle Valo return 0;
951772c31eeSKalle Valo }
952bdcd8170SKalle Valo
ath6kl_fetch_fw_apin(struct ath6kl * ar,const char * name)95365a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
95450d41234SKalle Valo {
95550d41234SKalle Valo size_t magic_len, len, ie_len;
95650d41234SKalle Valo const struct firmware *fw;
95750d41234SKalle Valo struct ath6kl_fw_ie *hdr;
958c0038972SKalle Valo char filename[100];
95950d41234SKalle Valo const u8 *data;
96097e0496dSKalle Valo int ret, ie_id, i, index, bit;
9618a137480SKalle Valo __le32 *val;
96250d41234SKalle Valo
96365a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
96450d41234SKalle Valo
96550d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev);
966efc2b2b5SBen Greear if (ret) {
967efc2b2b5SBen Greear ath6kl_err("Failed request firmware, rv: %d\n", ret);
96850d41234SKalle Valo return ret;
969efc2b2b5SBen Greear }
97050d41234SKalle Valo
97150d41234SKalle Valo data = fw->data;
97250d41234SKalle Valo len = fw->size;
97350d41234SKalle Valo
97450d41234SKalle Valo /* magic also includes the null byte, check that as well */
97550d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
97650d41234SKalle Valo
97750d41234SKalle Valo if (len < magic_len) {
978efc2b2b5SBen Greear ath6kl_err("Magic length is invalid, len: %zd magic_len: %zd\n",
979efc2b2b5SBen Greear len, magic_len);
98050d41234SKalle Valo ret = -EINVAL;
98150d41234SKalle Valo goto out;
98250d41234SKalle Valo }
98350d41234SKalle Valo
98450d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
985efc2b2b5SBen Greear ath6kl_err("Magic is invalid, magic_len: %zd\n",
986efc2b2b5SBen Greear magic_len);
98750d41234SKalle Valo ret = -EINVAL;
98850d41234SKalle Valo goto out;
98950d41234SKalle Valo }
99050d41234SKalle Valo
99150d41234SKalle Valo len -= magic_len;
99250d41234SKalle Valo data += magic_len;
99350d41234SKalle Valo
99450d41234SKalle Valo /* loop elements */
99550d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) {
99650d41234SKalle Valo /* hdr is unaligned! */
99750d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data;
99850d41234SKalle Valo
99950d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id);
100050d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len);
100150d41234SKalle Valo
100250d41234SKalle Valo len -= sizeof(*hdr);
100350d41234SKalle Valo data += sizeof(*hdr);
100450d41234SKalle Valo
1005efc2b2b5SBen Greear ath6kl_dbg(ATH6KL_DBG_BOOT, "ie-id: %d len: %zd (0x%zx)\n",
1006efc2b2b5SBen Greear ie_id, ie_len, ie_len);
1007efc2b2b5SBen Greear
100850d41234SKalle Valo if (len < ie_len) {
1009efc2b2b5SBen Greear ath6kl_err("IE len is invalid, len: %zd ie_len: %zd ie-id: %d\n",
1010efc2b2b5SBen Greear len, ie_len, ie_id);
101150d41234SKalle Valo ret = -EINVAL;
101250d41234SKalle Valo goto out;
101350d41234SKalle Valo }
101450d41234SKalle Valo
101550d41234SKalle Valo switch (ie_id) {
1016b5b6f6a9SNaveen Singh case ATH6KL_FW_IE_FW_VERSION:
1017*bf99f11dSWolfram Sang strscpy(ar->wiphy->fw_version, data,
101853cc3291SBen Greear min(sizeof(ar->wiphy->fw_version), ie_len+1));
1019b5b6f6a9SNaveen Singh
1020b5b6f6a9SNaveen Singh ath6kl_dbg(ATH6KL_DBG_BOOT,
1021b5b6f6a9SNaveen Singh "found fw version %s\n",
1022b5b6f6a9SNaveen Singh ar->wiphy->fw_version);
1023b5b6f6a9SNaveen Singh break;
102450d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE:
1025ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
10266bc36431SKalle Valo ie_len);
10276bc36431SKalle Valo
102850d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
102950d41234SKalle Valo
103050d41234SKalle Valo if (ar->fw_otp == NULL) {
1031efc2b2b5SBen Greear ath6kl_err("fw_otp cannot be allocated\n");
103250d41234SKalle Valo ret = -ENOMEM;
103350d41234SKalle Valo goto out;
103450d41234SKalle Valo }
103550d41234SKalle Valo
103650d41234SKalle Valo ar->fw_otp_len = ie_len;
103750d41234SKalle Valo break;
103850d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE:
1039ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
10406bc36431SKalle Valo ie_len);
10416bc36431SKalle Valo
10425f1127ffSKalle Valo /* in testmode we already might have a fw file */
10435f1127ffSKalle Valo if (ar->fw != NULL)
10445f1127ffSKalle Valo break;
10455f1127ffSKalle Valo
10468437754cSVivek Natarajan ar->fw = vmalloc(ie_len);
104750d41234SKalle Valo
104850d41234SKalle Valo if (ar->fw == NULL) {
1049efc2b2b5SBen Greear ath6kl_err("fw storage cannot be allocated, len: %zd\n", ie_len);
105050d41234SKalle Valo ret = -ENOMEM;
105150d41234SKalle Valo goto out;
105250d41234SKalle Valo }
105350d41234SKalle Valo
10548437754cSVivek Natarajan memcpy(ar->fw, data, ie_len);
105550d41234SKalle Valo ar->fw_len = ie_len;
105650d41234SKalle Valo break;
105750d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE:
1058ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
10596bc36431SKalle Valo ie_len);
10606bc36431SKalle Valo
106150d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
106250d41234SKalle Valo
106350d41234SKalle Valo if (ar->fw_patch == NULL) {
1064efc2b2b5SBen Greear ath6kl_err("fw_patch storage cannot be allocated, len: %zd\n", ie_len);
106550d41234SKalle Valo ret = -ENOMEM;
106650d41234SKalle Valo goto out;
106750d41234SKalle Valo }
106850d41234SKalle Valo
106950d41234SKalle Valo ar->fw_patch_len = ie_len;
107050d41234SKalle Valo break;
10718a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
10728a137480SKalle Valo val = (__le32 *) data;
10738a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val);
10746bc36431SKalle Valo
10756bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
107610d49878SHans Wennborg "found reserved ram size ie %d\n",
10776bc36431SKalle Valo ar->hw.reserved_ram_size);
10788a137480SKalle Valo break;
107997e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES:
10806bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
1081ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n",
10826bc36431SKalle Valo ie_len);
10836bc36431SKalle Valo
108497e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
1085277d90f4SKalle Valo index = i / 8;
108697e0496dSKalle Valo bit = i % 8;
108797e0496dSKalle Valo
1088c85251f8SThomas Pedersen if (index == ie_len)
1089c85251f8SThomas Pedersen break;
1090c85251f8SThomas Pedersen
109197e0496dSKalle Valo if (data[index] & (1 << bit))
109297e0496dSKalle Valo __set_bit(i, ar->fw_capabilities);
109397e0496dSKalle Valo }
10946bc36431SKalle Valo
10956bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
10966bc36431SKalle Valo ar->fw_capabilities,
10976bc36431SKalle Valo sizeof(ar->fw_capabilities));
109897e0496dSKalle Valo break;
10991b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR:
11001b4304daSKalle Valo if (ie_len != sizeof(*val))
11011b4304daSKalle Valo break;
11021b4304daSKalle Valo
11031b4304daSKalle Valo val = (__le32 *) data;
11041b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val);
11056bc36431SKalle Valo
11066bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
110703ef0250SKalle Valo "found patch address ie 0x%x\n",
11086bc36431SKalle Valo ar->hw.dataset_patch_addr);
11091b4304daSKalle Valo break;
111003ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR:
111103ef0250SKalle Valo if (ie_len != sizeof(*val))
111203ef0250SKalle Valo break;
111303ef0250SKalle Valo
111403ef0250SKalle Valo val = (__le32 *) data;
111503ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val);
111603ef0250SKalle Valo
111703ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
111803ef0250SKalle Valo "found board address ie 0x%x\n",
111903ef0250SKalle Valo ar->hw.board_addr);
112003ef0250SKalle Valo break;
1121368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX:
1122368b1b0fSKalle Valo if (ie_len != sizeof(*val))
1123368b1b0fSKalle Valo break;
1124368b1b0fSKalle Valo
1125368b1b0fSKalle Valo val = (__le32 *) data;
1126368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
1127368b1b0fSKalle Valo ATH6KL_VIF_MAX);
1128368b1b0fSKalle Valo
1129f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p)
1130f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2;
1131f143379dSVasanthakumar Thiagarajan
1132368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
1133368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max);
1134368b1b0fSKalle Valo break;
113550d41234SKalle Valo default:
11366bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
113750d41234SKalle Valo le32_to_cpup(&hdr->id));
113850d41234SKalle Valo break;
113950d41234SKalle Valo }
114050d41234SKalle Valo
114150d41234SKalle Valo len -= ie_len;
114250d41234SKalle Valo data += ie_len;
1143999eb686SYueHaibing }
114450d41234SKalle Valo
114550d41234SKalle Valo ret = 0;
114650d41234SKalle Valo out:
114750d41234SKalle Valo release_firmware(fw);
114850d41234SKalle Valo
114950d41234SKalle Valo return ret;
115050d41234SKalle Valo }
115150d41234SKalle Valo
ath6kl_init_fetch_firmwares(struct ath6kl * ar)115245eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
115350d41234SKalle Valo {
115450d41234SKalle Valo int ret;
115550d41234SKalle Valo
115650d41234SKalle Valo ret = ath6kl_fetch_board_file(ar);
115750d41234SKalle Valo if (ret)
115850d41234SKalle Valo return ret;
115950d41234SKalle Valo
11605f1127ffSKalle Valo ret = ath6kl_fetch_testmode_file(ar);
11615f1127ffSKalle Valo if (ret)
11625f1127ffSKalle Valo return ret;
11635f1127ffSKalle Valo
116478803770SJessica Wu ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API5_FILE);
116578803770SJessica Wu if (ret == 0) {
116678803770SJessica Wu ar->fw_api = 5;
116778803770SJessica Wu goto out;
116878803770SJessica Wu }
116978803770SJessica Wu
1170b1f47e3aSThomas Pedersen ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API4_FILE);
1171b1f47e3aSThomas Pedersen if (ret == 0) {
1172b1f47e3aSThomas Pedersen ar->fw_api = 4;
1173b1f47e3aSThomas Pedersen goto out;
1174b1f47e3aSThomas Pedersen }
1175b1f47e3aSThomas Pedersen
117665a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
11776bc36431SKalle Valo if (ret == 0) {
117865a8b4ccSKalle Valo ar->fw_api = 3;
117965a8b4ccSKalle Valo goto out;
118065a8b4ccSKalle Valo }
118165a8b4ccSKalle Valo
118265a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
118365a8b4ccSKalle Valo if (ret == 0) {
118465a8b4ccSKalle Valo ar->fw_api = 2;
118565a8b4ccSKalle Valo goto out;
11866bc36431SKalle Valo }
118750d41234SKalle Valo
118850d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar);
118950d41234SKalle Valo if (ret)
119050d41234SKalle Valo return ret;
119150d41234SKalle Valo
119265a8b4ccSKalle Valo ar->fw_api = 1;
119365a8b4ccSKalle Valo
119465a8b4ccSKalle Valo out:
119565a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
11966bc36431SKalle Valo
119750d41234SKalle Valo return 0;
119850d41234SKalle Valo }
119950d41234SKalle Valo
ath6kl_upload_board_file(struct ath6kl * ar)1200bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar)
1201bdcd8170SKalle Valo {
1202bdcd8170SKalle Valo u32 board_address, board_ext_address, param;
120331024d99SKevin Fang u32 board_data_size, board_ext_data_size;
1204bdcd8170SKalle Valo int ret;
1205bdcd8170SKalle Valo
1206772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL))
1207772c31eeSKalle Valo return -ENOENT;
1208bdcd8170SKalle Valo
120931024d99SKevin Fang /*
121031024d99SKevin Fang * Determine where in Target RAM to write Board Data.
121131024d99SKevin Fang * For AR6004, host determine Target RAM address for
121231024d99SKevin Fang * writing board data.
121331024d99SKevin Fang */
12140d4d72bfSKalle Valo if (ar->hw.board_addr != 0) {
1215b0fc7c1aSKalle Valo board_address = ar->hw.board_addr;
121624fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data,
1217b0fc7c1aSKalle Valo board_address);
121831024d99SKevin Fang } else {
12191c3d95edSFrederic Danis ret = ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
12201c3d95edSFrederic Danis if (ret) {
12211c3d95edSFrederic Danis ath6kl_err("Failed to get board file target address.\n");
12221c3d95edSFrederic Danis return ret;
12231c3d95edSFrederic Danis }
122431024d99SKevin Fang }
122531024d99SKevin Fang
1226bdcd8170SKalle Valo /* determine where in target ram to write extended board data */
12271c3d95edSFrederic Danis ret = ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
12281c3d95edSFrederic Danis if (ret) {
12291c3d95edSFrederic Danis ath6kl_err("Failed to get extended board file target address.\n");
12301c3d95edSFrederic Danis return ret;
12311c3d95edSFrederic Danis }
1232bdcd8170SKalle Valo
123350e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 &&
123450e2740bSKalle Valo board_ext_address == 0) {
1235bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n");
1236bdcd8170SKalle Valo return -EINVAL;
1237bdcd8170SKalle Valo }
1238bdcd8170SKalle Valo
123931024d99SKevin Fang switch (ar->target_type) {
124031024d99SKevin Fang case TARGET_TYPE_AR6003:
124131024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ;
124231024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
1243fb1ac2efSPrasanna Kumar if (ar->fw_board_len > (board_data_size + board_ext_data_size))
1244fb1ac2efSPrasanna Kumar board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
124531024d99SKevin Fang break;
124631024d99SKevin Fang case TARGET_TYPE_AR6004:
124731024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ;
124831024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
124931024d99SKevin Fang break;
125031024d99SKevin Fang default:
125131024d99SKevin Fang WARN_ON(1);
125231024d99SKevin Fang return -EINVAL;
125331024d99SKevin Fang }
125431024d99SKevin Fang
125550e2740bSKalle Valo if (board_ext_address &&
125650e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) {
1257bdcd8170SKalle Valo /* write extended board data */
12586bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
12596bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n",
12606bc36431SKalle Valo board_ext_address, board_ext_data_size);
12616bc36431SKalle Valo
1262bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address,
126331024d99SKevin Fang ar->fw_board + board_data_size,
126431024d99SKevin Fang board_ext_data_size);
1265bdcd8170SKalle Valo if (ret) {
1266bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n",
1267bdcd8170SKalle Valo ret);
1268bdcd8170SKalle Valo return ret;
1269bdcd8170SKalle Valo }
1270bdcd8170SKalle Valo
1271bdcd8170SKalle Valo /* record that extended board data is initialized */
127231024d99SKevin Fang param = (board_ext_data_size << 16) | 1;
127331024d99SKevin Fang
127424fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
1275bdcd8170SKalle Valo }
1276bdcd8170SKalle Valo
127731024d99SKevin Fang if (ar->fw_board_len < board_data_size) {
1278bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
1279bdcd8170SKalle Valo ret = -EINVAL;
1280bdcd8170SKalle Valo return ret;
1281bdcd8170SKalle Valo }
1282bdcd8170SKalle Valo
12836bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
12846bc36431SKalle Valo board_address, board_data_size);
12856bc36431SKalle Valo
1286bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
128731024d99SKevin Fang board_data_size);
1288bdcd8170SKalle Valo
1289bdcd8170SKalle Valo if (ret) {
1290bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret);
1291bdcd8170SKalle Valo return ret;
1292bdcd8170SKalle Valo }
1293bdcd8170SKalle Valo
1294bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */
129578803770SJessica Wu if ((ar->version.target_ver == AR6004_HW_1_3_VERSION) ||
129678803770SJessica Wu (ar->version.target_ver == AR6004_HW_3_0_VERSION))
129778803770SJessica Wu param = board_data_size;
129878803770SJessica Wu else
129978803770SJessica Wu param = 1;
130078803770SJessica Wu
130178803770SJessica Wu ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, param);
1302bdcd8170SKalle Valo
1303bdcd8170SKalle Valo return ret;
1304bdcd8170SKalle Valo }
1305bdcd8170SKalle Valo
ath6kl_upload_otp(struct ath6kl * ar)1306bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar)
1307bdcd8170SKalle Valo {
1308bdcd8170SKalle Valo u32 address, param;
1309bef26a7fSKalle Valo bool from_hw = false;
1310bdcd8170SKalle Valo int ret;
1311bdcd8170SKalle Valo
131250e2740bSKalle Valo if (ar->fw_otp == NULL)
131350e2740bSKalle Valo return 0;
1314bdcd8170SKalle Valo
1315a01ac414SKalle Valo address = ar->hw.app_load_addr;
1316bdcd8170SKalle Valo
1317ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
13186bc36431SKalle Valo ar->fw_otp_len);
13196bc36431SKalle Valo
1320bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
1321bdcd8170SKalle Valo ar->fw_otp_len);
1322bdcd8170SKalle Valo if (ret) {
1323bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret);
1324bdcd8170SKalle Valo return ret;
1325bdcd8170SKalle Valo }
1326bdcd8170SKalle Valo
1327639d0b89SKalle Valo /* read firmware start address */
132880fb2686SKalle Valo ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
1329639d0b89SKalle Valo
1330639d0b89SKalle Valo if (ret) {
1331639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret);
1332639d0b89SKalle Valo return ret;
1333639d0b89SKalle Valo }
1334639d0b89SKalle Valo
1335bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) {
1336639d0b89SKalle Valo ar->hw.app_start_override_addr = address;
1337bef26a7fSKalle Valo from_hw = true;
1338bef26a7fSKalle Valo }
1339639d0b89SKalle Valo
1340bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
1341bef26a7fSKalle Valo from_hw ? " (from hw)" : "",
13426bc36431SKalle Valo ar->hw.app_start_override_addr);
13436bc36431SKalle Valo
1344bdcd8170SKalle Valo /* execute the OTP code */
1345bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
1346bef26a7fSKalle Valo ar->hw.app_start_override_addr);
1347bdcd8170SKalle Valo param = 0;
1348bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m);
1349bdcd8170SKalle Valo
1350bdcd8170SKalle Valo return ret;
1351bdcd8170SKalle Valo }
1352bdcd8170SKalle Valo
ath6kl_upload_firmware(struct ath6kl * ar)1353bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar)
1354bdcd8170SKalle Valo {
1355bdcd8170SKalle Valo u32 address;
1356bdcd8170SKalle Valo int ret;
1357bdcd8170SKalle Valo
1358772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL))
135950e2740bSKalle Valo return 0;
1360bdcd8170SKalle Valo
1361a01ac414SKalle Valo address = ar->hw.app_load_addr;
1362bdcd8170SKalle Valo
1363ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
13646bc36431SKalle Valo address, ar->fw_len);
13656bc36431SKalle Valo
1366bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
1367bdcd8170SKalle Valo
1368bdcd8170SKalle Valo if (ret) {
1369bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret);
1370bdcd8170SKalle Valo return ret;
1371bdcd8170SKalle Valo }
1372bdcd8170SKalle Valo
137331024d99SKevin Fang /*
137431024d99SKevin Fang * Set starting address for firmware
137531024d99SKevin Fang * Don't need to setup app_start override addr on AR6004
137631024d99SKevin Fang */
137731024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) {
1378a01ac414SKalle Valo address = ar->hw.app_start_override_addr;
1379bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address);
138031024d99SKevin Fang }
1381bdcd8170SKalle Valo return ret;
1382bdcd8170SKalle Valo }
1383bdcd8170SKalle Valo
ath6kl_upload_patch(struct ath6kl * ar)1384bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar)
1385bdcd8170SKalle Valo {
138624fc32b3SKalle Valo u32 address;
1387bdcd8170SKalle Valo int ret;
1388bdcd8170SKalle Valo
138950e2740bSKalle Valo if (ar->fw_patch == NULL)
139050e2740bSKalle Valo return 0;
1391bdcd8170SKalle Valo
1392a01ac414SKalle Valo address = ar->hw.dataset_patch_addr;
1393bdcd8170SKalle Valo
1394ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
13956bc36431SKalle Valo address, ar->fw_patch_len);
13966bc36431SKalle Valo
1397bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
1398bdcd8170SKalle Valo if (ret) {
1399bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret);
1400bdcd8170SKalle Valo return ret;
1401bdcd8170SKalle Valo }
1402bdcd8170SKalle Valo
140324fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
1404bdcd8170SKalle Valo
1405bdcd8170SKalle Valo return 0;
1406bdcd8170SKalle Valo }
1407bdcd8170SKalle Valo
ath6kl_upload_testscript(struct ath6kl * ar)1408cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar)
1409cd23c1c9SAlex Yang {
141024fc32b3SKalle Valo u32 address;
1411cd23c1c9SAlex Yang int ret;
1412cd23c1c9SAlex Yang
14135f1127ffSKalle Valo if (ar->testmode != 2)
1414cd23c1c9SAlex Yang return 0;
1415cd23c1c9SAlex Yang
1416cd23c1c9SAlex Yang if (ar->fw_testscript == NULL)
1417cd23c1c9SAlex Yang return 0;
1418cd23c1c9SAlex Yang
1419cd23c1c9SAlex Yang address = ar->hw.testscript_addr;
1420cd23c1c9SAlex Yang
1421cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
1422cd23c1c9SAlex Yang address, ar->fw_testscript_len);
1423cd23c1c9SAlex Yang
1424cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
1425cd23c1c9SAlex Yang ar->fw_testscript_len);
1426cd23c1c9SAlex Yang if (ret) {
1427cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret);
1428cd23c1c9SAlex Yang return ret;
1429cd23c1c9SAlex Yang }
1430cd23c1c9SAlex Yang
143124fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
143278803770SJessica Wu
143378803770SJessica Wu if ((ar->version.target_ver != AR6004_HW_1_3_VERSION) &&
143478803770SJessica Wu (ar->version.target_ver != AR6004_HW_3_0_VERSION))
143524fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
143678803770SJessica Wu
143724fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
1438cd23c1c9SAlex Yang
1439cd23c1c9SAlex Yang return 0;
1440cd23c1c9SAlex Yang }
1441cd23c1c9SAlex Yang
ath6kl_init_upload(struct ath6kl * ar)1442bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar)
1443bdcd8170SKalle Valo {
1444bdcd8170SKalle Valo u32 param, options, sleep, address;
1445bdcd8170SKalle Valo int status = 0;
1446bdcd8170SKalle Valo
144731024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 &&
144831024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004)
1449bdcd8170SKalle Valo return -EINVAL;
1450bdcd8170SKalle Valo
1451bdcd8170SKalle Valo /* temporarily disable system sleep */
1452bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1453bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m);
1454bdcd8170SKalle Valo if (status)
1455bdcd8170SKalle Valo return status;
1456bdcd8170SKalle Valo
1457bdcd8170SKalle Valo options = param;
1458bdcd8170SKalle Valo
1459bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE;
1460bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1461bdcd8170SKalle Valo if (status)
1462bdcd8170SKalle Valo return status;
1463bdcd8170SKalle Valo
1464bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1465bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m);
1466bdcd8170SKalle Valo if (status)
1467bdcd8170SKalle Valo return status;
1468bdcd8170SKalle Valo
1469bdcd8170SKalle Valo sleep = param;
1470bdcd8170SKalle Valo
1471bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1);
1472bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1473bdcd8170SKalle Valo if (status)
1474bdcd8170SKalle Valo return status;
1475bdcd8170SKalle Valo
1476bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
1477bdcd8170SKalle Valo options, sleep);
1478bdcd8170SKalle Valo
1479bdcd8170SKalle Valo /* program analog PLL register */
148031024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */
148131024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) {
1482bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
1483bdcd8170SKalle Valo 0xF9104001);
148431024d99SKevin Fang
1485bdcd8170SKalle Valo if (status)
1486bdcd8170SKalle Valo return status;
1487bdcd8170SKalle Valo
1488bdcd8170SKalle Valo /* Run at 80/88MHz by default */
1489bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1);
1490bdcd8170SKalle Valo
1491bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
1492bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1493bdcd8170SKalle Valo if (status)
1494bdcd8170SKalle Valo return status;
149531024d99SKevin Fang }
1496bdcd8170SKalle Valo
1497bdcd8170SKalle Valo param = 0;
1498bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
1499bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1);
1500bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1501bdcd8170SKalle Valo if (status)
1502bdcd8170SKalle Valo return status;
1503bdcd8170SKalle Valo
1504bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */
1505a2e1be33SMohammed Shafi Shajakhan if (ar->hw.flags & ATH6KL_HW_SDIO_CRC_ERROR_WAR) {
1506bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n");
1507bdcd8170SKalle Valo
1508fa338be0SVasanthakumar Thiagarajan param = 0x28;
1509fa338be0SVasanthakumar Thiagarajan address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS;
1510fa338be0SVasanthakumar Thiagarajan status = ath6kl_bmi_reg_write(ar, address, param);
1511fa338be0SVasanthakumar Thiagarajan if (status)
1512fa338be0SVasanthakumar Thiagarajan return status;
1513fa338be0SVasanthakumar Thiagarajan
1514bdcd8170SKalle Valo param = 0x20;
1515bdcd8170SKalle Valo
1516bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
1517bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1518bdcd8170SKalle Valo if (status)
1519bdcd8170SKalle Valo return status;
1520bdcd8170SKalle Valo
1521bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
1522bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1523bdcd8170SKalle Valo if (status)
1524bdcd8170SKalle Valo return status;
1525bdcd8170SKalle Valo
1526bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
1527bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1528bdcd8170SKalle Valo if (status)
1529bdcd8170SKalle Valo return status;
1530bdcd8170SKalle Valo
1531bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
1532bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1533bdcd8170SKalle Valo if (status)
1534bdcd8170SKalle Valo return status;
1535bdcd8170SKalle Valo }
1536bdcd8170SKalle Valo
1537bdcd8170SKalle Valo /* write EEPROM data to Target RAM */
1538bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar);
1539bdcd8170SKalle Valo if (status)
1540bdcd8170SKalle Valo return status;
1541bdcd8170SKalle Valo
1542bdcd8170SKalle Valo /* transfer One time Programmable data */
1543bdcd8170SKalle Valo status = ath6kl_upload_otp(ar);
1544bdcd8170SKalle Valo if (status)
1545bdcd8170SKalle Valo return status;
1546bdcd8170SKalle Valo
1547bdcd8170SKalle Valo /* Download Target firmware */
1548bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar);
1549bdcd8170SKalle Valo if (status)
1550bdcd8170SKalle Valo return status;
1551bdcd8170SKalle Valo
1552bdcd8170SKalle Valo status = ath6kl_upload_patch(ar);
1553bdcd8170SKalle Valo if (status)
1554bdcd8170SKalle Valo return status;
1555bdcd8170SKalle Valo
1556cd23c1c9SAlex Yang /* Download the test script */
1557cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar);
1558cd23c1c9SAlex Yang if (status)
1559cd23c1c9SAlex Yang return status;
1560cd23c1c9SAlex Yang
1561bdcd8170SKalle Valo /* Restore system sleep */
1562bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1563bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep);
1564bdcd8170SKalle Valo if (status)
1565bdcd8170SKalle Valo return status;
1566bdcd8170SKalle Valo
1567bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1568bdcd8170SKalle Valo param = options | 0x20;
1569bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param);
1570bdcd8170SKalle Valo if (status)
1571bdcd8170SKalle Valo return status;
1572bdcd8170SKalle Valo
1573bdcd8170SKalle Valo return status;
1574bdcd8170SKalle Valo }
1575bdcd8170SKalle Valo
ath6kl_init_hw_params(struct ath6kl * ar)157645eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar)
1577a01ac414SKalle Valo {
15783f649ab7SKees Cook const struct ath6kl_hw *hw;
1579856f4b31SKalle Valo int i;
1580bef26a7fSKalle Valo
1581856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
1582856f4b31SKalle Valo hw = &hw_list[i];
1583bef26a7fSKalle Valo
1584856f4b31SKalle Valo if (hw->id == ar->version.target_ver)
1585a01ac414SKalle Valo break;
1586856f4b31SKalle Valo }
1587856f4b31SKalle Valo
1588856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) {
1589a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n",
1590a01ac414SKalle Valo ar->version.target_ver);
1591a01ac414SKalle Valo return -EINVAL;
1592a01ac414SKalle Valo }
1593a01ac414SKalle Valo
1594856f4b31SKalle Valo ar->hw = *hw;
1595856f4b31SKalle Valo
15966bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
15976bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
15986bc36431SKalle Valo ar->version.target_ver, ar->target_type,
15996bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
16006bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
16016bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
16026bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
16036bc36431SKalle Valo ar->hw.reserved_ram_size);
160439586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT,
160539586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d",
160639586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin);
16076bc36431SKalle Valo
1608a01ac414SKalle Valo return 0;
1609a01ac414SKalle Valo }
1610a01ac414SKalle Valo
ath6kl_init_get_hif_name(enum ath6kl_hif_type type)1611293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
1612293badf4SKalle Valo {
1613293badf4SKalle Valo switch (type) {
1614293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO:
1615293badf4SKalle Valo return "sdio";
1616293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB:
1617293badf4SKalle Valo return "usb";
1618293badf4SKalle Valo }
1619293badf4SKalle Valo
1620293badf4SKalle Valo return NULL;
1621293badf4SKalle Valo }
1622293badf4SKalle Valo
1623e72c2746SKalle Valo
1624e72c2746SKalle Valo static const struct fw_capa_str_map {
1625e72c2746SKalle Valo int id;
1626e72c2746SKalle Valo const char *name;
1627e72c2746SKalle Valo } fw_capa_map[] = {
1628e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_HOST_P2P, "host-p2p" },
1629e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_SCHED_SCAN, "sched-scan" },
1630e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, "sta-p2pdev-duplex" },
1631e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT, "inactivity-timeout" },
1632e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, "rsn-cap-override" },
1633e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER, "wow-mc-filter" },
1634e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_BMISS_ENHANCE, "bmiss-enhance" },
1635e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST, "sscan-match-list" },
1636e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD, "rssi-scan-thold" },
1637e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR, "custom-mac-addr" },
1638e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY, "tx-err-notify" },
1639e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_REGDOMAIN, "regdomain" },
1640e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2, "sched-scan-v2" },
1641e72c2746SKalle Valo { ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL, "hb-poll" },
1642eba95bceSKalle Valo { ATH6KL_FW_CAPABILITY_64BIT_RATES, "64bit-rates" },
1643eba95bceSKalle Valo { ATH6KL_FW_CAPABILITY_AP_INACTIVITY_MINS, "ap-inactivity-mins" },
1644eba95bceSKalle Valo { ATH6KL_FW_CAPABILITY_MAP_LP_ENDPOINT, "map-lp-endpoint" },
1645c1d32d30SJessica Wu { ATH6KL_FW_CAPABILITY_RATETABLE_MCS15, "ratetable-mcs15" },
164678803770SJessica Wu { ATH6KL_FW_CAPABILITY_NO_IP_CHECKSUM, "no-ip-checksum" },
1647e72c2746SKalle Valo };
1648e72c2746SKalle Valo
ath6kl_init_get_fw_capa_name(unsigned int id)1649e72c2746SKalle Valo static const char *ath6kl_init_get_fw_capa_name(unsigned int id)
1650e72c2746SKalle Valo {
1651e72c2746SKalle Valo int i;
1652e72c2746SKalle Valo
1653e72c2746SKalle Valo for (i = 0; i < ARRAY_SIZE(fw_capa_map); i++) {
1654e72c2746SKalle Valo if (fw_capa_map[i].id == id)
1655e72c2746SKalle Valo return fw_capa_map[i].name;
1656e72c2746SKalle Valo }
1657e72c2746SKalle Valo
1658e72c2746SKalle Valo return "<unknown>";
1659e72c2746SKalle Valo }
1660e72c2746SKalle Valo
ath6kl_init_get_fwcaps(struct ath6kl * ar,char * buf,size_t buf_len)1661e72c2746SKalle Valo static void ath6kl_init_get_fwcaps(struct ath6kl *ar, char *buf, size_t buf_len)
1662e72c2746SKalle Valo {
1663e72c2746SKalle Valo u8 *data = (u8 *) ar->fw_capabilities;
1664e72c2746SKalle Valo size_t trunc_len, len = 0;
1665e72c2746SKalle Valo int i, index, bit;
1666e72c2746SKalle Valo char *trunc = "...";
1667e72c2746SKalle Valo
1668e72c2746SKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
1669e72c2746SKalle Valo index = i / 8;
1670e72c2746SKalle Valo bit = i % 8;
1671e72c2746SKalle Valo
1672e72c2746SKalle Valo if (index >= sizeof(ar->fw_capabilities) * 4)
1673e72c2746SKalle Valo break;
1674e72c2746SKalle Valo
1675e72c2746SKalle Valo if (buf_len - len < 4) {
1676e72c2746SKalle Valo ath6kl_warn("firmware capability buffer too small!\n");
1677e72c2746SKalle Valo
1678e72c2746SKalle Valo /* add "..." to the end of string */
1679e72c2746SKalle Valo trunc_len = strlen(trunc) + 1;
1680e72c2746SKalle Valo strncpy(buf + buf_len - trunc_len, trunc, trunc_len);
1681e72c2746SKalle Valo
1682e72c2746SKalle Valo return;
1683e72c2746SKalle Valo }
1684e72c2746SKalle Valo
1685e72c2746SKalle Valo if (data[index] & (1 << bit)) {
1686e72c2746SKalle Valo len += scnprintf(buf + len, buf_len - len, "%s,",
1687e72c2746SKalle Valo ath6kl_init_get_fw_capa_name(i));
1688e72c2746SKalle Valo }
1689e72c2746SKalle Valo }
1690e72c2746SKalle Valo
1691e72c2746SKalle Valo /* overwrite the last comma */
1692e72c2746SKalle Valo if (len > 0)
1693e72c2746SKalle Valo len--;
1694e72c2746SKalle Valo
1695e72c2746SKalle Valo buf[len] = '\0';
1696e72c2746SKalle Valo }
1697e72c2746SKalle Valo
ath6kl_init_hw_reset(struct ath6kl * ar)1698ec1461dcSKalle Valo static int ath6kl_init_hw_reset(struct ath6kl *ar)
1699ec1461dcSKalle Valo {
1700ec1461dcSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "cold resetting the device");
1701ec1461dcSKalle Valo
1702ec1461dcSKalle Valo return ath6kl_diag_write32(ar, RESET_CONTROL_ADDRESS,
1703ec1461dcSKalle Valo cpu_to_le32(RESET_CONTROL_COLD_RST));
1704ec1461dcSKalle Valo }
1705ec1461dcSKalle Valo
__ath6kl_init_hw_start(struct ath6kl * ar)1706ede615d2SVasanthakumar Thiagarajan static int __ath6kl_init_hw_start(struct ath6kl *ar)
170720459ee2SKalle Valo {
170820459ee2SKalle Valo long timeleft;
170920459ee2SKalle Valo int ret, i;
1710e72c2746SKalle Valo char buf[200];
171120459ee2SKalle Valo
17125fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
17135fe4dffbSKalle Valo
171420459ee2SKalle Valo ret = ath6kl_hif_power_on(ar);
171520459ee2SKalle Valo if (ret)
171620459ee2SKalle Valo return ret;
171720459ee2SKalle Valo
171820459ee2SKalle Valo ret = ath6kl_configure_target(ar);
171920459ee2SKalle Valo if (ret)
172020459ee2SKalle Valo goto err_power_off;
172120459ee2SKalle Valo
172220459ee2SKalle Valo ret = ath6kl_init_upload(ar);
172320459ee2SKalle Valo if (ret)
172420459ee2SKalle Valo goto err_power_off;
172520459ee2SKalle Valo
172620459ee2SKalle Valo /* Do we need to finish the BMI phase */
1727bf978145SMohammed Shafi Shajakhan ret = ath6kl_bmi_done(ar);
1728bf978145SMohammed Shafi Shajakhan if (ret)
172920459ee2SKalle Valo goto err_power_off;
173020459ee2SKalle Valo
173120459ee2SKalle Valo /*
173220459ee2SKalle Valo * The reason we have to wait for the target here is that the
173320459ee2SKalle Valo * driver layer has to init BMI in order to set the host block
173420459ee2SKalle Valo * size.
173520459ee2SKalle Valo */
17364e1609c9SKalle Valo ret = ath6kl_htc_wait_target(ar->htc_target);
173744af3442SKalle Valo
173844af3442SKalle Valo if (ret == -ETIMEDOUT) {
173944af3442SKalle Valo /*
174044af3442SKalle Valo * Most likely USB target is in odd state after reboot and
174144af3442SKalle Valo * needs a reset. A cold reset makes the whole device
174244af3442SKalle Valo * disappear from USB bus and initialisation starts from
174344af3442SKalle Valo * beginning.
174444af3442SKalle Valo */
174544af3442SKalle Valo ath6kl_warn("htc wait target timed out, resetting device\n");
174644af3442SKalle Valo ath6kl_init_hw_reset(ar);
174744af3442SKalle Valo goto err_power_off;
174844af3442SKalle Valo } else if (ret) {
17494e1609c9SKalle Valo ath6kl_err("htc wait target failed: %d\n", ret);
175020459ee2SKalle Valo goto err_power_off;
175120459ee2SKalle Valo }
175220459ee2SKalle Valo
17534e1609c9SKalle Valo ret = ath6kl_init_service_ep(ar);
17544e1609c9SKalle Valo if (ret) {
175542f5fe34SColin Ian King ath6kl_err("Endpoint service initialization failed: %d\n", ret);
175620459ee2SKalle Valo goto err_cleanup_scatter;
175720459ee2SKalle Valo }
175820459ee2SKalle Valo
175920459ee2SKalle Valo /* setup credit distribution */
1760e76ac2bfSKalle Valo ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info);
176120459ee2SKalle Valo
176220459ee2SKalle Valo /* start HTC */
176320459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target);
176420459ee2SKalle Valo if (ret) {
176520459ee2SKalle Valo /* FIXME: call this */
176620459ee2SKalle Valo ath6kl_cookie_cleanup(ar);
176720459ee2SKalle Valo goto err_cleanup_scatter;
176820459ee2SKalle Valo }
176920459ee2SKalle Valo
177020459ee2SKalle Valo /* Wait for Wmi event to be ready */
177120459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq,
177220459ee2SKalle Valo test_bit(WMI_READY,
177320459ee2SKalle Valo &ar->flag),
177420459ee2SKalle Valo WMI_TIMEOUT);
1775ab1ef141SRaja Mani if (timeleft <= 0) {
1776ab1ef141SRaja Mani clear_bit(WMI_READY, &ar->flag);
1777ab1ef141SRaja Mani ath6kl_err("wmi is not ready or wait was interrupted: %ld\n",
1778ab1ef141SRaja Mani timeleft);
1779ab1ef141SRaja Mani ret = -EIO;
1780ab1ef141SRaja Mani goto err_htc_stop;
1781ab1ef141SRaja Mani }
178220459ee2SKalle Valo
178320459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
178420459ee2SKalle Valo
1785293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
178665a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n",
1787293badf4SKalle Valo ar->hw.name,
1788293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type),
1789293badf4SKalle Valo ar->wiphy->fw_version,
179065a8b4ccSKalle Valo ar->fw_api,
1791293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
1792e72c2746SKalle Valo ath6kl_init_get_fwcaps(ar, buf, sizeof(buf));
1793e72c2746SKalle Valo ath6kl_info("firmware supports: %s\n", buf);
1794293badf4SKalle Valo }
1795293badf4SKalle Valo
179620459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
179720459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
179820459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver);
179920459ee2SKalle Valo ret = -EIO;
180020459ee2SKalle Valo goto err_htc_stop;
180120459ee2SKalle Valo }
180220459ee2SKalle Valo
180320459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
180420459ee2SKalle Valo
180520459ee2SKalle Valo /* communicate the wmi protocol verision to the target */
180620459ee2SKalle Valo /* FIXME: return error */
180720459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0)
180820459ee2SKalle Valo ath6kl_err("unable to set the host app area\n");
180920459ee2SKalle Valo
181071f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) {
181120459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i);
181220459ee2SKalle Valo if (ret)
181320459ee2SKalle Valo goto err_htc_stop;
181420459ee2SKalle Valo }
181520459ee2SKalle Valo
181620459ee2SKalle Valo return 0;
181720459ee2SKalle Valo
181820459ee2SKalle Valo err_htc_stop:
181920459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target);
182020459ee2SKalle Valo err_cleanup_scatter:
182120459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar);
182220459ee2SKalle Valo err_power_off:
182320459ee2SKalle Valo ath6kl_hif_power_off(ar);
182420459ee2SKalle Valo
182520459ee2SKalle Valo return ret;
182620459ee2SKalle Valo }
182720459ee2SKalle Valo
ath6kl_init_hw_start(struct ath6kl * ar)1828ede615d2SVasanthakumar Thiagarajan int ath6kl_init_hw_start(struct ath6kl *ar)
1829ede615d2SVasanthakumar Thiagarajan {
1830ede615d2SVasanthakumar Thiagarajan int err;
1831ede615d2SVasanthakumar Thiagarajan
1832ede615d2SVasanthakumar Thiagarajan err = __ath6kl_init_hw_start(ar);
1833ede615d2SVasanthakumar Thiagarajan if (err)
1834ede615d2SVasanthakumar Thiagarajan return err;
1835ede615d2SVasanthakumar Thiagarajan ar->state = ATH6KL_STATE_ON;
1836ede615d2SVasanthakumar Thiagarajan return 0;
1837ede615d2SVasanthakumar Thiagarajan }
1838ede615d2SVasanthakumar Thiagarajan
__ath6kl_init_hw_stop(struct ath6kl * ar)1839ede615d2SVasanthakumar Thiagarajan static int __ath6kl_init_hw_stop(struct ath6kl *ar)
18405fe4dffbSKalle Valo {
18415fe4dffbSKalle Valo int ret;
18425fe4dffbSKalle Valo
18435fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
18445fe4dffbSKalle Valo
18455fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target);
18465fe4dffbSKalle Valo
18475fe4dffbSKalle Valo ath6kl_hif_stop(ar);
18485fe4dffbSKalle Valo
18495fe4dffbSKalle Valo ath6kl_bmi_reset(ar);
18505fe4dffbSKalle Valo
18515fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar);
18525fe4dffbSKalle Valo if (ret)
18535fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret);
18545fe4dffbSKalle Valo
1855ede615d2SVasanthakumar Thiagarajan return 0;
1856ede615d2SVasanthakumar Thiagarajan }
185776a9fbe2SKalle Valo
ath6kl_init_hw_stop(struct ath6kl * ar)1858ede615d2SVasanthakumar Thiagarajan int ath6kl_init_hw_stop(struct ath6kl *ar)
1859ede615d2SVasanthakumar Thiagarajan {
1860ede615d2SVasanthakumar Thiagarajan int err;
1861ede615d2SVasanthakumar Thiagarajan
1862ede615d2SVasanthakumar Thiagarajan err = __ath6kl_init_hw_stop(ar);
1863ede615d2SVasanthakumar Thiagarajan if (err)
1864ede615d2SVasanthakumar Thiagarajan return err;
1865ede615d2SVasanthakumar Thiagarajan ar->state = ATH6KL_STATE_OFF;
18665fe4dffbSKalle Valo return 0;
18675fe4dffbSKalle Valo }
18685fe4dffbSKalle Valo
ath6kl_init_hw_restart(struct ath6kl * ar)186984caf800SVasanthakumar Thiagarajan void ath6kl_init_hw_restart(struct ath6kl *ar)
187084caf800SVasanthakumar Thiagarajan {
187158109df6SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag);
187258109df6SVasanthakumar Thiagarajan
187384caf800SVasanthakumar Thiagarajan ath6kl_cfg80211_stop_all(ar);
187484caf800SVasanthakumar Thiagarajan
187558109df6SVasanthakumar Thiagarajan if (__ath6kl_init_hw_stop(ar)) {
187658109df6SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_RECOVERY, "Failed to stop during fw error recovery\n");
187784caf800SVasanthakumar Thiagarajan return;
187858109df6SVasanthakumar Thiagarajan }
187984caf800SVasanthakumar Thiagarajan
188084caf800SVasanthakumar Thiagarajan if (__ath6kl_init_hw_start(ar)) {
188184caf800SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_RECOVERY, "Failed to restart during fw error recovery\n");
188284caf800SVasanthakumar Thiagarajan return;
188384caf800SVasanthakumar Thiagarajan }
188484caf800SVasanthakumar Thiagarajan }
188584caf800SVasanthakumar Thiagarajan
ath6kl_stop_txrx(struct ath6kl * ar)1886bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar)
1887bdcd8170SKalle Valo {
1888990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif;
18891d2a4456SVasanthakumar Thiagarajan int i;
1890bdcd8170SKalle Valo
1891bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag);
1892bdcd8170SKalle Valo
1893bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) {
1894bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n");
1895bdcd8170SKalle Valo return;
1896bdcd8170SKalle Valo }
1897bdcd8170SKalle Valo
18981d2a4456SVasanthakumar Thiagarajan for (i = 0; i < AP_MAX_NUM_STA; i++)
18991d2a4456SVasanthakumar Thiagarajan aggr_reset_state(ar->sta_list[i].aggr_conn);
19001d2a4456SVasanthakumar Thiagarajan
190111f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock);
1902990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
1903990bd915SVasanthakumar Thiagarajan list_del(&vif->list);
190411f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock);
1905355b3a98SMohammed Shafi Shajakhan ath6kl_cfg80211_vif_stop(vif, test_bit(WMI_READY, &ar->flag));
190627929723SVasanthakumar Thiagarajan rtnl_lock();
1907a05829a7SJohannes Berg wiphy_lock(ar->wiphy);
1908c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif);
1909a05829a7SJohannes Berg wiphy_unlock(ar->wiphy);
191027929723SVasanthakumar Thiagarajan rtnl_unlock();
191111f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock);
1912990bd915SVasanthakumar Thiagarajan }
191311f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock);
1914bdcd8170SKalle Valo
19156db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag);
19166db8fa53SVasanthakumar Thiagarajan
1917f32036e8SVasanthakumar Thiagarajan if (ar->fw_recovery.enable)
1918f32036e8SVasanthakumar Thiagarajan del_timer_sync(&ar->fw_recovery.hb_timer);
1919f32036e8SVasanthakumar Thiagarajan
19206db8fa53SVasanthakumar Thiagarajan /*
19216db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We
19226db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and
19236db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually
19246db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect
19256db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes
19266db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs
19276db8fa53SVasanthakumar Thiagarajan * are collected.
19286db8fa53SVasanthakumar Thiagarajan */
19296db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi);
19306db8fa53SVasanthakumar Thiagarajan
19316db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag);
19326db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) {
19336db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
19346db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target);
1935bdcd8170SKalle Valo }
1936bdcd8170SKalle Valo
1937bdcd8170SKalle Valo /*
19386db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been
19396db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session.
1940bdcd8170SKalle Valo */
1941ec1461dcSKalle Valo ath6kl_init_hw_reset(ar);
1942bdcd8170SKalle Valo
1943e8ad9a06SVasanthakumar Thiagarajan up(&ar->sem);
1944bdcd8170SKalle Valo }
1945d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx);
1946