1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 41b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 5bdcd8170SKalle Valo * 6bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 7bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 8bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 9bdcd8170SKalle Valo * 10bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17bdcd8170SKalle Valo */ 18bdcd8170SKalle Valo 19516304b0SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20516304b0SJoe Perches 21c6efe578SStephen Rothwell #include <linux/moduleparam.h> 22f7830202SSangwook Lee #include <linux/errno.h> 23d6a434d6SKalle Valo #include <linux/export.h> 2492ecbff4SSam Leffler #include <linux/of.h> 25bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 268437754cSVivek Natarajan #include <linux/vmalloc.h> 27d6a434d6SKalle Valo 28bdcd8170SKalle Valo #include "core.h" 29bdcd8170SKalle Valo #include "cfg80211.h" 30bdcd8170SKalle Valo #include "target.h" 31bdcd8170SKalle Valo #include "debug.h" 32bdcd8170SKalle Valo #include "hif-ops.h" 33e76ac2bfSKalle Valo #include "htc-ops.h" 34bdcd8170SKalle Valo 35856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 36856f4b31SKalle Valo { 370d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 38293badf4SKalle Valo .name = "ar6003 hw 2.0", 39856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 40856f4b31SKalle Valo .app_load_addr = 0x543180, 41856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 42856f4b31SKalle Valo .reserved_ram_size = 6912, 4339586bf2SRyan Hsu .refclk_hz = 26000000, 4439586bf2SRyan Hsu .uarttx_pin = 8, 4506e360acSBala Shanmugam .flags = 0, 46856f4b31SKalle Valo 47856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 48856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 49d1a9421dSKalle Valo 50c0038972SKalle Valo .fw = { 51c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 52c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 53d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 54c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 55c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 56c0038972SKalle Valo }, 57c0038972SKalle Valo 58d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 59d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 60856f4b31SKalle Valo }, 61856f4b31SKalle Valo { 620d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 63293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 64856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 65856f4b31SKalle Valo .app_load_addr = 0x1234, 66856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 67856f4b31SKalle Valo .reserved_ram_size = 512, 6839586bf2SRyan Hsu .refclk_hz = 26000000, 6939586bf2SRyan Hsu .uarttx_pin = 8, 70cd23c1c9SAlex Yang .testscript_addr = 0x57ef74, 7106e360acSBala Shanmugam .flags = 0, 72d1a9421dSKalle Valo 73c0038972SKalle Valo .fw = { 74c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 75c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 76d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 77c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 78c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 79cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, 80cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, 81c0038972SKalle Valo }, 82c0038972SKalle Valo 83d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 84d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 85856f4b31SKalle Valo }, 86856f4b31SKalle Valo { 870d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 88293badf4SKalle Valo .name = "ar6004 hw 1.0", 89856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 90856f4b31SKalle Valo .app_load_addr = 0x1234, 91856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 92856f4b31SKalle Valo .reserved_ram_size = 19456, 930d4d72bfSKalle Valo .board_addr = 0x433900, 9439586bf2SRyan Hsu .refclk_hz = 26000000, 9539586bf2SRyan Hsu .uarttx_pin = 11, 9606e360acSBala Shanmugam .flags = ATH6KL_HW_FLAG_64BIT_RATES, 97d1a9421dSKalle Valo 98c0038972SKalle Valo .fw = { 99c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 100d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 101c0038972SKalle Valo }, 102c0038972SKalle Valo 103d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 104d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 105856f4b31SKalle Valo }, 106856f4b31SKalle Valo { 1070d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 108293badf4SKalle Valo .name = "ar6004 hw 1.1", 109856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 110856f4b31SKalle Valo .app_load_addr = 0x1234, 111856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 112856f4b31SKalle Valo .reserved_ram_size = 11264, 1130d4d72bfSKalle Valo .board_addr = 0x43d400, 11439586bf2SRyan Hsu .refclk_hz = 40000000, 11539586bf2SRyan Hsu .uarttx_pin = 11, 11606e360acSBala Shanmugam .flags = ATH6KL_HW_FLAG_64BIT_RATES, 117d1a9421dSKalle Valo 118c0038972SKalle Valo .fw = { 119c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 120d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 121c0038972SKalle Valo }, 122c0038972SKalle Valo 123d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 124d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 125856f4b31SKalle Valo }, 1266146ca69SRay Chen { 1276146ca69SRay Chen .id = AR6004_HW_1_2_VERSION, 1286146ca69SRay Chen .name = "ar6004 hw 1.2", 1296146ca69SRay Chen .dataset_patch_addr = 0x436ecc, 1306146ca69SRay Chen .app_load_addr = 0x1234, 1316146ca69SRay Chen .board_ext_data_addr = 0x437000, 1326146ca69SRay Chen .reserved_ram_size = 9216, 1336146ca69SRay Chen .board_addr = 0x435c00, 1346146ca69SRay Chen .refclk_hz = 40000000, 1356146ca69SRay Chen .uarttx_pin = 11, 13606e360acSBala Shanmugam .flags = ATH6KL_HW_FLAG_64BIT_RATES, 1376146ca69SRay Chen 1386146ca69SRay Chen .fw = { 1396146ca69SRay Chen .dir = AR6004_HW_1_2_FW_DIR, 1406146ca69SRay Chen .fw = AR6004_HW_1_2_FIRMWARE_FILE, 1416146ca69SRay Chen }, 1426146ca69SRay Chen .fw_board = AR6004_HW_1_2_BOARD_DATA_FILE, 1436146ca69SRay Chen .fw_default_board = AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE, 1446146ca69SRay Chen }, 145bf744f11SBala Shanmugam { 146bf744f11SBala Shanmugam .id = AR6004_HW_1_3_VERSION, 147bf744f11SBala Shanmugam .name = "ar6004 hw 1.3", 148bf744f11SBala Shanmugam .dataset_patch_addr = 0x437860, 149bf744f11SBala Shanmugam .app_load_addr = 0x1234, 150bf744f11SBala Shanmugam .board_ext_data_addr = 0x437000, 151bf744f11SBala Shanmugam .reserved_ram_size = 7168, 152bf744f11SBala Shanmugam .board_addr = 0x436400, 153bf744f11SBala Shanmugam .refclk_hz = 40000000, 154bf744f11SBala Shanmugam .uarttx_pin = 11, 155bf744f11SBala Shanmugam .flags = ATH6KL_HW_FLAG_64BIT_RATES, 156bf744f11SBala Shanmugam 157bf744f11SBala Shanmugam .fw = { 158bf744f11SBala Shanmugam .dir = AR6004_HW_1_3_FW_DIR, 159bf744f11SBala Shanmugam .fw = AR6004_HW_1_3_FIRMWARE_FILE, 160bf744f11SBala Shanmugam }, 161bf744f11SBala Shanmugam 162bf744f11SBala Shanmugam .fw_board = AR6004_HW_1_3_BOARD_DATA_FILE, 163bf744f11SBala Shanmugam .fw_default_board = AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE, 164bf744f11SBala Shanmugam }, 165856f4b31SKalle Valo }; 166856f4b31SKalle Valo 167bdcd8170SKalle Valo /* 168bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 169bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 170bdcd8170SKalle Valo * here. 171bdcd8170SKalle Valo */ 172bdcd8170SKalle Valo 173bdcd8170SKalle Valo /* 174bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 175bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 176bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 177bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 178bdcd8170SKalle Valo * Use value of zero to disable keepalive support 179bdcd8170SKalle Valo * Default: 60 seconds 180bdcd8170SKalle Valo */ 181bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 182bdcd8170SKalle Valo 183bdcd8170SKalle Valo /* 184bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 185bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 186bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 187bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 188bdcd8170SKalle Valo * it sends a new connect event 189bdcd8170SKalle Valo */ 190bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 191bdcd8170SKalle Valo 192bdcd8170SKalle Valo 193bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 194bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 195bdcd8170SKalle Valo { 196bdcd8170SKalle Valo struct sk_buff *skb; 197bdcd8170SKalle Valo u16 reserved; 198bdcd8170SKalle Valo 199bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 200bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 2011df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 202bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 203bdcd8170SKalle Valo 204bdcd8170SKalle Valo if (skb) 205bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 206bdcd8170SKalle Valo return skb; 207bdcd8170SKalle Valo } 208bdcd8170SKalle Valo 209e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 210bdcd8170SKalle Valo { 2113450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 2123450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 2133450334fSVasanthakumar Thiagarajan 2143450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 2153450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 2163450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 2173450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 2183450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 2193450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 2206f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 2218c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 2228c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 223f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 224bdcd8170SKalle Valo } 225bdcd8170SKalle Valo 226bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 227bdcd8170SKalle Valo { 228bdcd8170SKalle Valo u32 address, data; 229bdcd8170SKalle Valo struct host_app_area host_app_area; 230bdcd8170SKalle Valo 231bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 232bdcd8170SKalle Valo * instance in the host interest area */ 233bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 23431024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 235bdcd8170SKalle Valo 236addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 237bdcd8170SKalle Valo return -EIO; 238bdcd8170SKalle Valo 23931024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 240cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 241addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 242addb44beSKalle Valo sizeof(struct host_app_area))) 243bdcd8170SKalle Valo return -EIO; 244bdcd8170SKalle Valo 245bdcd8170SKalle Valo return 0; 246bdcd8170SKalle Valo } 247bdcd8170SKalle Valo 248bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 249bdcd8170SKalle Valo u8 ac, 250bdcd8170SKalle Valo enum htc_endpoint_id ep) 251bdcd8170SKalle Valo { 252bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 253bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 254bdcd8170SKalle Valo } 255bdcd8170SKalle Valo 256bdcd8170SKalle Valo /* connect to a service */ 257bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 258bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 259bdcd8170SKalle Valo char *desc) 260bdcd8170SKalle Valo { 261bdcd8170SKalle Valo int status; 262bdcd8170SKalle Valo struct htc_service_connect_resp response; 263bdcd8170SKalle Valo 264bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 265bdcd8170SKalle Valo 266ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 267bdcd8170SKalle Valo if (status) { 268bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 269bdcd8170SKalle Valo desc, status); 270bdcd8170SKalle Valo return status; 271bdcd8170SKalle Valo } 272bdcd8170SKalle Valo 273bdcd8170SKalle Valo switch (con_req->svc_id) { 274bdcd8170SKalle Valo case WMI_CONTROL_SVC: 275bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 276bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 277bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 278bdcd8170SKalle Valo break; 279bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 280bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 281bdcd8170SKalle Valo break; 282bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 283bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 284bdcd8170SKalle Valo break; 285bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 286bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 287bdcd8170SKalle Valo break; 288bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 289bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 290bdcd8170SKalle Valo break; 291bdcd8170SKalle Valo default: 292bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 293bdcd8170SKalle Valo return -EINVAL; 294bdcd8170SKalle Valo } 295bdcd8170SKalle Valo 296bdcd8170SKalle Valo return 0; 297bdcd8170SKalle Valo } 298bdcd8170SKalle Valo 299bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 300bdcd8170SKalle Valo { 301bdcd8170SKalle Valo struct htc_service_connect_req connect; 302bdcd8170SKalle Valo 303bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 304bdcd8170SKalle Valo 305bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 306900d6b3fSKalle Valo connect.ep_cb.tx_comp_multi = ath6kl_tx_complete; 307bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 308bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 309bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 310bdcd8170SKalle Valo 311bdcd8170SKalle Valo /* 312bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 313bdcd8170SKalle Valo * gets called. 314bdcd8170SKalle Valo */ 315bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 316bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 317bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 318bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 319bdcd8170SKalle Valo 320bdcd8170SKalle Valo /* connect to control service */ 321bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 322bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 323bdcd8170SKalle Valo return -EIO; 324bdcd8170SKalle Valo 325bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 326bdcd8170SKalle Valo 327bdcd8170SKalle Valo /* 328bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 329bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 330bdcd8170SKalle Valo * (802.3) frames on the send path. 331bdcd8170SKalle Valo */ 332bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 333bdcd8170SKalle Valo 334bdcd8170SKalle Valo /* 335bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 336bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 337bdcd8170SKalle Valo * packets. 338bdcd8170SKalle Valo */ 339bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 340bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 341bdcd8170SKalle Valo 342bdcd8170SKalle Valo /* 343bdcd8170SKalle Valo * For the remaining data services set the connection flag to 344bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 345bdcd8170SKalle Valo */ 346bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 347bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 348bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 349bdcd8170SKalle Valo 350bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 351bdcd8170SKalle Valo 352bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 353bdcd8170SKalle Valo return -EIO; 354bdcd8170SKalle Valo 355bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 356bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 357bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 358bdcd8170SKalle Valo return -EIO; 359bdcd8170SKalle Valo 360bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 361bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 362bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 363bdcd8170SKalle Valo return -EIO; 364bdcd8170SKalle Valo 365bdcd8170SKalle Valo /* 366bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 367bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 368bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 369bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 370bdcd8170SKalle Valo * mailboxes. 371bdcd8170SKalle Valo */ 372bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 373bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 374bdcd8170SKalle Valo return -EIO; 375bdcd8170SKalle Valo 376bdcd8170SKalle Valo return 0; 377bdcd8170SKalle Valo } 378bdcd8170SKalle Valo 379e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 380bdcd8170SKalle Valo { 381e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3823450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3836f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 384f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 385bdcd8170SKalle Valo } 386bdcd8170SKalle Valo 387bdcd8170SKalle Valo /* 388bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 389bdcd8170SKalle Valo * target is in the BMI phase. 390bdcd8170SKalle Valo */ 391bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 392bdcd8170SKalle Valo u8 htc_ctrl_buf) 393bdcd8170SKalle Valo { 394bdcd8170SKalle Valo int status; 395bdcd8170SKalle Valo u32 blk_size; 396bdcd8170SKalle Valo 397bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 398bdcd8170SKalle Valo 399bdcd8170SKalle Valo if (htc_ctrl_buf) 400bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 401bdcd8170SKalle Valo 402bdcd8170SKalle Valo /* set the host interest area for the block size */ 40324fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size); 404bdcd8170SKalle Valo if (status) { 405bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 406bdcd8170SKalle Valo goto out; 407bdcd8170SKalle Valo } 408bdcd8170SKalle Valo 409bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 410bdcd8170SKalle Valo blk_size, 411bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 412bdcd8170SKalle Valo 413bdcd8170SKalle Valo if (mbox_isr_yield_val) { 414bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 41524fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit, 41624fc32b3SKalle Valo mbox_isr_yield_val); 417bdcd8170SKalle Valo if (status) { 418bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 419bdcd8170SKalle Valo goto out; 420bdcd8170SKalle Valo } 421bdcd8170SKalle Valo } 422bdcd8170SKalle Valo 423bdcd8170SKalle Valo out: 424bdcd8170SKalle Valo return status; 425bdcd8170SKalle Valo } 426bdcd8170SKalle Valo 4270ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 428bdcd8170SKalle Valo { 4294dea08e0SJouni Malinen int ret; 430bdcd8170SKalle Valo 431bdcd8170SKalle Valo /* 432bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 433bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 434bdcd8170SKalle Valo * RxMetaVersion to 2. 435bdcd8170SKalle Valo */ 4361ca4d0b6SKalle Valo ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 4371ca4d0b6SKalle Valo ar->rx_meta_ver, 0, 0); 4381ca4d0b6SKalle Valo if (ret) { 4391ca4d0b6SKalle Valo ath6kl_err("unable to set the rx frame format: %d\n", ret); 4401ca4d0b6SKalle Valo return ret; 441bdcd8170SKalle Valo } 442bdcd8170SKalle Valo 4431ca4d0b6SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) { 4441ca4d0b6SKalle Valo ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 44505aab177SKalle Valo IGNORE_PS_FAIL_DURING_SCAN); 4461ca4d0b6SKalle Valo if (ret) { 4471ca4d0b6SKalle Valo ath6kl_err("unable to set power save fail event policy: %d\n", 4481ca4d0b6SKalle Valo ret); 4491ca4d0b6SKalle Valo return ret; 4501ca4d0b6SKalle Valo } 451bdcd8170SKalle Valo } 452bdcd8170SKalle Valo 4531ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) { 4541ca4d0b6SKalle Valo ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 45505aab177SKalle Valo WMI_FOLLOW_BARKER_IN_ERP); 4561ca4d0b6SKalle Valo if (ret) { 4571ca4d0b6SKalle Valo ath6kl_err("unable to set barker preamble policy: %d\n", 4581ca4d0b6SKalle Valo ret); 4591ca4d0b6SKalle Valo return ret; 4601ca4d0b6SKalle Valo } 461bdcd8170SKalle Valo } 462bdcd8170SKalle Valo 4631ca4d0b6SKalle Valo ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 4641ca4d0b6SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL); 4651ca4d0b6SKalle Valo if (ret) { 4661ca4d0b6SKalle Valo ath6kl_err("unable to set keep alive interval: %d\n", ret); 4671ca4d0b6SKalle Valo return ret; 468bdcd8170SKalle Valo } 469bdcd8170SKalle Valo 4701ca4d0b6SKalle Valo ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 4711ca4d0b6SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT); 4721ca4d0b6SKalle Valo if (ret) { 4731ca4d0b6SKalle Valo ath6kl_err("unable to set disconnect timeout: %d\n", ret); 4741ca4d0b6SKalle Valo return ret; 475bdcd8170SKalle Valo } 476bdcd8170SKalle Valo 4771ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) { 4781ca4d0b6SKalle Valo ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED); 4791ca4d0b6SKalle Valo if (ret) { 4801ca4d0b6SKalle Valo ath6kl_err("unable to set txop bursting: %d\n", ret); 4811ca4d0b6SKalle Valo return ret; 4821ca4d0b6SKalle Valo } 483bdcd8170SKalle Valo } 484bdcd8170SKalle Valo 485b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4860ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4876bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4884dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4894dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4904dea08e0SJouni Malinen if (ret) { 491cdeb8602SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, 492cdeb8602SKalle Valo "failed to request P2P capabilities (%d) - assuming P2P not supported\n", 493cdeb8602SKalle Valo ret); 4943db1cd5cSRusty Russell ar->p2p = false; 4956bbc7c35SJouni Malinen } 4966bbc7c35SJouni Malinen } 4976bbc7c35SJouni Malinen 498b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4996bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 5000ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 5016bbc7c35SJouni Malinen if (ret) { 502cdeb8602SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, 503cdeb8602SKalle Valo "failed to enable Probe Request reporting (%d)\n", 504cdeb8602SKalle Valo ret); 5056bbc7c35SJouni Malinen } 5064dea08e0SJouni Malinen } 5074dea08e0SJouni Malinen 5081ca4d0b6SKalle Valo return ret; 509bdcd8170SKalle Valo } 510bdcd8170SKalle Valo 511bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 512bdcd8170SKalle Valo { 513bdcd8170SKalle Valo u32 param, ram_reserved_size; 5143226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 51539586bf2SRyan Hsu int i, status; 516bdcd8170SKalle Valo 517f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 51824fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) { 519a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 520a10e2f2fSVasanthakumar Thiagarajan return -EIO; 521a10e2f2fSVasanthakumar Thiagarajan } 522a10e2f2fSVasanthakumar Thiagarajan 5237b85832dSVasanthakumar Thiagarajan /* 5247b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 5257b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 5267b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 5277b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 5287b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 5297b85832dSVasanthakumar Thiagarajan * configured for now. 5307b85832dSVasanthakumar Thiagarajan */ 531dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 532bdcd8170SKalle Valo 53371f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 5347b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 5357b85832dSVasanthakumar Thiagarajan 5367b85832dSVasanthakumar Thiagarajan /* 5371e8d13b0SVasanthakumar Thiagarajan * Submodes when fw does not support dynamic interface 5381e8d13b0SVasanthakumar Thiagarajan * switching: 5393226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 5407b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 5417b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 5421e8d13b0SVasanthakumar Thiagarajan * Otherwise, All the interface are initialized to p2p dev. 5437b85832dSVasanthakumar Thiagarajan */ 5443226f68aSVasanthakumar Thiagarajan 5451e8d13b0SVasanthakumar Thiagarajan if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 5461e8d13b0SVasanthakumar Thiagarajan ar->fw_capabilities)) { 5471e8d13b0SVasanthakumar Thiagarajan for (i = 0; i < ar->vif_max; i++) 5481e8d13b0SVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5491e8d13b0SVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5501e8d13b0SVasanthakumar Thiagarajan } else { 5513226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 5523226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 5533226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5543226f68aSVasanthakumar Thiagarajan 55571f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 5563226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5573226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5587b85832dSVasanthakumar Thiagarajan 559b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5607b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5611e8d13b0SVasanthakumar Thiagarajan } 5627b85832dSVasanthakumar Thiagarajan 56324fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest, 56424fc32b3SKalle Valo HTC_PROTOCOL_VERSION) != 0) { 565bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 566bdcd8170SKalle Valo return -EIO; 567bdcd8170SKalle Valo } 568bdcd8170SKalle Valo 569bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 570bdcd8170SKalle Valo param = 0; 571bdcd8170SKalle Valo 57280fb2686SKalle Valo if (ath6kl_bmi_read_hi32(ar, hi_option_flag, ¶m) != 0) { 573bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 574bdcd8170SKalle Valo return -EIO; 575bdcd8170SKalle Valo } 576bdcd8170SKalle Valo 57771f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5787b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5797b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5807b85832dSVasanthakumar Thiagarajan 581bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 582bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 583bdcd8170SKalle Valo 58424fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) { 585bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 586bdcd8170SKalle Valo return -EIO; 587bdcd8170SKalle Valo } 588bdcd8170SKalle Valo 589bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 590bdcd8170SKalle Valo 591bdcd8170SKalle Valo /* 592bdcd8170SKalle Valo * Hardcode the address use for the extended board data 593bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 594bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 595bdcd8170SKalle Valo * at init time, we have to workaround this from host. 596bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 597bdcd8170SKalle Valo * but possible in theory. 598bdcd8170SKalle Valo */ 599bdcd8170SKalle Valo 6006b42d308SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) { 601991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 602991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 603bdcd8170SKalle Valo 60424fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) { 605bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 606bdcd8170SKalle Valo return -EIO; 607bdcd8170SKalle Valo } 608991b27eaSKalle Valo 60924fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 61024fc32b3SKalle Valo ram_reserved_size) != 0) { 611bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 612bdcd8170SKalle Valo return -EIO; 613bdcd8170SKalle Valo } 6146b42d308SKalle Valo } 615bdcd8170SKalle Valo 616bdcd8170SKalle Valo /* set the block size for the target */ 617bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 618bdcd8170SKalle Valo /* use default number of control buffers */ 619bdcd8170SKalle Valo return -EIO; 620bdcd8170SKalle Valo 62139586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 62224fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin, 62324fc32b3SKalle Valo ar->hw.uarttx_pin); 62439586bf2SRyan Hsu if (status) 62539586bf2SRyan Hsu return status; 62639586bf2SRyan Hsu 62739586bf2SRyan Hsu /* Configure target refclk_hz */ 62824fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz); 62939586bf2SRyan Hsu if (status) 63039586bf2SRyan Hsu return status; 63139586bf2SRyan Hsu 632bdcd8170SKalle Valo return 0; 633bdcd8170SKalle Valo } 634bdcd8170SKalle Valo 635bdcd8170SKalle Valo /* firmware upload */ 636bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 637bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 638bdcd8170SKalle Valo { 639bdcd8170SKalle Valo const struct firmware *fw_entry; 640bdcd8170SKalle Valo int ret; 641bdcd8170SKalle Valo 642bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 643bdcd8170SKalle Valo if (ret) 644bdcd8170SKalle Valo return ret; 645bdcd8170SKalle Valo 646bdcd8170SKalle Valo *fw_len = fw_entry->size; 647bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 648bdcd8170SKalle Valo 649bdcd8170SKalle Valo if (*fw == NULL) 650bdcd8170SKalle Valo ret = -ENOMEM; 651bdcd8170SKalle Valo 652bdcd8170SKalle Valo release_firmware(fw_entry); 653bdcd8170SKalle Valo 654bdcd8170SKalle Valo return ret; 655bdcd8170SKalle Valo } 656bdcd8170SKalle Valo 65792ecbff4SSam Leffler #ifdef CONFIG_OF 65892ecbff4SSam Leffler /* 65992ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 66092ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 66192ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 66292ecbff4SSam Leffler * appropriate board-specific file. 66392ecbff4SSam Leffler */ 66492ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 66592ecbff4SSam Leffler { 66692ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 66792ecbff4SSam Leffler struct device_node *node; 66892ecbff4SSam Leffler char board_filename[64]; 66992ecbff4SSam Leffler const char *board_id; 67092ecbff4SSam Leffler int ret; 67192ecbff4SSam Leffler 67292ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 67392ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 67492ecbff4SSam Leffler if (board_id == NULL) { 67592ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 67692ecbff4SSam Leffler board_id_prop, node->name); 67792ecbff4SSam Leffler continue; 67892ecbff4SSam Leffler } 67992ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 680c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 68192ecbff4SSam Leffler 68292ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 68392ecbff4SSam Leffler &ar->fw_board_len); 68492ecbff4SSam Leffler if (ret) { 68592ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 68692ecbff4SSam Leffler board_filename, ret); 68792ecbff4SSam Leffler continue; 68892ecbff4SSam Leffler } 68992ecbff4SSam Leffler return true; 69092ecbff4SSam Leffler } 69192ecbff4SSam Leffler return false; 69292ecbff4SSam Leffler } 69392ecbff4SSam Leffler #else 69492ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 69592ecbff4SSam Leffler { 69692ecbff4SSam Leffler return false; 69792ecbff4SSam Leffler } 69892ecbff4SSam Leffler #endif /* CONFIG_OF */ 69992ecbff4SSam Leffler 700bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 701bdcd8170SKalle Valo { 702bdcd8170SKalle Valo const char *filename; 703bdcd8170SKalle Valo int ret; 704bdcd8170SKalle Valo 705772c31eeSKalle Valo if (ar->fw_board != NULL) 706772c31eeSKalle Valo return 0; 707772c31eeSKalle Valo 708d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 709d1a9421dSKalle Valo return -EINVAL; 710d1a9421dSKalle Valo 711d1a9421dSKalle Valo filename = ar->hw.fw_board; 712bdcd8170SKalle Valo 713bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 714bdcd8170SKalle Valo &ar->fw_board_len); 715bdcd8170SKalle Valo if (ret == 0) { 716bdcd8170SKalle Valo /* managed to get proper board file */ 717bdcd8170SKalle Valo return 0; 718bdcd8170SKalle Valo } 719bdcd8170SKalle Valo 72092ecbff4SSam Leffler if (check_device_tree(ar)) { 72192ecbff4SSam Leffler /* got board file from device tree */ 72292ecbff4SSam Leffler return 0; 72392ecbff4SSam Leffler } 72492ecbff4SSam Leffler 725bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 726bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 727bdcd8170SKalle Valo filename, ret); 728bdcd8170SKalle Valo 729d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 730bdcd8170SKalle Valo 731bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 732bdcd8170SKalle Valo &ar->fw_board_len); 733bdcd8170SKalle Valo if (ret) { 734bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 735bdcd8170SKalle Valo filename, ret); 736bdcd8170SKalle Valo return ret; 737bdcd8170SKalle Valo } 738bdcd8170SKalle Valo 739bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 740bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 741bdcd8170SKalle Valo 742bdcd8170SKalle Valo return 0; 743bdcd8170SKalle Valo } 744bdcd8170SKalle Valo 745772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 746772c31eeSKalle Valo { 747c0038972SKalle Valo char filename[100]; 748772c31eeSKalle Valo int ret; 749772c31eeSKalle Valo 750772c31eeSKalle Valo if (ar->fw_otp != NULL) 751772c31eeSKalle Valo return 0; 752772c31eeSKalle Valo 753c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 754d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 755d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 756772c31eeSKalle Valo return 0; 757772c31eeSKalle Valo } 758772c31eeSKalle Valo 759c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 760c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 761d1a9421dSKalle Valo 762772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 763772c31eeSKalle Valo &ar->fw_otp_len); 764772c31eeSKalle Valo if (ret) { 765772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 766772c31eeSKalle Valo filename, ret); 767772c31eeSKalle Valo return ret; 768772c31eeSKalle Valo } 769772c31eeSKalle Valo 770772c31eeSKalle Valo return 0; 771772c31eeSKalle Valo } 772772c31eeSKalle Valo 7735f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar) 774772c31eeSKalle Valo { 775c0038972SKalle Valo char filename[100]; 776772c31eeSKalle Valo int ret; 777772c31eeSKalle Valo 7785f1127ffSKalle Valo if (ar->testmode == 0) 779772c31eeSKalle Valo return 0; 780772c31eeSKalle Valo 7815f1127ffSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode); 7825f1127ffSKalle Valo 7835f1127ffSKalle Valo if (ar->testmode == 2) { 784cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) { 785cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n"); 786cd23c1c9SAlex Yang return -EOPNOTSUPP; 787cd23c1c9SAlex Yang } 788cd23c1c9SAlex Yang 789cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 790cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf); 791cd23c1c9SAlex Yang } else { 792c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 793cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n"); 794772c31eeSKalle Valo return -EOPNOTSUPP; 795772c31eeSKalle Valo } 796772c31eeSKalle Valo 797c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 798c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 799cd23c1c9SAlex Yang } 8005f1127ffSKalle Valo 801772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 802772c31eeSKalle Valo 8035f1127ffSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 8045f1127ffSKalle Valo if (ret) { 8055f1127ffSKalle Valo ath6kl_err("Failed to get testmode %d firmware file %s: %d\n", 8065f1127ffSKalle Valo ar->testmode, filename, ret); 8075f1127ffSKalle Valo return ret; 808772c31eeSKalle Valo } 809772c31eeSKalle Valo 8105f1127ffSKalle Valo return 0; 8115f1127ffSKalle Valo } 8125f1127ffSKalle Valo 8135f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 8145f1127ffSKalle Valo { 8155f1127ffSKalle Valo char filename[100]; 8165f1127ffSKalle Valo int ret; 8175f1127ffSKalle Valo 8185f1127ffSKalle Valo if (ar->fw != NULL) 8195f1127ffSKalle Valo return 0; 8205f1127ffSKalle Valo 821c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 822c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 823d1a9421dSKalle Valo return -EINVAL; 824d1a9421dSKalle Valo 825c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 826c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 827772c31eeSKalle Valo 828772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 829772c31eeSKalle Valo if (ret) { 830772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 831772c31eeSKalle Valo filename, ret); 832772c31eeSKalle Valo return ret; 833772c31eeSKalle Valo } 834772c31eeSKalle Valo 835772c31eeSKalle Valo return 0; 836772c31eeSKalle Valo } 837772c31eeSKalle Valo 838772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 839772c31eeSKalle Valo { 840c0038972SKalle Valo char filename[100]; 841772c31eeSKalle Valo int ret; 842772c31eeSKalle Valo 843d1a9421dSKalle Valo if (ar->fw_patch != NULL) 844772c31eeSKalle Valo return 0; 845772c31eeSKalle Valo 846c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 847d1a9421dSKalle Valo return 0; 848d1a9421dSKalle Valo 849c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 850c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 851d1a9421dSKalle Valo 852772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 853772c31eeSKalle Valo &ar->fw_patch_len); 854772c31eeSKalle Valo if (ret) { 855772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 856772c31eeSKalle Valo filename, ret); 857772c31eeSKalle Valo return ret; 858772c31eeSKalle Valo } 859772c31eeSKalle Valo 860772c31eeSKalle Valo return 0; 861772c31eeSKalle Valo } 862772c31eeSKalle Valo 863cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar) 864cd23c1c9SAlex Yang { 865cd23c1c9SAlex Yang char filename[100]; 866cd23c1c9SAlex Yang int ret; 867cd23c1c9SAlex Yang 8685f1127ffSKalle Valo if (ar->testmode != 2) 869cd23c1c9SAlex Yang return 0; 870cd23c1c9SAlex Yang 871cd23c1c9SAlex Yang if (ar->fw_testscript != NULL) 872cd23c1c9SAlex Yang return 0; 873cd23c1c9SAlex Yang 874cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL) 875cd23c1c9SAlex Yang return 0; 876cd23c1c9SAlex Yang 877cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 878cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript); 879cd23c1c9SAlex Yang 880cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 881cd23c1c9SAlex Yang &ar->fw_testscript_len); 882cd23c1c9SAlex Yang if (ret) { 883cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n", 884cd23c1c9SAlex Yang filename, ret); 885cd23c1c9SAlex Yang return ret; 886cd23c1c9SAlex Yang } 887cd23c1c9SAlex Yang 888cd23c1c9SAlex Yang return 0; 889cd23c1c9SAlex Yang } 890cd23c1c9SAlex Yang 89150d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 892772c31eeSKalle Valo { 893772c31eeSKalle Valo int ret; 894772c31eeSKalle Valo 895772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 896772c31eeSKalle Valo if (ret) 897772c31eeSKalle Valo return ret; 898772c31eeSKalle Valo 899772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 900772c31eeSKalle Valo if (ret) 901772c31eeSKalle Valo return ret; 902772c31eeSKalle Valo 903772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 904772c31eeSKalle Valo if (ret) 905772c31eeSKalle Valo return ret; 906772c31eeSKalle Valo 907cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar); 908cd23c1c9SAlex Yang if (ret) 909cd23c1c9SAlex Yang return ret; 910cd23c1c9SAlex Yang 911772c31eeSKalle Valo return 0; 912772c31eeSKalle Valo } 913bdcd8170SKalle Valo 91465a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 91550d41234SKalle Valo { 91650d41234SKalle Valo size_t magic_len, len, ie_len; 91750d41234SKalle Valo const struct firmware *fw; 91850d41234SKalle Valo struct ath6kl_fw_ie *hdr; 919c0038972SKalle Valo char filename[100]; 92050d41234SKalle Valo const u8 *data; 92197e0496dSKalle Valo int ret, ie_id, i, index, bit; 9228a137480SKalle Valo __le32 *val; 92350d41234SKalle Valo 92465a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 92550d41234SKalle Valo 92650d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 92750d41234SKalle Valo if (ret) 92850d41234SKalle Valo return ret; 92950d41234SKalle Valo 93050d41234SKalle Valo data = fw->data; 93150d41234SKalle Valo len = fw->size; 93250d41234SKalle Valo 93350d41234SKalle Valo /* magic also includes the null byte, check that as well */ 93450d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 93550d41234SKalle Valo 93650d41234SKalle Valo if (len < magic_len) { 93750d41234SKalle Valo ret = -EINVAL; 93850d41234SKalle Valo goto out; 93950d41234SKalle Valo } 94050d41234SKalle Valo 94150d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 94250d41234SKalle Valo ret = -EINVAL; 94350d41234SKalle Valo goto out; 94450d41234SKalle Valo } 94550d41234SKalle Valo 94650d41234SKalle Valo len -= magic_len; 94750d41234SKalle Valo data += magic_len; 94850d41234SKalle Valo 94950d41234SKalle Valo /* loop elements */ 95050d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 95150d41234SKalle Valo /* hdr is unaligned! */ 95250d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 95350d41234SKalle Valo 95450d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 95550d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 95650d41234SKalle Valo 95750d41234SKalle Valo len -= sizeof(*hdr); 95850d41234SKalle Valo data += sizeof(*hdr); 95950d41234SKalle Valo 96050d41234SKalle Valo if (len < ie_len) { 96150d41234SKalle Valo ret = -EINVAL; 96250d41234SKalle Valo goto out; 96350d41234SKalle Valo } 96450d41234SKalle Valo 96550d41234SKalle Valo switch (ie_id) { 966b5b6f6a9SNaveen Singh case ATH6KL_FW_IE_FW_VERSION: 967b5b6f6a9SNaveen Singh strlcpy(ar->wiphy->fw_version, data, 968b5b6f6a9SNaveen Singh sizeof(ar->wiphy->fw_version)); 969b5b6f6a9SNaveen Singh 970b5b6f6a9SNaveen Singh ath6kl_dbg(ATH6KL_DBG_BOOT, 971b5b6f6a9SNaveen Singh "found fw version %s\n", 972b5b6f6a9SNaveen Singh ar->wiphy->fw_version); 973b5b6f6a9SNaveen Singh break; 97450d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 975ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9766bc36431SKalle Valo ie_len); 9776bc36431SKalle Valo 97850d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 97950d41234SKalle Valo 98050d41234SKalle Valo if (ar->fw_otp == NULL) { 98150d41234SKalle Valo ret = -ENOMEM; 98250d41234SKalle Valo goto out; 98350d41234SKalle Valo } 98450d41234SKalle Valo 98550d41234SKalle Valo ar->fw_otp_len = ie_len; 98650d41234SKalle Valo break; 98750d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 988ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9896bc36431SKalle Valo ie_len); 9906bc36431SKalle Valo 9915f1127ffSKalle Valo /* in testmode we already might have a fw file */ 9925f1127ffSKalle Valo if (ar->fw != NULL) 9935f1127ffSKalle Valo break; 9945f1127ffSKalle Valo 9958437754cSVivek Natarajan ar->fw = vmalloc(ie_len); 99650d41234SKalle Valo 99750d41234SKalle Valo if (ar->fw == NULL) { 99850d41234SKalle Valo ret = -ENOMEM; 99950d41234SKalle Valo goto out; 100050d41234SKalle Valo } 100150d41234SKalle Valo 10028437754cSVivek Natarajan memcpy(ar->fw, data, ie_len); 100350d41234SKalle Valo ar->fw_len = ie_len; 100450d41234SKalle Valo break; 100550d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 1006ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 10076bc36431SKalle Valo ie_len); 10086bc36431SKalle Valo 100950d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 101050d41234SKalle Valo 101150d41234SKalle Valo if (ar->fw_patch == NULL) { 101250d41234SKalle Valo ret = -ENOMEM; 101350d41234SKalle Valo goto out; 101450d41234SKalle Valo } 101550d41234SKalle Valo 101650d41234SKalle Valo ar->fw_patch_len = ie_len; 101750d41234SKalle Valo break; 10188a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 10198a137480SKalle Valo val = (__le32 *) data; 10208a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 10216bc36431SKalle Valo 10226bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 10236bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 10246bc36431SKalle Valo ar->hw.reserved_ram_size); 10258a137480SKalle Valo break; 102697e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 10276bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1028ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 10296bc36431SKalle Valo ie_len); 10306bc36431SKalle Valo 103197e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 1032277d90f4SKalle Valo index = i / 8; 103397e0496dSKalle Valo bit = i % 8; 103497e0496dSKalle Valo 1035c85251f8SThomas Pedersen if (index == ie_len) 1036c85251f8SThomas Pedersen break; 1037c85251f8SThomas Pedersen 103897e0496dSKalle Valo if (data[index] & (1 << bit)) 103997e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 104097e0496dSKalle Valo } 10416bc36431SKalle Valo 10426bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 10436bc36431SKalle Valo ar->fw_capabilities, 10446bc36431SKalle Valo sizeof(ar->fw_capabilities)); 104597e0496dSKalle Valo break; 10461b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 10471b4304daSKalle Valo if (ie_len != sizeof(*val)) 10481b4304daSKalle Valo break; 10491b4304daSKalle Valo 10501b4304daSKalle Valo val = (__le32 *) data; 10511b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 10526bc36431SKalle Valo 10536bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 105403ef0250SKalle Valo "found patch address ie 0x%x\n", 10556bc36431SKalle Valo ar->hw.dataset_patch_addr); 10561b4304daSKalle Valo break; 105703ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 105803ef0250SKalle Valo if (ie_len != sizeof(*val)) 105903ef0250SKalle Valo break; 106003ef0250SKalle Valo 106103ef0250SKalle Valo val = (__le32 *) data; 106203ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 106303ef0250SKalle Valo 106403ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 106503ef0250SKalle Valo "found board address ie 0x%x\n", 106603ef0250SKalle Valo ar->hw.board_addr); 106703ef0250SKalle Valo break; 1068368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 1069368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 1070368b1b0fSKalle Valo break; 1071368b1b0fSKalle Valo 1072368b1b0fSKalle Valo val = (__le32 *) data; 1073368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 1074368b1b0fSKalle Valo ATH6KL_VIF_MAX); 1075368b1b0fSKalle Valo 1076f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 1077f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1078f143379dSVasanthakumar Thiagarajan 1079368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1080368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1081368b1b0fSKalle Valo break; 108250d41234SKalle Valo default: 10836bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 108450d41234SKalle Valo le32_to_cpup(&hdr->id)); 108550d41234SKalle Valo break; 108650d41234SKalle Valo } 108750d41234SKalle Valo 108850d41234SKalle Valo len -= ie_len; 108950d41234SKalle Valo data += ie_len; 109050d41234SKalle Valo }; 109150d41234SKalle Valo 109250d41234SKalle Valo ret = 0; 109350d41234SKalle Valo out: 109450d41234SKalle Valo release_firmware(fw); 109550d41234SKalle Valo 109650d41234SKalle Valo return ret; 109750d41234SKalle Valo } 109850d41234SKalle Valo 109945eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar) 110050d41234SKalle Valo { 110150d41234SKalle Valo int ret; 110250d41234SKalle Valo 110350d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 110450d41234SKalle Valo if (ret) 110550d41234SKalle Valo return ret; 110650d41234SKalle Valo 11075f1127ffSKalle Valo ret = ath6kl_fetch_testmode_file(ar); 11085f1127ffSKalle Valo if (ret) 11095f1127ffSKalle Valo return ret; 11105f1127ffSKalle Valo 1111b1f47e3aSThomas Pedersen ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API4_FILE); 1112b1f47e3aSThomas Pedersen if (ret == 0) { 1113b1f47e3aSThomas Pedersen ar->fw_api = 4; 1114b1f47e3aSThomas Pedersen goto out; 1115b1f47e3aSThomas Pedersen } 1116b1f47e3aSThomas Pedersen 111765a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 11186bc36431SKalle Valo if (ret == 0) { 111965a8b4ccSKalle Valo ar->fw_api = 3; 112065a8b4ccSKalle Valo goto out; 112165a8b4ccSKalle Valo } 112265a8b4ccSKalle Valo 112365a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 112465a8b4ccSKalle Valo if (ret == 0) { 112565a8b4ccSKalle Valo ar->fw_api = 2; 112665a8b4ccSKalle Valo goto out; 11276bc36431SKalle Valo } 112850d41234SKalle Valo 112950d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 113050d41234SKalle Valo if (ret) 113150d41234SKalle Valo return ret; 113250d41234SKalle Valo 113365a8b4ccSKalle Valo ar->fw_api = 1; 113465a8b4ccSKalle Valo 113565a8b4ccSKalle Valo out: 113665a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 11376bc36431SKalle Valo 113850d41234SKalle Valo return 0; 113950d41234SKalle Valo } 114050d41234SKalle Valo 1141bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1142bdcd8170SKalle Valo { 1143bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 114431024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1145bdcd8170SKalle Valo int ret; 1146bdcd8170SKalle Valo 1147772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1148772c31eeSKalle Valo return -ENOENT; 1149bdcd8170SKalle Valo 115031024d99SKevin Fang /* 115131024d99SKevin Fang * Determine where in Target RAM to write Board Data. 115231024d99SKevin Fang * For AR6004, host determine Target RAM address for 115331024d99SKevin Fang * writing board data. 115431024d99SKevin Fang */ 11550d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 1156b0fc7c1aSKalle Valo board_address = ar->hw.board_addr; 115724fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data, 1158b0fc7c1aSKalle Valo board_address); 115931024d99SKevin Fang } else { 116080fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address); 116131024d99SKevin Fang } 116231024d99SKevin Fang 1163bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 116480fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address); 1165bdcd8170SKalle Valo 116650e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 116750e2740bSKalle Valo board_ext_address == 0) { 1168bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1169bdcd8170SKalle Valo return -EINVAL; 1170bdcd8170SKalle Valo } 1171bdcd8170SKalle Valo 117231024d99SKevin Fang switch (ar->target_type) { 117331024d99SKevin Fang case TARGET_TYPE_AR6003: 117431024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 117531024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 1176fb1ac2efSPrasanna Kumar if (ar->fw_board_len > (board_data_size + board_ext_data_size)) 1177fb1ac2efSPrasanna Kumar board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2; 117831024d99SKevin Fang break; 117931024d99SKevin Fang case TARGET_TYPE_AR6004: 118031024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 118131024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 118231024d99SKevin Fang break; 118331024d99SKevin Fang default: 118431024d99SKevin Fang WARN_ON(1); 118531024d99SKevin Fang return -EINVAL; 118631024d99SKevin Fang break; 118731024d99SKevin Fang } 118831024d99SKevin Fang 118950e2740bSKalle Valo if (board_ext_address && 119050e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 119131024d99SKevin Fang 1192bdcd8170SKalle Valo /* write extended board data */ 11936bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11946bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11956bc36431SKalle Valo board_ext_address, board_ext_data_size); 11966bc36431SKalle Valo 1197bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 119831024d99SKevin Fang ar->fw_board + board_data_size, 119931024d99SKevin Fang board_ext_data_size); 1200bdcd8170SKalle Valo if (ret) { 1201bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1202bdcd8170SKalle Valo ret); 1203bdcd8170SKalle Valo return ret; 1204bdcd8170SKalle Valo } 1205bdcd8170SKalle Valo 1206bdcd8170SKalle Valo /* record that extended board data is initialized */ 120731024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 120831024d99SKevin Fang 120924fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param); 1210bdcd8170SKalle Valo } 1211bdcd8170SKalle Valo 121231024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1213bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1214bdcd8170SKalle Valo ret = -EINVAL; 1215bdcd8170SKalle Valo return ret; 1216bdcd8170SKalle Valo } 1217bdcd8170SKalle Valo 12186bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 12196bc36431SKalle Valo board_address, board_data_size); 12206bc36431SKalle Valo 1221bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 122231024d99SKevin Fang board_data_size); 1223bdcd8170SKalle Valo 1224bdcd8170SKalle Valo if (ret) { 1225bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1226bdcd8170SKalle Valo return ret; 1227bdcd8170SKalle Valo } 1228bdcd8170SKalle Valo 1229bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 123024fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1); 1231bdcd8170SKalle Valo 1232bdcd8170SKalle Valo return ret; 1233bdcd8170SKalle Valo } 1234bdcd8170SKalle Valo 1235bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1236bdcd8170SKalle Valo { 1237bdcd8170SKalle Valo u32 address, param; 1238bef26a7fSKalle Valo bool from_hw = false; 1239bdcd8170SKalle Valo int ret; 1240bdcd8170SKalle Valo 124150e2740bSKalle Valo if (ar->fw_otp == NULL) 124250e2740bSKalle Valo return 0; 1243bdcd8170SKalle Valo 1244a01ac414SKalle Valo address = ar->hw.app_load_addr; 1245bdcd8170SKalle Valo 1246ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 12476bc36431SKalle Valo ar->fw_otp_len); 12486bc36431SKalle Valo 1249bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1250bdcd8170SKalle Valo ar->fw_otp_len); 1251bdcd8170SKalle Valo if (ret) { 1252bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1253bdcd8170SKalle Valo return ret; 1254bdcd8170SKalle Valo } 1255bdcd8170SKalle Valo 1256639d0b89SKalle Valo /* read firmware start address */ 125780fb2686SKalle Valo ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address); 1258639d0b89SKalle Valo 1259639d0b89SKalle Valo if (ret) { 1260639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1261639d0b89SKalle Valo return ret; 1262639d0b89SKalle Valo } 1263639d0b89SKalle Valo 1264bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1265639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1266bef26a7fSKalle Valo from_hw = true; 1267bef26a7fSKalle Valo } 1268639d0b89SKalle Valo 1269bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1270bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 12716bc36431SKalle Valo ar->hw.app_start_override_addr); 12726bc36431SKalle Valo 1273bdcd8170SKalle Valo /* execute the OTP code */ 1274bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1275bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1276bdcd8170SKalle Valo param = 0; 1277bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1278bdcd8170SKalle Valo 1279bdcd8170SKalle Valo return ret; 1280bdcd8170SKalle Valo } 1281bdcd8170SKalle Valo 1282bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1283bdcd8170SKalle Valo { 1284bdcd8170SKalle Valo u32 address; 1285bdcd8170SKalle Valo int ret; 1286bdcd8170SKalle Valo 1287772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 128850e2740bSKalle Valo return 0; 1289bdcd8170SKalle Valo 1290a01ac414SKalle Valo address = ar->hw.app_load_addr; 1291bdcd8170SKalle Valo 1292ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12936bc36431SKalle Valo address, ar->fw_len); 12946bc36431SKalle Valo 1295bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1296bdcd8170SKalle Valo 1297bdcd8170SKalle Valo if (ret) { 1298bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1299bdcd8170SKalle Valo return ret; 1300bdcd8170SKalle Valo } 1301bdcd8170SKalle Valo 130231024d99SKevin Fang /* 130331024d99SKevin Fang * Set starting address for firmware 130431024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 130531024d99SKevin Fang */ 130631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1307a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1308bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 130931024d99SKevin Fang } 1310bdcd8170SKalle Valo return ret; 1311bdcd8170SKalle Valo } 1312bdcd8170SKalle Valo 1313bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1314bdcd8170SKalle Valo { 131524fc32b3SKalle Valo u32 address; 1316bdcd8170SKalle Valo int ret; 1317bdcd8170SKalle Valo 131850e2740bSKalle Valo if (ar->fw_patch == NULL) 131950e2740bSKalle Valo return 0; 1320bdcd8170SKalle Valo 1321a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1322bdcd8170SKalle Valo 1323ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 13246bc36431SKalle Valo address, ar->fw_patch_len); 13256bc36431SKalle Valo 1326bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1327bdcd8170SKalle Valo if (ret) { 1328bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1329bdcd8170SKalle Valo return ret; 1330bdcd8170SKalle Valo } 1331bdcd8170SKalle Valo 133224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address); 1333bdcd8170SKalle Valo 1334bdcd8170SKalle Valo return 0; 1335bdcd8170SKalle Valo } 1336bdcd8170SKalle Valo 1337cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar) 1338cd23c1c9SAlex Yang { 133924fc32b3SKalle Valo u32 address; 1340cd23c1c9SAlex Yang int ret; 1341cd23c1c9SAlex Yang 13425f1127ffSKalle Valo if (ar->testmode != 2) 1343cd23c1c9SAlex Yang return 0; 1344cd23c1c9SAlex Yang 1345cd23c1c9SAlex Yang if (ar->fw_testscript == NULL) 1346cd23c1c9SAlex Yang return 0; 1347cd23c1c9SAlex Yang 1348cd23c1c9SAlex Yang address = ar->hw.testscript_addr; 1349cd23c1c9SAlex Yang 1350cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1351cd23c1c9SAlex Yang address, ar->fw_testscript_len); 1352cd23c1c9SAlex Yang 1353cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1354cd23c1c9SAlex Yang ar->fw_testscript_len); 1355cd23c1c9SAlex Yang if (ret) { 1356cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret); 1357cd23c1c9SAlex Yang return ret; 1358cd23c1c9SAlex Yang } 1359cd23c1c9SAlex Yang 136024fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address); 136124fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096); 136224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1); 1363cd23c1c9SAlex Yang 1364cd23c1c9SAlex Yang return 0; 1365cd23c1c9SAlex Yang } 1366cd23c1c9SAlex Yang 1367bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1368bdcd8170SKalle Valo { 1369bdcd8170SKalle Valo u32 param, options, sleep, address; 1370bdcd8170SKalle Valo int status = 0; 1371bdcd8170SKalle Valo 137231024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 137331024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1374bdcd8170SKalle Valo return -EINVAL; 1375bdcd8170SKalle Valo 1376bdcd8170SKalle Valo /* temporarily disable system sleep */ 1377bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1378bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1379bdcd8170SKalle Valo if (status) 1380bdcd8170SKalle Valo return status; 1381bdcd8170SKalle Valo 1382bdcd8170SKalle Valo options = param; 1383bdcd8170SKalle Valo 1384bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1385bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1386bdcd8170SKalle Valo if (status) 1387bdcd8170SKalle Valo return status; 1388bdcd8170SKalle Valo 1389bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1390bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1391bdcd8170SKalle Valo if (status) 1392bdcd8170SKalle Valo return status; 1393bdcd8170SKalle Valo 1394bdcd8170SKalle Valo sleep = param; 1395bdcd8170SKalle Valo 1396bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1397bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1398bdcd8170SKalle Valo if (status) 1399bdcd8170SKalle Valo return status; 1400bdcd8170SKalle Valo 1401bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1402bdcd8170SKalle Valo options, sleep); 1403bdcd8170SKalle Valo 1404bdcd8170SKalle Valo /* program analog PLL register */ 140531024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 140631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1407bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1408bdcd8170SKalle Valo 0xF9104001); 140931024d99SKevin Fang 1410bdcd8170SKalle Valo if (status) 1411bdcd8170SKalle Valo return status; 1412bdcd8170SKalle Valo 1413bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1414bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1415bdcd8170SKalle Valo 1416bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1417bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1418bdcd8170SKalle Valo if (status) 1419bdcd8170SKalle Valo return status; 142031024d99SKevin Fang } 1421bdcd8170SKalle Valo 1422bdcd8170SKalle Valo param = 0; 1423bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1424bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1425bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1426bdcd8170SKalle Valo if (status) 1427bdcd8170SKalle Valo return status; 1428bdcd8170SKalle Valo 1429bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 14304480bb59SRaja Mani if (ar->version.target_ver == AR6003_HW_2_0_VERSION || 14314480bb59SRaja Mani ar->version.target_ver == AR6003_HW_2_1_1_VERSION) { 1432bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1433bdcd8170SKalle Valo 1434fa338be0SVasanthakumar Thiagarajan param = 0x28; 1435fa338be0SVasanthakumar Thiagarajan address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS; 1436fa338be0SVasanthakumar Thiagarajan status = ath6kl_bmi_reg_write(ar, address, param); 1437fa338be0SVasanthakumar Thiagarajan if (status) 1438fa338be0SVasanthakumar Thiagarajan return status; 1439fa338be0SVasanthakumar Thiagarajan 1440bdcd8170SKalle Valo param = 0x20; 1441bdcd8170SKalle Valo 1442bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1443bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1444bdcd8170SKalle Valo if (status) 1445bdcd8170SKalle Valo return status; 1446bdcd8170SKalle Valo 1447bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1448bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1449bdcd8170SKalle Valo if (status) 1450bdcd8170SKalle Valo return status; 1451bdcd8170SKalle Valo 1452bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1453bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1454bdcd8170SKalle Valo if (status) 1455bdcd8170SKalle Valo return status; 1456bdcd8170SKalle Valo 1457bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1458bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1459bdcd8170SKalle Valo if (status) 1460bdcd8170SKalle Valo return status; 1461bdcd8170SKalle Valo } 1462bdcd8170SKalle Valo 1463bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1464bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1465bdcd8170SKalle Valo if (status) 1466bdcd8170SKalle Valo return status; 1467bdcd8170SKalle Valo 1468bdcd8170SKalle Valo /* transfer One time Programmable data */ 1469bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1470bdcd8170SKalle Valo if (status) 1471bdcd8170SKalle Valo return status; 1472bdcd8170SKalle Valo 1473bdcd8170SKalle Valo /* Download Target firmware */ 1474bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1475bdcd8170SKalle Valo if (status) 1476bdcd8170SKalle Valo return status; 1477bdcd8170SKalle Valo 1478bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1479bdcd8170SKalle Valo if (status) 1480bdcd8170SKalle Valo return status; 1481bdcd8170SKalle Valo 1482cd23c1c9SAlex Yang /* Download the test script */ 1483cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar); 1484cd23c1c9SAlex Yang if (status) 1485cd23c1c9SAlex Yang return status; 1486cd23c1c9SAlex Yang 1487bdcd8170SKalle Valo /* Restore system sleep */ 1488bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1489bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1490bdcd8170SKalle Valo if (status) 1491bdcd8170SKalle Valo return status; 1492bdcd8170SKalle Valo 1493bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1494bdcd8170SKalle Valo param = options | 0x20; 1495bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1496bdcd8170SKalle Valo if (status) 1497bdcd8170SKalle Valo return status; 1498bdcd8170SKalle Valo 1499bdcd8170SKalle Valo return status; 1500bdcd8170SKalle Valo } 1501bdcd8170SKalle Valo 150245eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar) 1503a01ac414SKalle Valo { 15041b46dc04SKalle Valo const struct ath6kl_hw *uninitialized_var(hw); 1505856f4b31SKalle Valo int i; 1506bef26a7fSKalle Valo 1507856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1508856f4b31SKalle Valo hw = &hw_list[i]; 1509bef26a7fSKalle Valo 1510856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1511a01ac414SKalle Valo break; 1512856f4b31SKalle Valo } 1513856f4b31SKalle Valo 1514856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1515a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1516a01ac414SKalle Valo ar->version.target_ver); 1517a01ac414SKalle Valo return -EINVAL; 1518a01ac414SKalle Valo } 1519a01ac414SKalle Valo 1520856f4b31SKalle Valo ar->hw = *hw; 1521856f4b31SKalle Valo 15226bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 15236bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 15246bc36431SKalle Valo ar->version.target_ver, ar->target_type, 15256bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 15266bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 15276bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 15286bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 15296bc36431SKalle Valo ar->hw.reserved_ram_size); 153039586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 153139586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 153239586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 15336bc36431SKalle Valo 1534a01ac414SKalle Valo return 0; 1535a01ac414SKalle Valo } 1536a01ac414SKalle Valo 1537293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1538293badf4SKalle Valo { 1539293badf4SKalle Valo switch (type) { 1540293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1541293badf4SKalle Valo return "sdio"; 1542293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1543293badf4SKalle Valo return "usb"; 1544293badf4SKalle Valo } 1545293badf4SKalle Valo 1546293badf4SKalle Valo return NULL; 1547293badf4SKalle Valo } 1548293badf4SKalle Valo 15495fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 155020459ee2SKalle Valo { 155120459ee2SKalle Valo long timeleft; 155220459ee2SKalle Valo int ret, i; 155320459ee2SKalle Valo 15545fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 15555fe4dffbSKalle Valo 155620459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 155720459ee2SKalle Valo if (ret) 155820459ee2SKalle Valo return ret; 155920459ee2SKalle Valo 156020459ee2SKalle Valo ret = ath6kl_configure_target(ar); 156120459ee2SKalle Valo if (ret) 156220459ee2SKalle Valo goto err_power_off; 156320459ee2SKalle Valo 156420459ee2SKalle Valo ret = ath6kl_init_upload(ar); 156520459ee2SKalle Valo if (ret) 156620459ee2SKalle Valo goto err_power_off; 156720459ee2SKalle Valo 156820459ee2SKalle Valo /* Do we need to finish the BMI phase */ 156920459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 157020459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 157120459ee2SKalle Valo ret = -EIO; 157220459ee2SKalle Valo goto err_power_off; 157320459ee2SKalle Valo } 157420459ee2SKalle Valo 157520459ee2SKalle Valo /* 157620459ee2SKalle Valo * The reason we have to wait for the target here is that the 157720459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 157820459ee2SKalle Valo * size. 157920459ee2SKalle Valo */ 158020459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 158120459ee2SKalle Valo ret = -EIO; 158220459ee2SKalle Valo goto err_power_off; 158320459ee2SKalle Valo } 158420459ee2SKalle Valo 158520459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 158620459ee2SKalle Valo ret = -EIO; 158720459ee2SKalle Valo goto err_cleanup_scatter; 158820459ee2SKalle Valo } 158920459ee2SKalle Valo 159020459ee2SKalle Valo /* setup credit distribution */ 1591e76ac2bfSKalle Valo ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info); 159220459ee2SKalle Valo 159320459ee2SKalle Valo /* start HTC */ 159420459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 159520459ee2SKalle Valo if (ret) { 159620459ee2SKalle Valo /* FIXME: call this */ 159720459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 159820459ee2SKalle Valo goto err_cleanup_scatter; 159920459ee2SKalle Valo } 160020459ee2SKalle Valo 160120459ee2SKalle Valo /* Wait for Wmi event to be ready */ 160220459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 160320459ee2SKalle Valo test_bit(WMI_READY, 160420459ee2SKalle Valo &ar->flag), 160520459ee2SKalle Valo WMI_TIMEOUT); 160620459ee2SKalle Valo 160720459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 160820459ee2SKalle Valo 1609293badf4SKalle Valo 1610293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 161165a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1612293badf4SKalle Valo ar->hw.name, 1613293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1614293badf4SKalle Valo ar->wiphy->fw_version, 161565a8b4ccSKalle Valo ar->fw_api, 1616293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1617293badf4SKalle Valo } 1618293badf4SKalle Valo 161920459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 162020459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 162120459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 162220459ee2SKalle Valo ret = -EIO; 162320459ee2SKalle Valo goto err_htc_stop; 162420459ee2SKalle Valo } 162520459ee2SKalle Valo 162620459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 162720459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 162820459ee2SKalle Valo ret = -EIO; 162920459ee2SKalle Valo goto err_htc_stop; 163020459ee2SKalle Valo } 163120459ee2SKalle Valo 163220459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 163320459ee2SKalle Valo 163420459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 163520459ee2SKalle Valo /* FIXME: return error */ 163620459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 163720459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 163820459ee2SKalle Valo 163971f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 164020459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 164120459ee2SKalle Valo if (ret) 164220459ee2SKalle Valo goto err_htc_stop; 164320459ee2SKalle Valo } 164420459ee2SKalle Valo 164576a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 164676a9fbe2SKalle Valo 164720459ee2SKalle Valo return 0; 164820459ee2SKalle Valo 164920459ee2SKalle Valo err_htc_stop: 165020459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 165120459ee2SKalle Valo err_cleanup_scatter: 165220459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 165320459ee2SKalle Valo err_power_off: 165420459ee2SKalle Valo ath6kl_hif_power_off(ar); 165520459ee2SKalle Valo 165620459ee2SKalle Valo return ret; 165720459ee2SKalle Valo } 165820459ee2SKalle Valo 16595fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 16605fe4dffbSKalle Valo { 16615fe4dffbSKalle Valo int ret; 16625fe4dffbSKalle Valo 16635fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 16645fe4dffbSKalle Valo 16655fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 16665fe4dffbSKalle Valo 16675fe4dffbSKalle Valo ath6kl_hif_stop(ar); 16685fe4dffbSKalle Valo 16695fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 16705fe4dffbSKalle Valo 16715fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 16725fe4dffbSKalle Valo if (ret) 16735fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 16745fe4dffbSKalle Valo 167576a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 167676a9fbe2SKalle Valo 16775fe4dffbSKalle Valo return 0; 16785fe4dffbSKalle Valo } 16795fe4dffbSKalle Valo 1680c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ 168155055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 16826db8fa53SVasanthakumar Thiagarajan { 16836db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 16846db8fa53SVasanthakumar Thiagarajan bool discon_issued; 16856db8fa53SVasanthakumar Thiagarajan 16866db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 16876db8fa53SVasanthakumar Thiagarajan 16886db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 16896db8fa53SVasanthakumar Thiagarajan 16906db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 16916db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 16926db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 16936db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 16946db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 16956db8fa53SVasanthakumar Thiagarajan 16966db8fa53SVasanthakumar Thiagarajan if (discon_issued) 16976db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 16986db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 16996db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 17006db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 17016db8fa53SVasanthakumar Thiagarajan } 17026db8fa53SVasanthakumar Thiagarajan 17036db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 17046db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 17056db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 17066db8fa53SVasanthakumar Thiagarajan } 1707c422d52dSThomas Pedersen 1708c422d52dSThomas Pedersen /* need to clean up enhanced bmiss detection fw state */ 1709c422d52dSThomas Pedersen ath6kl_cfg80211_sta_bmiss_enhance(vif, false); 17106db8fa53SVasanthakumar Thiagarajan } 17116db8fa53SVasanthakumar Thiagarajan 1712bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1713bdcd8170SKalle Valo { 1714990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 17151d2a4456SVasanthakumar Thiagarajan int i; 1716bdcd8170SKalle Valo 1717bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1718bdcd8170SKalle Valo 1719bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1720bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1721bdcd8170SKalle Valo return; 1722bdcd8170SKalle Valo } 1723bdcd8170SKalle Valo 17241d2a4456SVasanthakumar Thiagarajan for (i = 0; i < AP_MAX_NUM_STA; i++) 17251d2a4456SVasanthakumar Thiagarajan aggr_reset_state(ar->sta_list[i].aggr_conn); 17261d2a4456SVasanthakumar Thiagarajan 172711f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1728990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1729990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 173011f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1731990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 173227929723SVasanthakumar Thiagarajan rtnl_lock(); 1733c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif); 173427929723SVasanthakumar Thiagarajan rtnl_unlock(); 173511f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1736990bd915SVasanthakumar Thiagarajan } 173711f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1738bdcd8170SKalle Valo 17396db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 17406db8fa53SVasanthakumar Thiagarajan 17416db8fa53SVasanthakumar Thiagarajan /* 17426db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 17436db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 17446db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 17456db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 17466db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 17476db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 17486db8fa53SVasanthakumar Thiagarajan * are collected. 17496db8fa53SVasanthakumar Thiagarajan */ 17506db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 17516db8fa53SVasanthakumar Thiagarajan 17526db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 17536db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 17546db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 17556db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1756bdcd8170SKalle Valo } 1757bdcd8170SKalle Valo 1758bdcd8170SKalle Valo /* 17596db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 17606db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1761bdcd8170SKalle Valo */ 17626db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 17636db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 17646db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1765bdcd8170SKalle Valo 17666db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1767e8ad9a06SVasanthakumar Thiagarajan 1768e8ad9a06SVasanthakumar Thiagarajan up(&ar->sem); 1769bdcd8170SKalle Valo } 1770d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx); 1771