1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 41b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 5bdcd8170SKalle Valo * 6bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 7bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 8bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 9bdcd8170SKalle Valo * 10bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17bdcd8170SKalle Valo */ 18bdcd8170SKalle Valo 19c6efe578SStephen Rothwell #include <linux/moduleparam.h> 20f7830202SSangwook Lee #include <linux/errno.h> 21d6a434d6SKalle Valo #include <linux/export.h> 2292ecbff4SSam Leffler #include <linux/of.h> 23bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 24d6a434d6SKalle Valo 25bdcd8170SKalle Valo #include "core.h" 26bdcd8170SKalle Valo #include "cfg80211.h" 27bdcd8170SKalle Valo #include "target.h" 28bdcd8170SKalle Valo #include "debug.h" 29bdcd8170SKalle Valo #include "hif-ops.h" 30bdcd8170SKalle Valo 31856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 32856f4b31SKalle Valo { 330d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 34293badf4SKalle Valo .name = "ar6003 hw 2.0", 35856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 36856f4b31SKalle Valo .app_load_addr = 0x543180, 37856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 38856f4b31SKalle Valo .reserved_ram_size = 6912, 3939586bf2SRyan Hsu .refclk_hz = 26000000, 4039586bf2SRyan Hsu .uarttx_pin = 8, 41856f4b31SKalle Valo 42856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 43856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 44d1a9421dSKalle Valo 45c0038972SKalle Valo .fw = { 46c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 47c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 48d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 49c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 50c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 51c0038972SKalle Valo }, 52c0038972SKalle Valo 53d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 54d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 55856f4b31SKalle Valo }, 56856f4b31SKalle Valo { 570d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 58293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 59856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 60856f4b31SKalle Valo .app_load_addr = 0x1234, 61856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 62856f4b31SKalle Valo .reserved_ram_size = 512, 6339586bf2SRyan Hsu .refclk_hz = 26000000, 6439586bf2SRyan Hsu .uarttx_pin = 8, 65cd23c1c9SAlex Yang .testscript_addr = 0x57ef74, 66d1a9421dSKalle Valo 67c0038972SKalle Valo .fw = { 68c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 69c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 70d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 71c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 72c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 73cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, 74cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, 75c0038972SKalle Valo }, 76c0038972SKalle Valo 77d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 78d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 79856f4b31SKalle Valo }, 80856f4b31SKalle Valo { 810d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 82293badf4SKalle Valo .name = "ar6004 hw 1.0", 83856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 84856f4b31SKalle Valo .app_load_addr = 0x1234, 85856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 86856f4b31SKalle Valo .reserved_ram_size = 19456, 870d4d72bfSKalle Valo .board_addr = 0x433900, 8839586bf2SRyan Hsu .refclk_hz = 26000000, 8939586bf2SRyan Hsu .uarttx_pin = 11, 90d1a9421dSKalle Valo 91c0038972SKalle Valo .fw = { 92c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 93d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 94c0038972SKalle Valo }, 95c0038972SKalle Valo 96d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 97d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 98856f4b31SKalle Valo }, 99856f4b31SKalle Valo { 1000d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 101293badf4SKalle Valo .name = "ar6004 hw 1.1", 102856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 103856f4b31SKalle Valo .app_load_addr = 0x1234, 104856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 105856f4b31SKalle Valo .reserved_ram_size = 11264, 1060d4d72bfSKalle Valo .board_addr = 0x43d400, 10739586bf2SRyan Hsu .refclk_hz = 40000000, 10839586bf2SRyan Hsu .uarttx_pin = 11, 109d1a9421dSKalle Valo 110c0038972SKalle Valo .fw = { 111c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 112d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 113c0038972SKalle Valo }, 114c0038972SKalle Valo 115d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 116d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 117856f4b31SKalle Valo }, 118856f4b31SKalle Valo }; 119856f4b31SKalle Valo 120bdcd8170SKalle Valo /* 121bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 122bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 123bdcd8170SKalle Valo * here. 124bdcd8170SKalle Valo */ 125bdcd8170SKalle Valo 126bdcd8170SKalle Valo /* 127bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 128bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 129bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 130bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 131bdcd8170SKalle Valo * Use value of zero to disable keepalive support 132bdcd8170SKalle Valo * Default: 60 seconds 133bdcd8170SKalle Valo */ 134bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 135bdcd8170SKalle Valo 136bdcd8170SKalle Valo /* 137bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 138bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 139bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 140bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 141bdcd8170SKalle Valo * it sends a new connect event 142bdcd8170SKalle Valo */ 143bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 144bdcd8170SKalle Valo 145bdcd8170SKalle Valo 146bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 147bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 148bdcd8170SKalle Valo { 149bdcd8170SKalle Valo struct sk_buff *skb; 150bdcd8170SKalle Valo u16 reserved; 151bdcd8170SKalle Valo 152bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 153bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 1541df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 155bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 156bdcd8170SKalle Valo 157bdcd8170SKalle Valo if (skb) 158bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 159bdcd8170SKalle Valo return skb; 160bdcd8170SKalle Valo } 161bdcd8170SKalle Valo 162e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 163bdcd8170SKalle Valo { 1643450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 1653450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 1663450334fSVasanthakumar Thiagarajan 1673450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 1683450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 1693450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 1703450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 1713450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 1723450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 1736f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 1748c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 1758c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 176f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 177bdcd8170SKalle Valo } 178bdcd8170SKalle Valo 179bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 180bdcd8170SKalle Valo { 181bdcd8170SKalle Valo u32 address, data; 182bdcd8170SKalle Valo struct host_app_area host_app_area; 183bdcd8170SKalle Valo 184bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 185bdcd8170SKalle Valo * instance in the host interest area */ 186bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 18731024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 188bdcd8170SKalle Valo 189addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 190bdcd8170SKalle Valo return -EIO; 191bdcd8170SKalle Valo 19231024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 193cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 194addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 195addb44beSKalle Valo sizeof(struct host_app_area))) 196bdcd8170SKalle Valo return -EIO; 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo return 0; 199bdcd8170SKalle Valo } 200bdcd8170SKalle Valo 201bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 202bdcd8170SKalle Valo u8 ac, 203bdcd8170SKalle Valo enum htc_endpoint_id ep) 204bdcd8170SKalle Valo { 205bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 206bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 207bdcd8170SKalle Valo } 208bdcd8170SKalle Valo 209bdcd8170SKalle Valo /* connect to a service */ 210bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 211bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 212bdcd8170SKalle Valo char *desc) 213bdcd8170SKalle Valo { 214bdcd8170SKalle Valo int status; 215bdcd8170SKalle Valo struct htc_service_connect_resp response; 216bdcd8170SKalle Valo 217bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 218bdcd8170SKalle Valo 219ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 220bdcd8170SKalle Valo if (status) { 221bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 222bdcd8170SKalle Valo desc, status); 223bdcd8170SKalle Valo return status; 224bdcd8170SKalle Valo } 225bdcd8170SKalle Valo 226bdcd8170SKalle Valo switch (con_req->svc_id) { 227bdcd8170SKalle Valo case WMI_CONTROL_SVC: 228bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 229bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 230bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 231bdcd8170SKalle Valo break; 232bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 233bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 234bdcd8170SKalle Valo break; 235bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 236bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 237bdcd8170SKalle Valo break; 238bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 239bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 240bdcd8170SKalle Valo break; 241bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 242bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 243bdcd8170SKalle Valo break; 244bdcd8170SKalle Valo default: 245bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 246bdcd8170SKalle Valo return -EINVAL; 247bdcd8170SKalle Valo } 248bdcd8170SKalle Valo 249bdcd8170SKalle Valo return 0; 250bdcd8170SKalle Valo } 251bdcd8170SKalle Valo 252bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 253bdcd8170SKalle Valo { 254bdcd8170SKalle Valo struct htc_service_connect_req connect; 255bdcd8170SKalle Valo 256bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 257bdcd8170SKalle Valo 258bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 259bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 260bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 261bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo /* 264bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 265bdcd8170SKalle Valo * gets called. 266bdcd8170SKalle Valo */ 267bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 268bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 269bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 270bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 271bdcd8170SKalle Valo 272bdcd8170SKalle Valo /* connect to control service */ 273bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 274bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 275bdcd8170SKalle Valo return -EIO; 276bdcd8170SKalle Valo 277bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 278bdcd8170SKalle Valo 279bdcd8170SKalle Valo /* 280bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 281bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 282bdcd8170SKalle Valo * (802.3) frames on the send path. 283bdcd8170SKalle Valo */ 284bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 285bdcd8170SKalle Valo 286bdcd8170SKalle Valo /* 287bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 288bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 289bdcd8170SKalle Valo * packets. 290bdcd8170SKalle Valo */ 291bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 292bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 293bdcd8170SKalle Valo 294bdcd8170SKalle Valo /* 295bdcd8170SKalle Valo * For the remaining data services set the connection flag to 296bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 297bdcd8170SKalle Valo */ 298bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 299bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 300bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 301bdcd8170SKalle Valo 302bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 303bdcd8170SKalle Valo 304bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 305bdcd8170SKalle Valo return -EIO; 306bdcd8170SKalle Valo 307bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 308bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 309bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 310bdcd8170SKalle Valo return -EIO; 311bdcd8170SKalle Valo 312bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 313bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 314bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 315bdcd8170SKalle Valo return -EIO; 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo /* 318bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 319bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 320bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 321bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 322bdcd8170SKalle Valo * mailboxes. 323bdcd8170SKalle Valo */ 324bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 325bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 326bdcd8170SKalle Valo return -EIO; 327bdcd8170SKalle Valo 328bdcd8170SKalle Valo return 0; 329bdcd8170SKalle Valo } 330bdcd8170SKalle Valo 331e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 332bdcd8170SKalle Valo { 333e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3343450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3356f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 336f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 337bdcd8170SKalle Valo } 338bdcd8170SKalle Valo 339bdcd8170SKalle Valo /* 340bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 341bdcd8170SKalle Valo * target is in the BMI phase. 342bdcd8170SKalle Valo */ 343bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 344bdcd8170SKalle Valo u8 htc_ctrl_buf) 345bdcd8170SKalle Valo { 346bdcd8170SKalle Valo int status; 347bdcd8170SKalle Valo u32 blk_size; 348bdcd8170SKalle Valo 349bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 350bdcd8170SKalle Valo 351bdcd8170SKalle Valo if (htc_ctrl_buf) 352bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 353bdcd8170SKalle Valo 354bdcd8170SKalle Valo /* set the host interest area for the block size */ 35524fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size); 356bdcd8170SKalle Valo if (status) { 357bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 358bdcd8170SKalle Valo goto out; 359bdcd8170SKalle Valo } 360bdcd8170SKalle Valo 361bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 362bdcd8170SKalle Valo blk_size, 363bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 364bdcd8170SKalle Valo 365bdcd8170SKalle Valo if (mbox_isr_yield_val) { 366bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 36724fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit, 36824fc32b3SKalle Valo mbox_isr_yield_val); 369bdcd8170SKalle Valo if (status) { 370bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 371bdcd8170SKalle Valo goto out; 372bdcd8170SKalle Valo } 373bdcd8170SKalle Valo } 374bdcd8170SKalle Valo 375bdcd8170SKalle Valo out: 376bdcd8170SKalle Valo return status; 377bdcd8170SKalle Valo } 378bdcd8170SKalle Valo 3790ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 380bdcd8170SKalle Valo { 3814dea08e0SJouni Malinen int ret; 382bdcd8170SKalle Valo 383bdcd8170SKalle Valo /* 384bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 385bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 386bdcd8170SKalle Valo * RxMetaVersion to 2. 387bdcd8170SKalle Valo */ 3881ca4d0b6SKalle Valo ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 3891ca4d0b6SKalle Valo ar->rx_meta_ver, 0, 0); 3901ca4d0b6SKalle Valo if (ret) { 3911ca4d0b6SKalle Valo ath6kl_err("unable to set the rx frame format: %d\n", ret); 3921ca4d0b6SKalle Valo return ret; 393bdcd8170SKalle Valo } 394bdcd8170SKalle Valo 3951ca4d0b6SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) { 3961ca4d0b6SKalle Valo ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 39705aab177SKalle Valo IGNORE_PS_FAIL_DURING_SCAN); 3981ca4d0b6SKalle Valo if (ret) { 3991ca4d0b6SKalle Valo ath6kl_err("unable to set power save fail event policy: %d\n", 4001ca4d0b6SKalle Valo ret); 4011ca4d0b6SKalle Valo return ret; 4021ca4d0b6SKalle Valo } 403bdcd8170SKalle Valo } 404bdcd8170SKalle Valo 4051ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) { 4061ca4d0b6SKalle Valo ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 40705aab177SKalle Valo WMI_FOLLOW_BARKER_IN_ERP); 4081ca4d0b6SKalle Valo if (ret) { 4091ca4d0b6SKalle Valo ath6kl_err("unable to set barker preamble policy: %d\n", 4101ca4d0b6SKalle Valo ret); 4111ca4d0b6SKalle Valo return ret; 4121ca4d0b6SKalle Valo } 413bdcd8170SKalle Valo } 414bdcd8170SKalle Valo 4151ca4d0b6SKalle Valo ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 4161ca4d0b6SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL); 4171ca4d0b6SKalle Valo if (ret) { 4181ca4d0b6SKalle Valo ath6kl_err("unable to set keep alive interval: %d\n", ret); 4191ca4d0b6SKalle Valo return ret; 420bdcd8170SKalle Valo } 421bdcd8170SKalle Valo 4221ca4d0b6SKalle Valo ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 4231ca4d0b6SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT); 4241ca4d0b6SKalle Valo if (ret) { 4251ca4d0b6SKalle Valo ath6kl_err("unable to set disconnect timeout: %d\n", ret); 4261ca4d0b6SKalle Valo return ret; 427bdcd8170SKalle Valo } 428bdcd8170SKalle Valo 4291ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) { 4301ca4d0b6SKalle Valo ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED); 4311ca4d0b6SKalle Valo if (ret) { 4321ca4d0b6SKalle Valo ath6kl_err("unable to set txop bursting: %d\n", ret); 4331ca4d0b6SKalle Valo return ret; 4341ca4d0b6SKalle Valo } 435bdcd8170SKalle Valo } 436bdcd8170SKalle Valo 437b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4380ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4396bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4404dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4414dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4424dea08e0SJouni Malinen if (ret) { 4434dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4446bbc7c35SJouni Malinen "capabilities (%d) - assuming P2P not " 4456bbc7c35SJouni Malinen "supported\n", ret); 4463db1cd5cSRusty Russell ar->p2p = false; 4476bbc7c35SJouni Malinen } 4486bbc7c35SJouni Malinen } 4496bbc7c35SJouni Malinen 450b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4516bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 4520ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 4536bbc7c35SJouni Malinen if (ret) { 4546bbc7c35SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " 4556bbc7c35SJouni Malinen "Request reporting (%d)\n", ret); 4566bbc7c35SJouni Malinen } 4574dea08e0SJouni Malinen } 4584dea08e0SJouni Malinen 4591ca4d0b6SKalle Valo return ret; 460bdcd8170SKalle Valo } 461bdcd8170SKalle Valo 462bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 463bdcd8170SKalle Valo { 464bdcd8170SKalle Valo u32 param, ram_reserved_size; 4653226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 46639586bf2SRyan Hsu int i, status; 467bdcd8170SKalle Valo 468f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 46924fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) { 470a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 471a10e2f2fSVasanthakumar Thiagarajan return -EIO; 472a10e2f2fSVasanthakumar Thiagarajan } 473a10e2f2fSVasanthakumar Thiagarajan 4747b85832dSVasanthakumar Thiagarajan /* 4757b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 4767b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 4777b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 4787b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 4797b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 4807b85832dSVasanthakumar Thiagarajan * configured for now. 4817b85832dSVasanthakumar Thiagarajan */ 482dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 483bdcd8170SKalle Valo 48471f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 4857b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 4867b85832dSVasanthakumar Thiagarajan 4877b85832dSVasanthakumar Thiagarajan /* 4883226f68aSVasanthakumar Thiagarajan * By default, submodes : 4893226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 4907b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 4917b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 4927b85832dSVasanthakumar Thiagarajan */ 4933226f68aSVasanthakumar Thiagarajan 4943226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 4953226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 4963226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 4973226f68aSVasanthakumar Thiagarajan 49871f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 4993226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5003226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5017b85832dSVasanthakumar Thiagarajan 502b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5037b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5047b85832dSVasanthakumar Thiagarajan 50524fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest, 50624fc32b3SKalle Valo HTC_PROTOCOL_VERSION) != 0) { 507bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 508bdcd8170SKalle Valo return -EIO; 509bdcd8170SKalle Valo } 510bdcd8170SKalle Valo 511bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 512bdcd8170SKalle Valo param = 0; 513bdcd8170SKalle Valo 51480fb2686SKalle Valo if (ath6kl_bmi_read_hi32(ar, hi_option_flag, ¶m) != 0) { 515bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 516bdcd8170SKalle Valo return -EIO; 517bdcd8170SKalle Valo } 518bdcd8170SKalle Valo 51971f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5207b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5217b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5227b85832dSVasanthakumar Thiagarajan 523bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 524bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 525bdcd8170SKalle Valo 52624fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) { 527bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 528bdcd8170SKalle Valo return -EIO; 529bdcd8170SKalle Valo } 530bdcd8170SKalle Valo 531bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 532bdcd8170SKalle Valo 533bdcd8170SKalle Valo /* 534bdcd8170SKalle Valo * Hardcode the address use for the extended board data 535bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 536bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 537bdcd8170SKalle Valo * at init time, we have to workaround this from host. 538bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 539bdcd8170SKalle Valo * but possible in theory. 540bdcd8170SKalle Valo */ 541bdcd8170SKalle Valo 542991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 543991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 544bdcd8170SKalle Valo 54524fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) { 546bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 547bdcd8170SKalle Valo return -EIO; 548bdcd8170SKalle Valo } 549991b27eaSKalle Valo 55024fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 55124fc32b3SKalle Valo ram_reserved_size) != 0) { 552bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 553bdcd8170SKalle Valo return -EIO; 554bdcd8170SKalle Valo } 555bdcd8170SKalle Valo 556bdcd8170SKalle Valo /* set the block size for the target */ 557bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 558bdcd8170SKalle Valo /* use default number of control buffers */ 559bdcd8170SKalle Valo return -EIO; 560bdcd8170SKalle Valo 56139586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 56224fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin, 56324fc32b3SKalle Valo ar->hw.uarttx_pin); 56439586bf2SRyan Hsu if (status) 56539586bf2SRyan Hsu return status; 56639586bf2SRyan Hsu 56739586bf2SRyan Hsu /* Configure target refclk_hz */ 56824fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz); 56939586bf2SRyan Hsu if (status) 57039586bf2SRyan Hsu return status; 57139586bf2SRyan Hsu 572bdcd8170SKalle Valo return 0; 573bdcd8170SKalle Valo } 574bdcd8170SKalle Valo 575bdcd8170SKalle Valo /* firmware upload */ 576bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 577bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 578bdcd8170SKalle Valo { 579bdcd8170SKalle Valo const struct firmware *fw_entry; 580bdcd8170SKalle Valo int ret; 581bdcd8170SKalle Valo 582bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 583bdcd8170SKalle Valo if (ret) 584bdcd8170SKalle Valo return ret; 585bdcd8170SKalle Valo 586bdcd8170SKalle Valo *fw_len = fw_entry->size; 587bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 588bdcd8170SKalle Valo 589bdcd8170SKalle Valo if (*fw == NULL) 590bdcd8170SKalle Valo ret = -ENOMEM; 591bdcd8170SKalle Valo 592bdcd8170SKalle Valo release_firmware(fw_entry); 593bdcd8170SKalle Valo 594bdcd8170SKalle Valo return ret; 595bdcd8170SKalle Valo } 596bdcd8170SKalle Valo 59792ecbff4SSam Leffler #ifdef CONFIG_OF 59892ecbff4SSam Leffler /* 59992ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 60092ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 60192ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 60292ecbff4SSam Leffler * appropriate board-specific file. 60392ecbff4SSam Leffler */ 60492ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 60592ecbff4SSam Leffler { 60692ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 60792ecbff4SSam Leffler struct device_node *node; 60892ecbff4SSam Leffler char board_filename[64]; 60992ecbff4SSam Leffler const char *board_id; 61092ecbff4SSam Leffler int ret; 61192ecbff4SSam Leffler 61292ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 61392ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 61492ecbff4SSam Leffler if (board_id == NULL) { 61592ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 61692ecbff4SSam Leffler board_id_prop, node->name); 61792ecbff4SSam Leffler continue; 61892ecbff4SSam Leffler } 61992ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 620c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 62192ecbff4SSam Leffler 62292ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 62392ecbff4SSam Leffler &ar->fw_board_len); 62492ecbff4SSam Leffler if (ret) { 62592ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 62692ecbff4SSam Leffler board_filename, ret); 62792ecbff4SSam Leffler continue; 62892ecbff4SSam Leffler } 62992ecbff4SSam Leffler return true; 63092ecbff4SSam Leffler } 63192ecbff4SSam Leffler return false; 63292ecbff4SSam Leffler } 63392ecbff4SSam Leffler #else 63492ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 63592ecbff4SSam Leffler { 63692ecbff4SSam Leffler return false; 63792ecbff4SSam Leffler } 63892ecbff4SSam Leffler #endif /* CONFIG_OF */ 63992ecbff4SSam Leffler 640bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 641bdcd8170SKalle Valo { 642bdcd8170SKalle Valo const char *filename; 643bdcd8170SKalle Valo int ret; 644bdcd8170SKalle Valo 645772c31eeSKalle Valo if (ar->fw_board != NULL) 646772c31eeSKalle Valo return 0; 647772c31eeSKalle Valo 648d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 649d1a9421dSKalle Valo return -EINVAL; 650d1a9421dSKalle Valo 651d1a9421dSKalle Valo filename = ar->hw.fw_board; 652bdcd8170SKalle Valo 653bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 654bdcd8170SKalle Valo &ar->fw_board_len); 655bdcd8170SKalle Valo if (ret == 0) { 656bdcd8170SKalle Valo /* managed to get proper board file */ 657bdcd8170SKalle Valo return 0; 658bdcd8170SKalle Valo } 659bdcd8170SKalle Valo 66092ecbff4SSam Leffler if (check_device_tree(ar)) { 66192ecbff4SSam Leffler /* got board file from device tree */ 66292ecbff4SSam Leffler return 0; 66392ecbff4SSam Leffler } 66492ecbff4SSam Leffler 665bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 666bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 667bdcd8170SKalle Valo filename, ret); 668bdcd8170SKalle Valo 669d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 670bdcd8170SKalle Valo 671bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 672bdcd8170SKalle Valo &ar->fw_board_len); 673bdcd8170SKalle Valo if (ret) { 674bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 675bdcd8170SKalle Valo filename, ret); 676bdcd8170SKalle Valo return ret; 677bdcd8170SKalle Valo } 678bdcd8170SKalle Valo 679bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 680bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 681bdcd8170SKalle Valo 682bdcd8170SKalle Valo return 0; 683bdcd8170SKalle Valo } 684bdcd8170SKalle Valo 685772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 686772c31eeSKalle Valo { 687c0038972SKalle Valo char filename[100]; 688772c31eeSKalle Valo int ret; 689772c31eeSKalle Valo 690772c31eeSKalle Valo if (ar->fw_otp != NULL) 691772c31eeSKalle Valo return 0; 692772c31eeSKalle Valo 693c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 694d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 695d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 696772c31eeSKalle Valo return 0; 697772c31eeSKalle Valo } 698772c31eeSKalle Valo 699c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 700c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 701d1a9421dSKalle Valo 702772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 703772c31eeSKalle Valo &ar->fw_otp_len); 704772c31eeSKalle Valo if (ret) { 705772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 706772c31eeSKalle Valo filename, ret); 707772c31eeSKalle Valo return ret; 708772c31eeSKalle Valo } 709772c31eeSKalle Valo 710772c31eeSKalle Valo return 0; 711772c31eeSKalle Valo } 712772c31eeSKalle Valo 7135f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar) 714772c31eeSKalle Valo { 715c0038972SKalle Valo char filename[100]; 716772c31eeSKalle Valo int ret; 717772c31eeSKalle Valo 7185f1127ffSKalle Valo if (ar->testmode == 0) 719772c31eeSKalle Valo return 0; 720772c31eeSKalle Valo 7215f1127ffSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode); 7225f1127ffSKalle Valo 7235f1127ffSKalle Valo if (ar->testmode == 2) { 724cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) { 725cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n"); 726cd23c1c9SAlex Yang return -EOPNOTSUPP; 727cd23c1c9SAlex Yang } 728cd23c1c9SAlex Yang 729cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 730cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf); 731cd23c1c9SAlex Yang } else { 732c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 733cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n"); 734772c31eeSKalle Valo return -EOPNOTSUPP; 735772c31eeSKalle Valo } 736772c31eeSKalle Valo 737c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 738c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 739cd23c1c9SAlex Yang } 7405f1127ffSKalle Valo 741772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 742772c31eeSKalle Valo 7435f1127ffSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 7445f1127ffSKalle Valo if (ret) { 7455f1127ffSKalle Valo ath6kl_err("Failed to get testmode %d firmware file %s: %d\n", 7465f1127ffSKalle Valo ar->testmode, filename, ret); 7475f1127ffSKalle Valo return ret; 748772c31eeSKalle Valo } 749772c31eeSKalle Valo 7505f1127ffSKalle Valo return 0; 7515f1127ffSKalle Valo } 7525f1127ffSKalle Valo 7535f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 7545f1127ffSKalle Valo { 7555f1127ffSKalle Valo char filename[100]; 7565f1127ffSKalle Valo int ret; 7575f1127ffSKalle Valo 7585f1127ffSKalle Valo if (ar->fw != NULL) 7595f1127ffSKalle Valo return 0; 7605f1127ffSKalle Valo 761c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 762c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 763d1a9421dSKalle Valo return -EINVAL; 764d1a9421dSKalle Valo 765c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 766c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 767772c31eeSKalle Valo 768772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 769772c31eeSKalle Valo if (ret) { 770772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 771772c31eeSKalle Valo filename, ret); 772772c31eeSKalle Valo return ret; 773772c31eeSKalle Valo } 774772c31eeSKalle Valo 775772c31eeSKalle Valo return 0; 776772c31eeSKalle Valo } 777772c31eeSKalle Valo 778772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 779772c31eeSKalle Valo { 780c0038972SKalle Valo char filename[100]; 781772c31eeSKalle Valo int ret; 782772c31eeSKalle Valo 783d1a9421dSKalle Valo if (ar->fw_patch != NULL) 784772c31eeSKalle Valo return 0; 785772c31eeSKalle Valo 786c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 787d1a9421dSKalle Valo return 0; 788d1a9421dSKalle Valo 789c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 790c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 791d1a9421dSKalle Valo 792772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 793772c31eeSKalle Valo &ar->fw_patch_len); 794772c31eeSKalle Valo if (ret) { 795772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 796772c31eeSKalle Valo filename, ret); 797772c31eeSKalle Valo return ret; 798772c31eeSKalle Valo } 799772c31eeSKalle Valo 800772c31eeSKalle Valo return 0; 801772c31eeSKalle Valo } 802772c31eeSKalle Valo 803cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar) 804cd23c1c9SAlex Yang { 805cd23c1c9SAlex Yang char filename[100]; 806cd23c1c9SAlex Yang int ret; 807cd23c1c9SAlex Yang 8085f1127ffSKalle Valo if (ar->testmode != 2) 809cd23c1c9SAlex Yang return 0; 810cd23c1c9SAlex Yang 811cd23c1c9SAlex Yang if (ar->fw_testscript != NULL) 812cd23c1c9SAlex Yang return 0; 813cd23c1c9SAlex Yang 814cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL) 815cd23c1c9SAlex Yang return 0; 816cd23c1c9SAlex Yang 817cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 818cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript); 819cd23c1c9SAlex Yang 820cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 821cd23c1c9SAlex Yang &ar->fw_testscript_len); 822cd23c1c9SAlex Yang if (ret) { 823cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n", 824cd23c1c9SAlex Yang filename, ret); 825cd23c1c9SAlex Yang return ret; 826cd23c1c9SAlex Yang } 827cd23c1c9SAlex Yang 828cd23c1c9SAlex Yang return 0; 829cd23c1c9SAlex Yang } 830cd23c1c9SAlex Yang 83150d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 832772c31eeSKalle Valo { 833772c31eeSKalle Valo int ret; 834772c31eeSKalle Valo 835772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 836772c31eeSKalle Valo if (ret) 837772c31eeSKalle Valo return ret; 838772c31eeSKalle Valo 839772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 840772c31eeSKalle Valo if (ret) 841772c31eeSKalle Valo return ret; 842772c31eeSKalle Valo 843772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 844772c31eeSKalle Valo if (ret) 845772c31eeSKalle Valo return ret; 846772c31eeSKalle Valo 847cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar); 848cd23c1c9SAlex Yang if (ret) 849cd23c1c9SAlex Yang return ret; 850cd23c1c9SAlex Yang 851772c31eeSKalle Valo return 0; 852772c31eeSKalle Valo } 853bdcd8170SKalle Valo 85465a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 85550d41234SKalle Valo { 85650d41234SKalle Valo size_t magic_len, len, ie_len; 85750d41234SKalle Valo const struct firmware *fw; 85850d41234SKalle Valo struct ath6kl_fw_ie *hdr; 859c0038972SKalle Valo char filename[100]; 86050d41234SKalle Valo const u8 *data; 86197e0496dSKalle Valo int ret, ie_id, i, index, bit; 8628a137480SKalle Valo __le32 *val; 86350d41234SKalle Valo 86465a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 86550d41234SKalle Valo 86650d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 86750d41234SKalle Valo if (ret) 86850d41234SKalle Valo return ret; 86950d41234SKalle Valo 87050d41234SKalle Valo data = fw->data; 87150d41234SKalle Valo len = fw->size; 87250d41234SKalle Valo 87350d41234SKalle Valo /* magic also includes the null byte, check that as well */ 87450d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 87550d41234SKalle Valo 87650d41234SKalle Valo if (len < magic_len) { 87750d41234SKalle Valo ret = -EINVAL; 87850d41234SKalle Valo goto out; 87950d41234SKalle Valo } 88050d41234SKalle Valo 88150d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 88250d41234SKalle Valo ret = -EINVAL; 88350d41234SKalle Valo goto out; 88450d41234SKalle Valo } 88550d41234SKalle Valo 88650d41234SKalle Valo len -= magic_len; 88750d41234SKalle Valo data += magic_len; 88850d41234SKalle Valo 88950d41234SKalle Valo /* loop elements */ 89050d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 89150d41234SKalle Valo /* hdr is unaligned! */ 89250d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 89350d41234SKalle Valo 89450d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 89550d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 89650d41234SKalle Valo 89750d41234SKalle Valo len -= sizeof(*hdr); 89850d41234SKalle Valo data += sizeof(*hdr); 89950d41234SKalle Valo 90050d41234SKalle Valo if (len < ie_len) { 90150d41234SKalle Valo ret = -EINVAL; 90250d41234SKalle Valo goto out; 90350d41234SKalle Valo } 90450d41234SKalle Valo 90550d41234SKalle Valo switch (ie_id) { 90650d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 907ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9086bc36431SKalle Valo ie_len); 9096bc36431SKalle Valo 91050d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 91150d41234SKalle Valo 91250d41234SKalle Valo if (ar->fw_otp == NULL) { 91350d41234SKalle Valo ret = -ENOMEM; 91450d41234SKalle Valo goto out; 91550d41234SKalle Valo } 91650d41234SKalle Valo 91750d41234SKalle Valo ar->fw_otp_len = ie_len; 91850d41234SKalle Valo break; 91950d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 920ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9216bc36431SKalle Valo ie_len); 9226bc36431SKalle Valo 9235f1127ffSKalle Valo /* in testmode we already might have a fw file */ 9245f1127ffSKalle Valo if (ar->fw != NULL) 9255f1127ffSKalle Valo break; 9265f1127ffSKalle Valo 92750d41234SKalle Valo ar->fw = kmemdup(data, ie_len, GFP_KERNEL); 92850d41234SKalle Valo 92950d41234SKalle Valo if (ar->fw == NULL) { 93050d41234SKalle Valo ret = -ENOMEM; 93150d41234SKalle Valo goto out; 93250d41234SKalle Valo } 93350d41234SKalle Valo 93450d41234SKalle Valo ar->fw_len = ie_len; 93550d41234SKalle Valo break; 93650d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 937ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 9386bc36431SKalle Valo ie_len); 9396bc36431SKalle Valo 94050d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 94150d41234SKalle Valo 94250d41234SKalle Valo if (ar->fw_patch == NULL) { 94350d41234SKalle Valo ret = -ENOMEM; 94450d41234SKalle Valo goto out; 94550d41234SKalle Valo } 94650d41234SKalle Valo 94750d41234SKalle Valo ar->fw_patch_len = ie_len; 94850d41234SKalle Valo break; 9498a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 9508a137480SKalle Valo val = (__le32 *) data; 9518a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 9526bc36431SKalle Valo 9536bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 9546bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 9556bc36431SKalle Valo ar->hw.reserved_ram_size); 9568a137480SKalle Valo break; 95797e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 958277d90f4SKalle Valo if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) 959277d90f4SKalle Valo break; 960277d90f4SKalle Valo 9616bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 962ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 9636bc36431SKalle Valo ie_len); 9646bc36431SKalle Valo 96597e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 966277d90f4SKalle Valo index = i / 8; 96797e0496dSKalle Valo bit = i % 8; 96897e0496dSKalle Valo 96997e0496dSKalle Valo if (data[index] & (1 << bit)) 97097e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 97197e0496dSKalle Valo } 9726bc36431SKalle Valo 9736bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 9746bc36431SKalle Valo ar->fw_capabilities, 9756bc36431SKalle Valo sizeof(ar->fw_capabilities)); 97697e0496dSKalle Valo break; 9771b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 9781b4304daSKalle Valo if (ie_len != sizeof(*val)) 9791b4304daSKalle Valo break; 9801b4304daSKalle Valo 9811b4304daSKalle Valo val = (__le32 *) data; 9821b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 9836bc36431SKalle Valo 9846bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 98503ef0250SKalle Valo "found patch address ie 0x%x\n", 9866bc36431SKalle Valo ar->hw.dataset_patch_addr); 9871b4304daSKalle Valo break; 98803ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 98903ef0250SKalle Valo if (ie_len != sizeof(*val)) 99003ef0250SKalle Valo break; 99103ef0250SKalle Valo 99203ef0250SKalle Valo val = (__le32 *) data; 99303ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 99403ef0250SKalle Valo 99503ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 99603ef0250SKalle Valo "found board address ie 0x%x\n", 99703ef0250SKalle Valo ar->hw.board_addr); 99803ef0250SKalle Valo break; 999368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 1000368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 1001368b1b0fSKalle Valo break; 1002368b1b0fSKalle Valo 1003368b1b0fSKalle Valo val = (__le32 *) data; 1004368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 1005368b1b0fSKalle Valo ATH6KL_VIF_MAX); 1006368b1b0fSKalle Valo 1007f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 1008f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1009f143379dSVasanthakumar Thiagarajan 1010368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1011368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1012368b1b0fSKalle Valo break; 101350d41234SKalle Valo default: 10146bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 101550d41234SKalle Valo le32_to_cpup(&hdr->id)); 101650d41234SKalle Valo break; 101750d41234SKalle Valo } 101850d41234SKalle Valo 101950d41234SKalle Valo len -= ie_len; 102050d41234SKalle Valo data += ie_len; 102150d41234SKalle Valo }; 102250d41234SKalle Valo 102350d41234SKalle Valo ret = 0; 102450d41234SKalle Valo out: 102550d41234SKalle Valo release_firmware(fw); 102650d41234SKalle Valo 102750d41234SKalle Valo return ret; 102850d41234SKalle Valo } 102950d41234SKalle Valo 103045eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar) 103150d41234SKalle Valo { 103250d41234SKalle Valo int ret; 103350d41234SKalle Valo 103450d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 103550d41234SKalle Valo if (ret) 103650d41234SKalle Valo return ret; 103750d41234SKalle Valo 10385f1127ffSKalle Valo ret = ath6kl_fetch_testmode_file(ar); 10395f1127ffSKalle Valo if (ret) 10405f1127ffSKalle Valo return ret; 10415f1127ffSKalle Valo 104265a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 10436bc36431SKalle Valo if (ret == 0) { 104465a8b4ccSKalle Valo ar->fw_api = 3; 104565a8b4ccSKalle Valo goto out; 104665a8b4ccSKalle Valo } 104765a8b4ccSKalle Valo 104865a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 104965a8b4ccSKalle Valo if (ret == 0) { 105065a8b4ccSKalle Valo ar->fw_api = 2; 105165a8b4ccSKalle Valo goto out; 10526bc36431SKalle Valo } 105350d41234SKalle Valo 105450d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 105550d41234SKalle Valo if (ret) 105650d41234SKalle Valo return ret; 105750d41234SKalle Valo 105865a8b4ccSKalle Valo ar->fw_api = 1; 105965a8b4ccSKalle Valo 106065a8b4ccSKalle Valo out: 106165a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 10626bc36431SKalle Valo 106350d41234SKalle Valo return 0; 106450d41234SKalle Valo } 106550d41234SKalle Valo 1066bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1067bdcd8170SKalle Valo { 1068bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 106931024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1070bdcd8170SKalle Valo int ret; 1071bdcd8170SKalle Valo 1072772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1073772c31eeSKalle Valo return -ENOENT; 1074bdcd8170SKalle Valo 107531024d99SKevin Fang /* 107631024d99SKevin Fang * Determine where in Target RAM to write Board Data. 107731024d99SKevin Fang * For AR6004, host determine Target RAM address for 107831024d99SKevin Fang * writing board data. 107931024d99SKevin Fang */ 10800d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 1081b0fc7c1aSKalle Valo board_address = ar->hw.board_addr; 108224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data, 1083b0fc7c1aSKalle Valo board_address); 108431024d99SKevin Fang } else { 108580fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address); 108631024d99SKevin Fang } 108731024d99SKevin Fang 1088bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 108980fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address); 1090bdcd8170SKalle Valo 109150e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 109250e2740bSKalle Valo board_ext_address == 0) { 1093bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1094bdcd8170SKalle Valo return -EINVAL; 1095bdcd8170SKalle Valo } 1096bdcd8170SKalle Valo 109731024d99SKevin Fang switch (ar->target_type) { 109831024d99SKevin Fang case TARGET_TYPE_AR6003: 109931024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 110031024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 1101fb1ac2efSPrasanna Kumar if (ar->fw_board_len > (board_data_size + board_ext_data_size)) 1102fb1ac2efSPrasanna Kumar board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2; 110331024d99SKevin Fang break; 110431024d99SKevin Fang case TARGET_TYPE_AR6004: 110531024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 110631024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 110731024d99SKevin Fang break; 110831024d99SKevin Fang default: 110931024d99SKevin Fang WARN_ON(1); 111031024d99SKevin Fang return -EINVAL; 111131024d99SKevin Fang break; 111231024d99SKevin Fang } 111331024d99SKevin Fang 111450e2740bSKalle Valo if (board_ext_address && 111550e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 111631024d99SKevin Fang 1117bdcd8170SKalle Valo /* write extended board data */ 11186bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11196bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11206bc36431SKalle Valo board_ext_address, board_ext_data_size); 11216bc36431SKalle Valo 1122bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 112331024d99SKevin Fang ar->fw_board + board_data_size, 112431024d99SKevin Fang board_ext_data_size); 1125bdcd8170SKalle Valo if (ret) { 1126bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1127bdcd8170SKalle Valo ret); 1128bdcd8170SKalle Valo return ret; 1129bdcd8170SKalle Valo } 1130bdcd8170SKalle Valo 1131bdcd8170SKalle Valo /* record that extended board data is initialized */ 113231024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 113331024d99SKevin Fang 113424fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param); 1135bdcd8170SKalle Valo } 1136bdcd8170SKalle Valo 113731024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1138bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1139bdcd8170SKalle Valo ret = -EINVAL; 1140bdcd8170SKalle Valo return ret; 1141bdcd8170SKalle Valo } 1142bdcd8170SKalle Valo 11436bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 11446bc36431SKalle Valo board_address, board_data_size); 11456bc36431SKalle Valo 1146bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 114731024d99SKevin Fang board_data_size); 1148bdcd8170SKalle Valo 1149bdcd8170SKalle Valo if (ret) { 1150bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1151bdcd8170SKalle Valo return ret; 1152bdcd8170SKalle Valo } 1153bdcd8170SKalle Valo 1154bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 115524fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1); 1156bdcd8170SKalle Valo 1157bdcd8170SKalle Valo return ret; 1158bdcd8170SKalle Valo } 1159bdcd8170SKalle Valo 1160bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1161bdcd8170SKalle Valo { 1162bdcd8170SKalle Valo u32 address, param; 1163bef26a7fSKalle Valo bool from_hw = false; 1164bdcd8170SKalle Valo int ret; 1165bdcd8170SKalle Valo 116650e2740bSKalle Valo if (ar->fw_otp == NULL) 116750e2740bSKalle Valo return 0; 1168bdcd8170SKalle Valo 1169a01ac414SKalle Valo address = ar->hw.app_load_addr; 1170bdcd8170SKalle Valo 1171ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 11726bc36431SKalle Valo ar->fw_otp_len); 11736bc36431SKalle Valo 1174bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1175bdcd8170SKalle Valo ar->fw_otp_len); 1176bdcd8170SKalle Valo if (ret) { 1177bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1178bdcd8170SKalle Valo return ret; 1179bdcd8170SKalle Valo } 1180bdcd8170SKalle Valo 1181639d0b89SKalle Valo /* read firmware start address */ 118280fb2686SKalle Valo ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address); 1183639d0b89SKalle Valo 1184639d0b89SKalle Valo if (ret) { 1185639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1186639d0b89SKalle Valo return ret; 1187639d0b89SKalle Valo } 1188639d0b89SKalle Valo 1189bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1190639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1191bef26a7fSKalle Valo from_hw = true; 1192bef26a7fSKalle Valo } 1193639d0b89SKalle Valo 1194bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1195bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 11966bc36431SKalle Valo ar->hw.app_start_override_addr); 11976bc36431SKalle Valo 1198bdcd8170SKalle Valo /* execute the OTP code */ 1199bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1200bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1201bdcd8170SKalle Valo param = 0; 1202bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1203bdcd8170SKalle Valo 1204bdcd8170SKalle Valo return ret; 1205bdcd8170SKalle Valo } 1206bdcd8170SKalle Valo 1207bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1208bdcd8170SKalle Valo { 1209bdcd8170SKalle Valo u32 address; 1210bdcd8170SKalle Valo int ret; 1211bdcd8170SKalle Valo 1212772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 121350e2740bSKalle Valo return 0; 1214bdcd8170SKalle Valo 1215a01ac414SKalle Valo address = ar->hw.app_load_addr; 1216bdcd8170SKalle Valo 1217ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12186bc36431SKalle Valo address, ar->fw_len); 12196bc36431SKalle Valo 1220bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1221bdcd8170SKalle Valo 1222bdcd8170SKalle Valo if (ret) { 1223bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1224bdcd8170SKalle Valo return ret; 1225bdcd8170SKalle Valo } 1226bdcd8170SKalle Valo 122731024d99SKevin Fang /* 122831024d99SKevin Fang * Set starting address for firmware 122931024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 123031024d99SKevin Fang */ 123131024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1232a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1233bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 123431024d99SKevin Fang } 1235bdcd8170SKalle Valo return ret; 1236bdcd8170SKalle Valo } 1237bdcd8170SKalle Valo 1238bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1239bdcd8170SKalle Valo { 124024fc32b3SKalle Valo u32 address; 1241bdcd8170SKalle Valo int ret; 1242bdcd8170SKalle Valo 124350e2740bSKalle Valo if (ar->fw_patch == NULL) 124450e2740bSKalle Valo return 0; 1245bdcd8170SKalle Valo 1246a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1247bdcd8170SKalle Valo 1248ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 12496bc36431SKalle Valo address, ar->fw_patch_len); 12506bc36431SKalle Valo 1251bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1252bdcd8170SKalle Valo if (ret) { 1253bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1254bdcd8170SKalle Valo return ret; 1255bdcd8170SKalle Valo } 1256bdcd8170SKalle Valo 125724fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address); 1258bdcd8170SKalle Valo 1259bdcd8170SKalle Valo return 0; 1260bdcd8170SKalle Valo } 1261bdcd8170SKalle Valo 1262cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar) 1263cd23c1c9SAlex Yang { 126424fc32b3SKalle Valo u32 address; 1265cd23c1c9SAlex Yang int ret; 1266cd23c1c9SAlex Yang 12675f1127ffSKalle Valo if (ar->testmode != 2) 1268cd23c1c9SAlex Yang return 0; 1269cd23c1c9SAlex Yang 1270cd23c1c9SAlex Yang if (ar->fw_testscript == NULL) 1271cd23c1c9SAlex Yang return 0; 1272cd23c1c9SAlex Yang 1273cd23c1c9SAlex Yang address = ar->hw.testscript_addr; 1274cd23c1c9SAlex Yang 1275cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1276cd23c1c9SAlex Yang address, ar->fw_testscript_len); 1277cd23c1c9SAlex Yang 1278cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1279cd23c1c9SAlex Yang ar->fw_testscript_len); 1280cd23c1c9SAlex Yang if (ret) { 1281cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret); 1282cd23c1c9SAlex Yang return ret; 1283cd23c1c9SAlex Yang } 1284cd23c1c9SAlex Yang 128524fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address); 128624fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096); 128724fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1); 1288cd23c1c9SAlex Yang 1289cd23c1c9SAlex Yang return 0; 1290cd23c1c9SAlex Yang } 1291cd23c1c9SAlex Yang 1292bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1293bdcd8170SKalle Valo { 1294bdcd8170SKalle Valo u32 param, options, sleep, address; 1295bdcd8170SKalle Valo int status = 0; 1296bdcd8170SKalle Valo 129731024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 129831024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1299bdcd8170SKalle Valo return -EINVAL; 1300bdcd8170SKalle Valo 1301bdcd8170SKalle Valo /* temporarily disable system sleep */ 1302bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1303bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1304bdcd8170SKalle Valo if (status) 1305bdcd8170SKalle Valo return status; 1306bdcd8170SKalle Valo 1307bdcd8170SKalle Valo options = param; 1308bdcd8170SKalle Valo 1309bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1310bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1311bdcd8170SKalle Valo if (status) 1312bdcd8170SKalle Valo return status; 1313bdcd8170SKalle Valo 1314bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1315bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1316bdcd8170SKalle Valo if (status) 1317bdcd8170SKalle Valo return status; 1318bdcd8170SKalle Valo 1319bdcd8170SKalle Valo sleep = param; 1320bdcd8170SKalle Valo 1321bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1322bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1323bdcd8170SKalle Valo if (status) 1324bdcd8170SKalle Valo return status; 1325bdcd8170SKalle Valo 1326bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1327bdcd8170SKalle Valo options, sleep); 1328bdcd8170SKalle Valo 1329bdcd8170SKalle Valo /* program analog PLL register */ 133031024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 133131024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1332bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1333bdcd8170SKalle Valo 0xF9104001); 133431024d99SKevin Fang 1335bdcd8170SKalle Valo if (status) 1336bdcd8170SKalle Valo return status; 1337bdcd8170SKalle Valo 1338bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1339bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1340bdcd8170SKalle Valo 1341bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1342bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1343bdcd8170SKalle Valo if (status) 1344bdcd8170SKalle Valo return status; 134531024d99SKevin Fang } 1346bdcd8170SKalle Valo 1347bdcd8170SKalle Valo param = 0; 1348bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1349bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1350bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1351bdcd8170SKalle Valo if (status) 1352bdcd8170SKalle Valo return status; 1353bdcd8170SKalle Valo 1354bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 13554480bb59SRaja Mani if (ar->version.target_ver == AR6003_HW_2_0_VERSION || 13564480bb59SRaja Mani ar->version.target_ver == AR6003_HW_2_1_1_VERSION) { 1357bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1358bdcd8170SKalle Valo 1359bdcd8170SKalle Valo param = 0x20; 1360bdcd8170SKalle Valo 1361bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1362bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1363bdcd8170SKalle Valo if (status) 1364bdcd8170SKalle Valo return status; 1365bdcd8170SKalle Valo 1366bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1367bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1368bdcd8170SKalle Valo if (status) 1369bdcd8170SKalle Valo return status; 1370bdcd8170SKalle Valo 1371bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1372bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1373bdcd8170SKalle Valo if (status) 1374bdcd8170SKalle Valo return status; 1375bdcd8170SKalle Valo 1376bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1377bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1378bdcd8170SKalle Valo if (status) 1379bdcd8170SKalle Valo return status; 1380bdcd8170SKalle Valo } 1381bdcd8170SKalle Valo 1382bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1383bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1384bdcd8170SKalle Valo if (status) 1385bdcd8170SKalle Valo return status; 1386bdcd8170SKalle Valo 1387bdcd8170SKalle Valo /* transfer One time Programmable data */ 1388bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1389bdcd8170SKalle Valo if (status) 1390bdcd8170SKalle Valo return status; 1391bdcd8170SKalle Valo 1392bdcd8170SKalle Valo /* Download Target firmware */ 1393bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1394bdcd8170SKalle Valo if (status) 1395bdcd8170SKalle Valo return status; 1396bdcd8170SKalle Valo 1397bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1398bdcd8170SKalle Valo if (status) 1399bdcd8170SKalle Valo return status; 1400bdcd8170SKalle Valo 1401cd23c1c9SAlex Yang /* Download the test script */ 1402cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar); 1403cd23c1c9SAlex Yang if (status) 1404cd23c1c9SAlex Yang return status; 1405cd23c1c9SAlex Yang 1406bdcd8170SKalle Valo /* Restore system sleep */ 1407bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1408bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1409bdcd8170SKalle Valo if (status) 1410bdcd8170SKalle Valo return status; 1411bdcd8170SKalle Valo 1412bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1413bdcd8170SKalle Valo param = options | 0x20; 1414bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1415bdcd8170SKalle Valo if (status) 1416bdcd8170SKalle Valo return status; 1417bdcd8170SKalle Valo 1418bdcd8170SKalle Valo return status; 1419bdcd8170SKalle Valo } 1420bdcd8170SKalle Valo 142145eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar) 1422a01ac414SKalle Valo { 14231b46dc04SKalle Valo const struct ath6kl_hw *uninitialized_var(hw); 1424856f4b31SKalle Valo int i; 1425bef26a7fSKalle Valo 1426856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1427856f4b31SKalle Valo hw = &hw_list[i]; 1428bef26a7fSKalle Valo 1429856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1430a01ac414SKalle Valo break; 1431856f4b31SKalle Valo } 1432856f4b31SKalle Valo 1433856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1434a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1435a01ac414SKalle Valo ar->version.target_ver); 1436a01ac414SKalle Valo return -EINVAL; 1437a01ac414SKalle Valo } 1438a01ac414SKalle Valo 1439856f4b31SKalle Valo ar->hw = *hw; 1440856f4b31SKalle Valo 14416bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14426bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 14436bc36431SKalle Valo ar->version.target_ver, ar->target_type, 14446bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 14456bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14466bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 14476bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 14486bc36431SKalle Valo ar->hw.reserved_ram_size); 144939586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 145039586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 145139586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 14526bc36431SKalle Valo 1453a01ac414SKalle Valo return 0; 1454a01ac414SKalle Valo } 1455a01ac414SKalle Valo 1456293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1457293badf4SKalle Valo { 1458293badf4SKalle Valo switch (type) { 1459293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1460293badf4SKalle Valo return "sdio"; 1461293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1462293badf4SKalle Valo return "usb"; 1463293badf4SKalle Valo } 1464293badf4SKalle Valo 1465293badf4SKalle Valo return NULL; 1466293badf4SKalle Valo } 1467293badf4SKalle Valo 14685fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 146920459ee2SKalle Valo { 147020459ee2SKalle Valo long timeleft; 147120459ee2SKalle Valo int ret, i; 147220459ee2SKalle Valo 14735fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 14745fe4dffbSKalle Valo 147520459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 147620459ee2SKalle Valo if (ret) 147720459ee2SKalle Valo return ret; 147820459ee2SKalle Valo 147920459ee2SKalle Valo ret = ath6kl_configure_target(ar); 148020459ee2SKalle Valo if (ret) 148120459ee2SKalle Valo goto err_power_off; 148220459ee2SKalle Valo 148320459ee2SKalle Valo ret = ath6kl_init_upload(ar); 148420459ee2SKalle Valo if (ret) 148520459ee2SKalle Valo goto err_power_off; 148620459ee2SKalle Valo 148720459ee2SKalle Valo /* Do we need to finish the BMI phase */ 148820459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 148920459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 149020459ee2SKalle Valo ret = -EIO; 149120459ee2SKalle Valo goto err_power_off; 149220459ee2SKalle Valo } 149320459ee2SKalle Valo 149420459ee2SKalle Valo /* 149520459ee2SKalle Valo * The reason we have to wait for the target here is that the 149620459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 149720459ee2SKalle Valo * size. 149820459ee2SKalle Valo */ 149920459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 150020459ee2SKalle Valo ret = -EIO; 150120459ee2SKalle Valo goto err_power_off; 150220459ee2SKalle Valo } 150320459ee2SKalle Valo 150420459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 150520459ee2SKalle Valo ret = -EIO; 150620459ee2SKalle Valo goto err_cleanup_scatter; 150720459ee2SKalle Valo } 150820459ee2SKalle Valo 150920459ee2SKalle Valo /* setup credit distribution */ 151020459ee2SKalle Valo ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info); 151120459ee2SKalle Valo 151220459ee2SKalle Valo /* start HTC */ 151320459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 151420459ee2SKalle Valo if (ret) { 151520459ee2SKalle Valo /* FIXME: call this */ 151620459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 151720459ee2SKalle Valo goto err_cleanup_scatter; 151820459ee2SKalle Valo } 151920459ee2SKalle Valo 152020459ee2SKalle Valo /* Wait for Wmi event to be ready */ 152120459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 152220459ee2SKalle Valo test_bit(WMI_READY, 152320459ee2SKalle Valo &ar->flag), 152420459ee2SKalle Valo WMI_TIMEOUT); 152520459ee2SKalle Valo 152620459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 152720459ee2SKalle Valo 1528293badf4SKalle Valo 1529293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 153065a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1531293badf4SKalle Valo ar->hw.name, 1532293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1533293badf4SKalle Valo ar->wiphy->fw_version, 153465a8b4ccSKalle Valo ar->fw_api, 1535293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1536293badf4SKalle Valo } 1537293badf4SKalle Valo 153820459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 153920459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 154020459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 154120459ee2SKalle Valo ret = -EIO; 154220459ee2SKalle Valo goto err_htc_stop; 154320459ee2SKalle Valo } 154420459ee2SKalle Valo 154520459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 154620459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 154720459ee2SKalle Valo ret = -EIO; 154820459ee2SKalle Valo goto err_htc_stop; 154920459ee2SKalle Valo } 155020459ee2SKalle Valo 155120459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 155220459ee2SKalle Valo 155320459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 155420459ee2SKalle Valo /* FIXME: return error */ 155520459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 155620459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 155720459ee2SKalle Valo 155871f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 155920459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 156020459ee2SKalle Valo if (ret) 156120459ee2SKalle Valo goto err_htc_stop; 156220459ee2SKalle Valo } 156320459ee2SKalle Valo 156476a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 156576a9fbe2SKalle Valo 156620459ee2SKalle Valo return 0; 156720459ee2SKalle Valo 156820459ee2SKalle Valo err_htc_stop: 156920459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 157020459ee2SKalle Valo err_cleanup_scatter: 157120459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 157220459ee2SKalle Valo err_power_off: 157320459ee2SKalle Valo ath6kl_hif_power_off(ar); 157420459ee2SKalle Valo 157520459ee2SKalle Valo return ret; 157620459ee2SKalle Valo } 157720459ee2SKalle Valo 15785fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 15795fe4dffbSKalle Valo { 15805fe4dffbSKalle Valo int ret; 15815fe4dffbSKalle Valo 15825fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 15835fe4dffbSKalle Valo 15845fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 15855fe4dffbSKalle Valo 15865fe4dffbSKalle Valo ath6kl_hif_stop(ar); 15875fe4dffbSKalle Valo 15885fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 15895fe4dffbSKalle Valo 15905fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 15915fe4dffbSKalle Valo if (ret) 15925fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 15935fe4dffbSKalle Valo 159476a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 159576a9fbe2SKalle Valo 15965fe4dffbSKalle Valo return 0; 15975fe4dffbSKalle Valo } 15985fe4dffbSKalle Valo 1599c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ 160055055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 16016db8fa53SVasanthakumar Thiagarajan { 16026db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 16036db8fa53SVasanthakumar Thiagarajan bool discon_issued; 16046db8fa53SVasanthakumar Thiagarajan 16056db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 16066db8fa53SVasanthakumar Thiagarajan 16076db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 16086db8fa53SVasanthakumar Thiagarajan 16096db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 16106db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 16116db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 16126db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 16136db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 16146db8fa53SVasanthakumar Thiagarajan 16156db8fa53SVasanthakumar Thiagarajan if (discon_issued) 16166db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 16176db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 16186db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 16196db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 16206db8fa53SVasanthakumar Thiagarajan } 16216db8fa53SVasanthakumar Thiagarajan 16226db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 16236db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 16246db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 16256db8fa53SVasanthakumar Thiagarajan } 16266db8fa53SVasanthakumar Thiagarajan } 16276db8fa53SVasanthakumar Thiagarajan 1628bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1629bdcd8170SKalle Valo { 1630990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 16311d2a4456SVasanthakumar Thiagarajan int i; 1632bdcd8170SKalle Valo 1633bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1634bdcd8170SKalle Valo 1635bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1636bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1637bdcd8170SKalle Valo return; 1638bdcd8170SKalle Valo } 1639bdcd8170SKalle Valo 16401d2a4456SVasanthakumar Thiagarajan for (i = 0; i < AP_MAX_NUM_STA; i++) 16411d2a4456SVasanthakumar Thiagarajan aggr_reset_state(ar->sta_list[i].aggr_conn); 16421d2a4456SVasanthakumar Thiagarajan 164311f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1644990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1645990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 164611f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1647990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 164827929723SVasanthakumar Thiagarajan rtnl_lock(); 1649c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif); 165027929723SVasanthakumar Thiagarajan rtnl_unlock(); 165111f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1652990bd915SVasanthakumar Thiagarajan } 165311f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1654bdcd8170SKalle Valo 16556db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 16566db8fa53SVasanthakumar Thiagarajan 16576db8fa53SVasanthakumar Thiagarajan /* 16586db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 16596db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 16606db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 16616db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 16626db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 16636db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 16646db8fa53SVasanthakumar Thiagarajan * are collected. 16656db8fa53SVasanthakumar Thiagarajan */ 16666db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 16676db8fa53SVasanthakumar Thiagarajan 16686db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 16696db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 16706db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 16716db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1672bdcd8170SKalle Valo } 1673bdcd8170SKalle Valo 1674bdcd8170SKalle Valo /* 16756db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 16766db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1677bdcd8170SKalle Valo */ 16786db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 16796db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 16806db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1681bdcd8170SKalle Valo 16826db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1683e8ad9a06SVasanthakumar Thiagarajan 1684e8ad9a06SVasanthakumar Thiagarajan up(&ar->sem); 1685bdcd8170SKalle Valo } 1686d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx); 1687