1bdcd8170SKalle Valo 
2bdcd8170SKalle Valo /*
3bdcd8170SKalle Valo  * Copyright (c) 2011 Atheros Communications Inc.
41b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
5bdcd8170SKalle Valo  *
6bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
7bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
8bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
9bdcd8170SKalle Valo  *
10bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17bdcd8170SKalle Valo  */
18bdcd8170SKalle Valo 
19c6efe578SStephen Rothwell #include <linux/moduleparam.h>
20f7830202SSangwook Lee #include <linux/errno.h>
21d6a434d6SKalle Valo #include <linux/export.h>
2292ecbff4SSam Leffler #include <linux/of.h>
23bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h>
24d6a434d6SKalle Valo 
25bdcd8170SKalle Valo #include "core.h"
26bdcd8170SKalle Valo #include "cfg80211.h"
27bdcd8170SKalle Valo #include "target.h"
28bdcd8170SKalle Valo #include "debug.h"
29bdcd8170SKalle Valo #include "hif-ops.h"
30bdcd8170SKalle Valo 
31856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = {
32856f4b31SKalle Valo 	{
330d0192baSKalle Valo 		.id				= AR6003_HW_2_0_VERSION,
34293badf4SKalle Valo 		.name				= "ar6003 hw 2.0",
35856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57e884,
36856f4b31SKalle Valo 		.app_load_addr			= 0x543180,
37856f4b31SKalle Valo 		.board_ext_data_addr		= 0x57e500,
38856f4b31SKalle Valo 		.reserved_ram_size		= 6912,
3939586bf2SRyan Hsu 		.refclk_hz			= 26000000,
4039586bf2SRyan Hsu 		.uarttx_pin			= 8,
41856f4b31SKalle Valo 
42856f4b31SKalle Valo 		/* hw2.0 needs override address hardcoded */
43856f4b31SKalle Valo 		.app_start_override_addr	= 0x944C00,
44d1a9421dSKalle Valo 
45c0038972SKalle Valo 		.fw = {
46c0038972SKalle Valo 			.dir		= AR6003_HW_2_0_FW_DIR,
47c0038972SKalle Valo 			.otp		= AR6003_HW_2_0_OTP_FILE,
48d1a9421dSKalle Valo 			.fw		= AR6003_HW_2_0_FIRMWARE_FILE,
49c0038972SKalle Valo 			.tcmd		= AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
50c0038972SKalle Valo 			.patch		= AR6003_HW_2_0_PATCH_FILE,
51c0038972SKalle Valo 		},
52c0038972SKalle Valo 
53d1a9421dSKalle Valo 		.fw_board		= AR6003_HW_2_0_BOARD_DATA_FILE,
54d1a9421dSKalle Valo 		.fw_default_board	= AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
55856f4b31SKalle Valo 	},
56856f4b31SKalle Valo 	{
570d0192baSKalle Valo 		.id				= AR6003_HW_2_1_1_VERSION,
58293badf4SKalle Valo 		.name				= "ar6003 hw 2.1.1",
59856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57ff74,
60856f4b31SKalle Valo 		.app_load_addr			= 0x1234,
61856f4b31SKalle Valo 		.board_ext_data_addr		= 0x542330,
62856f4b31SKalle Valo 		.reserved_ram_size		= 512,
6339586bf2SRyan Hsu 		.refclk_hz			= 26000000,
6439586bf2SRyan Hsu 		.uarttx_pin			= 8,
65cd23c1c9SAlex Yang 		.testscript_addr		= 0x57ef74,
66d1a9421dSKalle Valo 
67c0038972SKalle Valo 		.fw = {
68c0038972SKalle Valo 			.dir		= AR6003_HW_2_1_1_FW_DIR,
69c0038972SKalle Valo 			.otp		= AR6003_HW_2_1_1_OTP_FILE,
70d1a9421dSKalle Valo 			.fw		= AR6003_HW_2_1_1_FIRMWARE_FILE,
71c0038972SKalle Valo 			.tcmd		= AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
72c0038972SKalle Valo 			.patch		= AR6003_HW_2_1_1_PATCH_FILE,
73cd23c1c9SAlex Yang 			.utf		= AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
74cd23c1c9SAlex Yang 			.testscript	= AR6003_HW_2_1_1_TESTSCRIPT_FILE,
75c0038972SKalle Valo 		},
76c0038972SKalle Valo 
77d1a9421dSKalle Valo 		.fw_board		= AR6003_HW_2_1_1_BOARD_DATA_FILE,
78d1a9421dSKalle Valo 		.fw_default_board	= AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
79856f4b31SKalle Valo 	},
80856f4b31SKalle Valo 	{
810d0192baSKalle Valo 		.id				= AR6004_HW_1_0_VERSION,
82293badf4SKalle Valo 		.name				= "ar6004 hw 1.0",
83856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57e884,
84856f4b31SKalle Valo 		.app_load_addr			= 0x1234,
85856f4b31SKalle Valo 		.board_ext_data_addr		= 0x437000,
86856f4b31SKalle Valo 		.reserved_ram_size		= 19456,
870d4d72bfSKalle Valo 		.board_addr			= 0x433900,
8839586bf2SRyan Hsu 		.refclk_hz			= 26000000,
8939586bf2SRyan Hsu 		.uarttx_pin			= 11,
90d1a9421dSKalle Valo 
91c0038972SKalle Valo 		.fw = {
92c0038972SKalle Valo 			.dir		= AR6004_HW_1_0_FW_DIR,
93d1a9421dSKalle Valo 			.fw		= AR6004_HW_1_0_FIRMWARE_FILE,
94c0038972SKalle Valo 		},
95c0038972SKalle Valo 
96d1a9421dSKalle Valo 		.fw_board		= AR6004_HW_1_0_BOARD_DATA_FILE,
97d1a9421dSKalle Valo 		.fw_default_board	= AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
98856f4b31SKalle Valo 	},
99856f4b31SKalle Valo 	{
1000d0192baSKalle Valo 		.id				= AR6004_HW_1_1_VERSION,
101293badf4SKalle Valo 		.name				= "ar6004 hw 1.1",
102856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57e884,
103856f4b31SKalle Valo 		.app_load_addr			= 0x1234,
104856f4b31SKalle Valo 		.board_ext_data_addr		= 0x437000,
105856f4b31SKalle Valo 		.reserved_ram_size		= 11264,
1060d4d72bfSKalle Valo 		.board_addr			= 0x43d400,
10739586bf2SRyan Hsu 		.refclk_hz			= 40000000,
10839586bf2SRyan Hsu 		.uarttx_pin			= 11,
109d1a9421dSKalle Valo 
110c0038972SKalle Valo 		.fw = {
111c0038972SKalle Valo 			.dir		= AR6004_HW_1_1_FW_DIR,
112d1a9421dSKalle Valo 			.fw		= AR6004_HW_1_1_FIRMWARE_FILE,
113c0038972SKalle Valo 		},
114c0038972SKalle Valo 
115d1a9421dSKalle Valo 		.fw_board		= AR6004_HW_1_1_BOARD_DATA_FILE,
116d1a9421dSKalle Valo 		.fw_default_board	= AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
117856f4b31SKalle Valo 	},
118856f4b31SKalle Valo };
119856f4b31SKalle Valo 
120bdcd8170SKalle Valo /*
121bdcd8170SKalle Valo  * Include definitions here that can be used to tune the WLAN module
122bdcd8170SKalle Valo  * behavior. Different customers can tune the behavior as per their needs,
123bdcd8170SKalle Valo  * here.
124bdcd8170SKalle Valo  */
125bdcd8170SKalle Valo 
126bdcd8170SKalle Valo /*
127bdcd8170SKalle Valo  * This configuration item enable/disable keepalive support.
128bdcd8170SKalle Valo  * Keepalive support: In the absence of any data traffic to AP, null
129bdcd8170SKalle Valo  * frames will be sent to the AP at periodic interval, to keep the association
130bdcd8170SKalle Valo  * active. This configuration item defines the periodic interval.
131bdcd8170SKalle Valo  * Use value of zero to disable keepalive support
132bdcd8170SKalle Valo  * Default: 60 seconds
133bdcd8170SKalle Valo  */
134bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
135bdcd8170SKalle Valo 
136bdcd8170SKalle Valo /*
137bdcd8170SKalle Valo  * This configuration item sets the value of disconnect timeout
138bdcd8170SKalle Valo  * Firmware delays sending the disconnec event to the host for this
139bdcd8170SKalle Valo  * timeout after is gets disconnected from the current AP.
140bdcd8170SKalle Valo  * If the firmware successly roams within the disconnect timeout
141bdcd8170SKalle Valo  * it sends a new connect event
142bdcd8170SKalle Valo  */
143bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
144bdcd8170SKalle Valo 
145bdcd8170SKalle Valo 
146bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET    64
147bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size)
148bdcd8170SKalle Valo {
149bdcd8170SKalle Valo 	struct sk_buff *skb;
150bdcd8170SKalle Valo 	u16 reserved;
151bdcd8170SKalle Valo 
152bdcd8170SKalle Valo 	/* Add chacheline space at front and back of buffer */
153bdcd8170SKalle Valo 	reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
1541df94a85SVasanthakumar Thiagarajan 		   sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
155bdcd8170SKalle Valo 	skb = dev_alloc_skb(size + reserved);
156bdcd8170SKalle Valo 
157bdcd8170SKalle Valo 	if (skb)
158bdcd8170SKalle Valo 		skb_reserve(skb, reserved - L1_CACHE_BYTES);
159bdcd8170SKalle Valo 	return skb;
160bdcd8170SKalle Valo }
161bdcd8170SKalle Valo 
162e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif)
163bdcd8170SKalle Valo {
1643450334fSVasanthakumar Thiagarajan 	vif->ssid_len = 0;
1653450334fSVasanthakumar Thiagarajan 	memset(vif->ssid, 0, sizeof(vif->ssid));
1663450334fSVasanthakumar Thiagarajan 
1673450334fSVasanthakumar Thiagarajan 	vif->dot11_auth_mode = OPEN_AUTH;
1683450334fSVasanthakumar Thiagarajan 	vif->auth_mode = NONE_AUTH;
1693450334fSVasanthakumar Thiagarajan 	vif->prwise_crypto = NONE_CRYPT;
1703450334fSVasanthakumar Thiagarajan 	vif->prwise_crypto_len = 0;
1713450334fSVasanthakumar Thiagarajan 	vif->grp_crypto = NONE_CRYPT;
1723450334fSVasanthakumar Thiagarajan 	vif->grp_crypto_len = 0;
1736f2a73f9SVasanthakumar Thiagarajan 	memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
1748c8b65e3SVasanthakumar Thiagarajan 	memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
1758c8b65e3SVasanthakumar Thiagarajan 	memset(vif->bssid, 0, sizeof(vif->bssid));
176f74bac54SVasanthakumar Thiagarajan 	vif->bss_ch = 0;
177bdcd8170SKalle Valo }
178bdcd8170SKalle Valo 
179bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar)
180bdcd8170SKalle Valo {
181bdcd8170SKalle Valo 	u32 address, data;
182bdcd8170SKalle Valo 	struct host_app_area host_app_area;
183bdcd8170SKalle Valo 
184bdcd8170SKalle Valo 	/* Fetch the address of the host_app_area_s
185bdcd8170SKalle Valo 	 * instance in the host interest area */
186bdcd8170SKalle Valo 	address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
18731024d99SKevin Fang 	address = TARG_VTOP(ar->target_type, address);
188bdcd8170SKalle Valo 
189addb44beSKalle Valo 	if (ath6kl_diag_read32(ar, address, &data))
190bdcd8170SKalle Valo 		return -EIO;
191bdcd8170SKalle Valo 
19231024d99SKevin Fang 	address = TARG_VTOP(ar->target_type, data);
193cbf49a6fSKalle Valo 	host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
194addb44beSKalle Valo 	if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
195addb44beSKalle Valo 			      sizeof(struct host_app_area)))
196bdcd8170SKalle Valo 		return -EIO;
197bdcd8170SKalle Valo 
198bdcd8170SKalle Valo 	return 0;
199bdcd8170SKalle Valo }
200bdcd8170SKalle Valo 
201bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar,
202bdcd8170SKalle Valo 				  u8 ac,
203bdcd8170SKalle Valo 				  enum htc_endpoint_id ep)
204bdcd8170SKalle Valo {
205bdcd8170SKalle Valo 	ar->ac2ep_map[ac] = ep;
206bdcd8170SKalle Valo 	ar->ep2ac_map[ep] = ac;
207bdcd8170SKalle Valo }
208bdcd8170SKalle Valo 
209bdcd8170SKalle Valo /* connect to a service */
210bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar,
211bdcd8170SKalle Valo 				 struct htc_service_connect_req  *con_req,
212bdcd8170SKalle Valo 				 char *desc)
213bdcd8170SKalle Valo {
214bdcd8170SKalle Valo 	int status;
215bdcd8170SKalle Valo 	struct htc_service_connect_resp response;
216bdcd8170SKalle Valo 
217bdcd8170SKalle Valo 	memset(&response, 0, sizeof(response));
218bdcd8170SKalle Valo 
219ad226ec2SKalle Valo 	status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
220bdcd8170SKalle Valo 	if (status) {
221bdcd8170SKalle Valo 		ath6kl_err("failed to connect to %s service status:%d\n",
222bdcd8170SKalle Valo 			   desc, status);
223bdcd8170SKalle Valo 		return status;
224bdcd8170SKalle Valo 	}
225bdcd8170SKalle Valo 
226bdcd8170SKalle Valo 	switch (con_req->svc_id) {
227bdcd8170SKalle Valo 	case WMI_CONTROL_SVC:
228bdcd8170SKalle Valo 		if (test_bit(WMI_ENABLED, &ar->flag))
229bdcd8170SKalle Valo 			ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
230bdcd8170SKalle Valo 		ar->ctrl_ep = response.endpoint;
231bdcd8170SKalle Valo 		break;
232bdcd8170SKalle Valo 	case WMI_DATA_BE_SVC:
233bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
234bdcd8170SKalle Valo 		break;
235bdcd8170SKalle Valo 	case WMI_DATA_BK_SVC:
236bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
237bdcd8170SKalle Valo 		break;
238bdcd8170SKalle Valo 	case WMI_DATA_VI_SVC:
239bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
240bdcd8170SKalle Valo 		break;
241bdcd8170SKalle Valo 	case WMI_DATA_VO_SVC:
242bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
243bdcd8170SKalle Valo 		break;
244bdcd8170SKalle Valo 	default:
245bdcd8170SKalle Valo 		ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
246bdcd8170SKalle Valo 		return -EINVAL;
247bdcd8170SKalle Valo 	}
248bdcd8170SKalle Valo 
249bdcd8170SKalle Valo 	return 0;
250bdcd8170SKalle Valo }
251bdcd8170SKalle Valo 
252bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar)
253bdcd8170SKalle Valo {
254bdcd8170SKalle Valo 	struct htc_service_connect_req connect;
255bdcd8170SKalle Valo 
256bdcd8170SKalle Valo 	memset(&connect, 0, sizeof(connect));
257bdcd8170SKalle Valo 
258bdcd8170SKalle Valo 	/* these fields are the same for all service endpoints */
259bdcd8170SKalle Valo 	connect.ep_cb.rx = ath6kl_rx;
260bdcd8170SKalle Valo 	connect.ep_cb.rx_refill = ath6kl_rx_refill;
261bdcd8170SKalle Valo 	connect.ep_cb.tx_full = ath6kl_tx_queue_full;
262bdcd8170SKalle Valo 
263bdcd8170SKalle Valo 	/*
264bdcd8170SKalle Valo 	 * Set the max queue depth so that our ath6kl_tx_queue_full handler
265bdcd8170SKalle Valo 	 * gets called.
266bdcd8170SKalle Valo 	*/
267bdcd8170SKalle Valo 	connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
268bdcd8170SKalle Valo 	connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
269bdcd8170SKalle Valo 	if (!connect.ep_cb.rx_refill_thresh)
270bdcd8170SKalle Valo 		connect.ep_cb.rx_refill_thresh++;
271bdcd8170SKalle Valo 
272bdcd8170SKalle Valo 	/* connect to control service */
273bdcd8170SKalle Valo 	connect.svc_id = WMI_CONTROL_SVC;
274bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
275bdcd8170SKalle Valo 		return -EIO;
276bdcd8170SKalle Valo 
277bdcd8170SKalle Valo 	connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
278bdcd8170SKalle Valo 
279bdcd8170SKalle Valo 	/*
280bdcd8170SKalle Valo 	 * Limit the HTC message size on the send path, although e can
281bdcd8170SKalle Valo 	 * receive A-MSDU frames of 4K, we will only send ethernet-sized
282bdcd8170SKalle Valo 	 * (802.3) frames on the send path.
283bdcd8170SKalle Valo 	 */
284bdcd8170SKalle Valo 	connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
285bdcd8170SKalle Valo 
286bdcd8170SKalle Valo 	/*
287bdcd8170SKalle Valo 	 * To reduce the amount of committed memory for larger A_MSDU
288bdcd8170SKalle Valo 	 * frames, use the recv-alloc threshold mechanism for larger
289bdcd8170SKalle Valo 	 * packets.
290bdcd8170SKalle Valo 	 */
291bdcd8170SKalle Valo 	connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
292bdcd8170SKalle Valo 	connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
293bdcd8170SKalle Valo 
294bdcd8170SKalle Valo 	/*
295bdcd8170SKalle Valo 	 * For the remaining data services set the connection flag to
296bdcd8170SKalle Valo 	 * reduce dribbling, if configured to do so.
297bdcd8170SKalle Valo 	 */
298bdcd8170SKalle Valo 	connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
299bdcd8170SKalle Valo 	connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
300bdcd8170SKalle Valo 	connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
301bdcd8170SKalle Valo 
302bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_BE_SVC;
303bdcd8170SKalle Valo 
304bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
305bdcd8170SKalle Valo 		return -EIO;
306bdcd8170SKalle Valo 
307bdcd8170SKalle Valo 	/* connect to back-ground map this to WMI LOW_PRI */
308bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_BK_SVC;
309bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
310bdcd8170SKalle Valo 		return -EIO;
311bdcd8170SKalle Valo 
312bdcd8170SKalle Valo 	/* connect to Video service, map this to to HI PRI */
313bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_VI_SVC;
314bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
315bdcd8170SKalle Valo 		return -EIO;
316bdcd8170SKalle Valo 
317bdcd8170SKalle Valo 	/*
318bdcd8170SKalle Valo 	 * Connect to VO service, this is currently not mapped to a WMI
319bdcd8170SKalle Valo 	 * priority stream due to historical reasons. WMI originally
320bdcd8170SKalle Valo 	 * defined 3 priorities over 3 mailboxes We can change this when
321bdcd8170SKalle Valo 	 * WMI is reworked so that priorities are not dependent on
322bdcd8170SKalle Valo 	 * mailboxes.
323bdcd8170SKalle Valo 	 */
324bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_VO_SVC;
325bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
326bdcd8170SKalle Valo 		return -EIO;
327bdcd8170SKalle Valo 
328bdcd8170SKalle Valo 	return 0;
329bdcd8170SKalle Valo }
330bdcd8170SKalle Valo 
331e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif)
332bdcd8170SKalle Valo {
333e29f25f5SVasanthakumar Thiagarajan 	ath6kl_init_profile_info(vif);
3343450334fSVasanthakumar Thiagarajan 	vif->def_txkey_index = 0;
3356f2a73f9SVasanthakumar Thiagarajan 	memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
336f74bac54SVasanthakumar Thiagarajan 	vif->ch_hint = 0;
337bdcd8170SKalle Valo }
338bdcd8170SKalle Valo 
339bdcd8170SKalle Valo /*
340bdcd8170SKalle Valo  * Set HTC/Mbox operational parameters, this can only be called when the
341bdcd8170SKalle Valo  * target is in the BMI phase.
342bdcd8170SKalle Valo  */
343bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
344bdcd8170SKalle Valo 				 u8 htc_ctrl_buf)
345bdcd8170SKalle Valo {
346bdcd8170SKalle Valo 	int status;
347bdcd8170SKalle Valo 	u32 blk_size;
348bdcd8170SKalle Valo 
349bdcd8170SKalle Valo 	blk_size = ar->mbox_info.block_size;
350bdcd8170SKalle Valo 
351bdcd8170SKalle Valo 	if (htc_ctrl_buf)
352bdcd8170SKalle Valo 		blk_size |=  ((u32)htc_ctrl_buf) << 16;
353bdcd8170SKalle Valo 
354bdcd8170SKalle Valo 	/* set the host interest area for the block size */
35524fc32b3SKalle Valo 	status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
356bdcd8170SKalle Valo 	if (status) {
357bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for IO block size failed\n");
358bdcd8170SKalle Valo 		goto out;
359bdcd8170SKalle Valo 	}
360bdcd8170SKalle Valo 
361bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
362bdcd8170SKalle Valo 		   blk_size,
363bdcd8170SKalle Valo 		   ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
364bdcd8170SKalle Valo 
365bdcd8170SKalle Valo 	if (mbox_isr_yield_val) {
366bdcd8170SKalle Valo 		/* set the host interest area for the mbox ISR yield limit */
36724fc32b3SKalle Valo 		status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
36824fc32b3SKalle Valo 					       mbox_isr_yield_val);
369bdcd8170SKalle Valo 		if (status) {
370bdcd8170SKalle Valo 			ath6kl_err("bmi_write_memory for yield limit failed\n");
371bdcd8170SKalle Valo 			goto out;
372bdcd8170SKalle Valo 		}
373bdcd8170SKalle Valo 	}
374bdcd8170SKalle Valo 
375bdcd8170SKalle Valo out:
376bdcd8170SKalle Valo 	return status;
377bdcd8170SKalle Valo }
378bdcd8170SKalle Valo 
3790ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
380bdcd8170SKalle Valo {
381bdcd8170SKalle Valo 	int status = 0;
3824dea08e0SJouni Malinen 	int ret;
383bdcd8170SKalle Valo 
384bdcd8170SKalle Valo 	/*
385bdcd8170SKalle Valo 	 * Configure the device for rx dot11 header rules. "0,0" are the
386bdcd8170SKalle Valo 	 * default values. Required if checksum offload is needed. Set
387bdcd8170SKalle Valo 	 * RxMetaVersion to 2.
388bdcd8170SKalle Valo 	 */
3890ce59445SVasanthakumar Thiagarajan 	if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
390bdcd8170SKalle Valo 					       ar->rx_meta_ver, 0, 0)) {
391bdcd8170SKalle Valo 		ath6kl_err("unable to set the rx frame format\n");
392bdcd8170SKalle Valo 		status = -EIO;
393bdcd8170SKalle Valo 	}
394bdcd8170SKalle Valo 
395bdcd8170SKalle Valo 	if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN)
3960ce59445SVasanthakumar Thiagarajan 		if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
397bdcd8170SKalle Valo 		     IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
398bdcd8170SKalle Valo 			ath6kl_err("unable to set power save fail event policy\n");
399bdcd8170SKalle Valo 			status = -EIO;
400bdcd8170SKalle Valo 		}
401bdcd8170SKalle Valo 
402bdcd8170SKalle Valo 	if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER))
4030ce59445SVasanthakumar Thiagarajan 		if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
404bdcd8170SKalle Valo 		     WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) {
405bdcd8170SKalle Valo 			ath6kl_err("unable to set barker preamble policy\n");
406bdcd8170SKalle Valo 			status = -EIO;
407bdcd8170SKalle Valo 		}
408bdcd8170SKalle Valo 
4090ce59445SVasanthakumar Thiagarajan 	if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
410bdcd8170SKalle Valo 					 WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) {
411bdcd8170SKalle Valo 		ath6kl_err("unable to set keep alive interval\n");
412bdcd8170SKalle Valo 		status = -EIO;
413bdcd8170SKalle Valo 	}
414bdcd8170SKalle Valo 
4150ce59445SVasanthakumar Thiagarajan 	if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
416bdcd8170SKalle Valo 				       WLAN_CONFIG_DISCONNECT_TIMEOUT)) {
417bdcd8170SKalle Valo 		ath6kl_err("unable to set disconnect timeout\n");
418bdcd8170SKalle Valo 		status = -EIO;
419bdcd8170SKalle Valo 	}
420bdcd8170SKalle Valo 
421bdcd8170SKalle Valo 	if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST))
4220ce59445SVasanthakumar Thiagarajan 		if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) {
423bdcd8170SKalle Valo 			ath6kl_err("unable to set txop bursting\n");
424bdcd8170SKalle Valo 			status = -EIO;
425bdcd8170SKalle Valo 		}
426bdcd8170SKalle Valo 
427b64de356SVasanthakumar Thiagarajan 	if (ar->p2p && (ar->vif_max == 1 || idx)) {
4280ce59445SVasanthakumar Thiagarajan 		ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
4296bbc7c35SJouni Malinen 					      P2P_FLAG_CAPABILITIES_REQ |
4304dea08e0SJouni Malinen 					      P2P_FLAG_MACADDR_REQ |
4314dea08e0SJouni Malinen 					      P2P_FLAG_HMODEL_REQ);
4324dea08e0SJouni Malinen 		if (ret) {
4334dea08e0SJouni Malinen 			ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
4346bbc7c35SJouni Malinen 				   "capabilities (%d) - assuming P2P not "
4356bbc7c35SJouni Malinen 				   "supported\n", ret);
4363db1cd5cSRusty Russell 			ar->p2p = false;
4376bbc7c35SJouni Malinen 		}
4386bbc7c35SJouni Malinen 	}
4396bbc7c35SJouni Malinen 
440b64de356SVasanthakumar Thiagarajan 	if (ar->p2p && (ar->vif_max == 1 || idx)) {
4416bbc7c35SJouni Malinen 		/* Enable Probe Request reporting for P2P */
4420ce59445SVasanthakumar Thiagarajan 		ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
4436bbc7c35SJouni Malinen 		if (ret) {
4446bbc7c35SJouni Malinen 			ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
4456bbc7c35SJouni Malinen 				   "Request reporting (%d)\n", ret);
4466bbc7c35SJouni Malinen 		}
4474dea08e0SJouni Malinen 	}
4484dea08e0SJouni Malinen 
449bdcd8170SKalle Valo 	return status;
450bdcd8170SKalle Valo }
451bdcd8170SKalle Valo 
452bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar)
453bdcd8170SKalle Valo {
454bdcd8170SKalle Valo 	u32 param, ram_reserved_size;
4553226f68aSVasanthakumar Thiagarajan 	u8 fw_iftype, fw_mode = 0, fw_submode = 0;
45639586bf2SRyan Hsu 	int i, status;
457bdcd8170SKalle Valo 
458f29af978SKalle Valo 	param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
45924fc32b3SKalle Valo 	if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
460a10e2f2fSVasanthakumar Thiagarajan 		ath6kl_err("bmi_write_memory for uart debug failed\n");
461a10e2f2fSVasanthakumar Thiagarajan 		return -EIO;
462a10e2f2fSVasanthakumar Thiagarajan 	}
463a10e2f2fSVasanthakumar Thiagarajan 
4647b85832dSVasanthakumar Thiagarajan 	/*
4657b85832dSVasanthakumar Thiagarajan 	 * Note: Even though the firmware interface type is
4667b85832dSVasanthakumar Thiagarajan 	 * chosen as BSS_STA for all three interfaces, can
4677b85832dSVasanthakumar Thiagarajan 	 * be configured to IBSS/AP as long as the fw submode
4687b85832dSVasanthakumar Thiagarajan 	 * remains normal mode (0 - AP, STA and IBSS). But
4697b85832dSVasanthakumar Thiagarajan 	 * due to an target assert in firmware only one interface is
4707b85832dSVasanthakumar Thiagarajan 	 * configured for now.
4717b85832dSVasanthakumar Thiagarajan 	 */
472dd3751f7SVasanthakumar Thiagarajan 	fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
473bdcd8170SKalle Valo 
47471f96ee6SKalle Valo 	for (i = 0; i < ar->vif_max; i++)
4757b85832dSVasanthakumar Thiagarajan 		fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
4767b85832dSVasanthakumar Thiagarajan 
4777b85832dSVasanthakumar Thiagarajan 	/*
4783226f68aSVasanthakumar Thiagarajan 	 * By default, submodes :
4793226f68aSVasanthakumar Thiagarajan 	 *		vif[0] - AP/STA/IBSS
4807b85832dSVasanthakumar Thiagarajan 	 *		vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
4817b85832dSVasanthakumar Thiagarajan 	 *		vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
4827b85832dSVasanthakumar Thiagarajan 	 */
4833226f68aSVasanthakumar Thiagarajan 
4843226f68aSVasanthakumar Thiagarajan 	for (i = 0; i < ar->max_norm_iface; i++)
4853226f68aSVasanthakumar Thiagarajan 		fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
4863226f68aSVasanthakumar Thiagarajan 			      (i * HI_OPTION_FW_SUBMODE_BITS);
4873226f68aSVasanthakumar Thiagarajan 
48871f96ee6SKalle Valo 	for (i = ar->max_norm_iface; i < ar->vif_max; i++)
4893226f68aSVasanthakumar Thiagarajan 		fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
4903226f68aSVasanthakumar Thiagarajan 			      (i * HI_OPTION_FW_SUBMODE_BITS);
4917b85832dSVasanthakumar Thiagarajan 
492b64de356SVasanthakumar Thiagarajan 	if (ar->p2p && ar->vif_max == 1)
4937b85832dSVasanthakumar Thiagarajan 		fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
4947b85832dSVasanthakumar Thiagarajan 
49524fc32b3SKalle Valo 	if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
49624fc32b3SKalle Valo 				  HTC_PROTOCOL_VERSION) != 0) {
497bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for htc version failed\n");
498bdcd8170SKalle Valo 		return -EIO;
499bdcd8170SKalle Valo 	}
500bdcd8170SKalle Valo 
501bdcd8170SKalle Valo 	/* set the firmware mode to STA/IBSS/AP */
502bdcd8170SKalle Valo 	param = 0;
503bdcd8170SKalle Valo 
50480fb2686SKalle Valo 	if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
505bdcd8170SKalle Valo 		ath6kl_err("bmi_read_memory for setting fwmode failed\n");
506bdcd8170SKalle Valo 		return -EIO;
507bdcd8170SKalle Valo 	}
508bdcd8170SKalle Valo 
50971f96ee6SKalle Valo 	param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
5107b85832dSVasanthakumar Thiagarajan 	param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
5117b85832dSVasanthakumar Thiagarajan 	param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
5127b85832dSVasanthakumar Thiagarajan 
513bdcd8170SKalle Valo 	param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
514bdcd8170SKalle Valo 	param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
515bdcd8170SKalle Valo 
51624fc32b3SKalle Valo 	if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
517bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for setting fwmode failed\n");
518bdcd8170SKalle Valo 		return -EIO;
519bdcd8170SKalle Valo 	}
520bdcd8170SKalle Valo 
521bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
522bdcd8170SKalle Valo 
523bdcd8170SKalle Valo 	/*
524bdcd8170SKalle Valo 	 * Hardcode the address use for the extended board data
525bdcd8170SKalle Valo 	 * Ideally this should be pre-allocate by the OS at boot time
526bdcd8170SKalle Valo 	 * But since it is a new feature and board data is loaded
527bdcd8170SKalle Valo 	 * at init time, we have to workaround this from host.
528bdcd8170SKalle Valo 	 * It is difficult to patch the firmware boot code,
529bdcd8170SKalle Valo 	 * but possible in theory.
530bdcd8170SKalle Valo 	 */
531bdcd8170SKalle Valo 
532991b27eaSKalle Valo 	param = ar->hw.board_ext_data_addr;
533991b27eaSKalle Valo 	ram_reserved_size = ar->hw.reserved_ram_size;
534bdcd8170SKalle Valo 
53524fc32b3SKalle Valo 	if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
536bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
537bdcd8170SKalle Valo 		return -EIO;
538bdcd8170SKalle Valo 	}
539991b27eaSKalle Valo 
54024fc32b3SKalle Valo 	if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
54124fc32b3SKalle Valo 				  ram_reserved_size) != 0) {
542bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
543bdcd8170SKalle Valo 		return -EIO;
544bdcd8170SKalle Valo 	}
545bdcd8170SKalle Valo 
546bdcd8170SKalle Valo 	/* set the block size for the target */
547bdcd8170SKalle Valo 	if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
548bdcd8170SKalle Valo 		/* use default number of control buffers */
549bdcd8170SKalle Valo 		return -EIO;
550bdcd8170SKalle Valo 
55139586bf2SRyan Hsu 	/* Configure GPIO AR600x UART */
55224fc32b3SKalle Valo 	status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
55324fc32b3SKalle Valo 				       ar->hw.uarttx_pin);
55439586bf2SRyan Hsu 	if (status)
55539586bf2SRyan Hsu 		return status;
55639586bf2SRyan Hsu 
55739586bf2SRyan Hsu 	/* Configure target refclk_hz */
55824fc32b3SKalle Valo 	status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
55939586bf2SRyan Hsu 	if (status)
56039586bf2SRyan Hsu 		return status;
56139586bf2SRyan Hsu 
562bdcd8170SKalle Valo 	return 0;
563bdcd8170SKalle Valo }
564bdcd8170SKalle Valo 
565bdcd8170SKalle Valo /* firmware upload */
566bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
567bdcd8170SKalle Valo 			 u8 **fw, size_t *fw_len)
568bdcd8170SKalle Valo {
569bdcd8170SKalle Valo 	const struct firmware *fw_entry;
570bdcd8170SKalle Valo 	int ret;
571bdcd8170SKalle Valo 
572bdcd8170SKalle Valo 	ret = request_firmware(&fw_entry, filename, ar->dev);
573bdcd8170SKalle Valo 	if (ret)
574bdcd8170SKalle Valo 		return ret;
575bdcd8170SKalle Valo 
576bdcd8170SKalle Valo 	*fw_len = fw_entry->size;
577bdcd8170SKalle Valo 	*fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
578bdcd8170SKalle Valo 
579bdcd8170SKalle Valo 	if (*fw == NULL)
580bdcd8170SKalle Valo 		ret = -ENOMEM;
581bdcd8170SKalle Valo 
582bdcd8170SKalle Valo 	release_firmware(fw_entry);
583bdcd8170SKalle Valo 
584bdcd8170SKalle Valo 	return ret;
585bdcd8170SKalle Valo }
586bdcd8170SKalle Valo 
58792ecbff4SSam Leffler #ifdef CONFIG_OF
58892ecbff4SSam Leffler /*
58992ecbff4SSam Leffler  * Check the device tree for a board-id and use it to construct
59092ecbff4SSam Leffler  * the pathname to the firmware file.  Used (for now) to find a
59192ecbff4SSam Leffler  * fallback to the "bdata.bin" file--typically a symlink to the
59292ecbff4SSam Leffler  * appropriate board-specific file.
59392ecbff4SSam Leffler  */
59492ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar)
59592ecbff4SSam Leffler {
59692ecbff4SSam Leffler 	static const char *board_id_prop = "atheros,board-id";
59792ecbff4SSam Leffler 	struct device_node *node;
59892ecbff4SSam Leffler 	char board_filename[64];
59992ecbff4SSam Leffler 	const char *board_id;
60092ecbff4SSam Leffler 	int ret;
60192ecbff4SSam Leffler 
60292ecbff4SSam Leffler 	for_each_compatible_node(node, NULL, "atheros,ath6kl") {
60392ecbff4SSam Leffler 		board_id = of_get_property(node, board_id_prop, NULL);
60492ecbff4SSam Leffler 		if (board_id == NULL) {
60592ecbff4SSam Leffler 			ath6kl_warn("No \"%s\" property on %s node.\n",
60692ecbff4SSam Leffler 				    board_id_prop, node->name);
60792ecbff4SSam Leffler 			continue;
60892ecbff4SSam Leffler 		}
60992ecbff4SSam Leffler 		snprintf(board_filename, sizeof(board_filename),
610c0038972SKalle Valo 			 "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
61192ecbff4SSam Leffler 
61292ecbff4SSam Leffler 		ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
61392ecbff4SSam Leffler 				    &ar->fw_board_len);
61492ecbff4SSam Leffler 		if (ret) {
61592ecbff4SSam Leffler 			ath6kl_err("Failed to get DT board file %s: %d\n",
61692ecbff4SSam Leffler 				   board_filename, ret);
61792ecbff4SSam Leffler 			continue;
61892ecbff4SSam Leffler 		}
61992ecbff4SSam Leffler 		return true;
62092ecbff4SSam Leffler 	}
62192ecbff4SSam Leffler 	return false;
62292ecbff4SSam Leffler }
62392ecbff4SSam Leffler #else
62492ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar)
62592ecbff4SSam Leffler {
62692ecbff4SSam Leffler 	return false;
62792ecbff4SSam Leffler }
62892ecbff4SSam Leffler #endif /* CONFIG_OF */
62992ecbff4SSam Leffler 
630bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar)
631bdcd8170SKalle Valo {
632bdcd8170SKalle Valo 	const char *filename;
633bdcd8170SKalle Valo 	int ret;
634bdcd8170SKalle Valo 
635772c31eeSKalle Valo 	if (ar->fw_board != NULL)
636772c31eeSKalle Valo 		return 0;
637772c31eeSKalle Valo 
638d1a9421dSKalle Valo 	if (WARN_ON(ar->hw.fw_board == NULL))
639d1a9421dSKalle Valo 		return -EINVAL;
640d1a9421dSKalle Valo 
641d1a9421dSKalle Valo 	filename = ar->hw.fw_board;
642bdcd8170SKalle Valo 
643bdcd8170SKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
644bdcd8170SKalle Valo 			    &ar->fw_board_len);
645bdcd8170SKalle Valo 	if (ret == 0) {
646bdcd8170SKalle Valo 		/* managed to get proper board file */
647bdcd8170SKalle Valo 		return 0;
648bdcd8170SKalle Valo 	}
649bdcd8170SKalle Valo 
65092ecbff4SSam Leffler 	if (check_device_tree(ar)) {
65192ecbff4SSam Leffler 		/* got board file from device tree */
65292ecbff4SSam Leffler 		return 0;
65392ecbff4SSam Leffler 	}
65492ecbff4SSam Leffler 
655bdcd8170SKalle Valo 	/* there was no proper board file, try to use default instead */
656bdcd8170SKalle Valo 	ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
657bdcd8170SKalle Valo 		    filename, ret);
658bdcd8170SKalle Valo 
659d1a9421dSKalle Valo 	filename = ar->hw.fw_default_board;
660bdcd8170SKalle Valo 
661bdcd8170SKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
662bdcd8170SKalle Valo 			    &ar->fw_board_len);
663bdcd8170SKalle Valo 	if (ret) {
664bdcd8170SKalle Valo 		ath6kl_err("Failed to get default board file %s: %d\n",
665bdcd8170SKalle Valo 			   filename, ret);
666bdcd8170SKalle Valo 		return ret;
667bdcd8170SKalle Valo 	}
668bdcd8170SKalle Valo 
669bdcd8170SKalle Valo 	ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
670bdcd8170SKalle Valo 	ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
671bdcd8170SKalle Valo 
672bdcd8170SKalle Valo 	return 0;
673bdcd8170SKalle Valo }
674bdcd8170SKalle Valo 
675772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar)
676772c31eeSKalle Valo {
677c0038972SKalle Valo 	char filename[100];
678772c31eeSKalle Valo 	int ret;
679772c31eeSKalle Valo 
680772c31eeSKalle Valo 	if (ar->fw_otp != NULL)
681772c31eeSKalle Valo 		return 0;
682772c31eeSKalle Valo 
683c0038972SKalle Valo 	if (ar->hw.fw.otp == NULL) {
684d1a9421dSKalle Valo 		ath6kl_dbg(ATH6KL_DBG_BOOT,
685d1a9421dSKalle Valo 			   "no OTP file configured for this hw\n");
686772c31eeSKalle Valo 		return 0;
687772c31eeSKalle Valo 	}
688772c31eeSKalle Valo 
689c0038972SKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s",
690c0038972SKalle Valo 		 ar->hw.fw.dir, ar->hw.fw.otp);
691d1a9421dSKalle Valo 
692772c31eeSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
693772c31eeSKalle Valo 			    &ar->fw_otp_len);
694772c31eeSKalle Valo 	if (ret) {
695772c31eeSKalle Valo 		ath6kl_err("Failed to get OTP file %s: %d\n",
696772c31eeSKalle Valo 			   filename, ret);
697772c31eeSKalle Valo 		return ret;
698772c31eeSKalle Valo 	}
699772c31eeSKalle Valo 
700772c31eeSKalle Valo 	return 0;
701772c31eeSKalle Valo }
702772c31eeSKalle Valo 
7035f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
704772c31eeSKalle Valo {
705c0038972SKalle Valo 	char filename[100];
706772c31eeSKalle Valo 	int ret;
707772c31eeSKalle Valo 
7085f1127ffSKalle Valo 	if (ar->testmode == 0)
709772c31eeSKalle Valo 		return 0;
710772c31eeSKalle Valo 
7115f1127ffSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
7125f1127ffSKalle Valo 
7135f1127ffSKalle Valo 	if (ar->testmode == 2) {
714cd23c1c9SAlex Yang 		if (ar->hw.fw.utf == NULL) {
715cd23c1c9SAlex Yang 			ath6kl_warn("testmode 2 not supported\n");
716cd23c1c9SAlex Yang 			return -EOPNOTSUPP;
717cd23c1c9SAlex Yang 		}
718cd23c1c9SAlex Yang 
719cd23c1c9SAlex Yang 		snprintf(filename, sizeof(filename), "%s/%s",
720cd23c1c9SAlex Yang 			 ar->hw.fw.dir, ar->hw.fw.utf);
721cd23c1c9SAlex Yang 	} else {
722c0038972SKalle Valo 		if (ar->hw.fw.tcmd == NULL) {
723cd23c1c9SAlex Yang 			ath6kl_warn("testmode 1 not supported\n");
724772c31eeSKalle Valo 			return -EOPNOTSUPP;
725772c31eeSKalle Valo 		}
726772c31eeSKalle Valo 
727c0038972SKalle Valo 		snprintf(filename, sizeof(filename), "%s/%s",
728c0038972SKalle Valo 			 ar->hw.fw.dir, ar->hw.fw.tcmd);
729cd23c1c9SAlex Yang 	}
7305f1127ffSKalle Valo 
731772c31eeSKalle Valo 	set_bit(TESTMODE, &ar->flag);
732772c31eeSKalle Valo 
7335f1127ffSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
7345f1127ffSKalle Valo 	if (ret) {
7355f1127ffSKalle Valo 		ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
7365f1127ffSKalle Valo 			   ar->testmode, filename, ret);
7375f1127ffSKalle Valo 		return ret;
738772c31eeSKalle Valo 	}
739772c31eeSKalle Valo 
7405f1127ffSKalle Valo 	return 0;
7415f1127ffSKalle Valo }
7425f1127ffSKalle Valo 
7435f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar)
7445f1127ffSKalle Valo {
7455f1127ffSKalle Valo 	char filename[100];
7465f1127ffSKalle Valo 	int ret;
7475f1127ffSKalle Valo 
7485f1127ffSKalle Valo 	if (ar->fw != NULL)
7495f1127ffSKalle Valo 		return 0;
7505f1127ffSKalle Valo 
751c0038972SKalle Valo 	/* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
752c0038972SKalle Valo 	if (WARN_ON(ar->hw.fw.fw == NULL))
753d1a9421dSKalle Valo 		return -EINVAL;
754d1a9421dSKalle Valo 
755c0038972SKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s",
756c0038972SKalle Valo 		 ar->hw.fw.dir, ar->hw.fw.fw);
757772c31eeSKalle Valo 
758772c31eeSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
759772c31eeSKalle Valo 	if (ret) {
760772c31eeSKalle Valo 		ath6kl_err("Failed to get firmware file %s: %d\n",
761772c31eeSKalle Valo 			   filename, ret);
762772c31eeSKalle Valo 		return ret;
763772c31eeSKalle Valo 	}
764772c31eeSKalle Valo 
765772c31eeSKalle Valo 	return 0;
766772c31eeSKalle Valo }
767772c31eeSKalle Valo 
768772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar)
769772c31eeSKalle Valo {
770c0038972SKalle Valo 	char filename[100];
771772c31eeSKalle Valo 	int ret;
772772c31eeSKalle Valo 
773d1a9421dSKalle Valo 	if (ar->fw_patch != NULL)
774772c31eeSKalle Valo 		return 0;
775772c31eeSKalle Valo 
776c0038972SKalle Valo 	if (ar->hw.fw.patch == NULL)
777d1a9421dSKalle Valo 		return 0;
778d1a9421dSKalle Valo 
779c0038972SKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s",
780c0038972SKalle Valo 		 ar->hw.fw.dir, ar->hw.fw.patch);
781d1a9421dSKalle Valo 
782772c31eeSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
783772c31eeSKalle Valo 			    &ar->fw_patch_len);
784772c31eeSKalle Valo 	if (ret) {
785772c31eeSKalle Valo 		ath6kl_err("Failed to get patch file %s: %d\n",
786772c31eeSKalle Valo 			   filename, ret);
787772c31eeSKalle Valo 		return ret;
788772c31eeSKalle Valo 	}
789772c31eeSKalle Valo 
790772c31eeSKalle Valo 	return 0;
791772c31eeSKalle Valo }
792772c31eeSKalle Valo 
793cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
794cd23c1c9SAlex Yang {
795cd23c1c9SAlex Yang 	char filename[100];
796cd23c1c9SAlex Yang 	int ret;
797cd23c1c9SAlex Yang 
7985f1127ffSKalle Valo 	if (ar->testmode != 2)
799cd23c1c9SAlex Yang 		return 0;
800cd23c1c9SAlex Yang 
801cd23c1c9SAlex Yang 	if (ar->fw_testscript != NULL)
802cd23c1c9SAlex Yang 		return 0;
803cd23c1c9SAlex Yang 
804cd23c1c9SAlex Yang 	if (ar->hw.fw.testscript == NULL)
805cd23c1c9SAlex Yang 		return 0;
806cd23c1c9SAlex Yang 
807cd23c1c9SAlex Yang 	snprintf(filename, sizeof(filename), "%s/%s",
808cd23c1c9SAlex Yang 		 ar->hw.fw.dir, ar->hw.fw.testscript);
809cd23c1c9SAlex Yang 
810cd23c1c9SAlex Yang 	ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
811cd23c1c9SAlex Yang 				&ar->fw_testscript_len);
812cd23c1c9SAlex Yang 	if (ret) {
813cd23c1c9SAlex Yang 		ath6kl_err("Failed to get testscript file %s: %d\n",
814cd23c1c9SAlex Yang 			   filename, ret);
815cd23c1c9SAlex Yang 		return ret;
816cd23c1c9SAlex Yang 	}
817cd23c1c9SAlex Yang 
818cd23c1c9SAlex Yang 	return 0;
819cd23c1c9SAlex Yang }
820cd23c1c9SAlex Yang 
82150d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
822772c31eeSKalle Valo {
823772c31eeSKalle Valo 	int ret;
824772c31eeSKalle Valo 
825772c31eeSKalle Valo 	ret = ath6kl_fetch_otp_file(ar);
826772c31eeSKalle Valo 	if (ret)
827772c31eeSKalle Valo 		return ret;
828772c31eeSKalle Valo 
829772c31eeSKalle Valo 	ret = ath6kl_fetch_fw_file(ar);
830772c31eeSKalle Valo 	if (ret)
831772c31eeSKalle Valo 		return ret;
832772c31eeSKalle Valo 
833772c31eeSKalle Valo 	ret = ath6kl_fetch_patch_file(ar);
834772c31eeSKalle Valo 	if (ret)
835772c31eeSKalle Valo 		return ret;
836772c31eeSKalle Valo 
837cd23c1c9SAlex Yang 	ret = ath6kl_fetch_testscript_file(ar);
838cd23c1c9SAlex Yang 	if (ret)
839cd23c1c9SAlex Yang 		return ret;
840cd23c1c9SAlex Yang 
841772c31eeSKalle Valo 	return 0;
842772c31eeSKalle Valo }
843bdcd8170SKalle Valo 
84465a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
84550d41234SKalle Valo {
84650d41234SKalle Valo 	size_t magic_len, len, ie_len;
84750d41234SKalle Valo 	const struct firmware *fw;
84850d41234SKalle Valo 	struct ath6kl_fw_ie *hdr;
849c0038972SKalle Valo 	char filename[100];
85050d41234SKalle Valo 	const u8 *data;
85197e0496dSKalle Valo 	int ret, ie_id, i, index, bit;
8528a137480SKalle Valo 	__le32 *val;
85350d41234SKalle Valo 
85465a8b4ccSKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
85550d41234SKalle Valo 
85650d41234SKalle Valo 	ret = request_firmware(&fw, filename, ar->dev);
85750d41234SKalle Valo 	if (ret)
85850d41234SKalle Valo 		return ret;
85950d41234SKalle Valo 
86050d41234SKalle Valo 	data = fw->data;
86150d41234SKalle Valo 	len = fw->size;
86250d41234SKalle Valo 
86350d41234SKalle Valo 	/* magic also includes the null byte, check that as well */
86450d41234SKalle Valo 	magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
86550d41234SKalle Valo 
86650d41234SKalle Valo 	if (len < magic_len) {
86750d41234SKalle Valo 		ret = -EINVAL;
86850d41234SKalle Valo 		goto out;
86950d41234SKalle Valo 	}
87050d41234SKalle Valo 
87150d41234SKalle Valo 	if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
87250d41234SKalle Valo 		ret = -EINVAL;
87350d41234SKalle Valo 		goto out;
87450d41234SKalle Valo 	}
87550d41234SKalle Valo 
87650d41234SKalle Valo 	len -= magic_len;
87750d41234SKalle Valo 	data += magic_len;
87850d41234SKalle Valo 
87950d41234SKalle Valo 	/* loop elements */
88050d41234SKalle Valo 	while (len > sizeof(struct ath6kl_fw_ie)) {
88150d41234SKalle Valo 		/* hdr is unaligned! */
88250d41234SKalle Valo 		hdr = (struct ath6kl_fw_ie *) data;
88350d41234SKalle Valo 
88450d41234SKalle Valo 		ie_id = le32_to_cpup(&hdr->id);
88550d41234SKalle Valo 		ie_len = le32_to_cpup(&hdr->len);
88650d41234SKalle Valo 
88750d41234SKalle Valo 		len -= sizeof(*hdr);
88850d41234SKalle Valo 		data += sizeof(*hdr);
88950d41234SKalle Valo 
89050d41234SKalle Valo 		if (len < ie_len) {
89150d41234SKalle Valo 			ret = -EINVAL;
89250d41234SKalle Valo 			goto out;
89350d41234SKalle Valo 		}
89450d41234SKalle Valo 
89550d41234SKalle Valo 		switch (ie_id) {
89650d41234SKalle Valo 		case ATH6KL_FW_IE_OTP_IMAGE:
897ef548626SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
8986bc36431SKalle Valo 				   ie_len);
8996bc36431SKalle Valo 
90050d41234SKalle Valo 			ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
90150d41234SKalle Valo 
90250d41234SKalle Valo 			if (ar->fw_otp == NULL) {
90350d41234SKalle Valo 				ret = -ENOMEM;
90450d41234SKalle Valo 				goto out;
90550d41234SKalle Valo 			}
90650d41234SKalle Valo 
90750d41234SKalle Valo 			ar->fw_otp_len = ie_len;
90850d41234SKalle Valo 			break;
90950d41234SKalle Valo 		case ATH6KL_FW_IE_FW_IMAGE:
910ef548626SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
9116bc36431SKalle Valo 				   ie_len);
9126bc36431SKalle Valo 
9135f1127ffSKalle Valo 			/* in testmode we already might have a fw file */
9145f1127ffSKalle Valo 			if (ar->fw != NULL)
9155f1127ffSKalle Valo 				break;
9165f1127ffSKalle Valo 
91750d41234SKalle Valo 			ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
91850d41234SKalle Valo 
91950d41234SKalle Valo 			if (ar->fw == NULL) {
92050d41234SKalle Valo 				ret = -ENOMEM;
92150d41234SKalle Valo 				goto out;
92250d41234SKalle Valo 			}
92350d41234SKalle Valo 
92450d41234SKalle Valo 			ar->fw_len = ie_len;
92550d41234SKalle Valo 			break;
92650d41234SKalle Valo 		case ATH6KL_FW_IE_PATCH_IMAGE:
927ef548626SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
9286bc36431SKalle Valo 				   ie_len);
9296bc36431SKalle Valo 
93050d41234SKalle Valo 			ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
93150d41234SKalle Valo 
93250d41234SKalle Valo 			if (ar->fw_patch == NULL) {
93350d41234SKalle Valo 				ret = -ENOMEM;
93450d41234SKalle Valo 				goto out;
93550d41234SKalle Valo 			}
93650d41234SKalle Valo 
93750d41234SKalle Valo 			ar->fw_patch_len = ie_len;
93850d41234SKalle Valo 			break;
9398a137480SKalle Valo 		case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
9408a137480SKalle Valo 			val = (__le32 *) data;
9418a137480SKalle Valo 			ar->hw.reserved_ram_size = le32_to_cpup(val);
9426bc36431SKalle Valo 
9436bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
9446bc36431SKalle Valo 				   "found reserved ram size ie 0x%d\n",
9456bc36431SKalle Valo 				   ar->hw.reserved_ram_size);
9468a137480SKalle Valo 			break;
94797e0496dSKalle Valo 		case ATH6KL_FW_IE_CAPABILITIES:
948277d90f4SKalle Valo 			if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
949277d90f4SKalle Valo 				break;
950277d90f4SKalle Valo 
9516bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
952ef548626SKalle Valo 				   "found firmware capabilities ie (%zd B)\n",
9536bc36431SKalle Valo 				   ie_len);
9546bc36431SKalle Valo 
95597e0496dSKalle Valo 			for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
956277d90f4SKalle Valo 				index = i / 8;
95797e0496dSKalle Valo 				bit = i % 8;
95897e0496dSKalle Valo 
95997e0496dSKalle Valo 				if (data[index] & (1 << bit))
96097e0496dSKalle Valo 					__set_bit(i, ar->fw_capabilities);
96197e0496dSKalle Valo 			}
9626bc36431SKalle Valo 
9636bc36431SKalle Valo 			ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
9646bc36431SKalle Valo 					ar->fw_capabilities,
9656bc36431SKalle Valo 					sizeof(ar->fw_capabilities));
96697e0496dSKalle Valo 			break;
9671b4304daSKalle Valo 		case ATH6KL_FW_IE_PATCH_ADDR:
9681b4304daSKalle Valo 			if (ie_len != sizeof(*val))
9691b4304daSKalle Valo 				break;
9701b4304daSKalle Valo 
9711b4304daSKalle Valo 			val = (__le32 *) data;
9721b4304daSKalle Valo 			ar->hw.dataset_patch_addr = le32_to_cpup(val);
9736bc36431SKalle Valo 
9746bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
97503ef0250SKalle Valo 				   "found patch address ie 0x%x\n",
9766bc36431SKalle Valo 				   ar->hw.dataset_patch_addr);
9771b4304daSKalle Valo 			break;
97803ef0250SKalle Valo 		case ATH6KL_FW_IE_BOARD_ADDR:
97903ef0250SKalle Valo 			if (ie_len != sizeof(*val))
98003ef0250SKalle Valo 				break;
98103ef0250SKalle Valo 
98203ef0250SKalle Valo 			val = (__le32 *) data;
98303ef0250SKalle Valo 			ar->hw.board_addr = le32_to_cpup(val);
98403ef0250SKalle Valo 
98503ef0250SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
98603ef0250SKalle Valo 				   "found board address ie 0x%x\n",
98703ef0250SKalle Valo 				   ar->hw.board_addr);
98803ef0250SKalle Valo 			break;
989368b1b0fSKalle Valo 		case ATH6KL_FW_IE_VIF_MAX:
990368b1b0fSKalle Valo 			if (ie_len != sizeof(*val))
991368b1b0fSKalle Valo 				break;
992368b1b0fSKalle Valo 
993368b1b0fSKalle Valo 			val = (__le32 *) data;
994368b1b0fSKalle Valo 			ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
995368b1b0fSKalle Valo 					    ATH6KL_VIF_MAX);
996368b1b0fSKalle Valo 
997f143379dSVasanthakumar Thiagarajan 			if (ar->vif_max > 1 && !ar->p2p)
998f143379dSVasanthakumar Thiagarajan 				ar->max_norm_iface = 2;
999f143379dSVasanthakumar Thiagarajan 
1000368b1b0fSKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
1001368b1b0fSKalle Valo 				   "found vif max ie %d\n", ar->vif_max);
1002368b1b0fSKalle Valo 			break;
100350d41234SKalle Valo 		default:
10046bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
100550d41234SKalle Valo 				   le32_to_cpup(&hdr->id));
100650d41234SKalle Valo 			break;
100750d41234SKalle Valo 		}
100850d41234SKalle Valo 
100950d41234SKalle Valo 		len -= ie_len;
101050d41234SKalle Valo 		data += ie_len;
101150d41234SKalle Valo 	};
101250d41234SKalle Valo 
101350d41234SKalle Valo 	ret = 0;
101450d41234SKalle Valo out:
101550d41234SKalle Valo 	release_firmware(fw);
101650d41234SKalle Valo 
101750d41234SKalle Valo 	return ret;
101850d41234SKalle Valo }
101950d41234SKalle Valo 
102045eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
102150d41234SKalle Valo {
102250d41234SKalle Valo 	int ret;
102350d41234SKalle Valo 
102450d41234SKalle Valo 	ret = ath6kl_fetch_board_file(ar);
102550d41234SKalle Valo 	if (ret)
102650d41234SKalle Valo 		return ret;
102750d41234SKalle Valo 
10285f1127ffSKalle Valo 	ret = ath6kl_fetch_testmode_file(ar);
10295f1127ffSKalle Valo 	if (ret)
10305f1127ffSKalle Valo 		return ret;
10315f1127ffSKalle Valo 
103265a8b4ccSKalle Valo 	ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
10336bc36431SKalle Valo 	if (ret == 0) {
103465a8b4ccSKalle Valo 		ar->fw_api = 3;
103565a8b4ccSKalle Valo 		goto out;
103665a8b4ccSKalle Valo 	}
103765a8b4ccSKalle Valo 
103865a8b4ccSKalle Valo 	ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
103965a8b4ccSKalle Valo 	if (ret == 0) {
104065a8b4ccSKalle Valo 		ar->fw_api = 2;
104165a8b4ccSKalle Valo 		goto out;
10426bc36431SKalle Valo 	}
104350d41234SKalle Valo 
104450d41234SKalle Valo 	ret = ath6kl_fetch_fw_api1(ar);
104550d41234SKalle Valo 	if (ret)
104650d41234SKalle Valo 		return ret;
104750d41234SKalle Valo 
104865a8b4ccSKalle Valo 	ar->fw_api = 1;
104965a8b4ccSKalle Valo 
105065a8b4ccSKalle Valo out:
105165a8b4ccSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
10526bc36431SKalle Valo 
105350d41234SKalle Valo 	return 0;
105450d41234SKalle Valo }
105550d41234SKalle Valo 
1056bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar)
1057bdcd8170SKalle Valo {
1058bdcd8170SKalle Valo 	u32 board_address, board_ext_address, param;
105931024d99SKevin Fang 	u32 board_data_size, board_ext_data_size;
1060bdcd8170SKalle Valo 	int ret;
1061bdcd8170SKalle Valo 
1062772c31eeSKalle Valo 	if (WARN_ON(ar->fw_board == NULL))
1063772c31eeSKalle Valo 		return -ENOENT;
1064bdcd8170SKalle Valo 
106531024d99SKevin Fang 	/*
106631024d99SKevin Fang 	 * Determine where in Target RAM to write Board Data.
106731024d99SKevin Fang 	 * For AR6004, host determine Target RAM address for
106831024d99SKevin Fang 	 * writing board data.
106931024d99SKevin Fang 	 */
10700d4d72bfSKalle Valo 	if (ar->hw.board_addr != 0) {
107124fc32b3SKalle Valo 		ath6kl_bmi_write_hi32(ar, hi_board_data,
107224fc32b3SKalle Valo 				      ar->hw.board_addr);
107331024d99SKevin Fang 	} else {
107480fb2686SKalle Valo 		ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
107531024d99SKevin Fang 	}
107631024d99SKevin Fang 
1077bdcd8170SKalle Valo 	/* determine where in target ram to write extended board data */
107880fb2686SKalle Valo 	ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
1079bdcd8170SKalle Valo 
108050e2740bSKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003 &&
108150e2740bSKalle Valo 	    board_ext_address == 0) {
1082bdcd8170SKalle Valo 		ath6kl_err("Failed to get board file target address.\n");
1083bdcd8170SKalle Valo 		return -EINVAL;
1084bdcd8170SKalle Valo 	}
1085bdcd8170SKalle Valo 
108631024d99SKevin Fang 	switch (ar->target_type) {
108731024d99SKevin Fang 	case TARGET_TYPE_AR6003:
108831024d99SKevin Fang 		board_data_size = AR6003_BOARD_DATA_SZ;
108931024d99SKevin Fang 		board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
1090fb1ac2efSPrasanna Kumar 		if (ar->fw_board_len > (board_data_size + board_ext_data_size))
1091fb1ac2efSPrasanna Kumar 			board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
109231024d99SKevin Fang 		break;
109331024d99SKevin Fang 	case TARGET_TYPE_AR6004:
109431024d99SKevin Fang 		board_data_size = AR6004_BOARD_DATA_SZ;
109531024d99SKevin Fang 		board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
109631024d99SKevin Fang 		break;
109731024d99SKevin Fang 	default:
109831024d99SKevin Fang 		WARN_ON(1);
109931024d99SKevin Fang 		return -EINVAL;
110031024d99SKevin Fang 		break;
110131024d99SKevin Fang 	}
110231024d99SKevin Fang 
110350e2740bSKalle Valo 	if (board_ext_address &&
110450e2740bSKalle Valo 	    ar->fw_board_len == (board_data_size + board_ext_data_size)) {
110531024d99SKevin Fang 
1106bdcd8170SKalle Valo 		/* write extended board data */
11076bc36431SKalle Valo 		ath6kl_dbg(ATH6KL_DBG_BOOT,
11086bc36431SKalle Valo 			   "writing extended board data to 0x%x (%d B)\n",
11096bc36431SKalle Valo 			   board_ext_address, board_ext_data_size);
11106bc36431SKalle Valo 
1111bdcd8170SKalle Valo 		ret = ath6kl_bmi_write(ar, board_ext_address,
111231024d99SKevin Fang 				       ar->fw_board + board_data_size,
111331024d99SKevin Fang 				       board_ext_data_size);
1114bdcd8170SKalle Valo 		if (ret) {
1115bdcd8170SKalle Valo 			ath6kl_err("Failed to write extended board data: %d\n",
1116bdcd8170SKalle Valo 				   ret);
1117bdcd8170SKalle Valo 			return ret;
1118bdcd8170SKalle Valo 		}
1119bdcd8170SKalle Valo 
1120bdcd8170SKalle Valo 		/* record that extended board data is initialized */
112131024d99SKevin Fang 		param = (board_ext_data_size << 16) | 1;
112231024d99SKevin Fang 
112324fc32b3SKalle Valo 		ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
1124bdcd8170SKalle Valo 	}
1125bdcd8170SKalle Valo 
112631024d99SKevin Fang 	if (ar->fw_board_len < board_data_size) {
1127bdcd8170SKalle Valo 		ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
1128bdcd8170SKalle Valo 		ret = -EINVAL;
1129bdcd8170SKalle Valo 		return ret;
1130bdcd8170SKalle Valo 	}
1131bdcd8170SKalle Valo 
11326bc36431SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
11336bc36431SKalle Valo 		   board_address, board_data_size);
11346bc36431SKalle Valo 
1135bdcd8170SKalle Valo 	ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
113631024d99SKevin Fang 			       board_data_size);
1137bdcd8170SKalle Valo 
1138bdcd8170SKalle Valo 	if (ret) {
1139bdcd8170SKalle Valo 		ath6kl_err("Board file bmi write failed: %d\n", ret);
1140bdcd8170SKalle Valo 		return ret;
1141bdcd8170SKalle Valo 	}
1142bdcd8170SKalle Valo 
1143bdcd8170SKalle Valo 	/* record the fact that Board Data IS initialized */
114424fc32b3SKalle Valo 	ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
1145bdcd8170SKalle Valo 
1146bdcd8170SKalle Valo 	return ret;
1147bdcd8170SKalle Valo }
1148bdcd8170SKalle Valo 
1149bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar)
1150bdcd8170SKalle Valo {
1151bdcd8170SKalle Valo 	u32 address, param;
1152bef26a7fSKalle Valo 	bool from_hw = false;
1153bdcd8170SKalle Valo 	int ret;
1154bdcd8170SKalle Valo 
115550e2740bSKalle Valo 	if (ar->fw_otp == NULL)
115650e2740bSKalle Valo 		return 0;
1157bdcd8170SKalle Valo 
1158a01ac414SKalle Valo 	address = ar->hw.app_load_addr;
1159bdcd8170SKalle Valo 
1160ef548626SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
11616bc36431SKalle Valo 		   ar->fw_otp_len);
11626bc36431SKalle Valo 
1163bdcd8170SKalle Valo 	ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
1164bdcd8170SKalle Valo 				       ar->fw_otp_len);
1165bdcd8170SKalle Valo 	if (ret) {
1166bdcd8170SKalle Valo 		ath6kl_err("Failed to upload OTP file: %d\n", ret);
1167bdcd8170SKalle Valo 		return ret;
1168bdcd8170SKalle Valo 	}
1169bdcd8170SKalle Valo 
1170639d0b89SKalle Valo 	/* read firmware start address */
117180fb2686SKalle Valo 	ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
1172639d0b89SKalle Valo 
1173639d0b89SKalle Valo 	if (ret) {
1174639d0b89SKalle Valo 		ath6kl_err("Failed to read hi_app_start: %d\n", ret);
1175639d0b89SKalle Valo 		return ret;
1176639d0b89SKalle Valo 	}
1177639d0b89SKalle Valo 
1178bef26a7fSKalle Valo 	if (ar->hw.app_start_override_addr == 0) {
1179639d0b89SKalle Valo 		ar->hw.app_start_override_addr = address;
1180bef26a7fSKalle Valo 		from_hw = true;
1181bef26a7fSKalle Valo 	}
1182639d0b89SKalle Valo 
1183bef26a7fSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
1184bef26a7fSKalle Valo 		   from_hw ? " (from hw)" : "",
11856bc36431SKalle Valo 		   ar->hw.app_start_override_addr);
11866bc36431SKalle Valo 
1187bdcd8170SKalle Valo 	/* execute the OTP code */
1188bef26a7fSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
1189bef26a7fSKalle Valo 		   ar->hw.app_start_override_addr);
1190bdcd8170SKalle Valo 	param = 0;
1191bef26a7fSKalle Valo 	ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
1192bdcd8170SKalle Valo 
1193bdcd8170SKalle Valo 	return ret;
1194bdcd8170SKalle Valo }
1195bdcd8170SKalle Valo 
1196bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar)
1197bdcd8170SKalle Valo {
1198bdcd8170SKalle Valo 	u32 address;
1199bdcd8170SKalle Valo 	int ret;
1200bdcd8170SKalle Valo 
1201772c31eeSKalle Valo 	if (WARN_ON(ar->fw == NULL))
120250e2740bSKalle Valo 		return 0;
1203bdcd8170SKalle Valo 
1204a01ac414SKalle Valo 	address = ar->hw.app_load_addr;
1205bdcd8170SKalle Valo 
1206ef548626SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
12076bc36431SKalle Valo 		   address, ar->fw_len);
12086bc36431SKalle Valo 
1209bdcd8170SKalle Valo 	ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
1210bdcd8170SKalle Valo 
1211bdcd8170SKalle Valo 	if (ret) {
1212bdcd8170SKalle Valo 		ath6kl_err("Failed to write firmware: %d\n", ret);
1213bdcd8170SKalle Valo 		return ret;
1214bdcd8170SKalle Valo 	}
1215bdcd8170SKalle Valo 
121631024d99SKevin Fang 	/*
121731024d99SKevin Fang 	 * Set starting address for firmware
121831024d99SKevin Fang 	 * Don't need to setup app_start override addr on AR6004
121931024d99SKevin Fang 	 */
122031024d99SKevin Fang 	if (ar->target_type != TARGET_TYPE_AR6004) {
1221a01ac414SKalle Valo 		address = ar->hw.app_start_override_addr;
1222bdcd8170SKalle Valo 		ath6kl_bmi_set_app_start(ar, address);
122331024d99SKevin Fang 	}
1224bdcd8170SKalle Valo 	return ret;
1225bdcd8170SKalle Valo }
1226bdcd8170SKalle Valo 
1227bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar)
1228bdcd8170SKalle Valo {
122924fc32b3SKalle Valo 	u32 address;
1230bdcd8170SKalle Valo 	int ret;
1231bdcd8170SKalle Valo 
123250e2740bSKalle Valo 	if (ar->fw_patch == NULL)
123350e2740bSKalle Valo 		return 0;
1234bdcd8170SKalle Valo 
1235a01ac414SKalle Valo 	address = ar->hw.dataset_patch_addr;
1236bdcd8170SKalle Valo 
1237ef548626SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
12386bc36431SKalle Valo 		   address, ar->fw_patch_len);
12396bc36431SKalle Valo 
1240bdcd8170SKalle Valo 	ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
1241bdcd8170SKalle Valo 	if (ret) {
1242bdcd8170SKalle Valo 		ath6kl_err("Failed to write patch file: %d\n", ret);
1243bdcd8170SKalle Valo 		return ret;
1244bdcd8170SKalle Valo 	}
1245bdcd8170SKalle Valo 
124624fc32b3SKalle Valo 	ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
1247bdcd8170SKalle Valo 
1248bdcd8170SKalle Valo 	return 0;
1249bdcd8170SKalle Valo }
1250bdcd8170SKalle Valo 
1251cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar)
1252cd23c1c9SAlex Yang {
125324fc32b3SKalle Valo 	u32 address;
1254cd23c1c9SAlex Yang 	int ret;
1255cd23c1c9SAlex Yang 
12565f1127ffSKalle Valo 	if (ar->testmode != 2)
1257cd23c1c9SAlex Yang 		return 0;
1258cd23c1c9SAlex Yang 
1259cd23c1c9SAlex Yang 	if (ar->fw_testscript == NULL)
1260cd23c1c9SAlex Yang 		return 0;
1261cd23c1c9SAlex Yang 
1262cd23c1c9SAlex Yang 	address = ar->hw.testscript_addr;
1263cd23c1c9SAlex Yang 
1264cd23c1c9SAlex Yang 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
1265cd23c1c9SAlex Yang 		   address, ar->fw_testscript_len);
1266cd23c1c9SAlex Yang 
1267cd23c1c9SAlex Yang 	ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
1268cd23c1c9SAlex Yang 		ar->fw_testscript_len);
1269cd23c1c9SAlex Yang 	if (ret) {
1270cd23c1c9SAlex Yang 		ath6kl_err("Failed to write testscript file: %d\n", ret);
1271cd23c1c9SAlex Yang 		return ret;
1272cd23c1c9SAlex Yang 	}
1273cd23c1c9SAlex Yang 
127424fc32b3SKalle Valo 	ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
127524fc32b3SKalle Valo 	ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
127624fc32b3SKalle Valo 	ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
1277cd23c1c9SAlex Yang 
1278cd23c1c9SAlex Yang 	return 0;
1279cd23c1c9SAlex Yang }
1280cd23c1c9SAlex Yang 
1281bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar)
1282bdcd8170SKalle Valo {
1283bdcd8170SKalle Valo 	u32 param, options, sleep, address;
1284bdcd8170SKalle Valo 	int status = 0;
1285bdcd8170SKalle Valo 
128631024d99SKevin Fang 	if (ar->target_type != TARGET_TYPE_AR6003 &&
128731024d99SKevin Fang 	    ar->target_type != TARGET_TYPE_AR6004)
1288bdcd8170SKalle Valo 		return -EINVAL;
1289bdcd8170SKalle Valo 
1290bdcd8170SKalle Valo 	/* temporarily disable system sleep */
1291bdcd8170SKalle Valo 	address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1292bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_read(ar, address, &param);
1293bdcd8170SKalle Valo 	if (status)
1294bdcd8170SKalle Valo 		return status;
1295bdcd8170SKalle Valo 
1296bdcd8170SKalle Valo 	options = param;
1297bdcd8170SKalle Valo 
1298bdcd8170SKalle Valo 	param |= ATH6KL_OPTION_SLEEP_DISABLE;
1299bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1300bdcd8170SKalle Valo 	if (status)
1301bdcd8170SKalle Valo 		return status;
1302bdcd8170SKalle Valo 
1303bdcd8170SKalle Valo 	address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1304bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_read(ar, address, &param);
1305bdcd8170SKalle Valo 	if (status)
1306bdcd8170SKalle Valo 		return status;
1307bdcd8170SKalle Valo 
1308bdcd8170SKalle Valo 	sleep = param;
1309bdcd8170SKalle Valo 
1310bdcd8170SKalle Valo 	param |= SM(SYSTEM_SLEEP_DISABLE, 1);
1311bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1312bdcd8170SKalle Valo 	if (status)
1313bdcd8170SKalle Valo 		return status;
1314bdcd8170SKalle Valo 
1315bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
1316bdcd8170SKalle Valo 		   options, sleep);
1317bdcd8170SKalle Valo 
1318bdcd8170SKalle Valo 	/* program analog PLL register */
131931024d99SKevin Fang 	/* no need to control 40/44MHz clock on AR6004 */
132031024d99SKevin Fang 	if (ar->target_type != TARGET_TYPE_AR6004) {
1321bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
1322bdcd8170SKalle Valo 					      0xF9104001);
132331024d99SKevin Fang 
1324bdcd8170SKalle Valo 		if (status)
1325bdcd8170SKalle Valo 			return status;
1326bdcd8170SKalle Valo 
1327bdcd8170SKalle Valo 		/* Run at 80/88MHz by default */
1328bdcd8170SKalle Valo 		param = SM(CPU_CLOCK_STANDARD, 1);
1329bdcd8170SKalle Valo 
1330bdcd8170SKalle Valo 		address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
1331bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1332bdcd8170SKalle Valo 		if (status)
1333bdcd8170SKalle Valo 			return status;
133431024d99SKevin Fang 	}
1335bdcd8170SKalle Valo 
1336bdcd8170SKalle Valo 	param = 0;
1337bdcd8170SKalle Valo 	address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
1338bdcd8170SKalle Valo 	param = SM(LPO_CAL_ENABLE, 1);
1339bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1340bdcd8170SKalle Valo 	if (status)
1341bdcd8170SKalle Valo 		return status;
1342bdcd8170SKalle Valo 
1343bdcd8170SKalle Valo 	/* WAR to avoid SDIO CRC err */
13444480bb59SRaja Mani 	if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
13454480bb59SRaja Mani 	    ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
1346bdcd8170SKalle Valo 		ath6kl_err("temporary war to avoid sdio crc error\n");
1347bdcd8170SKalle Valo 
1348bdcd8170SKalle Valo 		param = 0x20;
1349bdcd8170SKalle Valo 
1350bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
1351bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1352bdcd8170SKalle Valo 		if (status)
1353bdcd8170SKalle Valo 			return status;
1354bdcd8170SKalle Valo 
1355bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
1356bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1357bdcd8170SKalle Valo 		if (status)
1358bdcd8170SKalle Valo 			return status;
1359bdcd8170SKalle Valo 
1360bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
1361bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1362bdcd8170SKalle Valo 		if (status)
1363bdcd8170SKalle Valo 			return status;
1364bdcd8170SKalle Valo 
1365bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
1366bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1367bdcd8170SKalle Valo 		if (status)
1368bdcd8170SKalle Valo 			return status;
1369bdcd8170SKalle Valo 	}
1370bdcd8170SKalle Valo 
1371bdcd8170SKalle Valo 	/* write EEPROM data to Target RAM */
1372bdcd8170SKalle Valo 	status = ath6kl_upload_board_file(ar);
1373bdcd8170SKalle Valo 	if (status)
1374bdcd8170SKalle Valo 		return status;
1375bdcd8170SKalle Valo 
1376bdcd8170SKalle Valo 	/* transfer One time Programmable data */
1377bdcd8170SKalle Valo 	status = ath6kl_upload_otp(ar);
1378bdcd8170SKalle Valo 	if (status)
1379bdcd8170SKalle Valo 		return status;
1380bdcd8170SKalle Valo 
1381bdcd8170SKalle Valo 	/* Download Target firmware */
1382bdcd8170SKalle Valo 	status = ath6kl_upload_firmware(ar);
1383bdcd8170SKalle Valo 	if (status)
1384bdcd8170SKalle Valo 		return status;
1385bdcd8170SKalle Valo 
1386bdcd8170SKalle Valo 	status = ath6kl_upload_patch(ar);
1387bdcd8170SKalle Valo 	if (status)
1388bdcd8170SKalle Valo 		return status;
1389bdcd8170SKalle Valo 
1390cd23c1c9SAlex Yang 	/* Download the test script */
1391cd23c1c9SAlex Yang 	status = ath6kl_upload_testscript(ar);
1392cd23c1c9SAlex Yang 	if (status)
1393cd23c1c9SAlex Yang 		return status;
1394cd23c1c9SAlex Yang 
1395bdcd8170SKalle Valo 	/* Restore system sleep */
1396bdcd8170SKalle Valo 	address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1397bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, sleep);
1398bdcd8170SKalle Valo 	if (status)
1399bdcd8170SKalle Valo 		return status;
1400bdcd8170SKalle Valo 
1401bdcd8170SKalle Valo 	address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1402bdcd8170SKalle Valo 	param = options | 0x20;
1403bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1404bdcd8170SKalle Valo 	if (status)
1405bdcd8170SKalle Valo 		return status;
1406bdcd8170SKalle Valo 
1407bdcd8170SKalle Valo 	return status;
1408bdcd8170SKalle Valo }
1409bdcd8170SKalle Valo 
141045eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar)
1411a01ac414SKalle Valo {
14121b46dc04SKalle Valo 	const struct ath6kl_hw *uninitialized_var(hw);
1413856f4b31SKalle Valo 	int i;
1414bef26a7fSKalle Valo 
1415856f4b31SKalle Valo 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
1416856f4b31SKalle Valo 		hw = &hw_list[i];
1417bef26a7fSKalle Valo 
1418856f4b31SKalle Valo 		if (hw->id == ar->version.target_ver)
1419a01ac414SKalle Valo 			break;
1420856f4b31SKalle Valo 	}
1421856f4b31SKalle Valo 
1422856f4b31SKalle Valo 	if (i == ARRAY_SIZE(hw_list)) {
1423a01ac414SKalle Valo 		ath6kl_err("Unsupported hardware version: 0x%x\n",
1424a01ac414SKalle Valo 			   ar->version.target_ver);
1425a01ac414SKalle Valo 		return -EINVAL;
1426a01ac414SKalle Valo 	}
1427a01ac414SKalle Valo 
1428856f4b31SKalle Valo 	ar->hw = *hw;
1429856f4b31SKalle Valo 
14306bc36431SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT,
14316bc36431SKalle Valo 		   "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
14326bc36431SKalle Valo 		   ar->version.target_ver, ar->target_type,
14336bc36431SKalle Valo 		   ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
14346bc36431SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT,
14356bc36431SKalle Valo 		   "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
14366bc36431SKalle Valo 		   ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
14376bc36431SKalle Valo 		   ar->hw.reserved_ram_size);
143839586bf2SRyan Hsu 	ath6kl_dbg(ATH6KL_DBG_BOOT,
143939586bf2SRyan Hsu 		   "refclk_hz %d uarttx_pin %d",
144039586bf2SRyan Hsu 		   ar->hw.refclk_hz, ar->hw.uarttx_pin);
14416bc36431SKalle Valo 
1442a01ac414SKalle Valo 	return 0;
1443a01ac414SKalle Valo }
1444a01ac414SKalle Valo 
1445293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
1446293badf4SKalle Valo {
1447293badf4SKalle Valo 	switch (type) {
1448293badf4SKalle Valo 	case ATH6KL_HIF_TYPE_SDIO:
1449293badf4SKalle Valo 		return "sdio";
1450293badf4SKalle Valo 	case ATH6KL_HIF_TYPE_USB:
1451293badf4SKalle Valo 		return "usb";
1452293badf4SKalle Valo 	}
1453293badf4SKalle Valo 
1454293badf4SKalle Valo 	return NULL;
1455293badf4SKalle Valo }
1456293badf4SKalle Valo 
14575fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar)
145820459ee2SKalle Valo {
145920459ee2SKalle Valo 	long timeleft;
146020459ee2SKalle Valo 	int ret, i;
146120459ee2SKalle Valo 
14625fe4dffbSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
14635fe4dffbSKalle Valo 
146420459ee2SKalle Valo 	ret = ath6kl_hif_power_on(ar);
146520459ee2SKalle Valo 	if (ret)
146620459ee2SKalle Valo 		return ret;
146720459ee2SKalle Valo 
146820459ee2SKalle Valo 	ret = ath6kl_configure_target(ar);
146920459ee2SKalle Valo 	if (ret)
147020459ee2SKalle Valo 		goto err_power_off;
147120459ee2SKalle Valo 
147220459ee2SKalle Valo 	ret = ath6kl_init_upload(ar);
147320459ee2SKalle Valo 	if (ret)
147420459ee2SKalle Valo 		goto err_power_off;
147520459ee2SKalle Valo 
147620459ee2SKalle Valo 	/* Do we need to finish the BMI phase */
147720459ee2SKalle Valo 	/* FIXME: return error from ath6kl_bmi_done() */
147820459ee2SKalle Valo 	if (ath6kl_bmi_done(ar)) {
147920459ee2SKalle Valo 		ret = -EIO;
148020459ee2SKalle Valo 		goto err_power_off;
148120459ee2SKalle Valo 	}
148220459ee2SKalle Valo 
148320459ee2SKalle Valo 	/*
148420459ee2SKalle Valo 	 * The reason we have to wait for the target here is that the
148520459ee2SKalle Valo 	 * driver layer has to init BMI in order to set the host block
148620459ee2SKalle Valo 	 * size.
148720459ee2SKalle Valo 	 */
148820459ee2SKalle Valo 	if (ath6kl_htc_wait_target(ar->htc_target)) {
148920459ee2SKalle Valo 		ret = -EIO;
149020459ee2SKalle Valo 		goto err_power_off;
149120459ee2SKalle Valo 	}
149220459ee2SKalle Valo 
149320459ee2SKalle Valo 	if (ath6kl_init_service_ep(ar)) {
149420459ee2SKalle Valo 		ret = -EIO;
149520459ee2SKalle Valo 		goto err_cleanup_scatter;
149620459ee2SKalle Valo 	}
149720459ee2SKalle Valo 
149820459ee2SKalle Valo 	/* setup credit distribution */
149920459ee2SKalle Valo 	ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
150020459ee2SKalle Valo 
150120459ee2SKalle Valo 	/* start HTC */
150220459ee2SKalle Valo 	ret = ath6kl_htc_start(ar->htc_target);
150320459ee2SKalle Valo 	if (ret) {
150420459ee2SKalle Valo 		/* FIXME: call this */
150520459ee2SKalle Valo 		ath6kl_cookie_cleanup(ar);
150620459ee2SKalle Valo 		goto err_cleanup_scatter;
150720459ee2SKalle Valo 	}
150820459ee2SKalle Valo 
150920459ee2SKalle Valo 	/* Wait for Wmi event to be ready */
151020459ee2SKalle Valo 	timeleft = wait_event_interruptible_timeout(ar->event_wq,
151120459ee2SKalle Valo 						    test_bit(WMI_READY,
151220459ee2SKalle Valo 							     &ar->flag),
151320459ee2SKalle Valo 						    WMI_TIMEOUT);
151420459ee2SKalle Valo 
151520459ee2SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
151620459ee2SKalle Valo 
1517293badf4SKalle Valo 
1518293badf4SKalle Valo 	if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
151965a8b4ccSKalle Valo 		ath6kl_info("%s %s fw %s api %d%s\n",
1520293badf4SKalle Valo 			    ar->hw.name,
1521293badf4SKalle Valo 			    ath6kl_init_get_hif_name(ar->hif_type),
1522293badf4SKalle Valo 			    ar->wiphy->fw_version,
152365a8b4ccSKalle Valo 			    ar->fw_api,
1524293badf4SKalle Valo 			    test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
1525293badf4SKalle Valo 	}
1526293badf4SKalle Valo 
152720459ee2SKalle Valo 	if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
152820459ee2SKalle Valo 		ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
152920459ee2SKalle Valo 			   ATH6KL_ABI_VERSION, ar->version.abi_ver);
153020459ee2SKalle Valo 		ret = -EIO;
153120459ee2SKalle Valo 		goto err_htc_stop;
153220459ee2SKalle Valo 	}
153320459ee2SKalle Valo 
153420459ee2SKalle Valo 	if (!timeleft || signal_pending(current)) {
153520459ee2SKalle Valo 		ath6kl_err("wmi is not ready or wait was interrupted\n");
153620459ee2SKalle Valo 		ret = -EIO;
153720459ee2SKalle Valo 		goto err_htc_stop;
153820459ee2SKalle Valo 	}
153920459ee2SKalle Valo 
154020459ee2SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
154120459ee2SKalle Valo 
154220459ee2SKalle Valo 	/* communicate the wmi protocol verision to the target */
154320459ee2SKalle Valo 	/* FIXME: return error */
154420459ee2SKalle Valo 	if ((ath6kl_set_host_app_area(ar)) != 0)
154520459ee2SKalle Valo 		ath6kl_err("unable to set the host app area\n");
154620459ee2SKalle Valo 
154771f96ee6SKalle Valo 	for (i = 0; i < ar->vif_max; i++) {
154820459ee2SKalle Valo 		ret = ath6kl_target_config_wlan_params(ar, i);
154920459ee2SKalle Valo 		if (ret)
155020459ee2SKalle Valo 			goto err_htc_stop;
155120459ee2SKalle Valo 	}
155220459ee2SKalle Valo 
155376a9fbe2SKalle Valo 	ar->state = ATH6KL_STATE_ON;
155476a9fbe2SKalle Valo 
155520459ee2SKalle Valo 	return 0;
155620459ee2SKalle Valo 
155720459ee2SKalle Valo err_htc_stop:
155820459ee2SKalle Valo 	ath6kl_htc_stop(ar->htc_target);
155920459ee2SKalle Valo err_cleanup_scatter:
156020459ee2SKalle Valo 	ath6kl_hif_cleanup_scatter(ar);
156120459ee2SKalle Valo err_power_off:
156220459ee2SKalle Valo 	ath6kl_hif_power_off(ar);
156320459ee2SKalle Valo 
156420459ee2SKalle Valo 	return ret;
156520459ee2SKalle Valo }
156620459ee2SKalle Valo 
15675fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar)
15685fe4dffbSKalle Valo {
15695fe4dffbSKalle Valo 	int ret;
15705fe4dffbSKalle Valo 
15715fe4dffbSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
15725fe4dffbSKalle Valo 
15735fe4dffbSKalle Valo 	ath6kl_htc_stop(ar->htc_target);
15745fe4dffbSKalle Valo 
15755fe4dffbSKalle Valo 	ath6kl_hif_stop(ar);
15765fe4dffbSKalle Valo 
15775fe4dffbSKalle Valo 	ath6kl_bmi_reset(ar);
15785fe4dffbSKalle Valo 
15795fe4dffbSKalle Valo 	ret = ath6kl_hif_power_off(ar);
15805fe4dffbSKalle Valo 	if (ret)
15815fe4dffbSKalle Valo 		ath6kl_warn("failed to power off hif: %d\n", ret);
15825fe4dffbSKalle Valo 
158376a9fbe2SKalle Valo 	ar->state = ATH6KL_STATE_OFF;
158476a9fbe2SKalle Valo 
15855fe4dffbSKalle Valo 	return 0;
15865fe4dffbSKalle Valo }
15875fe4dffbSKalle Valo 
1588c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
158955055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
15906db8fa53SVasanthakumar Thiagarajan {
15916db8fa53SVasanthakumar Thiagarajan 	static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
15926db8fa53SVasanthakumar Thiagarajan 	bool discon_issued;
15936db8fa53SVasanthakumar Thiagarajan 
15946db8fa53SVasanthakumar Thiagarajan 	netif_stop_queue(vif->ndev);
15956db8fa53SVasanthakumar Thiagarajan 
15966db8fa53SVasanthakumar Thiagarajan 	clear_bit(WLAN_ENABLED, &vif->flags);
15976db8fa53SVasanthakumar Thiagarajan 
15986db8fa53SVasanthakumar Thiagarajan 	if (wmi_ready) {
15996db8fa53SVasanthakumar Thiagarajan 		discon_issued = test_bit(CONNECTED, &vif->flags) ||
16006db8fa53SVasanthakumar Thiagarajan 				test_bit(CONNECT_PEND, &vif->flags);
16016db8fa53SVasanthakumar Thiagarajan 		ath6kl_disconnect(vif);
16026db8fa53SVasanthakumar Thiagarajan 		del_timer(&vif->disconnect_timer);
16036db8fa53SVasanthakumar Thiagarajan 
16046db8fa53SVasanthakumar Thiagarajan 		if (discon_issued)
16056db8fa53SVasanthakumar Thiagarajan 			ath6kl_disconnect_event(vif, DISCONNECT_CMD,
16066db8fa53SVasanthakumar Thiagarajan 						(vif->nw_type & AP_NETWORK) ?
16076db8fa53SVasanthakumar Thiagarajan 						bcast_mac : vif->bssid,
16086db8fa53SVasanthakumar Thiagarajan 						0, NULL, 0);
16096db8fa53SVasanthakumar Thiagarajan 	}
16106db8fa53SVasanthakumar Thiagarajan 
16116db8fa53SVasanthakumar Thiagarajan 	if (vif->scan_req) {
16126db8fa53SVasanthakumar Thiagarajan 		cfg80211_scan_done(vif->scan_req, true);
16136db8fa53SVasanthakumar Thiagarajan 		vif->scan_req = NULL;
16146db8fa53SVasanthakumar Thiagarajan 	}
16156db8fa53SVasanthakumar Thiagarajan }
16166db8fa53SVasanthakumar Thiagarajan 
1617bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar)
1618bdcd8170SKalle Valo {
1619990bd915SVasanthakumar Thiagarajan 	struct ath6kl_vif *vif, *tmp_vif;
16201d2a4456SVasanthakumar Thiagarajan 	int i;
1621bdcd8170SKalle Valo 
1622bdcd8170SKalle Valo 	set_bit(DESTROY_IN_PROGRESS, &ar->flag);
1623bdcd8170SKalle Valo 
1624bdcd8170SKalle Valo 	if (down_interruptible(&ar->sem)) {
1625bdcd8170SKalle Valo 		ath6kl_err("down_interruptible failed\n");
1626bdcd8170SKalle Valo 		return;
1627bdcd8170SKalle Valo 	}
1628bdcd8170SKalle Valo 
16291d2a4456SVasanthakumar Thiagarajan 	for (i = 0; i < AP_MAX_NUM_STA; i++)
16301d2a4456SVasanthakumar Thiagarajan 		aggr_reset_state(ar->sta_list[i].aggr_conn);
16311d2a4456SVasanthakumar Thiagarajan 
163211f6e40dSVasanthakumar Thiagarajan 	spin_lock_bh(&ar->list_lock);
1633990bd915SVasanthakumar Thiagarajan 	list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
1634990bd915SVasanthakumar Thiagarajan 		list_del(&vif->list);
163511f6e40dSVasanthakumar Thiagarajan 		spin_unlock_bh(&ar->list_lock);
1636990bd915SVasanthakumar Thiagarajan 		ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
163727929723SVasanthakumar Thiagarajan 		rtnl_lock();
1638c25889e8SKalle Valo 		ath6kl_cfg80211_vif_cleanup(vif);
163927929723SVasanthakumar Thiagarajan 		rtnl_unlock();
164011f6e40dSVasanthakumar Thiagarajan 		spin_lock_bh(&ar->list_lock);
1641990bd915SVasanthakumar Thiagarajan 	}
164211f6e40dSVasanthakumar Thiagarajan 	spin_unlock_bh(&ar->list_lock);
1643bdcd8170SKalle Valo 
16446db8fa53SVasanthakumar Thiagarajan 	clear_bit(WMI_READY, &ar->flag);
16456db8fa53SVasanthakumar Thiagarajan 
16466db8fa53SVasanthakumar Thiagarajan 	/*
16476db8fa53SVasanthakumar Thiagarajan 	 * After wmi_shudown all WMI events will be dropped. We
16486db8fa53SVasanthakumar Thiagarajan 	 * need to cleanup the buffers allocated in AP mode and
16496db8fa53SVasanthakumar Thiagarajan 	 * give disconnect notification to stack, which usually
16506db8fa53SVasanthakumar Thiagarajan 	 * happens in the disconnect_event. Simulate the disconnect
16516db8fa53SVasanthakumar Thiagarajan 	 * event by calling the function directly. Sometimes
16526db8fa53SVasanthakumar Thiagarajan 	 * disconnect_event will be received when the debug logs
16536db8fa53SVasanthakumar Thiagarajan 	 * are collected.
16546db8fa53SVasanthakumar Thiagarajan 	 */
16556db8fa53SVasanthakumar Thiagarajan 	ath6kl_wmi_shutdown(ar->wmi);
16566db8fa53SVasanthakumar Thiagarajan 
16576db8fa53SVasanthakumar Thiagarajan 	clear_bit(WMI_ENABLED, &ar->flag);
16586db8fa53SVasanthakumar Thiagarajan 	if (ar->htc_target) {
16596db8fa53SVasanthakumar Thiagarajan 		ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
16606db8fa53SVasanthakumar Thiagarajan 		ath6kl_htc_stop(ar->htc_target);
1661bdcd8170SKalle Valo 	}
1662bdcd8170SKalle Valo 
1663bdcd8170SKalle Valo 	/*
16646db8fa53SVasanthakumar Thiagarajan 	 * Try to reset the device if we can. The driver may have been
16656db8fa53SVasanthakumar Thiagarajan 	 * configure NOT to reset the target during a debug session.
1666bdcd8170SKalle Valo 	 */
16676db8fa53SVasanthakumar Thiagarajan 	ath6kl_dbg(ATH6KL_DBG_TRC,
16686db8fa53SVasanthakumar Thiagarajan 		   "attempting to reset target on instance destroy\n");
16696db8fa53SVasanthakumar Thiagarajan 	ath6kl_reset_device(ar, ar->target_type, true, true);
1670bdcd8170SKalle Valo 
16716db8fa53SVasanthakumar Thiagarajan 	clear_bit(WLAN_ENABLED, &ar->flag);
1672e8ad9a06SVasanthakumar Thiagarajan 
1673e8ad9a06SVasanthakumar Thiagarajan 	up(&ar->sem);
1674bdcd8170SKalle Valo }
1675d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx);
1676