1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 41b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 5bdcd8170SKalle Valo * 6bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 7bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 8bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 9bdcd8170SKalle Valo * 10bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17bdcd8170SKalle Valo */ 18bdcd8170SKalle Valo 19516304b0SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20516304b0SJoe Perches 21c6efe578SStephen Rothwell #include <linux/moduleparam.h> 22f7830202SSangwook Lee #include <linux/errno.h> 23d6a434d6SKalle Valo #include <linux/export.h> 2492ecbff4SSam Leffler #include <linux/of.h> 25bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 268437754cSVivek Natarajan #include <linux/vmalloc.h> 27d6a434d6SKalle Valo 28bdcd8170SKalle Valo #include "core.h" 29bdcd8170SKalle Valo #include "cfg80211.h" 30bdcd8170SKalle Valo #include "target.h" 31bdcd8170SKalle Valo #include "debug.h" 32bdcd8170SKalle Valo #include "hif-ops.h" 33e76ac2bfSKalle Valo #include "htc-ops.h" 34bdcd8170SKalle Valo 35856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 36856f4b31SKalle Valo { 370d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 38293badf4SKalle Valo .name = "ar6003 hw 2.0", 39856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 40856f4b31SKalle Valo .app_load_addr = 0x543180, 41856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 42856f4b31SKalle Valo .reserved_ram_size = 6912, 4339586bf2SRyan Hsu .refclk_hz = 26000000, 4439586bf2SRyan Hsu .uarttx_pin = 8, 45856f4b31SKalle Valo 46856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 47856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 48d1a9421dSKalle Valo 49c0038972SKalle Valo .fw = { 50c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 51c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 52d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 53c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 54c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 55c0038972SKalle Valo }, 56c0038972SKalle Valo 57d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 58d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 59856f4b31SKalle Valo }, 60856f4b31SKalle Valo { 610d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 62293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 63856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 64856f4b31SKalle Valo .app_load_addr = 0x1234, 65856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 66856f4b31SKalle Valo .reserved_ram_size = 512, 6739586bf2SRyan Hsu .refclk_hz = 26000000, 6839586bf2SRyan Hsu .uarttx_pin = 8, 69cd23c1c9SAlex Yang .testscript_addr = 0x57ef74, 70d1a9421dSKalle Valo 71c0038972SKalle Valo .fw = { 72c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 73c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 74d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 75c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 76c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 77cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, 78cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, 79c0038972SKalle Valo }, 80c0038972SKalle Valo 81d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 82d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 83856f4b31SKalle Valo }, 84856f4b31SKalle Valo { 850d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 86293badf4SKalle Valo .name = "ar6004 hw 1.0", 87856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 88856f4b31SKalle Valo .app_load_addr = 0x1234, 89856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 90856f4b31SKalle Valo .reserved_ram_size = 19456, 910d4d72bfSKalle Valo .board_addr = 0x433900, 9239586bf2SRyan Hsu .refclk_hz = 26000000, 9339586bf2SRyan Hsu .uarttx_pin = 11, 94d1a9421dSKalle Valo 95c0038972SKalle Valo .fw = { 96c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 97d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 98c0038972SKalle Valo }, 99c0038972SKalle Valo 100d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 101d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 102856f4b31SKalle Valo }, 103856f4b31SKalle Valo { 1040d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 105293badf4SKalle Valo .name = "ar6004 hw 1.1", 106856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 107856f4b31SKalle Valo .app_load_addr = 0x1234, 108856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 109856f4b31SKalle Valo .reserved_ram_size = 11264, 1100d4d72bfSKalle Valo .board_addr = 0x43d400, 11139586bf2SRyan Hsu .refclk_hz = 40000000, 11239586bf2SRyan Hsu .uarttx_pin = 11, 113d1a9421dSKalle Valo 114c0038972SKalle Valo .fw = { 115c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 116d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 117c0038972SKalle Valo }, 118c0038972SKalle Valo 119d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 120d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 121856f4b31SKalle Valo }, 1226146ca69SRay Chen { 1236146ca69SRay Chen .id = AR6004_HW_1_2_VERSION, 1246146ca69SRay Chen .name = "ar6004 hw 1.2", 1256146ca69SRay Chen .dataset_patch_addr = 0x436ecc, 1266146ca69SRay Chen .app_load_addr = 0x1234, 1276146ca69SRay Chen .board_ext_data_addr = 0x437000, 1286146ca69SRay Chen .reserved_ram_size = 9216, 1296146ca69SRay Chen .board_addr = 0x435c00, 1306146ca69SRay Chen .refclk_hz = 40000000, 1316146ca69SRay Chen .uarttx_pin = 11, 1326146ca69SRay Chen 1336146ca69SRay Chen .fw = { 1346146ca69SRay Chen .dir = AR6004_HW_1_2_FW_DIR, 1356146ca69SRay Chen .fw = AR6004_HW_1_2_FIRMWARE_FILE, 1366146ca69SRay Chen }, 1376146ca69SRay Chen .fw_board = AR6004_HW_1_2_BOARD_DATA_FILE, 1386146ca69SRay Chen .fw_default_board = AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE, 1396146ca69SRay Chen }, 140856f4b31SKalle Valo }; 141856f4b31SKalle Valo 142bdcd8170SKalle Valo /* 143bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 144bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 145bdcd8170SKalle Valo * here. 146bdcd8170SKalle Valo */ 147bdcd8170SKalle Valo 148bdcd8170SKalle Valo /* 149bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 150bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 151bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 152bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 153bdcd8170SKalle Valo * Use value of zero to disable keepalive support 154bdcd8170SKalle Valo * Default: 60 seconds 155bdcd8170SKalle Valo */ 156bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 157bdcd8170SKalle Valo 158bdcd8170SKalle Valo /* 159bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 160bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 161bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 162bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 163bdcd8170SKalle Valo * it sends a new connect event 164bdcd8170SKalle Valo */ 165bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 166bdcd8170SKalle Valo 167bdcd8170SKalle Valo 168bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 169bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 170bdcd8170SKalle Valo { 171bdcd8170SKalle Valo struct sk_buff *skb; 172bdcd8170SKalle Valo u16 reserved; 173bdcd8170SKalle Valo 174bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 175bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 1761df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 177bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 178bdcd8170SKalle Valo 179bdcd8170SKalle Valo if (skb) 180bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 181bdcd8170SKalle Valo return skb; 182bdcd8170SKalle Valo } 183bdcd8170SKalle Valo 184e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 185bdcd8170SKalle Valo { 1863450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 1873450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 1883450334fSVasanthakumar Thiagarajan 1893450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 1903450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 1913450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 1923450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 1933450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 1943450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 1956f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 1968c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 1978c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 198f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 199bdcd8170SKalle Valo } 200bdcd8170SKalle Valo 201bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 202bdcd8170SKalle Valo { 203bdcd8170SKalle Valo u32 address, data; 204bdcd8170SKalle Valo struct host_app_area host_app_area; 205bdcd8170SKalle Valo 206bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 207bdcd8170SKalle Valo * instance in the host interest area */ 208bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 20931024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 210bdcd8170SKalle Valo 211addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 212bdcd8170SKalle Valo return -EIO; 213bdcd8170SKalle Valo 21431024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 215cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 216addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 217addb44beSKalle Valo sizeof(struct host_app_area))) 218bdcd8170SKalle Valo return -EIO; 219bdcd8170SKalle Valo 220bdcd8170SKalle Valo return 0; 221bdcd8170SKalle Valo } 222bdcd8170SKalle Valo 223bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 224bdcd8170SKalle Valo u8 ac, 225bdcd8170SKalle Valo enum htc_endpoint_id ep) 226bdcd8170SKalle Valo { 227bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 228bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 229bdcd8170SKalle Valo } 230bdcd8170SKalle Valo 231bdcd8170SKalle Valo /* connect to a service */ 232bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 233bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 234bdcd8170SKalle Valo char *desc) 235bdcd8170SKalle Valo { 236bdcd8170SKalle Valo int status; 237bdcd8170SKalle Valo struct htc_service_connect_resp response; 238bdcd8170SKalle Valo 239bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 240bdcd8170SKalle Valo 241ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 242bdcd8170SKalle Valo if (status) { 243bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 244bdcd8170SKalle Valo desc, status); 245bdcd8170SKalle Valo return status; 246bdcd8170SKalle Valo } 247bdcd8170SKalle Valo 248bdcd8170SKalle Valo switch (con_req->svc_id) { 249bdcd8170SKalle Valo case WMI_CONTROL_SVC: 250bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 251bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 252bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 253bdcd8170SKalle Valo break; 254bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 255bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 256bdcd8170SKalle Valo break; 257bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 258bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 259bdcd8170SKalle Valo break; 260bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 261bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 262bdcd8170SKalle Valo break; 263bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 264bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 265bdcd8170SKalle Valo break; 266bdcd8170SKalle Valo default: 267bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 268bdcd8170SKalle Valo return -EINVAL; 269bdcd8170SKalle Valo } 270bdcd8170SKalle Valo 271bdcd8170SKalle Valo return 0; 272bdcd8170SKalle Valo } 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 275bdcd8170SKalle Valo { 276bdcd8170SKalle Valo struct htc_service_connect_req connect; 277bdcd8170SKalle Valo 278bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 279bdcd8170SKalle Valo 280bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 281900d6b3fSKalle Valo connect.ep_cb.tx_comp_multi = ath6kl_tx_complete; 282bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 283bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 284bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 285bdcd8170SKalle Valo 286bdcd8170SKalle Valo /* 287bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 288bdcd8170SKalle Valo * gets called. 289bdcd8170SKalle Valo */ 290bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 291bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 292bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 293bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 294bdcd8170SKalle Valo 295bdcd8170SKalle Valo /* connect to control service */ 296bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 297bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 298bdcd8170SKalle Valo return -EIO; 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 301bdcd8170SKalle Valo 302bdcd8170SKalle Valo /* 303bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 304bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 305bdcd8170SKalle Valo * (802.3) frames on the send path. 306bdcd8170SKalle Valo */ 307bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo /* 310bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 311bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 312bdcd8170SKalle Valo * packets. 313bdcd8170SKalle Valo */ 314bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 315bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo /* 318bdcd8170SKalle Valo * For the remaining data services set the connection flag to 319bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 320bdcd8170SKalle Valo */ 321bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 322bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 323bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 324bdcd8170SKalle Valo 325bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 326bdcd8170SKalle Valo 327bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 328bdcd8170SKalle Valo return -EIO; 329bdcd8170SKalle Valo 330bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 331bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 332bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 333bdcd8170SKalle Valo return -EIO; 334bdcd8170SKalle Valo 335bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 336bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 337bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 338bdcd8170SKalle Valo return -EIO; 339bdcd8170SKalle Valo 340bdcd8170SKalle Valo /* 341bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 342bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 343bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 344bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 345bdcd8170SKalle Valo * mailboxes. 346bdcd8170SKalle Valo */ 347bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 348bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 349bdcd8170SKalle Valo return -EIO; 350bdcd8170SKalle Valo 351bdcd8170SKalle Valo return 0; 352bdcd8170SKalle Valo } 353bdcd8170SKalle Valo 354e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 355bdcd8170SKalle Valo { 356e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3573450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3586f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 359f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 360bdcd8170SKalle Valo } 361bdcd8170SKalle Valo 362bdcd8170SKalle Valo /* 363bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 364bdcd8170SKalle Valo * target is in the BMI phase. 365bdcd8170SKalle Valo */ 366bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 367bdcd8170SKalle Valo u8 htc_ctrl_buf) 368bdcd8170SKalle Valo { 369bdcd8170SKalle Valo int status; 370bdcd8170SKalle Valo u32 blk_size; 371bdcd8170SKalle Valo 372bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 373bdcd8170SKalle Valo 374bdcd8170SKalle Valo if (htc_ctrl_buf) 375bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 376bdcd8170SKalle Valo 377bdcd8170SKalle Valo /* set the host interest area for the block size */ 37824fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size); 379bdcd8170SKalle Valo if (status) { 380bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 381bdcd8170SKalle Valo goto out; 382bdcd8170SKalle Valo } 383bdcd8170SKalle Valo 384bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 385bdcd8170SKalle Valo blk_size, 386bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 387bdcd8170SKalle Valo 388bdcd8170SKalle Valo if (mbox_isr_yield_val) { 389bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 39024fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit, 39124fc32b3SKalle Valo mbox_isr_yield_val); 392bdcd8170SKalle Valo if (status) { 393bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 394bdcd8170SKalle Valo goto out; 395bdcd8170SKalle Valo } 396bdcd8170SKalle Valo } 397bdcd8170SKalle Valo 398bdcd8170SKalle Valo out: 399bdcd8170SKalle Valo return status; 400bdcd8170SKalle Valo } 401bdcd8170SKalle Valo 4020ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 403bdcd8170SKalle Valo { 4044dea08e0SJouni Malinen int ret; 405bdcd8170SKalle Valo 406bdcd8170SKalle Valo /* 407bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 408bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 409bdcd8170SKalle Valo * RxMetaVersion to 2. 410bdcd8170SKalle Valo */ 4111ca4d0b6SKalle Valo ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 4121ca4d0b6SKalle Valo ar->rx_meta_ver, 0, 0); 4131ca4d0b6SKalle Valo if (ret) { 4141ca4d0b6SKalle Valo ath6kl_err("unable to set the rx frame format: %d\n", ret); 4151ca4d0b6SKalle Valo return ret; 416bdcd8170SKalle Valo } 417bdcd8170SKalle Valo 4181ca4d0b6SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) { 4191ca4d0b6SKalle Valo ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 42005aab177SKalle Valo IGNORE_PS_FAIL_DURING_SCAN); 4211ca4d0b6SKalle Valo if (ret) { 4221ca4d0b6SKalle Valo ath6kl_err("unable to set power save fail event policy: %d\n", 4231ca4d0b6SKalle Valo ret); 4241ca4d0b6SKalle Valo return ret; 4251ca4d0b6SKalle Valo } 426bdcd8170SKalle Valo } 427bdcd8170SKalle Valo 4281ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) { 4291ca4d0b6SKalle Valo ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 43005aab177SKalle Valo WMI_FOLLOW_BARKER_IN_ERP); 4311ca4d0b6SKalle Valo if (ret) { 4321ca4d0b6SKalle Valo ath6kl_err("unable to set barker preamble policy: %d\n", 4331ca4d0b6SKalle Valo ret); 4341ca4d0b6SKalle Valo return ret; 4351ca4d0b6SKalle Valo } 436bdcd8170SKalle Valo } 437bdcd8170SKalle Valo 4381ca4d0b6SKalle Valo ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 4391ca4d0b6SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL); 4401ca4d0b6SKalle Valo if (ret) { 4411ca4d0b6SKalle Valo ath6kl_err("unable to set keep alive interval: %d\n", ret); 4421ca4d0b6SKalle Valo return ret; 443bdcd8170SKalle Valo } 444bdcd8170SKalle Valo 4451ca4d0b6SKalle Valo ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 4461ca4d0b6SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT); 4471ca4d0b6SKalle Valo if (ret) { 4481ca4d0b6SKalle Valo ath6kl_err("unable to set disconnect timeout: %d\n", ret); 4491ca4d0b6SKalle Valo return ret; 450bdcd8170SKalle Valo } 451bdcd8170SKalle Valo 4521ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) { 4531ca4d0b6SKalle Valo ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED); 4541ca4d0b6SKalle Valo if (ret) { 4551ca4d0b6SKalle Valo ath6kl_err("unable to set txop bursting: %d\n", ret); 4561ca4d0b6SKalle Valo return ret; 4571ca4d0b6SKalle Valo } 458bdcd8170SKalle Valo } 459bdcd8170SKalle Valo 460b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4610ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4626bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4634dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4644dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4654dea08e0SJouni Malinen if (ret) { 4664dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4676bbc7c35SJouni Malinen "capabilities (%d) - assuming P2P not " 4686bbc7c35SJouni Malinen "supported\n", ret); 4693db1cd5cSRusty Russell ar->p2p = false; 4706bbc7c35SJouni Malinen } 4716bbc7c35SJouni Malinen } 4726bbc7c35SJouni Malinen 473b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4746bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 4750ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 4766bbc7c35SJouni Malinen if (ret) { 4776bbc7c35SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " 4786bbc7c35SJouni Malinen "Request reporting (%d)\n", ret); 4796bbc7c35SJouni Malinen } 4804dea08e0SJouni Malinen } 4814dea08e0SJouni Malinen 4821ca4d0b6SKalle Valo return ret; 483bdcd8170SKalle Valo } 484bdcd8170SKalle Valo 485bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 486bdcd8170SKalle Valo { 487bdcd8170SKalle Valo u32 param, ram_reserved_size; 4883226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 48939586bf2SRyan Hsu int i, status; 490bdcd8170SKalle Valo 491f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 49224fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) { 493a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 494a10e2f2fSVasanthakumar Thiagarajan return -EIO; 495a10e2f2fSVasanthakumar Thiagarajan } 496a10e2f2fSVasanthakumar Thiagarajan 4977b85832dSVasanthakumar Thiagarajan /* 4987b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 4997b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 5007b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 5017b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 5027b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 5037b85832dSVasanthakumar Thiagarajan * configured for now. 5047b85832dSVasanthakumar Thiagarajan */ 505dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 506bdcd8170SKalle Valo 50771f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 5087b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 5097b85832dSVasanthakumar Thiagarajan 5107b85832dSVasanthakumar Thiagarajan /* 5111e8d13b0SVasanthakumar Thiagarajan * Submodes when fw does not support dynamic interface 5121e8d13b0SVasanthakumar Thiagarajan * switching: 5133226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 5147b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 5157b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 5161e8d13b0SVasanthakumar Thiagarajan * Otherwise, All the interface are initialized to p2p dev. 5177b85832dSVasanthakumar Thiagarajan */ 5183226f68aSVasanthakumar Thiagarajan 5191e8d13b0SVasanthakumar Thiagarajan if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 5201e8d13b0SVasanthakumar Thiagarajan ar->fw_capabilities)) { 5211e8d13b0SVasanthakumar Thiagarajan for (i = 0; i < ar->vif_max; i++) 5221e8d13b0SVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5231e8d13b0SVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5241e8d13b0SVasanthakumar Thiagarajan } else { 5253226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 5263226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 5273226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5283226f68aSVasanthakumar Thiagarajan 52971f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 5303226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5313226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5327b85832dSVasanthakumar Thiagarajan 533b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5347b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5351e8d13b0SVasanthakumar Thiagarajan } 5367b85832dSVasanthakumar Thiagarajan 53724fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest, 53824fc32b3SKalle Valo HTC_PROTOCOL_VERSION) != 0) { 539bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 540bdcd8170SKalle Valo return -EIO; 541bdcd8170SKalle Valo } 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 544bdcd8170SKalle Valo param = 0; 545bdcd8170SKalle Valo 54680fb2686SKalle Valo if (ath6kl_bmi_read_hi32(ar, hi_option_flag, ¶m) != 0) { 547bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 548bdcd8170SKalle Valo return -EIO; 549bdcd8170SKalle Valo } 550bdcd8170SKalle Valo 55171f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5527b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5537b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5547b85832dSVasanthakumar Thiagarajan 555bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 556bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 557bdcd8170SKalle Valo 55824fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) { 559bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 560bdcd8170SKalle Valo return -EIO; 561bdcd8170SKalle Valo } 562bdcd8170SKalle Valo 563bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 564bdcd8170SKalle Valo 565bdcd8170SKalle Valo /* 566bdcd8170SKalle Valo * Hardcode the address use for the extended board data 567bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 568bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 569bdcd8170SKalle Valo * at init time, we have to workaround this from host. 570bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 571bdcd8170SKalle Valo * but possible in theory. 572bdcd8170SKalle Valo */ 573bdcd8170SKalle Valo 5746b42d308SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) { 575991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 576991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 577bdcd8170SKalle Valo 57824fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) { 579bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 580bdcd8170SKalle Valo return -EIO; 581bdcd8170SKalle Valo } 582991b27eaSKalle Valo 58324fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 58424fc32b3SKalle Valo ram_reserved_size) != 0) { 585bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 586bdcd8170SKalle Valo return -EIO; 587bdcd8170SKalle Valo } 5886b42d308SKalle Valo } 589bdcd8170SKalle Valo 590bdcd8170SKalle Valo /* set the block size for the target */ 591bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 592bdcd8170SKalle Valo /* use default number of control buffers */ 593bdcd8170SKalle Valo return -EIO; 594bdcd8170SKalle Valo 59539586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 59624fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin, 59724fc32b3SKalle Valo ar->hw.uarttx_pin); 59839586bf2SRyan Hsu if (status) 59939586bf2SRyan Hsu return status; 60039586bf2SRyan Hsu 60139586bf2SRyan Hsu /* Configure target refclk_hz */ 60224fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz); 60339586bf2SRyan Hsu if (status) 60439586bf2SRyan Hsu return status; 60539586bf2SRyan Hsu 606bdcd8170SKalle Valo return 0; 607bdcd8170SKalle Valo } 608bdcd8170SKalle Valo 609bdcd8170SKalle Valo /* firmware upload */ 610bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 611bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 612bdcd8170SKalle Valo { 613bdcd8170SKalle Valo const struct firmware *fw_entry; 614bdcd8170SKalle Valo int ret; 615bdcd8170SKalle Valo 616bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 617bdcd8170SKalle Valo if (ret) 618bdcd8170SKalle Valo return ret; 619bdcd8170SKalle Valo 620bdcd8170SKalle Valo *fw_len = fw_entry->size; 621bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 622bdcd8170SKalle Valo 623bdcd8170SKalle Valo if (*fw == NULL) 624bdcd8170SKalle Valo ret = -ENOMEM; 625bdcd8170SKalle Valo 626bdcd8170SKalle Valo release_firmware(fw_entry); 627bdcd8170SKalle Valo 628bdcd8170SKalle Valo return ret; 629bdcd8170SKalle Valo } 630bdcd8170SKalle Valo 63192ecbff4SSam Leffler #ifdef CONFIG_OF 63292ecbff4SSam Leffler /* 63392ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 63492ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 63592ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 63692ecbff4SSam Leffler * appropriate board-specific file. 63792ecbff4SSam Leffler */ 63892ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 63992ecbff4SSam Leffler { 64092ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 64192ecbff4SSam Leffler struct device_node *node; 64292ecbff4SSam Leffler char board_filename[64]; 64392ecbff4SSam Leffler const char *board_id; 64492ecbff4SSam Leffler int ret; 64592ecbff4SSam Leffler 64692ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 64792ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 64892ecbff4SSam Leffler if (board_id == NULL) { 64992ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 65092ecbff4SSam Leffler board_id_prop, node->name); 65192ecbff4SSam Leffler continue; 65292ecbff4SSam Leffler } 65392ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 654c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 65592ecbff4SSam Leffler 65692ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 65792ecbff4SSam Leffler &ar->fw_board_len); 65892ecbff4SSam Leffler if (ret) { 65992ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 66092ecbff4SSam Leffler board_filename, ret); 66192ecbff4SSam Leffler continue; 66292ecbff4SSam Leffler } 66392ecbff4SSam Leffler return true; 66492ecbff4SSam Leffler } 66592ecbff4SSam Leffler return false; 66692ecbff4SSam Leffler } 66792ecbff4SSam Leffler #else 66892ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 66992ecbff4SSam Leffler { 67092ecbff4SSam Leffler return false; 67192ecbff4SSam Leffler } 67292ecbff4SSam Leffler #endif /* CONFIG_OF */ 67392ecbff4SSam Leffler 674bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 675bdcd8170SKalle Valo { 676bdcd8170SKalle Valo const char *filename; 677bdcd8170SKalle Valo int ret; 678bdcd8170SKalle Valo 679772c31eeSKalle Valo if (ar->fw_board != NULL) 680772c31eeSKalle Valo return 0; 681772c31eeSKalle Valo 682d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 683d1a9421dSKalle Valo return -EINVAL; 684d1a9421dSKalle Valo 685d1a9421dSKalle Valo filename = ar->hw.fw_board; 686bdcd8170SKalle Valo 687bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 688bdcd8170SKalle Valo &ar->fw_board_len); 689bdcd8170SKalle Valo if (ret == 0) { 690bdcd8170SKalle Valo /* managed to get proper board file */ 691bdcd8170SKalle Valo return 0; 692bdcd8170SKalle Valo } 693bdcd8170SKalle Valo 69492ecbff4SSam Leffler if (check_device_tree(ar)) { 69592ecbff4SSam Leffler /* got board file from device tree */ 69692ecbff4SSam Leffler return 0; 69792ecbff4SSam Leffler } 69892ecbff4SSam Leffler 699bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 700bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 701bdcd8170SKalle Valo filename, ret); 702bdcd8170SKalle Valo 703d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 704bdcd8170SKalle Valo 705bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 706bdcd8170SKalle Valo &ar->fw_board_len); 707bdcd8170SKalle Valo if (ret) { 708bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 709bdcd8170SKalle Valo filename, ret); 710bdcd8170SKalle Valo return ret; 711bdcd8170SKalle Valo } 712bdcd8170SKalle Valo 713bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 714bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 715bdcd8170SKalle Valo 716bdcd8170SKalle Valo return 0; 717bdcd8170SKalle Valo } 718bdcd8170SKalle Valo 719772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 720772c31eeSKalle Valo { 721c0038972SKalle Valo char filename[100]; 722772c31eeSKalle Valo int ret; 723772c31eeSKalle Valo 724772c31eeSKalle Valo if (ar->fw_otp != NULL) 725772c31eeSKalle Valo return 0; 726772c31eeSKalle Valo 727c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 728d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 729d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 730772c31eeSKalle Valo return 0; 731772c31eeSKalle Valo } 732772c31eeSKalle Valo 733c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 734c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 735d1a9421dSKalle Valo 736772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 737772c31eeSKalle Valo &ar->fw_otp_len); 738772c31eeSKalle Valo if (ret) { 739772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 740772c31eeSKalle Valo filename, ret); 741772c31eeSKalle Valo return ret; 742772c31eeSKalle Valo } 743772c31eeSKalle Valo 744772c31eeSKalle Valo return 0; 745772c31eeSKalle Valo } 746772c31eeSKalle Valo 7475f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar) 748772c31eeSKalle Valo { 749c0038972SKalle Valo char filename[100]; 750772c31eeSKalle Valo int ret; 751772c31eeSKalle Valo 7525f1127ffSKalle Valo if (ar->testmode == 0) 753772c31eeSKalle Valo return 0; 754772c31eeSKalle Valo 7555f1127ffSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode); 7565f1127ffSKalle Valo 7575f1127ffSKalle Valo if (ar->testmode == 2) { 758cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) { 759cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n"); 760cd23c1c9SAlex Yang return -EOPNOTSUPP; 761cd23c1c9SAlex Yang } 762cd23c1c9SAlex Yang 763cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 764cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf); 765cd23c1c9SAlex Yang } else { 766c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 767cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n"); 768772c31eeSKalle Valo return -EOPNOTSUPP; 769772c31eeSKalle Valo } 770772c31eeSKalle Valo 771c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 772c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 773cd23c1c9SAlex Yang } 7745f1127ffSKalle Valo 775772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 776772c31eeSKalle Valo 7775f1127ffSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 7785f1127ffSKalle Valo if (ret) { 7795f1127ffSKalle Valo ath6kl_err("Failed to get testmode %d firmware file %s: %d\n", 7805f1127ffSKalle Valo ar->testmode, filename, ret); 7815f1127ffSKalle Valo return ret; 782772c31eeSKalle Valo } 783772c31eeSKalle Valo 7845f1127ffSKalle Valo return 0; 7855f1127ffSKalle Valo } 7865f1127ffSKalle Valo 7875f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 7885f1127ffSKalle Valo { 7895f1127ffSKalle Valo char filename[100]; 7905f1127ffSKalle Valo int ret; 7915f1127ffSKalle Valo 7925f1127ffSKalle Valo if (ar->fw != NULL) 7935f1127ffSKalle Valo return 0; 7945f1127ffSKalle Valo 795c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 796c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 797d1a9421dSKalle Valo return -EINVAL; 798d1a9421dSKalle Valo 799c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 800c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 801772c31eeSKalle Valo 802772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 803772c31eeSKalle Valo if (ret) { 804772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 805772c31eeSKalle Valo filename, ret); 806772c31eeSKalle Valo return ret; 807772c31eeSKalle Valo } 808772c31eeSKalle Valo 809772c31eeSKalle Valo return 0; 810772c31eeSKalle Valo } 811772c31eeSKalle Valo 812772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 813772c31eeSKalle Valo { 814c0038972SKalle Valo char filename[100]; 815772c31eeSKalle Valo int ret; 816772c31eeSKalle Valo 817d1a9421dSKalle Valo if (ar->fw_patch != NULL) 818772c31eeSKalle Valo return 0; 819772c31eeSKalle Valo 820c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 821d1a9421dSKalle Valo return 0; 822d1a9421dSKalle Valo 823c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 824c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 825d1a9421dSKalle Valo 826772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 827772c31eeSKalle Valo &ar->fw_patch_len); 828772c31eeSKalle Valo if (ret) { 829772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 830772c31eeSKalle Valo filename, ret); 831772c31eeSKalle Valo return ret; 832772c31eeSKalle Valo } 833772c31eeSKalle Valo 834772c31eeSKalle Valo return 0; 835772c31eeSKalle Valo } 836772c31eeSKalle Valo 837cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar) 838cd23c1c9SAlex Yang { 839cd23c1c9SAlex Yang char filename[100]; 840cd23c1c9SAlex Yang int ret; 841cd23c1c9SAlex Yang 8425f1127ffSKalle Valo if (ar->testmode != 2) 843cd23c1c9SAlex Yang return 0; 844cd23c1c9SAlex Yang 845cd23c1c9SAlex Yang if (ar->fw_testscript != NULL) 846cd23c1c9SAlex Yang return 0; 847cd23c1c9SAlex Yang 848cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL) 849cd23c1c9SAlex Yang return 0; 850cd23c1c9SAlex Yang 851cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 852cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript); 853cd23c1c9SAlex Yang 854cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 855cd23c1c9SAlex Yang &ar->fw_testscript_len); 856cd23c1c9SAlex Yang if (ret) { 857cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n", 858cd23c1c9SAlex Yang filename, ret); 859cd23c1c9SAlex Yang return ret; 860cd23c1c9SAlex Yang } 861cd23c1c9SAlex Yang 862cd23c1c9SAlex Yang return 0; 863cd23c1c9SAlex Yang } 864cd23c1c9SAlex Yang 86550d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 866772c31eeSKalle Valo { 867772c31eeSKalle Valo int ret; 868772c31eeSKalle Valo 869772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 870772c31eeSKalle Valo if (ret) 871772c31eeSKalle Valo return ret; 872772c31eeSKalle Valo 873772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 874772c31eeSKalle Valo if (ret) 875772c31eeSKalle Valo return ret; 876772c31eeSKalle Valo 877772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 878772c31eeSKalle Valo if (ret) 879772c31eeSKalle Valo return ret; 880772c31eeSKalle Valo 881cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar); 882cd23c1c9SAlex Yang if (ret) 883cd23c1c9SAlex Yang return ret; 884cd23c1c9SAlex Yang 885772c31eeSKalle Valo return 0; 886772c31eeSKalle Valo } 887bdcd8170SKalle Valo 88865a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 88950d41234SKalle Valo { 89050d41234SKalle Valo size_t magic_len, len, ie_len; 89150d41234SKalle Valo const struct firmware *fw; 89250d41234SKalle Valo struct ath6kl_fw_ie *hdr; 893c0038972SKalle Valo char filename[100]; 89450d41234SKalle Valo const u8 *data; 89597e0496dSKalle Valo int ret, ie_id, i, index, bit; 8968a137480SKalle Valo __le32 *val; 89750d41234SKalle Valo 89865a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 89950d41234SKalle Valo 90050d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 90150d41234SKalle Valo if (ret) 90250d41234SKalle Valo return ret; 90350d41234SKalle Valo 90450d41234SKalle Valo data = fw->data; 90550d41234SKalle Valo len = fw->size; 90650d41234SKalle Valo 90750d41234SKalle Valo /* magic also includes the null byte, check that as well */ 90850d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 90950d41234SKalle Valo 91050d41234SKalle Valo if (len < magic_len) { 91150d41234SKalle Valo ret = -EINVAL; 91250d41234SKalle Valo goto out; 91350d41234SKalle Valo } 91450d41234SKalle Valo 91550d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 91650d41234SKalle Valo ret = -EINVAL; 91750d41234SKalle Valo goto out; 91850d41234SKalle Valo } 91950d41234SKalle Valo 92050d41234SKalle Valo len -= magic_len; 92150d41234SKalle Valo data += magic_len; 92250d41234SKalle Valo 92350d41234SKalle Valo /* loop elements */ 92450d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 92550d41234SKalle Valo /* hdr is unaligned! */ 92650d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 92750d41234SKalle Valo 92850d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 92950d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 93050d41234SKalle Valo 93150d41234SKalle Valo len -= sizeof(*hdr); 93250d41234SKalle Valo data += sizeof(*hdr); 93350d41234SKalle Valo 93450d41234SKalle Valo if (len < ie_len) { 93550d41234SKalle Valo ret = -EINVAL; 93650d41234SKalle Valo goto out; 93750d41234SKalle Valo } 93850d41234SKalle Valo 93950d41234SKalle Valo switch (ie_id) { 94050d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 941ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9426bc36431SKalle Valo ie_len); 9436bc36431SKalle Valo 94450d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 94550d41234SKalle Valo 94650d41234SKalle Valo if (ar->fw_otp == NULL) { 94750d41234SKalle Valo ret = -ENOMEM; 94850d41234SKalle Valo goto out; 94950d41234SKalle Valo } 95050d41234SKalle Valo 95150d41234SKalle Valo ar->fw_otp_len = ie_len; 95250d41234SKalle Valo break; 95350d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 954ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9556bc36431SKalle Valo ie_len); 9566bc36431SKalle Valo 9575f1127ffSKalle Valo /* in testmode we already might have a fw file */ 9585f1127ffSKalle Valo if (ar->fw != NULL) 9595f1127ffSKalle Valo break; 9605f1127ffSKalle Valo 9618437754cSVivek Natarajan ar->fw = vmalloc(ie_len); 96250d41234SKalle Valo 96350d41234SKalle Valo if (ar->fw == NULL) { 96450d41234SKalle Valo ret = -ENOMEM; 96550d41234SKalle Valo goto out; 96650d41234SKalle Valo } 96750d41234SKalle Valo 9688437754cSVivek Natarajan memcpy(ar->fw, data, ie_len); 96950d41234SKalle Valo ar->fw_len = ie_len; 97050d41234SKalle Valo break; 97150d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 972ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 9736bc36431SKalle Valo ie_len); 9746bc36431SKalle Valo 97550d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 97650d41234SKalle Valo 97750d41234SKalle Valo if (ar->fw_patch == NULL) { 97850d41234SKalle Valo ret = -ENOMEM; 97950d41234SKalle Valo goto out; 98050d41234SKalle Valo } 98150d41234SKalle Valo 98250d41234SKalle Valo ar->fw_patch_len = ie_len; 98350d41234SKalle Valo break; 9848a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 9858a137480SKalle Valo val = (__le32 *) data; 9868a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 9876bc36431SKalle Valo 9886bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 9896bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 9906bc36431SKalle Valo ar->hw.reserved_ram_size); 9918a137480SKalle Valo break; 99297e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 993277d90f4SKalle Valo if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) 994277d90f4SKalle Valo break; 995277d90f4SKalle Valo 9966bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 997ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 9986bc36431SKalle Valo ie_len); 9996bc36431SKalle Valo 100097e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 1001277d90f4SKalle Valo index = i / 8; 100297e0496dSKalle Valo bit = i % 8; 100397e0496dSKalle Valo 100497e0496dSKalle Valo if (data[index] & (1 << bit)) 100597e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 100697e0496dSKalle Valo } 10076bc36431SKalle Valo 10086bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 10096bc36431SKalle Valo ar->fw_capabilities, 10106bc36431SKalle Valo sizeof(ar->fw_capabilities)); 101197e0496dSKalle Valo break; 10121b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 10131b4304daSKalle Valo if (ie_len != sizeof(*val)) 10141b4304daSKalle Valo break; 10151b4304daSKalle Valo 10161b4304daSKalle Valo val = (__le32 *) data; 10171b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 10186bc36431SKalle Valo 10196bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 102003ef0250SKalle Valo "found patch address ie 0x%x\n", 10216bc36431SKalle Valo ar->hw.dataset_patch_addr); 10221b4304daSKalle Valo break; 102303ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 102403ef0250SKalle Valo if (ie_len != sizeof(*val)) 102503ef0250SKalle Valo break; 102603ef0250SKalle Valo 102703ef0250SKalle Valo val = (__le32 *) data; 102803ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 102903ef0250SKalle Valo 103003ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 103103ef0250SKalle Valo "found board address ie 0x%x\n", 103203ef0250SKalle Valo ar->hw.board_addr); 103303ef0250SKalle Valo break; 1034368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 1035368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 1036368b1b0fSKalle Valo break; 1037368b1b0fSKalle Valo 1038368b1b0fSKalle Valo val = (__le32 *) data; 1039368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 1040368b1b0fSKalle Valo ATH6KL_VIF_MAX); 1041368b1b0fSKalle Valo 1042f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 1043f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1044f143379dSVasanthakumar Thiagarajan 1045368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1046368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1047368b1b0fSKalle Valo break; 104850d41234SKalle Valo default: 10496bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 105050d41234SKalle Valo le32_to_cpup(&hdr->id)); 105150d41234SKalle Valo break; 105250d41234SKalle Valo } 105350d41234SKalle Valo 105450d41234SKalle Valo len -= ie_len; 105550d41234SKalle Valo data += ie_len; 105650d41234SKalle Valo }; 105750d41234SKalle Valo 105850d41234SKalle Valo ret = 0; 105950d41234SKalle Valo out: 106050d41234SKalle Valo release_firmware(fw); 106150d41234SKalle Valo 106250d41234SKalle Valo return ret; 106350d41234SKalle Valo } 106450d41234SKalle Valo 106545eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar) 106650d41234SKalle Valo { 106750d41234SKalle Valo int ret; 106850d41234SKalle Valo 106950d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 107050d41234SKalle Valo if (ret) 107150d41234SKalle Valo return ret; 107250d41234SKalle Valo 10735f1127ffSKalle Valo ret = ath6kl_fetch_testmode_file(ar); 10745f1127ffSKalle Valo if (ret) 10755f1127ffSKalle Valo return ret; 10765f1127ffSKalle Valo 107765a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 10786bc36431SKalle Valo if (ret == 0) { 107965a8b4ccSKalle Valo ar->fw_api = 3; 108065a8b4ccSKalle Valo goto out; 108165a8b4ccSKalle Valo } 108265a8b4ccSKalle Valo 108365a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 108465a8b4ccSKalle Valo if (ret == 0) { 108565a8b4ccSKalle Valo ar->fw_api = 2; 108665a8b4ccSKalle Valo goto out; 10876bc36431SKalle Valo } 108850d41234SKalle Valo 108950d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 109050d41234SKalle Valo if (ret) 109150d41234SKalle Valo return ret; 109250d41234SKalle Valo 109365a8b4ccSKalle Valo ar->fw_api = 1; 109465a8b4ccSKalle Valo 109565a8b4ccSKalle Valo out: 109665a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 10976bc36431SKalle Valo 109850d41234SKalle Valo return 0; 109950d41234SKalle Valo } 110050d41234SKalle Valo 1101bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1102bdcd8170SKalle Valo { 1103bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 110431024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1105bdcd8170SKalle Valo int ret; 1106bdcd8170SKalle Valo 1107772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1108772c31eeSKalle Valo return -ENOENT; 1109bdcd8170SKalle Valo 111031024d99SKevin Fang /* 111131024d99SKevin Fang * Determine where in Target RAM to write Board Data. 111231024d99SKevin Fang * For AR6004, host determine Target RAM address for 111331024d99SKevin Fang * writing board data. 111431024d99SKevin Fang */ 11150d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 1116b0fc7c1aSKalle Valo board_address = ar->hw.board_addr; 111724fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data, 1118b0fc7c1aSKalle Valo board_address); 111931024d99SKevin Fang } else { 112080fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address); 112131024d99SKevin Fang } 112231024d99SKevin Fang 1123bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 112480fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address); 1125bdcd8170SKalle Valo 112650e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 112750e2740bSKalle Valo board_ext_address == 0) { 1128bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1129bdcd8170SKalle Valo return -EINVAL; 1130bdcd8170SKalle Valo } 1131bdcd8170SKalle Valo 113231024d99SKevin Fang switch (ar->target_type) { 113331024d99SKevin Fang case TARGET_TYPE_AR6003: 113431024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 113531024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 1136fb1ac2efSPrasanna Kumar if (ar->fw_board_len > (board_data_size + board_ext_data_size)) 1137fb1ac2efSPrasanna Kumar board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2; 113831024d99SKevin Fang break; 113931024d99SKevin Fang case TARGET_TYPE_AR6004: 114031024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 114131024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 114231024d99SKevin Fang break; 114331024d99SKevin Fang default: 114431024d99SKevin Fang WARN_ON(1); 114531024d99SKevin Fang return -EINVAL; 114631024d99SKevin Fang break; 114731024d99SKevin Fang } 114831024d99SKevin Fang 114950e2740bSKalle Valo if (board_ext_address && 115050e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 115131024d99SKevin Fang 1152bdcd8170SKalle Valo /* write extended board data */ 11536bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11546bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11556bc36431SKalle Valo board_ext_address, board_ext_data_size); 11566bc36431SKalle Valo 1157bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 115831024d99SKevin Fang ar->fw_board + board_data_size, 115931024d99SKevin Fang board_ext_data_size); 1160bdcd8170SKalle Valo if (ret) { 1161bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1162bdcd8170SKalle Valo ret); 1163bdcd8170SKalle Valo return ret; 1164bdcd8170SKalle Valo } 1165bdcd8170SKalle Valo 1166bdcd8170SKalle Valo /* record that extended board data is initialized */ 116731024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 116831024d99SKevin Fang 116924fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param); 1170bdcd8170SKalle Valo } 1171bdcd8170SKalle Valo 117231024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1173bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1174bdcd8170SKalle Valo ret = -EINVAL; 1175bdcd8170SKalle Valo return ret; 1176bdcd8170SKalle Valo } 1177bdcd8170SKalle Valo 11786bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 11796bc36431SKalle Valo board_address, board_data_size); 11806bc36431SKalle Valo 1181bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 118231024d99SKevin Fang board_data_size); 1183bdcd8170SKalle Valo 1184bdcd8170SKalle Valo if (ret) { 1185bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1186bdcd8170SKalle Valo return ret; 1187bdcd8170SKalle Valo } 1188bdcd8170SKalle Valo 1189bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 119024fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1); 1191bdcd8170SKalle Valo 1192bdcd8170SKalle Valo return ret; 1193bdcd8170SKalle Valo } 1194bdcd8170SKalle Valo 1195bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1196bdcd8170SKalle Valo { 1197bdcd8170SKalle Valo u32 address, param; 1198bef26a7fSKalle Valo bool from_hw = false; 1199bdcd8170SKalle Valo int ret; 1200bdcd8170SKalle Valo 120150e2740bSKalle Valo if (ar->fw_otp == NULL) 120250e2740bSKalle Valo return 0; 1203bdcd8170SKalle Valo 1204a01ac414SKalle Valo address = ar->hw.app_load_addr; 1205bdcd8170SKalle Valo 1206ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 12076bc36431SKalle Valo ar->fw_otp_len); 12086bc36431SKalle Valo 1209bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1210bdcd8170SKalle Valo ar->fw_otp_len); 1211bdcd8170SKalle Valo if (ret) { 1212bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1213bdcd8170SKalle Valo return ret; 1214bdcd8170SKalle Valo } 1215bdcd8170SKalle Valo 1216639d0b89SKalle Valo /* read firmware start address */ 121780fb2686SKalle Valo ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address); 1218639d0b89SKalle Valo 1219639d0b89SKalle Valo if (ret) { 1220639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1221639d0b89SKalle Valo return ret; 1222639d0b89SKalle Valo } 1223639d0b89SKalle Valo 1224bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1225639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1226bef26a7fSKalle Valo from_hw = true; 1227bef26a7fSKalle Valo } 1228639d0b89SKalle Valo 1229bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1230bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 12316bc36431SKalle Valo ar->hw.app_start_override_addr); 12326bc36431SKalle Valo 1233bdcd8170SKalle Valo /* execute the OTP code */ 1234bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1235bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1236bdcd8170SKalle Valo param = 0; 1237bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1238bdcd8170SKalle Valo 1239bdcd8170SKalle Valo return ret; 1240bdcd8170SKalle Valo } 1241bdcd8170SKalle Valo 1242bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1243bdcd8170SKalle Valo { 1244bdcd8170SKalle Valo u32 address; 1245bdcd8170SKalle Valo int ret; 1246bdcd8170SKalle Valo 1247772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 124850e2740bSKalle Valo return 0; 1249bdcd8170SKalle Valo 1250a01ac414SKalle Valo address = ar->hw.app_load_addr; 1251bdcd8170SKalle Valo 1252ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12536bc36431SKalle Valo address, ar->fw_len); 12546bc36431SKalle Valo 1255bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1256bdcd8170SKalle Valo 1257bdcd8170SKalle Valo if (ret) { 1258bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1259bdcd8170SKalle Valo return ret; 1260bdcd8170SKalle Valo } 1261bdcd8170SKalle Valo 126231024d99SKevin Fang /* 126331024d99SKevin Fang * Set starting address for firmware 126431024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 126531024d99SKevin Fang */ 126631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1267a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1268bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 126931024d99SKevin Fang } 1270bdcd8170SKalle Valo return ret; 1271bdcd8170SKalle Valo } 1272bdcd8170SKalle Valo 1273bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1274bdcd8170SKalle Valo { 127524fc32b3SKalle Valo u32 address; 1276bdcd8170SKalle Valo int ret; 1277bdcd8170SKalle Valo 127850e2740bSKalle Valo if (ar->fw_patch == NULL) 127950e2740bSKalle Valo return 0; 1280bdcd8170SKalle Valo 1281a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1282bdcd8170SKalle Valo 1283ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 12846bc36431SKalle Valo address, ar->fw_patch_len); 12856bc36431SKalle Valo 1286bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1287bdcd8170SKalle Valo if (ret) { 1288bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1289bdcd8170SKalle Valo return ret; 1290bdcd8170SKalle Valo } 1291bdcd8170SKalle Valo 129224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address); 1293bdcd8170SKalle Valo 1294bdcd8170SKalle Valo return 0; 1295bdcd8170SKalle Valo } 1296bdcd8170SKalle Valo 1297cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar) 1298cd23c1c9SAlex Yang { 129924fc32b3SKalle Valo u32 address; 1300cd23c1c9SAlex Yang int ret; 1301cd23c1c9SAlex Yang 13025f1127ffSKalle Valo if (ar->testmode != 2) 1303cd23c1c9SAlex Yang return 0; 1304cd23c1c9SAlex Yang 1305cd23c1c9SAlex Yang if (ar->fw_testscript == NULL) 1306cd23c1c9SAlex Yang return 0; 1307cd23c1c9SAlex Yang 1308cd23c1c9SAlex Yang address = ar->hw.testscript_addr; 1309cd23c1c9SAlex Yang 1310cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1311cd23c1c9SAlex Yang address, ar->fw_testscript_len); 1312cd23c1c9SAlex Yang 1313cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1314cd23c1c9SAlex Yang ar->fw_testscript_len); 1315cd23c1c9SAlex Yang if (ret) { 1316cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret); 1317cd23c1c9SAlex Yang return ret; 1318cd23c1c9SAlex Yang } 1319cd23c1c9SAlex Yang 132024fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address); 132124fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096); 132224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1); 1323cd23c1c9SAlex Yang 1324cd23c1c9SAlex Yang return 0; 1325cd23c1c9SAlex Yang } 1326cd23c1c9SAlex Yang 1327bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1328bdcd8170SKalle Valo { 1329bdcd8170SKalle Valo u32 param, options, sleep, address; 1330bdcd8170SKalle Valo int status = 0; 1331bdcd8170SKalle Valo 133231024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 133331024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1334bdcd8170SKalle Valo return -EINVAL; 1335bdcd8170SKalle Valo 1336bdcd8170SKalle Valo /* temporarily disable system sleep */ 1337bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1338bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1339bdcd8170SKalle Valo if (status) 1340bdcd8170SKalle Valo return status; 1341bdcd8170SKalle Valo 1342bdcd8170SKalle Valo options = param; 1343bdcd8170SKalle Valo 1344bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1345bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1346bdcd8170SKalle Valo if (status) 1347bdcd8170SKalle Valo return status; 1348bdcd8170SKalle Valo 1349bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1350bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1351bdcd8170SKalle Valo if (status) 1352bdcd8170SKalle Valo return status; 1353bdcd8170SKalle Valo 1354bdcd8170SKalle Valo sleep = param; 1355bdcd8170SKalle Valo 1356bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1357bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1358bdcd8170SKalle Valo if (status) 1359bdcd8170SKalle Valo return status; 1360bdcd8170SKalle Valo 1361bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1362bdcd8170SKalle Valo options, sleep); 1363bdcd8170SKalle Valo 1364bdcd8170SKalle Valo /* program analog PLL register */ 136531024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 136631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1367bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1368bdcd8170SKalle Valo 0xF9104001); 136931024d99SKevin Fang 1370bdcd8170SKalle Valo if (status) 1371bdcd8170SKalle Valo return status; 1372bdcd8170SKalle Valo 1373bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1374bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1375bdcd8170SKalle Valo 1376bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1377bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1378bdcd8170SKalle Valo if (status) 1379bdcd8170SKalle Valo return status; 138031024d99SKevin Fang } 1381bdcd8170SKalle Valo 1382bdcd8170SKalle Valo param = 0; 1383bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1384bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1385bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1386bdcd8170SKalle Valo if (status) 1387bdcd8170SKalle Valo return status; 1388bdcd8170SKalle Valo 1389bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 13904480bb59SRaja Mani if (ar->version.target_ver == AR6003_HW_2_0_VERSION || 13914480bb59SRaja Mani ar->version.target_ver == AR6003_HW_2_1_1_VERSION) { 1392bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1393bdcd8170SKalle Valo 1394bdcd8170SKalle Valo param = 0x20; 1395bdcd8170SKalle Valo 1396bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1397bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1398bdcd8170SKalle Valo if (status) 1399bdcd8170SKalle Valo return status; 1400bdcd8170SKalle Valo 1401bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1402bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1403bdcd8170SKalle Valo if (status) 1404bdcd8170SKalle Valo return status; 1405bdcd8170SKalle Valo 1406bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1407bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1408bdcd8170SKalle Valo if (status) 1409bdcd8170SKalle Valo return status; 1410bdcd8170SKalle Valo 1411bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1412bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1413bdcd8170SKalle Valo if (status) 1414bdcd8170SKalle Valo return status; 1415bdcd8170SKalle Valo } 1416bdcd8170SKalle Valo 1417bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1418bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1419bdcd8170SKalle Valo if (status) 1420bdcd8170SKalle Valo return status; 1421bdcd8170SKalle Valo 1422bdcd8170SKalle Valo /* transfer One time Programmable data */ 1423bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1424bdcd8170SKalle Valo if (status) 1425bdcd8170SKalle Valo return status; 1426bdcd8170SKalle Valo 1427bdcd8170SKalle Valo /* Download Target firmware */ 1428bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1429bdcd8170SKalle Valo if (status) 1430bdcd8170SKalle Valo return status; 1431bdcd8170SKalle Valo 1432bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1433bdcd8170SKalle Valo if (status) 1434bdcd8170SKalle Valo return status; 1435bdcd8170SKalle Valo 1436cd23c1c9SAlex Yang /* Download the test script */ 1437cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar); 1438cd23c1c9SAlex Yang if (status) 1439cd23c1c9SAlex Yang return status; 1440cd23c1c9SAlex Yang 1441bdcd8170SKalle Valo /* Restore system sleep */ 1442bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1443bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1444bdcd8170SKalle Valo if (status) 1445bdcd8170SKalle Valo return status; 1446bdcd8170SKalle Valo 1447bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1448bdcd8170SKalle Valo param = options | 0x20; 1449bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1450bdcd8170SKalle Valo if (status) 1451bdcd8170SKalle Valo return status; 1452bdcd8170SKalle Valo 1453bdcd8170SKalle Valo return status; 1454bdcd8170SKalle Valo } 1455bdcd8170SKalle Valo 145645eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar) 1457a01ac414SKalle Valo { 14581b46dc04SKalle Valo const struct ath6kl_hw *uninitialized_var(hw); 1459856f4b31SKalle Valo int i; 1460bef26a7fSKalle Valo 1461856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1462856f4b31SKalle Valo hw = &hw_list[i]; 1463bef26a7fSKalle Valo 1464856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1465a01ac414SKalle Valo break; 1466856f4b31SKalle Valo } 1467856f4b31SKalle Valo 1468856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1469a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1470a01ac414SKalle Valo ar->version.target_ver); 1471a01ac414SKalle Valo return -EINVAL; 1472a01ac414SKalle Valo } 1473a01ac414SKalle Valo 1474856f4b31SKalle Valo ar->hw = *hw; 1475856f4b31SKalle Valo 14766bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14776bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 14786bc36431SKalle Valo ar->version.target_ver, ar->target_type, 14796bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 14806bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14816bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 14826bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 14836bc36431SKalle Valo ar->hw.reserved_ram_size); 148439586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 148539586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 148639586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 14876bc36431SKalle Valo 1488a01ac414SKalle Valo return 0; 1489a01ac414SKalle Valo } 1490a01ac414SKalle Valo 1491293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1492293badf4SKalle Valo { 1493293badf4SKalle Valo switch (type) { 1494293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1495293badf4SKalle Valo return "sdio"; 1496293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1497293badf4SKalle Valo return "usb"; 1498293badf4SKalle Valo } 1499293badf4SKalle Valo 1500293badf4SKalle Valo return NULL; 1501293badf4SKalle Valo } 1502293badf4SKalle Valo 15035fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 150420459ee2SKalle Valo { 150520459ee2SKalle Valo long timeleft; 150620459ee2SKalle Valo int ret, i; 150720459ee2SKalle Valo 15085fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 15095fe4dffbSKalle Valo 151020459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 151120459ee2SKalle Valo if (ret) 151220459ee2SKalle Valo return ret; 151320459ee2SKalle Valo 151420459ee2SKalle Valo ret = ath6kl_configure_target(ar); 151520459ee2SKalle Valo if (ret) 151620459ee2SKalle Valo goto err_power_off; 151720459ee2SKalle Valo 151820459ee2SKalle Valo ret = ath6kl_init_upload(ar); 151920459ee2SKalle Valo if (ret) 152020459ee2SKalle Valo goto err_power_off; 152120459ee2SKalle Valo 152220459ee2SKalle Valo /* Do we need to finish the BMI phase */ 152320459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 152420459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 152520459ee2SKalle Valo ret = -EIO; 152620459ee2SKalle Valo goto err_power_off; 152720459ee2SKalle Valo } 152820459ee2SKalle Valo 152920459ee2SKalle Valo /* 153020459ee2SKalle Valo * The reason we have to wait for the target here is that the 153120459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 153220459ee2SKalle Valo * size. 153320459ee2SKalle Valo */ 153420459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 153520459ee2SKalle Valo ret = -EIO; 153620459ee2SKalle Valo goto err_power_off; 153720459ee2SKalle Valo } 153820459ee2SKalle Valo 153920459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 154020459ee2SKalle Valo ret = -EIO; 154120459ee2SKalle Valo goto err_cleanup_scatter; 154220459ee2SKalle Valo } 154320459ee2SKalle Valo 154420459ee2SKalle Valo /* setup credit distribution */ 1545e76ac2bfSKalle Valo ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info); 154620459ee2SKalle Valo 154720459ee2SKalle Valo /* start HTC */ 154820459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 154920459ee2SKalle Valo if (ret) { 155020459ee2SKalle Valo /* FIXME: call this */ 155120459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 155220459ee2SKalle Valo goto err_cleanup_scatter; 155320459ee2SKalle Valo } 155420459ee2SKalle Valo 155520459ee2SKalle Valo /* Wait for Wmi event to be ready */ 155620459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 155720459ee2SKalle Valo test_bit(WMI_READY, 155820459ee2SKalle Valo &ar->flag), 155920459ee2SKalle Valo WMI_TIMEOUT); 156020459ee2SKalle Valo 156120459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 156220459ee2SKalle Valo 1563293badf4SKalle Valo 1564293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 156565a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1566293badf4SKalle Valo ar->hw.name, 1567293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1568293badf4SKalle Valo ar->wiphy->fw_version, 156965a8b4ccSKalle Valo ar->fw_api, 1570293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1571293badf4SKalle Valo } 1572293badf4SKalle Valo 157320459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 157420459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 157520459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 157620459ee2SKalle Valo ret = -EIO; 157720459ee2SKalle Valo goto err_htc_stop; 157820459ee2SKalle Valo } 157920459ee2SKalle Valo 158020459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 158120459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 158220459ee2SKalle Valo ret = -EIO; 158320459ee2SKalle Valo goto err_htc_stop; 158420459ee2SKalle Valo } 158520459ee2SKalle Valo 158620459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 158720459ee2SKalle Valo 158820459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 158920459ee2SKalle Valo /* FIXME: return error */ 159020459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 159120459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 159220459ee2SKalle Valo 159371f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 159420459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 159520459ee2SKalle Valo if (ret) 159620459ee2SKalle Valo goto err_htc_stop; 159720459ee2SKalle Valo } 159820459ee2SKalle Valo 159976a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 160076a9fbe2SKalle Valo 160120459ee2SKalle Valo return 0; 160220459ee2SKalle Valo 160320459ee2SKalle Valo err_htc_stop: 160420459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 160520459ee2SKalle Valo err_cleanup_scatter: 160620459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 160720459ee2SKalle Valo err_power_off: 160820459ee2SKalle Valo ath6kl_hif_power_off(ar); 160920459ee2SKalle Valo 161020459ee2SKalle Valo return ret; 161120459ee2SKalle Valo } 161220459ee2SKalle Valo 16135fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 16145fe4dffbSKalle Valo { 16155fe4dffbSKalle Valo int ret; 16165fe4dffbSKalle Valo 16175fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 16185fe4dffbSKalle Valo 16195fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 16205fe4dffbSKalle Valo 16215fe4dffbSKalle Valo ath6kl_hif_stop(ar); 16225fe4dffbSKalle Valo 16235fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 16245fe4dffbSKalle Valo 16255fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 16265fe4dffbSKalle Valo if (ret) 16275fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 16285fe4dffbSKalle Valo 162976a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 163076a9fbe2SKalle Valo 16315fe4dffbSKalle Valo return 0; 16325fe4dffbSKalle Valo } 16335fe4dffbSKalle Valo 1634c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ 163555055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 16366db8fa53SVasanthakumar Thiagarajan { 16376db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 16386db8fa53SVasanthakumar Thiagarajan bool discon_issued; 16396db8fa53SVasanthakumar Thiagarajan 16406db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 16416db8fa53SVasanthakumar Thiagarajan 16426db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 16436db8fa53SVasanthakumar Thiagarajan 16446db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 16456db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 16466db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 16476db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 16486db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 16496db8fa53SVasanthakumar Thiagarajan 16506db8fa53SVasanthakumar Thiagarajan if (discon_issued) 16516db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 16526db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 16536db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 16546db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 16556db8fa53SVasanthakumar Thiagarajan } 16566db8fa53SVasanthakumar Thiagarajan 16576db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 16586db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 16596db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 16606db8fa53SVasanthakumar Thiagarajan } 16616db8fa53SVasanthakumar Thiagarajan } 16626db8fa53SVasanthakumar Thiagarajan 1663bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1664bdcd8170SKalle Valo { 1665990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 16661d2a4456SVasanthakumar Thiagarajan int i; 1667bdcd8170SKalle Valo 1668bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1669bdcd8170SKalle Valo 1670bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1671bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1672bdcd8170SKalle Valo return; 1673bdcd8170SKalle Valo } 1674bdcd8170SKalle Valo 16751d2a4456SVasanthakumar Thiagarajan for (i = 0; i < AP_MAX_NUM_STA; i++) 16761d2a4456SVasanthakumar Thiagarajan aggr_reset_state(ar->sta_list[i].aggr_conn); 16771d2a4456SVasanthakumar Thiagarajan 167811f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1679990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1680990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 168111f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1682990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 168327929723SVasanthakumar Thiagarajan rtnl_lock(); 1684c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif); 168527929723SVasanthakumar Thiagarajan rtnl_unlock(); 168611f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1687990bd915SVasanthakumar Thiagarajan } 168811f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1689bdcd8170SKalle Valo 16906db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 16916db8fa53SVasanthakumar Thiagarajan 16926db8fa53SVasanthakumar Thiagarajan /* 16936db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 16946db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 16956db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 16966db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 16976db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 16986db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 16996db8fa53SVasanthakumar Thiagarajan * are collected. 17006db8fa53SVasanthakumar Thiagarajan */ 17016db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 17026db8fa53SVasanthakumar Thiagarajan 17036db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 17046db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 17056db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 17066db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1707bdcd8170SKalle Valo } 1708bdcd8170SKalle Valo 1709bdcd8170SKalle Valo /* 17106db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 17116db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1712bdcd8170SKalle Valo */ 17136db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 17146db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 17156db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1716bdcd8170SKalle Valo 17176db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1718e8ad9a06SVasanthakumar Thiagarajan 1719e8ad9a06SVasanthakumar Thiagarajan up(&ar->sem); 1720bdcd8170SKalle Valo } 1721d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx); 1722