1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 19bdcd8170SKalle Valo #include "core.h" 20bdcd8170SKalle Valo #include "cfg80211.h" 21bdcd8170SKalle Valo #include "target.h" 22bdcd8170SKalle Valo #include "debug.h" 23bdcd8170SKalle Valo #include "hif-ops.h" 24bdcd8170SKalle Valo 25bdcd8170SKalle Valo unsigned int debug_mask; 26bdcd8170SKalle Valo 27bdcd8170SKalle Valo module_param(debug_mask, uint, 0644); 28bdcd8170SKalle Valo 29bdcd8170SKalle Valo /* 30bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 31bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 32bdcd8170SKalle Valo * here. 33bdcd8170SKalle Valo */ 34bdcd8170SKalle Valo 35bdcd8170SKalle Valo /* 36bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 37bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 38bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 39bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 40bdcd8170SKalle Valo * Use value of zero to disable keepalive support 41bdcd8170SKalle Valo * Default: 60 seconds 42bdcd8170SKalle Valo */ 43bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 44bdcd8170SKalle Valo 45bdcd8170SKalle Valo /* 46bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 47bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 48bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 49bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 50bdcd8170SKalle Valo * it sends a new connect event 51bdcd8170SKalle Valo */ 52bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 53bdcd8170SKalle Valo 54bdcd8170SKalle Valo #define CONFIG_AR600x_DEBUG_UART_TX_PIN 8 55bdcd8170SKalle Valo 56bdcd8170SKalle Valo enum addr_type { 57bdcd8170SKalle Valo DATASET_PATCH_ADDR, 58bdcd8170SKalle Valo APP_LOAD_ADDR, 59bdcd8170SKalle Valo APP_START_OVERRIDE_ADDR, 60bdcd8170SKalle Valo }; 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 63bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 64bdcd8170SKalle Valo { 65bdcd8170SKalle Valo struct sk_buff *skb; 66bdcd8170SKalle Valo u16 reserved; 67bdcd8170SKalle Valo 68bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 69bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 701df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 71bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 72bdcd8170SKalle Valo 73bdcd8170SKalle Valo if (skb) 74bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 75bdcd8170SKalle Valo return skb; 76bdcd8170SKalle Valo } 77bdcd8170SKalle Valo 78bdcd8170SKalle Valo void ath6kl_init_profile_info(struct ath6kl *ar) 79bdcd8170SKalle Valo { 80bdcd8170SKalle Valo ar->ssid_len = 0; 81bdcd8170SKalle Valo memset(ar->ssid, 0, sizeof(ar->ssid)); 82bdcd8170SKalle Valo 83bdcd8170SKalle Valo ar->dot11_auth_mode = OPEN_AUTH; 84bdcd8170SKalle Valo ar->auth_mode = NONE_AUTH; 85bdcd8170SKalle Valo ar->prwise_crypto = NONE_CRYPT; 86bdcd8170SKalle Valo ar->prwise_crypto_len = 0; 87bdcd8170SKalle Valo ar->grp_crypto = NONE_CRYPT; 88bdcd8170SKalle Valo ar->grp_crpto_len = 0; 89bdcd8170SKalle Valo memset(ar->wep_key_list, 0, sizeof(ar->wep_key_list)); 90bdcd8170SKalle Valo memset(ar->req_bssid, 0, sizeof(ar->req_bssid)); 91bdcd8170SKalle Valo memset(ar->bssid, 0, sizeof(ar->bssid)); 92bdcd8170SKalle Valo ar->bss_ch = 0; 93bdcd8170SKalle Valo ar->nw_type = ar->next_mode = INFRA_NETWORK; 94bdcd8170SKalle Valo } 95bdcd8170SKalle Valo 96bdcd8170SKalle Valo static u8 ath6kl_get_fw_iftype(struct ath6kl *ar) 97bdcd8170SKalle Valo { 98bdcd8170SKalle Valo switch (ar->nw_type) { 99bdcd8170SKalle Valo case INFRA_NETWORK: 100bdcd8170SKalle Valo return HI_OPTION_FW_MODE_BSS_STA; 101bdcd8170SKalle Valo case ADHOC_NETWORK: 102bdcd8170SKalle Valo return HI_OPTION_FW_MODE_IBSS; 103bdcd8170SKalle Valo case AP_NETWORK: 104bdcd8170SKalle Valo return HI_OPTION_FW_MODE_AP; 105bdcd8170SKalle Valo default: 106bdcd8170SKalle Valo ath6kl_err("Unsupported interface type :%d\n", ar->nw_type); 107bdcd8170SKalle Valo return 0xff; 108bdcd8170SKalle Valo } 109bdcd8170SKalle Valo } 110bdcd8170SKalle Valo 111bdcd8170SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 112bdcd8170SKalle Valo u32 item_offset) 113bdcd8170SKalle Valo { 114bdcd8170SKalle Valo u32 addr = 0; 115bdcd8170SKalle Valo 116bdcd8170SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 11731024d99SKevin Fang addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 11831024d99SKevin Fang else if (ar->target_type == TARGET_TYPE_AR6004) 11931024d99SKevin Fang addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 120bdcd8170SKalle Valo 121bdcd8170SKalle Valo return addr; 122bdcd8170SKalle Valo } 123bdcd8170SKalle Valo 124bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 125bdcd8170SKalle Valo { 126bdcd8170SKalle Valo u32 address, data; 127bdcd8170SKalle Valo struct host_app_area host_app_area; 128bdcd8170SKalle Valo 129bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 130bdcd8170SKalle Valo * instance in the host interest area */ 131bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 13231024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 133bdcd8170SKalle Valo 134bdcd8170SKalle Valo if (ath6kl_read_reg_diag(ar, &address, &data)) 135bdcd8170SKalle Valo return -EIO; 136bdcd8170SKalle Valo 13731024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 138bdcd8170SKalle Valo host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION; 139bdcd8170SKalle Valo if (ath6kl_access_datadiag(ar, address, 140bdcd8170SKalle Valo (u8 *)&host_app_area, 141bdcd8170SKalle Valo sizeof(struct host_app_area), false)) 142bdcd8170SKalle Valo return -EIO; 143bdcd8170SKalle Valo 144bdcd8170SKalle Valo return 0; 145bdcd8170SKalle Valo } 146bdcd8170SKalle Valo 147bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 148bdcd8170SKalle Valo u8 ac, 149bdcd8170SKalle Valo enum htc_endpoint_id ep) 150bdcd8170SKalle Valo { 151bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 152bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 153bdcd8170SKalle Valo } 154bdcd8170SKalle Valo 155bdcd8170SKalle Valo /* connect to a service */ 156bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 157bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 158bdcd8170SKalle Valo char *desc) 159bdcd8170SKalle Valo { 160bdcd8170SKalle Valo int status; 161bdcd8170SKalle Valo struct htc_service_connect_resp response; 162bdcd8170SKalle Valo 163bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 164bdcd8170SKalle Valo 165ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 166bdcd8170SKalle Valo if (status) { 167bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 168bdcd8170SKalle Valo desc, status); 169bdcd8170SKalle Valo return status; 170bdcd8170SKalle Valo } 171bdcd8170SKalle Valo 172bdcd8170SKalle Valo switch (con_req->svc_id) { 173bdcd8170SKalle Valo case WMI_CONTROL_SVC: 174bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 175bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 176bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 177bdcd8170SKalle Valo break; 178bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 179bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 180bdcd8170SKalle Valo break; 181bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 182bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 183bdcd8170SKalle Valo break; 184bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 185bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 186bdcd8170SKalle Valo break; 187bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 188bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 189bdcd8170SKalle Valo break; 190bdcd8170SKalle Valo default: 191bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 192bdcd8170SKalle Valo return -EINVAL; 193bdcd8170SKalle Valo } 194bdcd8170SKalle Valo 195bdcd8170SKalle Valo return 0; 196bdcd8170SKalle Valo } 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 199bdcd8170SKalle Valo { 200bdcd8170SKalle Valo struct htc_service_connect_req connect; 201bdcd8170SKalle Valo 202bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 203bdcd8170SKalle Valo 204bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 205bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 206bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 207bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 208bdcd8170SKalle Valo 209bdcd8170SKalle Valo /* 210bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 211bdcd8170SKalle Valo * gets called. 212bdcd8170SKalle Valo */ 213bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 214bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 215bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 216bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 217bdcd8170SKalle Valo 218bdcd8170SKalle Valo /* connect to control service */ 219bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 220bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 221bdcd8170SKalle Valo return -EIO; 222bdcd8170SKalle Valo 223bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 224bdcd8170SKalle Valo 225bdcd8170SKalle Valo /* 226bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 227bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 228bdcd8170SKalle Valo * (802.3) frames on the send path. 229bdcd8170SKalle Valo */ 230bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 231bdcd8170SKalle Valo 232bdcd8170SKalle Valo /* 233bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 234bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 235bdcd8170SKalle Valo * packets. 236bdcd8170SKalle Valo */ 237bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 238bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 239bdcd8170SKalle Valo 240bdcd8170SKalle Valo /* 241bdcd8170SKalle Valo * For the remaining data services set the connection flag to 242bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 243bdcd8170SKalle Valo */ 244bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 245bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 246bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 247bdcd8170SKalle Valo 248bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 249bdcd8170SKalle Valo 250bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 251bdcd8170SKalle Valo return -EIO; 252bdcd8170SKalle Valo 253bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 254bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 255bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 256bdcd8170SKalle Valo return -EIO; 257bdcd8170SKalle Valo 258bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 259bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 260bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 261bdcd8170SKalle Valo return -EIO; 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo /* 264bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 265bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 266bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 267bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 268bdcd8170SKalle Valo * mailboxes. 269bdcd8170SKalle Valo */ 270bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 271bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 272bdcd8170SKalle Valo return -EIO; 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo return 0; 275bdcd8170SKalle Valo } 276bdcd8170SKalle Valo 277bdcd8170SKalle Valo static void ath6kl_init_control_info(struct ath6kl *ar) 278bdcd8170SKalle Valo { 279bdcd8170SKalle Valo u8 ctr; 280bdcd8170SKalle Valo 281bdcd8170SKalle Valo clear_bit(WMI_ENABLED, &ar->flag); 282bdcd8170SKalle Valo ath6kl_init_profile_info(ar); 283bdcd8170SKalle Valo ar->def_txkey_index = 0; 284bdcd8170SKalle Valo memset(ar->wep_key_list, 0, sizeof(ar->wep_key_list)); 285bdcd8170SKalle Valo ar->ch_hint = 0; 286bdcd8170SKalle Valo ar->listen_intvl_t = A_DEFAULT_LISTEN_INTERVAL; 287bdcd8170SKalle Valo ar->listen_intvl_b = 0; 288bdcd8170SKalle Valo ar->tx_pwr = 0; 289bdcd8170SKalle Valo clear_bit(SKIP_SCAN, &ar->flag); 290bdcd8170SKalle Valo set_bit(WMM_ENABLED, &ar->flag); 291bdcd8170SKalle Valo ar->intra_bss = 1; 292bdcd8170SKalle Valo memset(&ar->sc_params, 0, sizeof(ar->sc_params)); 293bdcd8170SKalle Valo ar->sc_params.short_scan_ratio = WMI_SHORTSCANRATIO_DEFAULT; 294bdcd8170SKalle Valo ar->sc_params.scan_ctrl_flags = DEFAULT_SCAN_CTRL_FLAGS; 295bdcd8170SKalle Valo 296bdcd8170SKalle Valo memset((u8 *)ar->sta_list, 0, 297bdcd8170SKalle Valo AP_MAX_NUM_STA * sizeof(struct ath6kl_sta)); 298bdcd8170SKalle Valo 299bdcd8170SKalle Valo spin_lock_init(&ar->mcastpsq_lock); 300bdcd8170SKalle Valo 301bdcd8170SKalle Valo /* Init the PS queues */ 302bdcd8170SKalle Valo for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { 303bdcd8170SKalle Valo spin_lock_init(&ar->sta_list[ctr].psq_lock); 304bdcd8170SKalle Valo skb_queue_head_init(&ar->sta_list[ctr].psq); 305bdcd8170SKalle Valo } 306bdcd8170SKalle Valo 307bdcd8170SKalle Valo skb_queue_head_init(&ar->mcastpsq); 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo memcpy(ar->ap_country_code, DEF_AP_COUNTRY_CODE, 3); 310bdcd8170SKalle Valo } 311bdcd8170SKalle Valo 312bdcd8170SKalle Valo /* 313bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 314bdcd8170SKalle Valo * target is in the BMI phase. 315bdcd8170SKalle Valo */ 316bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 317bdcd8170SKalle Valo u8 htc_ctrl_buf) 318bdcd8170SKalle Valo { 319bdcd8170SKalle Valo int status; 320bdcd8170SKalle Valo u32 blk_size; 321bdcd8170SKalle Valo 322bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 323bdcd8170SKalle Valo 324bdcd8170SKalle Valo if (htc_ctrl_buf) 325bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 326bdcd8170SKalle Valo 327bdcd8170SKalle Valo /* set the host interest area for the block size */ 328bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 329bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 330bdcd8170SKalle Valo HI_ITEM(hi_mbox_io_block_sz)), 331bdcd8170SKalle Valo (u8 *)&blk_size, 332bdcd8170SKalle Valo 4); 333bdcd8170SKalle Valo if (status) { 334bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 335bdcd8170SKalle Valo goto out; 336bdcd8170SKalle Valo } 337bdcd8170SKalle Valo 338bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 339bdcd8170SKalle Valo blk_size, 340bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 341bdcd8170SKalle Valo 342bdcd8170SKalle Valo if (mbox_isr_yield_val) { 343bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 344bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 345bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 346bdcd8170SKalle Valo HI_ITEM(hi_mbox_isr_yield_limit)), 347bdcd8170SKalle Valo (u8 *)&mbox_isr_yield_val, 348bdcd8170SKalle Valo 4); 349bdcd8170SKalle Valo if (status) { 350bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 351bdcd8170SKalle Valo goto out; 352bdcd8170SKalle Valo } 353bdcd8170SKalle Valo } 354bdcd8170SKalle Valo 355bdcd8170SKalle Valo out: 356bdcd8170SKalle Valo return status; 357bdcd8170SKalle Valo } 358bdcd8170SKalle Valo 359bdcd8170SKalle Valo #define REG_DUMP_COUNT_AR6003 60 360bdcd8170SKalle Valo #define REGISTER_DUMP_LEN_MAX 60 361bdcd8170SKalle Valo 362bdcd8170SKalle Valo static void ath6kl_dump_target_assert_info(struct ath6kl *ar) 363bdcd8170SKalle Valo { 364bdcd8170SKalle Valo u32 address; 365bdcd8170SKalle Valo u32 regdump_loc = 0; 366bdcd8170SKalle Valo int status; 367bdcd8170SKalle Valo u32 regdump_val[REGISTER_DUMP_LEN_MAX]; 368bdcd8170SKalle Valo u32 i; 369bdcd8170SKalle Valo 370bdcd8170SKalle Valo if (ar->target_type != TARGET_TYPE_AR6003) 371bdcd8170SKalle Valo return; 372bdcd8170SKalle Valo 373bdcd8170SKalle Valo /* the reg dump pointer is copied to the host interest area */ 374bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state)); 37531024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 376bdcd8170SKalle Valo 377bdcd8170SKalle Valo /* read RAM location through diagnostic window */ 378bdcd8170SKalle Valo status = ath6kl_read_reg_diag(ar, &address, ®dump_loc); 379bdcd8170SKalle Valo 380bdcd8170SKalle Valo if (status || !regdump_loc) { 381bdcd8170SKalle Valo ath6kl_err("failed to get ptr to register dump area\n"); 382bdcd8170SKalle Valo return; 383bdcd8170SKalle Valo } 384bdcd8170SKalle Valo 385bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "location of register dump data: 0x%X\n", 386bdcd8170SKalle Valo regdump_loc); 38731024d99SKevin Fang regdump_loc = TARG_VTOP(ar->target_type, regdump_loc); 388bdcd8170SKalle Valo 389bdcd8170SKalle Valo /* fetch register dump data */ 390bdcd8170SKalle Valo status = ath6kl_access_datadiag(ar, 391bdcd8170SKalle Valo regdump_loc, 392bdcd8170SKalle Valo (u8 *)®dump_val[0], 393bdcd8170SKalle Valo REG_DUMP_COUNT_AR6003 * (sizeof(u32)), 394bdcd8170SKalle Valo true); 395bdcd8170SKalle Valo 396bdcd8170SKalle Valo if (status) { 397bdcd8170SKalle Valo ath6kl_err("failed to get register dump\n"); 398bdcd8170SKalle Valo return; 399bdcd8170SKalle Valo } 400bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "Register Dump:\n"); 401bdcd8170SKalle Valo 402bdcd8170SKalle Valo for (i = 0; i < REG_DUMP_COUNT_AR6003; i++) 403bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, " %d : 0x%8.8X\n", 404bdcd8170SKalle Valo i, regdump_val[i]); 405bdcd8170SKalle Valo 406bdcd8170SKalle Valo } 407bdcd8170SKalle Valo 408bdcd8170SKalle Valo void ath6kl_target_failure(struct ath6kl *ar) 409bdcd8170SKalle Valo { 410bdcd8170SKalle Valo ath6kl_err("target asserted\n"); 411bdcd8170SKalle Valo 412bdcd8170SKalle Valo /* try dumping target assertion information (if any) */ 413bdcd8170SKalle Valo ath6kl_dump_target_assert_info(ar); 414bdcd8170SKalle Valo 415bdcd8170SKalle Valo } 416bdcd8170SKalle Valo 417bdcd8170SKalle Valo static int ath6kl_target_config_wlan_params(struct ath6kl *ar) 418bdcd8170SKalle Valo { 419bdcd8170SKalle Valo int status = 0; 4204dea08e0SJouni Malinen int ret; 421bdcd8170SKalle Valo 422bdcd8170SKalle Valo /* 423bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 424bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 425bdcd8170SKalle Valo * RxMetaVersion to 2. 426bdcd8170SKalle Valo */ 427bdcd8170SKalle Valo if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, 428bdcd8170SKalle Valo ar->rx_meta_ver, 0, 0)) { 429bdcd8170SKalle Valo ath6kl_err("unable to set the rx frame format\n"); 430bdcd8170SKalle Valo status = -EIO; 431bdcd8170SKalle Valo } 432bdcd8170SKalle Valo 433bdcd8170SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) 434bdcd8170SKalle Valo if ((ath6kl_wmi_pmparams_cmd(ar->wmi, 0, 1, 0, 0, 1, 435bdcd8170SKalle Valo IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) { 436bdcd8170SKalle Valo ath6kl_err("unable to set power save fail event policy\n"); 437bdcd8170SKalle Valo status = -EIO; 438bdcd8170SKalle Valo } 439bdcd8170SKalle Valo 440bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) 441bdcd8170SKalle Valo if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, 0, 442bdcd8170SKalle Valo WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) { 443bdcd8170SKalle Valo ath6kl_err("unable to set barker preamble policy\n"); 444bdcd8170SKalle Valo status = -EIO; 445bdcd8170SKalle Valo } 446bdcd8170SKalle Valo 447bdcd8170SKalle Valo if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, 448bdcd8170SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) { 449bdcd8170SKalle Valo ath6kl_err("unable to set keep alive interval\n"); 450bdcd8170SKalle Valo status = -EIO; 451bdcd8170SKalle Valo } 452bdcd8170SKalle Valo 453bdcd8170SKalle Valo if (ath6kl_wmi_disctimeout_cmd(ar->wmi, 454bdcd8170SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT)) { 455bdcd8170SKalle Valo ath6kl_err("unable to set disconnect timeout\n"); 456bdcd8170SKalle Valo status = -EIO; 457bdcd8170SKalle Valo } 458bdcd8170SKalle Valo 459bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) 460bdcd8170SKalle Valo if (ath6kl_wmi_set_wmm_txop(ar->wmi, WMI_TXOP_DISABLED)) { 461bdcd8170SKalle Valo ath6kl_err("unable to set txop bursting\n"); 462bdcd8170SKalle Valo status = -EIO; 463bdcd8170SKalle Valo } 464bdcd8170SKalle Valo 4654dea08e0SJouni Malinen ret = ath6kl_wmi_info_req_cmd(ar->wmi, P2P_FLAG_CAPABILITIES_REQ | 4664dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4674dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4684dea08e0SJouni Malinen if (ret) { 4694dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4704dea08e0SJouni Malinen "capabilities (%d) - assuming P2P not supported\n", 4714dea08e0SJouni Malinen ret); 4724dea08e0SJouni Malinen } 4734dea08e0SJouni Malinen 474bdcd8170SKalle Valo return status; 475bdcd8170SKalle Valo } 476bdcd8170SKalle Valo 477bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 478bdcd8170SKalle Valo { 479bdcd8170SKalle Valo u32 param, ram_reserved_size; 480bdcd8170SKalle Valo u8 fw_iftype; 481bdcd8170SKalle Valo 482bdcd8170SKalle Valo fw_iftype = ath6kl_get_fw_iftype(ar); 483bdcd8170SKalle Valo if (fw_iftype == 0xff) 484bdcd8170SKalle Valo return -EINVAL; 485bdcd8170SKalle Valo 486bdcd8170SKalle Valo /* Tell target which HTC version it is used*/ 487bdcd8170SKalle Valo param = HTC_PROTOCOL_VERSION; 488bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 489bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 490bdcd8170SKalle Valo HI_ITEM(hi_app_host_interest)), 491bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 492bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 493bdcd8170SKalle Valo return -EIO; 494bdcd8170SKalle Valo } 495bdcd8170SKalle Valo 496bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 497bdcd8170SKalle Valo param = 0; 498bdcd8170SKalle Valo 499bdcd8170SKalle Valo if (ath6kl_bmi_read(ar, 500bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 501bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 502bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 503bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 504bdcd8170SKalle Valo return -EIO; 505bdcd8170SKalle Valo } 506bdcd8170SKalle Valo 507bdcd8170SKalle Valo param |= (1 << HI_OPTION_NUM_DEV_SHIFT); 508bdcd8170SKalle Valo param |= (fw_iftype << HI_OPTION_FW_MODE_SHIFT); 509bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 510bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 511bdcd8170SKalle Valo 512bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 513bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 514bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 515bdcd8170SKalle Valo (u8 *)¶m, 516bdcd8170SKalle Valo 4) != 0) { 517bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 518bdcd8170SKalle Valo return -EIO; 519bdcd8170SKalle Valo } 520bdcd8170SKalle Valo 521bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 522bdcd8170SKalle Valo 523bdcd8170SKalle Valo /* 524bdcd8170SKalle Valo * Hardcode the address use for the extended board data 525bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 526bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 527bdcd8170SKalle Valo * at init time, we have to workaround this from host. 528bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 529bdcd8170SKalle Valo * but possible in theory. 530bdcd8170SKalle Valo */ 531bdcd8170SKalle Valo 53231024d99SKevin Fang if (ar->target_type == TARGET_TYPE_AR6003 || 53331024d99SKevin Fang ar->target_type == TARGET_TYPE_AR6004) { 534bdcd8170SKalle Valo if (ar->version.target_ver == AR6003_REV2_VERSION) { 535bdcd8170SKalle Valo param = AR6003_REV2_BOARD_EXT_DATA_ADDRESS; 536bdcd8170SKalle Valo ram_reserved_size = AR6003_REV2_RAM_RESERVE_SIZE; 53731024d99SKevin Fang } else if (ar->version.target_ver == AR6004_REV1_VERSION) { 53831024d99SKevin Fang param = AR6004_REV1_BOARD_EXT_DATA_ADDRESS; 53931024d99SKevin Fang ram_reserved_size = AR6004_REV1_RAM_RESERVE_SIZE; 540bdcd8170SKalle Valo } else { 541bdcd8170SKalle Valo param = AR6003_REV3_BOARD_EXT_DATA_ADDRESS; 542bdcd8170SKalle Valo ram_reserved_size = AR6003_REV3_RAM_RESERVE_SIZE; 543bdcd8170SKalle Valo } 544bdcd8170SKalle Valo 545bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 546bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 547bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 548bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 549bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 550bdcd8170SKalle Valo return -EIO; 551bdcd8170SKalle Valo } 552bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 553bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 554bdcd8170SKalle Valo HI_ITEM(hi_end_ram_reserve_sz)), 555bdcd8170SKalle Valo (u8 *)&ram_reserved_size, 4) != 0) { 556bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 557bdcd8170SKalle Valo return -EIO; 558bdcd8170SKalle Valo } 559bdcd8170SKalle Valo } 560bdcd8170SKalle Valo 561bdcd8170SKalle Valo /* set the block size for the target */ 562bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 563bdcd8170SKalle Valo /* use default number of control buffers */ 564bdcd8170SKalle Valo return -EIO; 565bdcd8170SKalle Valo 566bdcd8170SKalle Valo return 0; 567bdcd8170SKalle Valo } 568bdcd8170SKalle Valo 569bdcd8170SKalle Valo struct ath6kl *ath6kl_core_alloc(struct device *sdev) 570bdcd8170SKalle Valo { 571bdcd8170SKalle Valo struct net_device *dev; 572bdcd8170SKalle Valo struct ath6kl *ar; 573bdcd8170SKalle Valo struct wireless_dev *wdev; 574bdcd8170SKalle Valo 575bdcd8170SKalle Valo wdev = ath6kl_cfg80211_init(sdev); 576bdcd8170SKalle Valo if (!wdev) { 577bdcd8170SKalle Valo ath6kl_err("ath6kl_cfg80211_init failed\n"); 578bdcd8170SKalle Valo return NULL; 579bdcd8170SKalle Valo } 580bdcd8170SKalle Valo 581bdcd8170SKalle Valo ar = wdev_priv(wdev); 582bdcd8170SKalle Valo ar->dev = sdev; 583bdcd8170SKalle Valo ar->wdev = wdev; 584bdcd8170SKalle Valo wdev->iftype = NL80211_IFTYPE_STATION; 585bdcd8170SKalle Valo 586d999ba3eSVasanthakumar Thiagarajan if (ath6kl_debug_init(ar)) { 587d999ba3eSVasanthakumar Thiagarajan ath6kl_err("Failed to initialize debugfs\n"); 588d999ba3eSVasanthakumar Thiagarajan ath6kl_cfg80211_deinit(ar); 589d999ba3eSVasanthakumar Thiagarajan return NULL; 590d999ba3eSVasanthakumar Thiagarajan } 591d999ba3eSVasanthakumar Thiagarajan 592bdcd8170SKalle Valo dev = alloc_netdev(0, "wlan%d", ether_setup); 593bdcd8170SKalle Valo if (!dev) { 594bdcd8170SKalle Valo ath6kl_err("no memory for network device instance\n"); 595bdcd8170SKalle Valo ath6kl_cfg80211_deinit(ar); 596bdcd8170SKalle Valo return NULL; 597bdcd8170SKalle Valo } 598bdcd8170SKalle Valo 599bdcd8170SKalle Valo dev->ieee80211_ptr = wdev; 600bdcd8170SKalle Valo SET_NETDEV_DEV(dev, wiphy_dev(wdev->wiphy)); 601bdcd8170SKalle Valo wdev->netdev = dev; 602bdcd8170SKalle Valo ar->sme_state = SME_DISCONNECTED; 603bdcd8170SKalle Valo ar->auto_auth_stage = AUTH_IDLE; 604bdcd8170SKalle Valo 605bdcd8170SKalle Valo init_netdev(dev); 606bdcd8170SKalle Valo 607bdcd8170SKalle Valo ar->net_dev = dev; 608575b5f34SRaja Mani set_bit(WLAN_ENABLED, &ar->flag); 609bdcd8170SKalle Valo 610bdcd8170SKalle Valo ar->wlan_pwr_state = WLAN_POWER_STATE_ON; 611bdcd8170SKalle Valo 612bdcd8170SKalle Valo spin_lock_init(&ar->lock); 613bdcd8170SKalle Valo 614bdcd8170SKalle Valo ath6kl_init_control_info(ar); 615bdcd8170SKalle Valo init_waitqueue_head(&ar->event_wq); 616bdcd8170SKalle Valo sema_init(&ar->sem, 1); 617bdcd8170SKalle Valo clear_bit(DESTROY_IN_PROGRESS, &ar->flag); 618bdcd8170SKalle Valo 619bdcd8170SKalle Valo INIT_LIST_HEAD(&ar->amsdu_rx_buffer_queue); 620bdcd8170SKalle Valo 621bdcd8170SKalle Valo setup_timer(&ar->disconnect_timer, disconnect_timer_handler, 622bdcd8170SKalle Valo (unsigned long) dev); 623bdcd8170SKalle Valo 624bdcd8170SKalle Valo return ar; 625bdcd8170SKalle Valo } 626bdcd8170SKalle Valo 627bdcd8170SKalle Valo int ath6kl_unavail_ev(struct ath6kl *ar) 628bdcd8170SKalle Valo { 629bdcd8170SKalle Valo ath6kl_destroy(ar->net_dev, 1); 630bdcd8170SKalle Valo 631bdcd8170SKalle Valo return 0; 632bdcd8170SKalle Valo } 633bdcd8170SKalle Valo 634bdcd8170SKalle Valo /* firmware upload */ 635bdcd8170SKalle Valo static u32 ath6kl_get_load_address(u32 target_ver, enum addr_type type) 636bdcd8170SKalle Valo { 637bdcd8170SKalle Valo WARN_ON(target_ver != AR6003_REV2_VERSION && 63831024d99SKevin Fang target_ver != AR6003_REV3_VERSION && 63931024d99SKevin Fang target_ver != AR6004_REV1_VERSION); 640bdcd8170SKalle Valo 641bdcd8170SKalle Valo switch (type) { 642bdcd8170SKalle Valo case DATASET_PATCH_ADDR: 643bdcd8170SKalle Valo return (target_ver == AR6003_REV2_VERSION) ? 644bdcd8170SKalle Valo AR6003_REV2_DATASET_PATCH_ADDRESS : 645bdcd8170SKalle Valo AR6003_REV3_DATASET_PATCH_ADDRESS; 646bdcd8170SKalle Valo case APP_LOAD_ADDR: 647bdcd8170SKalle Valo return (target_ver == AR6003_REV2_VERSION) ? 648bdcd8170SKalle Valo AR6003_REV2_APP_LOAD_ADDRESS : 649bdcd8170SKalle Valo 0x1234; 650bdcd8170SKalle Valo case APP_START_OVERRIDE_ADDR: 651bdcd8170SKalle Valo return (target_ver == AR6003_REV2_VERSION) ? 652bdcd8170SKalle Valo AR6003_REV2_APP_START_OVERRIDE : 653bdcd8170SKalle Valo AR6003_REV3_APP_START_OVERRIDE; 654bdcd8170SKalle Valo default: 655bdcd8170SKalle Valo return 0; 656bdcd8170SKalle Valo } 657bdcd8170SKalle Valo } 658bdcd8170SKalle Valo 659bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 660bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 661bdcd8170SKalle Valo { 662bdcd8170SKalle Valo const struct firmware *fw_entry; 663bdcd8170SKalle Valo int ret; 664bdcd8170SKalle Valo 665bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 666bdcd8170SKalle Valo if (ret) 667bdcd8170SKalle Valo return ret; 668bdcd8170SKalle Valo 669bdcd8170SKalle Valo *fw_len = fw_entry->size; 670bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 671bdcd8170SKalle Valo 672bdcd8170SKalle Valo if (*fw == NULL) 673bdcd8170SKalle Valo ret = -ENOMEM; 674bdcd8170SKalle Valo 675bdcd8170SKalle Valo release_firmware(fw_entry); 676bdcd8170SKalle Valo 677bdcd8170SKalle Valo return ret; 678bdcd8170SKalle Valo } 679bdcd8170SKalle Valo 680bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 681bdcd8170SKalle Valo { 682bdcd8170SKalle Valo const char *filename; 683bdcd8170SKalle Valo int ret; 684bdcd8170SKalle Valo 685bdcd8170SKalle Valo switch (ar->version.target_ver) { 686bdcd8170SKalle Valo case AR6003_REV2_VERSION: 687bdcd8170SKalle Valo filename = AR6003_REV2_BOARD_DATA_FILE; 688bdcd8170SKalle Valo break; 68931024d99SKevin Fang case AR6004_REV1_VERSION: 69031024d99SKevin Fang filename = AR6004_REV1_BOARD_DATA_FILE; 69131024d99SKevin Fang break; 692bdcd8170SKalle Valo default: 693bdcd8170SKalle Valo filename = AR6003_REV3_BOARD_DATA_FILE; 694bdcd8170SKalle Valo break; 695bdcd8170SKalle Valo } 696bdcd8170SKalle Valo 697bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 698bdcd8170SKalle Valo &ar->fw_board_len); 699bdcd8170SKalle Valo if (ret == 0) { 700bdcd8170SKalle Valo /* managed to get proper board file */ 701bdcd8170SKalle Valo return 0; 702bdcd8170SKalle Valo } 703bdcd8170SKalle Valo 704bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 705bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 706bdcd8170SKalle Valo filename, ret); 707bdcd8170SKalle Valo 708bdcd8170SKalle Valo switch (ar->version.target_ver) { 709bdcd8170SKalle Valo case AR6003_REV2_VERSION: 710bdcd8170SKalle Valo filename = AR6003_REV2_DEFAULT_BOARD_DATA_FILE; 711bdcd8170SKalle Valo break; 71231024d99SKevin Fang case AR6004_REV1_VERSION: 71331024d99SKevin Fang filename = AR6004_REV1_DEFAULT_BOARD_DATA_FILE; 71431024d99SKevin Fang break; 715bdcd8170SKalle Valo default: 716bdcd8170SKalle Valo filename = AR6003_REV3_DEFAULT_BOARD_DATA_FILE; 717bdcd8170SKalle Valo break; 718bdcd8170SKalle Valo } 719bdcd8170SKalle Valo 720bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 721bdcd8170SKalle Valo &ar->fw_board_len); 722bdcd8170SKalle Valo if (ret) { 723bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 724bdcd8170SKalle Valo filename, ret); 725bdcd8170SKalle Valo return ret; 726bdcd8170SKalle Valo } 727bdcd8170SKalle Valo 728bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 729bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 730bdcd8170SKalle Valo 731bdcd8170SKalle Valo return 0; 732bdcd8170SKalle Valo } 733bdcd8170SKalle Valo 734bdcd8170SKalle Valo 735bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 736bdcd8170SKalle Valo { 737bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 73831024d99SKevin Fang u32 board_data_size, board_ext_data_size; 739bdcd8170SKalle Valo int ret; 740bdcd8170SKalle Valo 741bdcd8170SKalle Valo if (ar->fw_board == NULL) { 742bdcd8170SKalle Valo ret = ath6kl_fetch_board_file(ar); 743bdcd8170SKalle Valo if (ret) 744bdcd8170SKalle Valo return ret; 745bdcd8170SKalle Valo } 746bdcd8170SKalle Valo 74731024d99SKevin Fang /* 74831024d99SKevin Fang * Determine where in Target RAM to write Board Data. 74931024d99SKevin Fang * For AR6004, host determine Target RAM address for 75031024d99SKevin Fang * writing board data. 75131024d99SKevin Fang */ 75231024d99SKevin Fang if (ar->target_type == TARGET_TYPE_AR6004) { 75331024d99SKevin Fang board_address = AR6004_REV1_BOARD_DATA_ADDRESS; 75431024d99SKevin Fang ath6kl_bmi_write(ar, 75531024d99SKevin Fang ath6kl_get_hi_item_addr(ar, 75631024d99SKevin Fang HI_ITEM(hi_board_data)), 75731024d99SKevin Fang (u8 *) &board_address, 4); 75831024d99SKevin Fang } else { 759bdcd8170SKalle Valo ath6kl_bmi_read(ar, 760bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 761bdcd8170SKalle Valo HI_ITEM(hi_board_data)), 762bdcd8170SKalle Valo (u8 *) &board_address, 4); 76331024d99SKevin Fang } 76431024d99SKevin Fang 765bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "board data download addr: 0x%x\n", 766bdcd8170SKalle Valo board_address); 767bdcd8170SKalle Valo 768bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 769bdcd8170SKalle Valo ath6kl_bmi_read(ar, 770bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 771bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 772bdcd8170SKalle Valo (u8 *) &board_ext_address, 4); 773bdcd8170SKalle Valo 774bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "board file download addr: 0x%x\n", 775bdcd8170SKalle Valo board_ext_address); 776bdcd8170SKalle Valo 777bdcd8170SKalle Valo if (board_ext_address == 0) { 778bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 779bdcd8170SKalle Valo return -EINVAL; 780bdcd8170SKalle Valo } 781bdcd8170SKalle Valo 78231024d99SKevin Fang switch (ar->target_type) { 78331024d99SKevin Fang case TARGET_TYPE_AR6003: 78431024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 78531024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 78631024d99SKevin Fang break; 78731024d99SKevin Fang case TARGET_TYPE_AR6004: 78831024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 78931024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 79031024d99SKevin Fang break; 79131024d99SKevin Fang default: 79231024d99SKevin Fang WARN_ON(1); 79331024d99SKevin Fang return -EINVAL; 79431024d99SKevin Fang break; 79531024d99SKevin Fang } 79631024d99SKevin Fang 79731024d99SKevin Fang if (ar->fw_board_len == (board_data_size + 79831024d99SKevin Fang board_ext_data_size)) { 79931024d99SKevin Fang 800bdcd8170SKalle Valo /* write extended board data */ 801bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 80231024d99SKevin Fang ar->fw_board + board_data_size, 80331024d99SKevin Fang board_ext_data_size); 804bdcd8170SKalle Valo if (ret) { 805bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 806bdcd8170SKalle Valo ret); 807bdcd8170SKalle Valo return ret; 808bdcd8170SKalle Valo } 809bdcd8170SKalle Valo 810bdcd8170SKalle Valo /* record that extended board data is initialized */ 81131024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 81231024d99SKevin Fang 813bdcd8170SKalle Valo ath6kl_bmi_write(ar, 814bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 815bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data_config)), 816bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 817bdcd8170SKalle Valo } 818bdcd8170SKalle Valo 81931024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 820bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 821bdcd8170SKalle Valo ret = -EINVAL; 822bdcd8170SKalle Valo return ret; 823bdcd8170SKalle Valo } 824bdcd8170SKalle Valo 825bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 82631024d99SKevin Fang board_data_size); 827bdcd8170SKalle Valo 828bdcd8170SKalle Valo if (ret) { 829bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 830bdcd8170SKalle Valo return ret; 831bdcd8170SKalle Valo } 832bdcd8170SKalle Valo 833bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 834bdcd8170SKalle Valo param = 1; 835bdcd8170SKalle Valo ath6kl_bmi_write(ar, 836bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 837bdcd8170SKalle Valo HI_ITEM(hi_board_data_initialized)), 838bdcd8170SKalle Valo (u8 *)¶m, 4); 839bdcd8170SKalle Valo 840bdcd8170SKalle Valo return ret; 841bdcd8170SKalle Valo } 842bdcd8170SKalle Valo 843bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 844bdcd8170SKalle Valo { 845bdcd8170SKalle Valo const char *filename; 846bdcd8170SKalle Valo u32 address, param; 847bdcd8170SKalle Valo int ret; 848bdcd8170SKalle Valo 849bdcd8170SKalle Valo switch (ar->version.target_ver) { 850bdcd8170SKalle Valo case AR6003_REV2_VERSION: 851bdcd8170SKalle Valo filename = AR6003_REV2_OTP_FILE; 852bdcd8170SKalle Valo break; 85331024d99SKevin Fang case AR6004_REV1_VERSION: 85431024d99SKevin Fang ath6kl_dbg(ATH6KL_DBG_TRC, "AR6004 doesn't need OTP file\n"); 85531024d99SKevin Fang return 0; 85631024d99SKevin Fang break; 857bdcd8170SKalle Valo default: 858bdcd8170SKalle Valo filename = AR6003_REV3_OTP_FILE; 859bdcd8170SKalle Valo break; 860bdcd8170SKalle Valo } 861bdcd8170SKalle Valo 862bdcd8170SKalle Valo if (ar->fw_otp == NULL) { 863bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 864bdcd8170SKalle Valo &ar->fw_otp_len); 865bdcd8170SKalle Valo if (ret) { 866bdcd8170SKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 867bdcd8170SKalle Valo filename, ret); 868bdcd8170SKalle Valo return ret; 869bdcd8170SKalle Valo } 870bdcd8170SKalle Valo } 871bdcd8170SKalle Valo 872bdcd8170SKalle Valo address = ath6kl_get_load_address(ar->version.target_ver, 873bdcd8170SKalle Valo APP_LOAD_ADDR); 874bdcd8170SKalle Valo 875bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 876bdcd8170SKalle Valo ar->fw_otp_len); 877bdcd8170SKalle Valo if (ret) { 878bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 879bdcd8170SKalle Valo return ret; 880bdcd8170SKalle Valo } 881bdcd8170SKalle Valo 882bdcd8170SKalle Valo /* execute the OTP code */ 883bdcd8170SKalle Valo param = 0; 884bdcd8170SKalle Valo address = ath6kl_get_load_address(ar->version.target_ver, 885bdcd8170SKalle Valo APP_START_OVERRIDE_ADDR); 886bdcd8170SKalle Valo ath6kl_bmi_execute(ar, address, ¶m); 887bdcd8170SKalle Valo 888bdcd8170SKalle Valo return ret; 889bdcd8170SKalle Valo } 890bdcd8170SKalle Valo 891bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 892bdcd8170SKalle Valo { 893bdcd8170SKalle Valo const char *filename; 894bdcd8170SKalle Valo u32 address; 895bdcd8170SKalle Valo int ret; 896bdcd8170SKalle Valo 897bdcd8170SKalle Valo switch (ar->version.target_ver) { 898bdcd8170SKalle Valo case AR6003_REV2_VERSION: 899bdcd8170SKalle Valo filename = AR6003_REV2_FIRMWARE_FILE; 900bdcd8170SKalle Valo break; 90131024d99SKevin Fang case AR6004_REV1_VERSION: 90231024d99SKevin Fang filename = AR6004_REV1_FIRMWARE_FILE; 90331024d99SKevin Fang break; 904bdcd8170SKalle Valo default: 905bdcd8170SKalle Valo filename = AR6003_REV3_FIRMWARE_FILE; 906bdcd8170SKalle Valo break; 907bdcd8170SKalle Valo } 908bdcd8170SKalle Valo 909bdcd8170SKalle Valo if (ar->fw == NULL) { 910bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 911bdcd8170SKalle Valo if (ret) { 912bdcd8170SKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 913bdcd8170SKalle Valo filename, ret); 914bdcd8170SKalle Valo return ret; 915bdcd8170SKalle Valo } 916bdcd8170SKalle Valo } 917bdcd8170SKalle Valo 918bdcd8170SKalle Valo address = ath6kl_get_load_address(ar->version.target_ver, 919bdcd8170SKalle Valo APP_LOAD_ADDR); 920bdcd8170SKalle Valo 921bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 922bdcd8170SKalle Valo 923bdcd8170SKalle Valo if (ret) { 924bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 925bdcd8170SKalle Valo return ret; 926bdcd8170SKalle Valo } 927bdcd8170SKalle Valo 92831024d99SKevin Fang /* 92931024d99SKevin Fang * Set starting address for firmware 93031024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 93131024d99SKevin Fang */ 93231024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 933bdcd8170SKalle Valo address = ath6kl_get_load_address(ar->version.target_ver, 934bdcd8170SKalle Valo APP_START_OVERRIDE_ADDR); 935bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 93631024d99SKevin Fang } 937bdcd8170SKalle Valo return ret; 938bdcd8170SKalle Valo } 939bdcd8170SKalle Valo 940bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 941bdcd8170SKalle Valo { 942bdcd8170SKalle Valo const char *filename; 943bdcd8170SKalle Valo u32 address, param; 944bdcd8170SKalle Valo int ret; 945bdcd8170SKalle Valo 946bdcd8170SKalle Valo switch (ar->version.target_ver) { 947bdcd8170SKalle Valo case AR6003_REV2_VERSION: 948bdcd8170SKalle Valo filename = AR6003_REV2_PATCH_FILE; 949bdcd8170SKalle Valo break; 95031024d99SKevin Fang case AR6004_REV1_VERSION: 95131024d99SKevin Fang /* FIXME: implement for AR6004 */ 95231024d99SKevin Fang return 0; 95331024d99SKevin Fang break; 954bdcd8170SKalle Valo default: 955bdcd8170SKalle Valo filename = AR6003_REV3_PATCH_FILE; 956bdcd8170SKalle Valo break; 957bdcd8170SKalle Valo } 958bdcd8170SKalle Valo 959bdcd8170SKalle Valo if (ar->fw_patch == NULL) { 960bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 961bdcd8170SKalle Valo &ar->fw_patch_len); 962bdcd8170SKalle Valo if (ret) { 963bdcd8170SKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 964bdcd8170SKalle Valo filename, ret); 965bdcd8170SKalle Valo return ret; 966bdcd8170SKalle Valo } 967bdcd8170SKalle Valo } 968bdcd8170SKalle Valo 969bdcd8170SKalle Valo address = ath6kl_get_load_address(ar->version.target_ver, 970bdcd8170SKalle Valo DATASET_PATCH_ADDR); 971bdcd8170SKalle Valo 972bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 973bdcd8170SKalle Valo if (ret) { 974bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 975bdcd8170SKalle Valo return ret; 976bdcd8170SKalle Valo } 977bdcd8170SKalle Valo 978bdcd8170SKalle Valo param = address; 979bdcd8170SKalle Valo ath6kl_bmi_write(ar, 980bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 981bdcd8170SKalle Valo HI_ITEM(hi_dset_list_head)), 982bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 983bdcd8170SKalle Valo 984bdcd8170SKalle Valo return 0; 985bdcd8170SKalle Valo } 986bdcd8170SKalle Valo 987bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 988bdcd8170SKalle Valo { 989bdcd8170SKalle Valo u32 param, options, sleep, address; 990bdcd8170SKalle Valo int status = 0; 991bdcd8170SKalle Valo 99231024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 99331024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 994bdcd8170SKalle Valo return -EINVAL; 995bdcd8170SKalle Valo 996bdcd8170SKalle Valo /* temporarily disable system sleep */ 997bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 998bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 999bdcd8170SKalle Valo if (status) 1000bdcd8170SKalle Valo return status; 1001bdcd8170SKalle Valo 1002bdcd8170SKalle Valo options = param; 1003bdcd8170SKalle Valo 1004bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1005bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1006bdcd8170SKalle Valo if (status) 1007bdcd8170SKalle Valo return status; 1008bdcd8170SKalle Valo 1009bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1010bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1011bdcd8170SKalle Valo if (status) 1012bdcd8170SKalle Valo return status; 1013bdcd8170SKalle Valo 1014bdcd8170SKalle Valo sleep = param; 1015bdcd8170SKalle Valo 1016bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1017bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1018bdcd8170SKalle Valo if (status) 1019bdcd8170SKalle Valo return status; 1020bdcd8170SKalle Valo 1021bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1022bdcd8170SKalle Valo options, sleep); 1023bdcd8170SKalle Valo 1024bdcd8170SKalle Valo /* program analog PLL register */ 102531024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 102631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1027bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1028bdcd8170SKalle Valo 0xF9104001); 102931024d99SKevin Fang 1030bdcd8170SKalle Valo if (status) 1031bdcd8170SKalle Valo return status; 1032bdcd8170SKalle Valo 1033bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1034bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1035bdcd8170SKalle Valo 1036bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1037bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1038bdcd8170SKalle Valo if (status) 1039bdcd8170SKalle Valo return status; 104031024d99SKevin Fang } 1041bdcd8170SKalle Valo 1042bdcd8170SKalle Valo param = 0; 1043bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1044bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1045bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1046bdcd8170SKalle Valo if (status) 1047bdcd8170SKalle Valo return status; 1048bdcd8170SKalle Valo 1049bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 1050bdcd8170SKalle Valo if (ar->version.target_ver == AR6003_REV2_VERSION) { 1051bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1052bdcd8170SKalle Valo 1053bdcd8170SKalle Valo param = 0x20; 1054bdcd8170SKalle Valo 1055bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1056bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1057bdcd8170SKalle Valo if (status) 1058bdcd8170SKalle Valo return status; 1059bdcd8170SKalle Valo 1060bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1061bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1062bdcd8170SKalle Valo if (status) 1063bdcd8170SKalle Valo return status; 1064bdcd8170SKalle Valo 1065bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1066bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1067bdcd8170SKalle Valo if (status) 1068bdcd8170SKalle Valo return status; 1069bdcd8170SKalle Valo 1070bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1071bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1072bdcd8170SKalle Valo if (status) 1073bdcd8170SKalle Valo return status; 1074bdcd8170SKalle Valo } 1075bdcd8170SKalle Valo 1076bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1077bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1078bdcd8170SKalle Valo if (status) 1079bdcd8170SKalle Valo return status; 1080bdcd8170SKalle Valo 1081bdcd8170SKalle Valo /* transfer One time Programmable data */ 1082bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1083bdcd8170SKalle Valo if (status) 1084bdcd8170SKalle Valo return status; 1085bdcd8170SKalle Valo 1086bdcd8170SKalle Valo /* Download Target firmware */ 1087bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1088bdcd8170SKalle Valo if (status) 1089bdcd8170SKalle Valo return status; 1090bdcd8170SKalle Valo 1091bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1092bdcd8170SKalle Valo if (status) 1093bdcd8170SKalle Valo return status; 1094bdcd8170SKalle Valo 1095bdcd8170SKalle Valo /* Restore system sleep */ 1096bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1097bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1098bdcd8170SKalle Valo if (status) 1099bdcd8170SKalle Valo return status; 1100bdcd8170SKalle Valo 1101bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1102bdcd8170SKalle Valo param = options | 0x20; 1103bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1104bdcd8170SKalle Valo if (status) 1105bdcd8170SKalle Valo return status; 1106bdcd8170SKalle Valo 1107bdcd8170SKalle Valo /* Configure GPIO AR6003 UART */ 1108bdcd8170SKalle Valo param = CONFIG_AR600x_DEBUG_UART_TX_PIN; 1109bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 1110bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1111bdcd8170SKalle Valo HI_ITEM(hi_dbg_uart_txpin)), 1112bdcd8170SKalle Valo (u8 *)¶m, 4); 1113bdcd8170SKalle Valo 1114bdcd8170SKalle Valo return status; 1115bdcd8170SKalle Valo } 1116bdcd8170SKalle Valo 1117bdcd8170SKalle Valo static int ath6kl_init(struct net_device *dev) 1118bdcd8170SKalle Valo { 1119bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 1120bdcd8170SKalle Valo int status = 0; 1121bdcd8170SKalle Valo s32 timeleft; 1122bdcd8170SKalle Valo 1123bdcd8170SKalle Valo if (!ar) 1124bdcd8170SKalle Valo return -EIO; 1125bdcd8170SKalle Valo 1126bdcd8170SKalle Valo /* Do we need to finish the BMI phase */ 1127bdcd8170SKalle Valo if (ath6kl_bmi_done(ar)) { 1128bdcd8170SKalle Valo status = -EIO; 1129bdcd8170SKalle Valo goto ath6kl_init_done; 1130bdcd8170SKalle Valo } 1131bdcd8170SKalle Valo 1132bdcd8170SKalle Valo /* Indicate that WMI is enabled (although not ready yet) */ 1133bdcd8170SKalle Valo set_bit(WMI_ENABLED, &ar->flag); 11342865785eSVasanthakumar Thiagarajan ar->wmi = ath6kl_wmi_init(ar); 1135bdcd8170SKalle Valo if (!ar->wmi) { 1136bdcd8170SKalle Valo ath6kl_err("failed to initialize wmi\n"); 1137bdcd8170SKalle Valo status = -EIO; 1138bdcd8170SKalle Valo goto ath6kl_init_done; 1139bdcd8170SKalle Valo } 1140bdcd8170SKalle Valo 1141bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: got wmi @ 0x%p.\n", __func__, ar->wmi); 1142bdcd8170SKalle Valo 1143852bd9d9SVasanthakumar Thiagarajan wlan_node_table_init(&ar->scan_table); 1144852bd9d9SVasanthakumar Thiagarajan 1145bdcd8170SKalle Valo /* 1146bdcd8170SKalle Valo * The reason we have to wait for the target here is that the 1147bdcd8170SKalle Valo * driver layer has to init BMI in order to set the host block 1148bdcd8170SKalle Valo * size. 1149bdcd8170SKalle Valo */ 1150ad226ec2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 1151bdcd8170SKalle Valo status = -EIO; 1152852bd9d9SVasanthakumar Thiagarajan goto err_node_cleanup; 1153bdcd8170SKalle Valo } 1154bdcd8170SKalle Valo 1155bdcd8170SKalle Valo if (ath6kl_init_service_ep(ar)) { 1156bdcd8170SKalle Valo status = -EIO; 1157bdcd8170SKalle Valo goto err_cleanup_scatter; 1158bdcd8170SKalle Valo } 1159bdcd8170SKalle Valo 1160bdcd8170SKalle Valo /* setup access class priority mappings */ 1161bdcd8170SKalle Valo ar->ac_stream_pri_map[WMM_AC_BK] = 0; /* lowest */ 1162bdcd8170SKalle Valo ar->ac_stream_pri_map[WMM_AC_BE] = 1; 1163bdcd8170SKalle Valo ar->ac_stream_pri_map[WMM_AC_VI] = 2; 1164bdcd8170SKalle Valo ar->ac_stream_pri_map[WMM_AC_VO] = 3; /* highest */ 1165bdcd8170SKalle Valo 1166bdcd8170SKalle Valo /* give our connected endpoints some buffers */ 1167bdcd8170SKalle Valo ath6kl_rx_refill(ar->htc_target, ar->ctrl_ep); 1168bdcd8170SKalle Valo ath6kl_rx_refill(ar->htc_target, ar->ac2ep_map[WMM_AC_BE]); 1169bdcd8170SKalle Valo 1170bdcd8170SKalle Valo /* allocate some buffers that handle larger AMSDU frames */ 1171bdcd8170SKalle Valo ath6kl_refill_amsdu_rxbufs(ar, ATH6KL_MAX_AMSDU_RX_BUFFERS); 1172bdcd8170SKalle Valo 1173bdcd8170SKalle Valo /* setup credit distribution */ 1174bdcd8170SKalle Valo ath6k_setup_credit_dist(ar->htc_target, &ar->credit_state_info); 1175bdcd8170SKalle Valo 1176bdcd8170SKalle Valo ath6kl_cookie_init(ar); 1177bdcd8170SKalle Valo 1178bdcd8170SKalle Valo /* start HTC */ 1179ad226ec2SKalle Valo status = ath6kl_htc_start(ar->htc_target); 1180bdcd8170SKalle Valo 1181bdcd8170SKalle Valo if (status) { 1182bdcd8170SKalle Valo ath6kl_cookie_cleanup(ar); 1183bdcd8170SKalle Valo goto err_rxbuf_cleanup; 1184bdcd8170SKalle Valo } 1185bdcd8170SKalle Valo 1186bdcd8170SKalle Valo /* Wait for Wmi event to be ready */ 1187bdcd8170SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 1188bdcd8170SKalle Valo test_bit(WMI_READY, 1189bdcd8170SKalle Valo &ar->flag), 1190bdcd8170SKalle Valo WMI_TIMEOUT); 1191bdcd8170SKalle Valo 1192bdcd8170SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 1193bdcd8170SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 1194bdcd8170SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 1195bdcd8170SKalle Valo status = -EIO; 1196bdcd8170SKalle Valo goto err_htc_stop; 1197bdcd8170SKalle Valo } 1198bdcd8170SKalle Valo 1199bdcd8170SKalle Valo if (!timeleft || signal_pending(current)) { 1200bdcd8170SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 1201bdcd8170SKalle Valo status = -EIO; 1202bdcd8170SKalle Valo goto err_htc_stop; 1203bdcd8170SKalle Valo } 1204bdcd8170SKalle Valo 1205bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 1206bdcd8170SKalle Valo 1207bdcd8170SKalle Valo /* communicate the wmi protocol verision to the target */ 1208bdcd8170SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 1209bdcd8170SKalle Valo ath6kl_err("unable to set the host app area\n"); 1210bdcd8170SKalle Valo 1211bdcd8170SKalle Valo ar->conf_flags = ATH6KL_CONF_IGNORE_ERP_BARKER | 1212bdcd8170SKalle Valo ATH6KL_CONF_ENABLE_11N | ATH6KL_CONF_ENABLE_TX_BURST; 1213bdcd8170SKalle Valo 1214bdcd8170SKalle Valo status = ath6kl_target_config_wlan_params(ar); 1215bdcd8170SKalle Valo if (!status) 1216bdcd8170SKalle Valo goto ath6kl_init_done; 1217bdcd8170SKalle Valo 1218bdcd8170SKalle Valo err_htc_stop: 1219ad226ec2SKalle Valo ath6kl_htc_stop(ar->htc_target); 1220bdcd8170SKalle Valo err_rxbuf_cleanup: 1221ad226ec2SKalle Valo ath6kl_htc_flush_rx_buf(ar->htc_target); 1222bdcd8170SKalle Valo ath6kl_cleanup_amsdu_rxbufs(ar); 1223bdcd8170SKalle Valo err_cleanup_scatter: 1224bdcd8170SKalle Valo ath6kl_hif_cleanup_scatter(ar); 1225852bd9d9SVasanthakumar Thiagarajan err_node_cleanup: 1226852bd9d9SVasanthakumar Thiagarajan wlan_node_table_cleanup(&ar->scan_table); 1227bdcd8170SKalle Valo ath6kl_wmi_shutdown(ar->wmi); 1228bdcd8170SKalle Valo clear_bit(WMI_ENABLED, &ar->flag); 1229bdcd8170SKalle Valo ar->wmi = NULL; 1230bdcd8170SKalle Valo 1231bdcd8170SKalle Valo ath6kl_init_done: 1232bdcd8170SKalle Valo return status; 1233bdcd8170SKalle Valo } 1234bdcd8170SKalle Valo 1235bdcd8170SKalle Valo int ath6kl_core_init(struct ath6kl *ar) 1236bdcd8170SKalle Valo { 1237bdcd8170SKalle Valo int ret = 0; 1238bdcd8170SKalle Valo struct ath6kl_bmi_target_info targ_info; 1239bdcd8170SKalle Valo 1240bdcd8170SKalle Valo ar->ath6kl_wq = create_singlethread_workqueue("ath6kl"); 1241bdcd8170SKalle Valo if (!ar->ath6kl_wq) 1242bdcd8170SKalle Valo return -ENOMEM; 1243bdcd8170SKalle Valo 1244bdcd8170SKalle Valo ret = ath6kl_bmi_init(ar); 1245bdcd8170SKalle Valo if (ret) 1246bdcd8170SKalle Valo goto err_wq; 1247bdcd8170SKalle Valo 1248bdcd8170SKalle Valo ret = ath6kl_bmi_get_target_info(ar, &targ_info); 1249bdcd8170SKalle Valo if (ret) 1250bdcd8170SKalle Valo goto err_bmi_cleanup; 1251bdcd8170SKalle Valo 1252bdcd8170SKalle Valo ar->version.target_ver = le32_to_cpu(targ_info.version); 1253bdcd8170SKalle Valo ar->target_type = le32_to_cpu(targ_info.type); 1254bdcd8170SKalle Valo ar->wdev->wiphy->hw_version = le32_to_cpu(targ_info.version); 1255bdcd8170SKalle Valo 1256bdcd8170SKalle Valo ret = ath6kl_configure_target(ar); 1257bdcd8170SKalle Valo if (ret) 1258bdcd8170SKalle Valo goto err_bmi_cleanup; 1259bdcd8170SKalle Valo 1260ad226ec2SKalle Valo ar->htc_target = ath6kl_htc_create(ar); 1261bdcd8170SKalle Valo 1262bdcd8170SKalle Valo if (!ar->htc_target) { 1263bdcd8170SKalle Valo ret = -ENOMEM; 1264bdcd8170SKalle Valo goto err_bmi_cleanup; 1265bdcd8170SKalle Valo } 1266bdcd8170SKalle Valo 1267bdcd8170SKalle Valo ar->aggr_cntxt = aggr_init(ar->net_dev); 1268bdcd8170SKalle Valo if (!ar->aggr_cntxt) { 1269bdcd8170SKalle Valo ath6kl_err("failed to initialize aggr\n"); 1270bdcd8170SKalle Valo ret = -ENOMEM; 1271bdcd8170SKalle Valo goto err_htc_cleanup; 1272bdcd8170SKalle Valo } 1273bdcd8170SKalle Valo 1274bdcd8170SKalle Valo ret = ath6kl_init_upload(ar); 1275bdcd8170SKalle Valo if (ret) 1276bdcd8170SKalle Valo goto err_htc_cleanup; 1277bdcd8170SKalle Valo 1278bdcd8170SKalle Valo ret = ath6kl_init(ar->net_dev); 1279bdcd8170SKalle Valo if (ret) 1280bdcd8170SKalle Valo goto err_htc_cleanup; 1281bdcd8170SKalle Valo 1282bdcd8170SKalle Valo /* This runs the init function if registered */ 1283bdcd8170SKalle Valo ret = register_netdev(ar->net_dev); 1284bdcd8170SKalle Valo if (ret) { 1285bdcd8170SKalle Valo ath6kl_err("register_netdev failed\n"); 1286bdcd8170SKalle Valo ath6kl_destroy(ar->net_dev, 0); 1287bdcd8170SKalle Valo return ret; 1288bdcd8170SKalle Valo } 1289bdcd8170SKalle Valo 1290bdcd8170SKalle Valo set_bit(NETDEV_REGISTERED, &ar->flag); 1291bdcd8170SKalle Valo 1292bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n", 1293bdcd8170SKalle Valo __func__, ar->net_dev->name, ar->net_dev, ar); 1294bdcd8170SKalle Valo 1295bdcd8170SKalle Valo return ret; 1296bdcd8170SKalle Valo 1297bdcd8170SKalle Valo err_htc_cleanup: 1298ad226ec2SKalle Valo ath6kl_htc_cleanup(ar->htc_target); 1299bdcd8170SKalle Valo err_bmi_cleanup: 1300bdcd8170SKalle Valo ath6kl_bmi_cleanup(ar); 1301bdcd8170SKalle Valo err_wq: 1302bdcd8170SKalle Valo destroy_workqueue(ar->ath6kl_wq); 1303bdcd8170SKalle Valo return ret; 1304bdcd8170SKalle Valo } 1305bdcd8170SKalle Valo 1306bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1307bdcd8170SKalle Valo { 1308bdcd8170SKalle Valo struct net_device *ndev = ar->net_dev; 1309bdcd8170SKalle Valo 1310bdcd8170SKalle Valo if (!ndev) 1311bdcd8170SKalle Valo return; 1312bdcd8170SKalle Valo 1313bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1314bdcd8170SKalle Valo 1315bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1316bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1317bdcd8170SKalle Valo return; 1318bdcd8170SKalle Valo } 1319bdcd8170SKalle Valo 1320bdcd8170SKalle Valo if (ar->wlan_pwr_state != WLAN_POWER_STATE_CUT_PWR) 1321bdcd8170SKalle Valo ath6kl_stop_endpoint(ndev, false, true); 1322bdcd8170SKalle Valo 1323575b5f34SRaja Mani clear_bit(WLAN_ENABLED, &ar->flag); 1324bdcd8170SKalle Valo } 1325bdcd8170SKalle Valo 1326bdcd8170SKalle Valo /* 1327bdcd8170SKalle Valo * We need to differentiate between the surprise and planned removal of the 1328bdcd8170SKalle Valo * device because of the following consideration: 1329bdcd8170SKalle Valo * 1330bdcd8170SKalle Valo * - In case of surprise removal, the hcd already frees up the pending 1331bdcd8170SKalle Valo * for the device and hence there is no need to unregister the function 1332bdcd8170SKalle Valo * driver inorder to get these requests. For planned removal, the function 1333bdcd8170SKalle Valo * driver has to explicitly unregister itself to have the hcd return all the 1334bdcd8170SKalle Valo * pending requests before the data structures for the devices are freed up. 1335bdcd8170SKalle Valo * Note that as per the current implementation, the function driver will 1336bdcd8170SKalle Valo * end up releasing all the devices since there is no API to selectively 1337bdcd8170SKalle Valo * release a particular device. 1338bdcd8170SKalle Valo * 1339bdcd8170SKalle Valo * - Certain commands issued to the target can be skipped for surprise 1340bdcd8170SKalle Valo * removal since they will anyway not go through. 1341bdcd8170SKalle Valo */ 1342bdcd8170SKalle Valo void ath6kl_destroy(struct net_device *dev, unsigned int unregister) 1343bdcd8170SKalle Valo { 1344bdcd8170SKalle Valo struct ath6kl *ar; 1345bdcd8170SKalle Valo 1346bdcd8170SKalle Valo if (!dev || !ath6kl_priv(dev)) { 1347bdcd8170SKalle Valo ath6kl_err("failed to get device structure\n"); 1348bdcd8170SKalle Valo return; 1349bdcd8170SKalle Valo } 1350bdcd8170SKalle Valo 1351bdcd8170SKalle Valo ar = ath6kl_priv(dev); 1352bdcd8170SKalle Valo 1353bdcd8170SKalle Valo destroy_workqueue(ar->ath6kl_wq); 1354bdcd8170SKalle Valo 1355bdcd8170SKalle Valo if (ar->htc_target) 1356ad226ec2SKalle Valo ath6kl_htc_cleanup(ar->htc_target); 1357bdcd8170SKalle Valo 1358bdcd8170SKalle Valo aggr_module_destroy(ar->aggr_cntxt); 1359bdcd8170SKalle Valo 1360bdcd8170SKalle Valo ath6kl_cookie_cleanup(ar); 1361bdcd8170SKalle Valo 1362bdcd8170SKalle Valo ath6kl_cleanup_amsdu_rxbufs(ar); 1363bdcd8170SKalle Valo 1364bdcd8170SKalle Valo ath6kl_bmi_cleanup(ar); 1365bdcd8170SKalle Valo 1366bdcd8170SKalle Valo if (unregister && test_bit(NETDEV_REGISTERED, &ar->flag)) { 1367bdcd8170SKalle Valo unregister_netdev(dev); 1368bdcd8170SKalle Valo clear_bit(NETDEV_REGISTERED, &ar->flag); 1369bdcd8170SKalle Valo } 1370bdcd8170SKalle Valo 1371bdcd8170SKalle Valo free_netdev(dev); 1372bdcd8170SKalle Valo 1373852bd9d9SVasanthakumar Thiagarajan wlan_node_table_cleanup(&ar->scan_table); 1374852bd9d9SVasanthakumar Thiagarajan 137519703573SRaja Mani kfree(ar->fw_board); 137619703573SRaja Mani kfree(ar->fw_otp); 137719703573SRaja Mani kfree(ar->fw); 137819703573SRaja Mani kfree(ar->fw_patch); 137919703573SRaja Mani 1380bdcd8170SKalle Valo ath6kl_cfg80211_deinit(ar); 1381bdcd8170SKalle Valo } 1382