1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 41b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 5bdcd8170SKalle Valo * 6bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 7bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 8bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 9bdcd8170SKalle Valo * 10bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17bdcd8170SKalle Valo */ 18bdcd8170SKalle Valo 19c6efe578SStephen Rothwell #include <linux/moduleparam.h> 20f7830202SSangwook Lee #include <linux/errno.h> 21d6a434d6SKalle Valo #include <linux/export.h> 2292ecbff4SSam Leffler #include <linux/of.h> 23bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 248437754cSVivek Natarajan #include <linux/vmalloc.h> 25d6a434d6SKalle Valo 26bdcd8170SKalle Valo #include "core.h" 27bdcd8170SKalle Valo #include "cfg80211.h" 28bdcd8170SKalle Valo #include "target.h" 29bdcd8170SKalle Valo #include "debug.h" 30bdcd8170SKalle Valo #include "hif-ops.h" 31e76ac2bfSKalle Valo #include "htc-ops.h" 32bdcd8170SKalle Valo 33856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 34856f4b31SKalle Valo { 350d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 36293badf4SKalle Valo .name = "ar6003 hw 2.0", 37856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 38856f4b31SKalle Valo .app_load_addr = 0x543180, 39856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 40856f4b31SKalle Valo .reserved_ram_size = 6912, 4139586bf2SRyan Hsu .refclk_hz = 26000000, 4239586bf2SRyan Hsu .uarttx_pin = 8, 43856f4b31SKalle Valo 44856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 45856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 46d1a9421dSKalle Valo 47c0038972SKalle Valo .fw = { 48c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 49c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 50d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 51c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 52c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 53c0038972SKalle Valo }, 54c0038972SKalle Valo 55d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 56d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 57856f4b31SKalle Valo }, 58856f4b31SKalle Valo { 590d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 60293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 61856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 62856f4b31SKalle Valo .app_load_addr = 0x1234, 63856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 64856f4b31SKalle Valo .reserved_ram_size = 512, 6539586bf2SRyan Hsu .refclk_hz = 26000000, 6639586bf2SRyan Hsu .uarttx_pin = 8, 67cd23c1c9SAlex Yang .testscript_addr = 0x57ef74, 68d1a9421dSKalle Valo 69c0038972SKalle Valo .fw = { 70c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 71c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 72d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 73c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 74c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 75cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, 76cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, 77c0038972SKalle Valo }, 78c0038972SKalle Valo 79d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 80d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 81856f4b31SKalle Valo }, 82856f4b31SKalle Valo { 830d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 84293badf4SKalle Valo .name = "ar6004 hw 1.0", 85856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 86856f4b31SKalle Valo .app_load_addr = 0x1234, 87856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 88856f4b31SKalle Valo .reserved_ram_size = 19456, 890d4d72bfSKalle Valo .board_addr = 0x433900, 9039586bf2SRyan Hsu .refclk_hz = 26000000, 9139586bf2SRyan Hsu .uarttx_pin = 11, 92d1a9421dSKalle Valo 93c0038972SKalle Valo .fw = { 94c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 95d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 96c0038972SKalle Valo }, 97c0038972SKalle Valo 98d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 99d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 100856f4b31SKalle Valo }, 101856f4b31SKalle Valo { 1020d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 103293badf4SKalle Valo .name = "ar6004 hw 1.1", 104856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 105856f4b31SKalle Valo .app_load_addr = 0x1234, 106856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 107856f4b31SKalle Valo .reserved_ram_size = 11264, 1080d4d72bfSKalle Valo .board_addr = 0x43d400, 10939586bf2SRyan Hsu .refclk_hz = 40000000, 11039586bf2SRyan Hsu .uarttx_pin = 11, 111d1a9421dSKalle Valo 112c0038972SKalle Valo .fw = { 113c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 114d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 115c0038972SKalle Valo }, 116c0038972SKalle Valo 117d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 118d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 119856f4b31SKalle Valo }, 120856f4b31SKalle Valo }; 121856f4b31SKalle Valo 122bdcd8170SKalle Valo /* 123bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 124bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 125bdcd8170SKalle Valo * here. 126bdcd8170SKalle Valo */ 127bdcd8170SKalle Valo 128bdcd8170SKalle Valo /* 129bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 130bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 131bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 132bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 133bdcd8170SKalle Valo * Use value of zero to disable keepalive support 134bdcd8170SKalle Valo * Default: 60 seconds 135bdcd8170SKalle Valo */ 136bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 137bdcd8170SKalle Valo 138bdcd8170SKalle Valo /* 139bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 140bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 141bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 142bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 143bdcd8170SKalle Valo * it sends a new connect event 144bdcd8170SKalle Valo */ 145bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 146bdcd8170SKalle Valo 147bdcd8170SKalle Valo 148bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 149bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 150bdcd8170SKalle Valo { 151bdcd8170SKalle Valo struct sk_buff *skb; 152bdcd8170SKalle Valo u16 reserved; 153bdcd8170SKalle Valo 154bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 155bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 1561df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 157bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 158bdcd8170SKalle Valo 159bdcd8170SKalle Valo if (skb) 160bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 161bdcd8170SKalle Valo return skb; 162bdcd8170SKalle Valo } 163bdcd8170SKalle Valo 164e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 165bdcd8170SKalle Valo { 1663450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 1673450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 1683450334fSVasanthakumar Thiagarajan 1693450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 1703450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 1713450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 1723450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 1733450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 1743450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 1756f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 1768c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 1778c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 178f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 179bdcd8170SKalle Valo } 180bdcd8170SKalle Valo 181bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 182bdcd8170SKalle Valo { 183bdcd8170SKalle Valo u32 address, data; 184bdcd8170SKalle Valo struct host_app_area host_app_area; 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 187bdcd8170SKalle Valo * instance in the host interest area */ 188bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 18931024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 190bdcd8170SKalle Valo 191addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 192bdcd8170SKalle Valo return -EIO; 193bdcd8170SKalle Valo 19431024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 195cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 196addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 197addb44beSKalle Valo sizeof(struct host_app_area))) 198bdcd8170SKalle Valo return -EIO; 199bdcd8170SKalle Valo 200bdcd8170SKalle Valo return 0; 201bdcd8170SKalle Valo } 202bdcd8170SKalle Valo 203bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 204bdcd8170SKalle Valo u8 ac, 205bdcd8170SKalle Valo enum htc_endpoint_id ep) 206bdcd8170SKalle Valo { 207bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 208bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 209bdcd8170SKalle Valo } 210bdcd8170SKalle Valo 211bdcd8170SKalle Valo /* connect to a service */ 212bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 213bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 214bdcd8170SKalle Valo char *desc) 215bdcd8170SKalle Valo { 216bdcd8170SKalle Valo int status; 217bdcd8170SKalle Valo struct htc_service_connect_resp response; 218bdcd8170SKalle Valo 219bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 220bdcd8170SKalle Valo 221ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 222bdcd8170SKalle Valo if (status) { 223bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 224bdcd8170SKalle Valo desc, status); 225bdcd8170SKalle Valo return status; 226bdcd8170SKalle Valo } 227bdcd8170SKalle Valo 228bdcd8170SKalle Valo switch (con_req->svc_id) { 229bdcd8170SKalle Valo case WMI_CONTROL_SVC: 230bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 231bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 232bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 233bdcd8170SKalle Valo break; 234bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 235bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 236bdcd8170SKalle Valo break; 237bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 238bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 239bdcd8170SKalle Valo break; 240bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 241bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 242bdcd8170SKalle Valo break; 243bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 244bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 245bdcd8170SKalle Valo break; 246bdcd8170SKalle Valo default: 247bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 248bdcd8170SKalle Valo return -EINVAL; 249bdcd8170SKalle Valo } 250bdcd8170SKalle Valo 251bdcd8170SKalle Valo return 0; 252bdcd8170SKalle Valo } 253bdcd8170SKalle Valo 254bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 255bdcd8170SKalle Valo { 256bdcd8170SKalle Valo struct htc_service_connect_req connect; 257bdcd8170SKalle Valo 258bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 259bdcd8170SKalle Valo 260bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 261900d6b3fSKalle Valo connect.ep_cb.tx_comp_multi = ath6kl_tx_complete; 262bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 263bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 264bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 265bdcd8170SKalle Valo 266bdcd8170SKalle Valo /* 267bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 268bdcd8170SKalle Valo * gets called. 269bdcd8170SKalle Valo */ 270bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 271bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 272bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 273bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 274bdcd8170SKalle Valo 275bdcd8170SKalle Valo /* connect to control service */ 276bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 277bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 278bdcd8170SKalle Valo return -EIO; 279bdcd8170SKalle Valo 280bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 281bdcd8170SKalle Valo 282bdcd8170SKalle Valo /* 283bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 284bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 285bdcd8170SKalle Valo * (802.3) frames on the send path. 286bdcd8170SKalle Valo */ 287bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo /* 290bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 291bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 292bdcd8170SKalle Valo * packets. 293bdcd8170SKalle Valo */ 294bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 295bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 296bdcd8170SKalle Valo 297bdcd8170SKalle Valo /* 298bdcd8170SKalle Valo * For the remaining data services set the connection flag to 299bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 300bdcd8170SKalle Valo */ 301bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 302bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 303bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 304bdcd8170SKalle Valo 305bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 306bdcd8170SKalle Valo 307bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 308bdcd8170SKalle Valo return -EIO; 309bdcd8170SKalle Valo 310bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 311bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 312bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 313bdcd8170SKalle Valo return -EIO; 314bdcd8170SKalle Valo 315bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 316bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 317bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 318bdcd8170SKalle Valo return -EIO; 319bdcd8170SKalle Valo 320bdcd8170SKalle Valo /* 321bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 322bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 323bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 324bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 325bdcd8170SKalle Valo * mailboxes. 326bdcd8170SKalle Valo */ 327bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 328bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 329bdcd8170SKalle Valo return -EIO; 330bdcd8170SKalle Valo 331bdcd8170SKalle Valo return 0; 332bdcd8170SKalle Valo } 333bdcd8170SKalle Valo 334e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 335bdcd8170SKalle Valo { 336e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3373450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3386f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 339f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 340bdcd8170SKalle Valo } 341bdcd8170SKalle Valo 342bdcd8170SKalle Valo /* 343bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 344bdcd8170SKalle Valo * target is in the BMI phase. 345bdcd8170SKalle Valo */ 346bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 347bdcd8170SKalle Valo u8 htc_ctrl_buf) 348bdcd8170SKalle Valo { 349bdcd8170SKalle Valo int status; 350bdcd8170SKalle Valo u32 blk_size; 351bdcd8170SKalle Valo 352bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 353bdcd8170SKalle Valo 354bdcd8170SKalle Valo if (htc_ctrl_buf) 355bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 356bdcd8170SKalle Valo 357bdcd8170SKalle Valo /* set the host interest area for the block size */ 35824fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size); 359bdcd8170SKalle Valo if (status) { 360bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 361bdcd8170SKalle Valo goto out; 362bdcd8170SKalle Valo } 363bdcd8170SKalle Valo 364bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 365bdcd8170SKalle Valo blk_size, 366bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 367bdcd8170SKalle Valo 368bdcd8170SKalle Valo if (mbox_isr_yield_val) { 369bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 37024fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit, 37124fc32b3SKalle Valo mbox_isr_yield_val); 372bdcd8170SKalle Valo if (status) { 373bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 374bdcd8170SKalle Valo goto out; 375bdcd8170SKalle Valo } 376bdcd8170SKalle Valo } 377bdcd8170SKalle Valo 378bdcd8170SKalle Valo out: 379bdcd8170SKalle Valo return status; 380bdcd8170SKalle Valo } 381bdcd8170SKalle Valo 3820ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 383bdcd8170SKalle Valo { 3844dea08e0SJouni Malinen int ret; 385bdcd8170SKalle Valo 386bdcd8170SKalle Valo /* 387bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 388bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 389bdcd8170SKalle Valo * RxMetaVersion to 2. 390bdcd8170SKalle Valo */ 3911ca4d0b6SKalle Valo ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 3921ca4d0b6SKalle Valo ar->rx_meta_ver, 0, 0); 3931ca4d0b6SKalle Valo if (ret) { 3941ca4d0b6SKalle Valo ath6kl_err("unable to set the rx frame format: %d\n", ret); 3951ca4d0b6SKalle Valo return ret; 396bdcd8170SKalle Valo } 397bdcd8170SKalle Valo 3981ca4d0b6SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) { 3991ca4d0b6SKalle Valo ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 40005aab177SKalle Valo IGNORE_PS_FAIL_DURING_SCAN); 4011ca4d0b6SKalle Valo if (ret) { 4021ca4d0b6SKalle Valo ath6kl_err("unable to set power save fail event policy: %d\n", 4031ca4d0b6SKalle Valo ret); 4041ca4d0b6SKalle Valo return ret; 4051ca4d0b6SKalle Valo } 406bdcd8170SKalle Valo } 407bdcd8170SKalle Valo 4081ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) { 4091ca4d0b6SKalle Valo ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 41005aab177SKalle Valo WMI_FOLLOW_BARKER_IN_ERP); 4111ca4d0b6SKalle Valo if (ret) { 4121ca4d0b6SKalle Valo ath6kl_err("unable to set barker preamble policy: %d\n", 4131ca4d0b6SKalle Valo ret); 4141ca4d0b6SKalle Valo return ret; 4151ca4d0b6SKalle Valo } 416bdcd8170SKalle Valo } 417bdcd8170SKalle Valo 4181ca4d0b6SKalle Valo ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 4191ca4d0b6SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL); 4201ca4d0b6SKalle Valo if (ret) { 4211ca4d0b6SKalle Valo ath6kl_err("unable to set keep alive interval: %d\n", ret); 4221ca4d0b6SKalle Valo return ret; 423bdcd8170SKalle Valo } 424bdcd8170SKalle Valo 4251ca4d0b6SKalle Valo ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 4261ca4d0b6SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT); 4271ca4d0b6SKalle Valo if (ret) { 4281ca4d0b6SKalle Valo ath6kl_err("unable to set disconnect timeout: %d\n", ret); 4291ca4d0b6SKalle Valo return ret; 430bdcd8170SKalle Valo } 431bdcd8170SKalle Valo 4321ca4d0b6SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) { 4331ca4d0b6SKalle Valo ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED); 4341ca4d0b6SKalle Valo if (ret) { 4351ca4d0b6SKalle Valo ath6kl_err("unable to set txop bursting: %d\n", ret); 4361ca4d0b6SKalle Valo return ret; 4371ca4d0b6SKalle Valo } 438bdcd8170SKalle Valo } 439bdcd8170SKalle Valo 440b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4410ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4426bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4434dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4444dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4454dea08e0SJouni Malinen if (ret) { 4464dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4476bbc7c35SJouni Malinen "capabilities (%d) - assuming P2P not " 4486bbc7c35SJouni Malinen "supported\n", ret); 4493db1cd5cSRusty Russell ar->p2p = false; 4506bbc7c35SJouni Malinen } 4516bbc7c35SJouni Malinen } 4526bbc7c35SJouni Malinen 453b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4546bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 4550ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 4566bbc7c35SJouni Malinen if (ret) { 4576bbc7c35SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " 4586bbc7c35SJouni Malinen "Request reporting (%d)\n", ret); 4596bbc7c35SJouni Malinen } 4604dea08e0SJouni Malinen } 4614dea08e0SJouni Malinen 4621ca4d0b6SKalle Valo return ret; 463bdcd8170SKalle Valo } 464bdcd8170SKalle Valo 465bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 466bdcd8170SKalle Valo { 467bdcd8170SKalle Valo u32 param, ram_reserved_size; 4683226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 46939586bf2SRyan Hsu int i, status; 470bdcd8170SKalle Valo 471f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 47224fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) { 473a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 474a10e2f2fSVasanthakumar Thiagarajan return -EIO; 475a10e2f2fSVasanthakumar Thiagarajan } 476a10e2f2fSVasanthakumar Thiagarajan 4777b85832dSVasanthakumar Thiagarajan /* 4787b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 4797b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 4807b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 4817b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 4827b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 4837b85832dSVasanthakumar Thiagarajan * configured for now. 4847b85832dSVasanthakumar Thiagarajan */ 485dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 486bdcd8170SKalle Valo 48771f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 4887b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 4897b85832dSVasanthakumar Thiagarajan 4907b85832dSVasanthakumar Thiagarajan /* 4911e8d13b0SVasanthakumar Thiagarajan * Submodes when fw does not support dynamic interface 4921e8d13b0SVasanthakumar Thiagarajan * switching: 4933226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 4947b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 4957b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 4961e8d13b0SVasanthakumar Thiagarajan * Otherwise, All the interface are initialized to p2p dev. 4977b85832dSVasanthakumar Thiagarajan */ 4983226f68aSVasanthakumar Thiagarajan 4991e8d13b0SVasanthakumar Thiagarajan if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 5001e8d13b0SVasanthakumar Thiagarajan ar->fw_capabilities)) { 5011e8d13b0SVasanthakumar Thiagarajan for (i = 0; i < ar->vif_max; i++) 5021e8d13b0SVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5031e8d13b0SVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5041e8d13b0SVasanthakumar Thiagarajan } else { 5053226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 5063226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 5073226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5083226f68aSVasanthakumar Thiagarajan 50971f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 5103226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5113226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5127b85832dSVasanthakumar Thiagarajan 513b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5147b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5151e8d13b0SVasanthakumar Thiagarajan } 5167b85832dSVasanthakumar Thiagarajan 51724fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest, 51824fc32b3SKalle Valo HTC_PROTOCOL_VERSION) != 0) { 519bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 520bdcd8170SKalle Valo return -EIO; 521bdcd8170SKalle Valo } 522bdcd8170SKalle Valo 523bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 524bdcd8170SKalle Valo param = 0; 525bdcd8170SKalle Valo 52680fb2686SKalle Valo if (ath6kl_bmi_read_hi32(ar, hi_option_flag, ¶m) != 0) { 527bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 528bdcd8170SKalle Valo return -EIO; 529bdcd8170SKalle Valo } 530bdcd8170SKalle Valo 53171f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5327b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5337b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5347b85832dSVasanthakumar Thiagarajan 535bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 536bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 537bdcd8170SKalle Valo 53824fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) { 539bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 540bdcd8170SKalle Valo return -EIO; 541bdcd8170SKalle Valo } 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 544bdcd8170SKalle Valo 545bdcd8170SKalle Valo /* 546bdcd8170SKalle Valo * Hardcode the address use for the extended board data 547bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 548bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 549bdcd8170SKalle Valo * at init time, we have to workaround this from host. 550bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 551bdcd8170SKalle Valo * but possible in theory. 552bdcd8170SKalle Valo */ 553bdcd8170SKalle Valo 5546b42d308SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) { 555991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 556991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 557bdcd8170SKalle Valo 55824fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) { 559bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 560bdcd8170SKalle Valo return -EIO; 561bdcd8170SKalle Valo } 562991b27eaSKalle Valo 56324fc32b3SKalle Valo if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 56424fc32b3SKalle Valo ram_reserved_size) != 0) { 565bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 566bdcd8170SKalle Valo return -EIO; 567bdcd8170SKalle Valo } 5686b42d308SKalle Valo } 569bdcd8170SKalle Valo 570bdcd8170SKalle Valo /* set the block size for the target */ 571bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 572bdcd8170SKalle Valo /* use default number of control buffers */ 573bdcd8170SKalle Valo return -EIO; 574bdcd8170SKalle Valo 57539586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 57624fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin, 57724fc32b3SKalle Valo ar->hw.uarttx_pin); 57839586bf2SRyan Hsu if (status) 57939586bf2SRyan Hsu return status; 58039586bf2SRyan Hsu 58139586bf2SRyan Hsu /* Configure target refclk_hz */ 58224fc32b3SKalle Valo status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz); 58339586bf2SRyan Hsu if (status) 58439586bf2SRyan Hsu return status; 58539586bf2SRyan Hsu 586bdcd8170SKalle Valo return 0; 587bdcd8170SKalle Valo } 588bdcd8170SKalle Valo 589bdcd8170SKalle Valo /* firmware upload */ 590bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 591bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 592bdcd8170SKalle Valo { 593bdcd8170SKalle Valo const struct firmware *fw_entry; 594bdcd8170SKalle Valo int ret; 595bdcd8170SKalle Valo 596bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 597bdcd8170SKalle Valo if (ret) 598bdcd8170SKalle Valo return ret; 599bdcd8170SKalle Valo 600bdcd8170SKalle Valo *fw_len = fw_entry->size; 601bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 602bdcd8170SKalle Valo 603bdcd8170SKalle Valo if (*fw == NULL) 604bdcd8170SKalle Valo ret = -ENOMEM; 605bdcd8170SKalle Valo 606bdcd8170SKalle Valo release_firmware(fw_entry); 607bdcd8170SKalle Valo 608bdcd8170SKalle Valo return ret; 609bdcd8170SKalle Valo } 610bdcd8170SKalle Valo 61192ecbff4SSam Leffler #ifdef CONFIG_OF 61292ecbff4SSam Leffler /* 61392ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 61492ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 61592ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 61692ecbff4SSam Leffler * appropriate board-specific file. 61792ecbff4SSam Leffler */ 61892ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 61992ecbff4SSam Leffler { 62092ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 62192ecbff4SSam Leffler struct device_node *node; 62292ecbff4SSam Leffler char board_filename[64]; 62392ecbff4SSam Leffler const char *board_id; 62492ecbff4SSam Leffler int ret; 62592ecbff4SSam Leffler 62692ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 62792ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 62892ecbff4SSam Leffler if (board_id == NULL) { 62992ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 63092ecbff4SSam Leffler board_id_prop, node->name); 63192ecbff4SSam Leffler continue; 63292ecbff4SSam Leffler } 63392ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 634c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 63592ecbff4SSam Leffler 63692ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 63792ecbff4SSam Leffler &ar->fw_board_len); 63892ecbff4SSam Leffler if (ret) { 63992ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 64092ecbff4SSam Leffler board_filename, ret); 64192ecbff4SSam Leffler continue; 64292ecbff4SSam Leffler } 64392ecbff4SSam Leffler return true; 64492ecbff4SSam Leffler } 64592ecbff4SSam Leffler return false; 64692ecbff4SSam Leffler } 64792ecbff4SSam Leffler #else 64892ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 64992ecbff4SSam Leffler { 65092ecbff4SSam Leffler return false; 65192ecbff4SSam Leffler } 65292ecbff4SSam Leffler #endif /* CONFIG_OF */ 65392ecbff4SSam Leffler 654bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 655bdcd8170SKalle Valo { 656bdcd8170SKalle Valo const char *filename; 657bdcd8170SKalle Valo int ret; 658bdcd8170SKalle Valo 659772c31eeSKalle Valo if (ar->fw_board != NULL) 660772c31eeSKalle Valo return 0; 661772c31eeSKalle Valo 662d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 663d1a9421dSKalle Valo return -EINVAL; 664d1a9421dSKalle Valo 665d1a9421dSKalle Valo filename = ar->hw.fw_board; 666bdcd8170SKalle Valo 667bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 668bdcd8170SKalle Valo &ar->fw_board_len); 669bdcd8170SKalle Valo if (ret == 0) { 670bdcd8170SKalle Valo /* managed to get proper board file */ 671bdcd8170SKalle Valo return 0; 672bdcd8170SKalle Valo } 673bdcd8170SKalle Valo 67492ecbff4SSam Leffler if (check_device_tree(ar)) { 67592ecbff4SSam Leffler /* got board file from device tree */ 67692ecbff4SSam Leffler return 0; 67792ecbff4SSam Leffler } 67892ecbff4SSam Leffler 679bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 680bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 681bdcd8170SKalle Valo filename, ret); 682bdcd8170SKalle Valo 683d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 684bdcd8170SKalle Valo 685bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 686bdcd8170SKalle Valo &ar->fw_board_len); 687bdcd8170SKalle Valo if (ret) { 688bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 689bdcd8170SKalle Valo filename, ret); 690bdcd8170SKalle Valo return ret; 691bdcd8170SKalle Valo } 692bdcd8170SKalle Valo 693bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 694bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 695bdcd8170SKalle Valo 696bdcd8170SKalle Valo return 0; 697bdcd8170SKalle Valo } 698bdcd8170SKalle Valo 699772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 700772c31eeSKalle Valo { 701c0038972SKalle Valo char filename[100]; 702772c31eeSKalle Valo int ret; 703772c31eeSKalle Valo 704772c31eeSKalle Valo if (ar->fw_otp != NULL) 705772c31eeSKalle Valo return 0; 706772c31eeSKalle Valo 707c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 708d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 709d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 710772c31eeSKalle Valo return 0; 711772c31eeSKalle Valo } 712772c31eeSKalle Valo 713c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 714c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 715d1a9421dSKalle Valo 716772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 717772c31eeSKalle Valo &ar->fw_otp_len); 718772c31eeSKalle Valo if (ret) { 719772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 720772c31eeSKalle Valo filename, ret); 721772c31eeSKalle Valo return ret; 722772c31eeSKalle Valo } 723772c31eeSKalle Valo 724772c31eeSKalle Valo return 0; 725772c31eeSKalle Valo } 726772c31eeSKalle Valo 7275f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar) 728772c31eeSKalle Valo { 729c0038972SKalle Valo char filename[100]; 730772c31eeSKalle Valo int ret; 731772c31eeSKalle Valo 7325f1127ffSKalle Valo if (ar->testmode == 0) 733772c31eeSKalle Valo return 0; 734772c31eeSKalle Valo 7355f1127ffSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode); 7365f1127ffSKalle Valo 7375f1127ffSKalle Valo if (ar->testmode == 2) { 738cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) { 739cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n"); 740cd23c1c9SAlex Yang return -EOPNOTSUPP; 741cd23c1c9SAlex Yang } 742cd23c1c9SAlex Yang 743cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 744cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf); 745cd23c1c9SAlex Yang } else { 746c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 747cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n"); 748772c31eeSKalle Valo return -EOPNOTSUPP; 749772c31eeSKalle Valo } 750772c31eeSKalle Valo 751c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 752c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 753cd23c1c9SAlex Yang } 7545f1127ffSKalle Valo 755772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 756772c31eeSKalle Valo 7575f1127ffSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 7585f1127ffSKalle Valo if (ret) { 7595f1127ffSKalle Valo ath6kl_err("Failed to get testmode %d firmware file %s: %d\n", 7605f1127ffSKalle Valo ar->testmode, filename, ret); 7615f1127ffSKalle Valo return ret; 762772c31eeSKalle Valo } 763772c31eeSKalle Valo 7645f1127ffSKalle Valo return 0; 7655f1127ffSKalle Valo } 7665f1127ffSKalle Valo 7675f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 7685f1127ffSKalle Valo { 7695f1127ffSKalle Valo char filename[100]; 7705f1127ffSKalle Valo int ret; 7715f1127ffSKalle Valo 7725f1127ffSKalle Valo if (ar->fw != NULL) 7735f1127ffSKalle Valo return 0; 7745f1127ffSKalle Valo 775c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 776c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 777d1a9421dSKalle Valo return -EINVAL; 778d1a9421dSKalle Valo 779c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 780c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 781772c31eeSKalle Valo 782772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 783772c31eeSKalle Valo if (ret) { 784772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 785772c31eeSKalle Valo filename, ret); 786772c31eeSKalle Valo return ret; 787772c31eeSKalle Valo } 788772c31eeSKalle Valo 789772c31eeSKalle Valo return 0; 790772c31eeSKalle Valo } 791772c31eeSKalle Valo 792772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 793772c31eeSKalle Valo { 794c0038972SKalle Valo char filename[100]; 795772c31eeSKalle Valo int ret; 796772c31eeSKalle Valo 797d1a9421dSKalle Valo if (ar->fw_patch != NULL) 798772c31eeSKalle Valo return 0; 799772c31eeSKalle Valo 800c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 801d1a9421dSKalle Valo return 0; 802d1a9421dSKalle Valo 803c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 804c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 805d1a9421dSKalle Valo 806772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 807772c31eeSKalle Valo &ar->fw_patch_len); 808772c31eeSKalle Valo if (ret) { 809772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 810772c31eeSKalle Valo filename, ret); 811772c31eeSKalle Valo return ret; 812772c31eeSKalle Valo } 813772c31eeSKalle Valo 814772c31eeSKalle Valo return 0; 815772c31eeSKalle Valo } 816772c31eeSKalle Valo 817cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar) 818cd23c1c9SAlex Yang { 819cd23c1c9SAlex Yang char filename[100]; 820cd23c1c9SAlex Yang int ret; 821cd23c1c9SAlex Yang 8225f1127ffSKalle Valo if (ar->testmode != 2) 823cd23c1c9SAlex Yang return 0; 824cd23c1c9SAlex Yang 825cd23c1c9SAlex Yang if (ar->fw_testscript != NULL) 826cd23c1c9SAlex Yang return 0; 827cd23c1c9SAlex Yang 828cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL) 829cd23c1c9SAlex Yang return 0; 830cd23c1c9SAlex Yang 831cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 832cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript); 833cd23c1c9SAlex Yang 834cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 835cd23c1c9SAlex Yang &ar->fw_testscript_len); 836cd23c1c9SAlex Yang if (ret) { 837cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n", 838cd23c1c9SAlex Yang filename, ret); 839cd23c1c9SAlex Yang return ret; 840cd23c1c9SAlex Yang } 841cd23c1c9SAlex Yang 842cd23c1c9SAlex Yang return 0; 843cd23c1c9SAlex Yang } 844cd23c1c9SAlex Yang 84550d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 846772c31eeSKalle Valo { 847772c31eeSKalle Valo int ret; 848772c31eeSKalle Valo 849772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 850772c31eeSKalle Valo if (ret) 851772c31eeSKalle Valo return ret; 852772c31eeSKalle Valo 853772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 854772c31eeSKalle Valo if (ret) 855772c31eeSKalle Valo return ret; 856772c31eeSKalle Valo 857772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 858772c31eeSKalle Valo if (ret) 859772c31eeSKalle Valo return ret; 860772c31eeSKalle Valo 861cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar); 862cd23c1c9SAlex Yang if (ret) 863cd23c1c9SAlex Yang return ret; 864cd23c1c9SAlex Yang 865772c31eeSKalle Valo return 0; 866772c31eeSKalle Valo } 867bdcd8170SKalle Valo 86865a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 86950d41234SKalle Valo { 87050d41234SKalle Valo size_t magic_len, len, ie_len; 87150d41234SKalle Valo const struct firmware *fw; 87250d41234SKalle Valo struct ath6kl_fw_ie *hdr; 873c0038972SKalle Valo char filename[100]; 87450d41234SKalle Valo const u8 *data; 87597e0496dSKalle Valo int ret, ie_id, i, index, bit; 8768a137480SKalle Valo __le32 *val; 87750d41234SKalle Valo 87865a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 87950d41234SKalle Valo 88050d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 88150d41234SKalle Valo if (ret) 88250d41234SKalle Valo return ret; 88350d41234SKalle Valo 88450d41234SKalle Valo data = fw->data; 88550d41234SKalle Valo len = fw->size; 88650d41234SKalle Valo 88750d41234SKalle Valo /* magic also includes the null byte, check that as well */ 88850d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 88950d41234SKalle Valo 89050d41234SKalle Valo if (len < magic_len) { 89150d41234SKalle Valo ret = -EINVAL; 89250d41234SKalle Valo goto out; 89350d41234SKalle Valo } 89450d41234SKalle Valo 89550d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 89650d41234SKalle Valo ret = -EINVAL; 89750d41234SKalle Valo goto out; 89850d41234SKalle Valo } 89950d41234SKalle Valo 90050d41234SKalle Valo len -= magic_len; 90150d41234SKalle Valo data += magic_len; 90250d41234SKalle Valo 90350d41234SKalle Valo /* loop elements */ 90450d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 90550d41234SKalle Valo /* hdr is unaligned! */ 90650d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 90750d41234SKalle Valo 90850d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 90950d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 91050d41234SKalle Valo 91150d41234SKalle Valo len -= sizeof(*hdr); 91250d41234SKalle Valo data += sizeof(*hdr); 91350d41234SKalle Valo 91450d41234SKalle Valo if (len < ie_len) { 91550d41234SKalle Valo ret = -EINVAL; 91650d41234SKalle Valo goto out; 91750d41234SKalle Valo } 91850d41234SKalle Valo 91950d41234SKalle Valo switch (ie_id) { 92050d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 921ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9226bc36431SKalle Valo ie_len); 9236bc36431SKalle Valo 92450d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 92550d41234SKalle Valo 92650d41234SKalle Valo if (ar->fw_otp == NULL) { 92750d41234SKalle Valo ret = -ENOMEM; 92850d41234SKalle Valo goto out; 92950d41234SKalle Valo } 93050d41234SKalle Valo 93150d41234SKalle Valo ar->fw_otp_len = ie_len; 93250d41234SKalle Valo break; 93350d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 934ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9356bc36431SKalle Valo ie_len); 9366bc36431SKalle Valo 9375f1127ffSKalle Valo /* in testmode we already might have a fw file */ 9385f1127ffSKalle Valo if (ar->fw != NULL) 9395f1127ffSKalle Valo break; 9405f1127ffSKalle Valo 9418437754cSVivek Natarajan ar->fw = vmalloc(ie_len); 94250d41234SKalle Valo 94350d41234SKalle Valo if (ar->fw == NULL) { 94450d41234SKalle Valo ret = -ENOMEM; 94550d41234SKalle Valo goto out; 94650d41234SKalle Valo } 94750d41234SKalle Valo 9488437754cSVivek Natarajan memcpy(ar->fw, data, ie_len); 94950d41234SKalle Valo ar->fw_len = ie_len; 95050d41234SKalle Valo break; 95150d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 952ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 9536bc36431SKalle Valo ie_len); 9546bc36431SKalle Valo 95550d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 95650d41234SKalle Valo 95750d41234SKalle Valo if (ar->fw_patch == NULL) { 95850d41234SKalle Valo ret = -ENOMEM; 95950d41234SKalle Valo goto out; 96050d41234SKalle Valo } 96150d41234SKalle Valo 96250d41234SKalle Valo ar->fw_patch_len = ie_len; 96350d41234SKalle Valo break; 9648a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 9658a137480SKalle Valo val = (__le32 *) data; 9668a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 9676bc36431SKalle Valo 9686bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 9696bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 9706bc36431SKalle Valo ar->hw.reserved_ram_size); 9718a137480SKalle Valo break; 97297e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 973277d90f4SKalle Valo if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) 974277d90f4SKalle Valo break; 975277d90f4SKalle Valo 9766bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 977ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 9786bc36431SKalle Valo ie_len); 9796bc36431SKalle Valo 98097e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 981277d90f4SKalle Valo index = i / 8; 98297e0496dSKalle Valo bit = i % 8; 98397e0496dSKalle Valo 98497e0496dSKalle Valo if (data[index] & (1 << bit)) 98597e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 98697e0496dSKalle Valo } 9876bc36431SKalle Valo 9886bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 9896bc36431SKalle Valo ar->fw_capabilities, 9906bc36431SKalle Valo sizeof(ar->fw_capabilities)); 99197e0496dSKalle Valo break; 9921b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 9931b4304daSKalle Valo if (ie_len != sizeof(*val)) 9941b4304daSKalle Valo break; 9951b4304daSKalle Valo 9961b4304daSKalle Valo val = (__le32 *) data; 9971b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 9986bc36431SKalle Valo 9996bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 100003ef0250SKalle Valo "found patch address ie 0x%x\n", 10016bc36431SKalle Valo ar->hw.dataset_patch_addr); 10021b4304daSKalle Valo break; 100303ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 100403ef0250SKalle Valo if (ie_len != sizeof(*val)) 100503ef0250SKalle Valo break; 100603ef0250SKalle Valo 100703ef0250SKalle Valo val = (__le32 *) data; 100803ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 100903ef0250SKalle Valo 101003ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 101103ef0250SKalle Valo "found board address ie 0x%x\n", 101203ef0250SKalle Valo ar->hw.board_addr); 101303ef0250SKalle Valo break; 1014368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 1015368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 1016368b1b0fSKalle Valo break; 1017368b1b0fSKalle Valo 1018368b1b0fSKalle Valo val = (__le32 *) data; 1019368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 1020368b1b0fSKalle Valo ATH6KL_VIF_MAX); 1021368b1b0fSKalle Valo 1022f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 1023f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1024f143379dSVasanthakumar Thiagarajan 1025368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1026368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1027368b1b0fSKalle Valo break; 102850d41234SKalle Valo default: 10296bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 103050d41234SKalle Valo le32_to_cpup(&hdr->id)); 103150d41234SKalle Valo break; 103250d41234SKalle Valo } 103350d41234SKalle Valo 103450d41234SKalle Valo len -= ie_len; 103550d41234SKalle Valo data += ie_len; 103650d41234SKalle Valo }; 103750d41234SKalle Valo 103850d41234SKalle Valo ret = 0; 103950d41234SKalle Valo out: 104050d41234SKalle Valo release_firmware(fw); 104150d41234SKalle Valo 104250d41234SKalle Valo return ret; 104350d41234SKalle Valo } 104450d41234SKalle Valo 104545eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar) 104650d41234SKalle Valo { 104750d41234SKalle Valo int ret; 104850d41234SKalle Valo 104950d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 105050d41234SKalle Valo if (ret) 105150d41234SKalle Valo return ret; 105250d41234SKalle Valo 10535f1127ffSKalle Valo ret = ath6kl_fetch_testmode_file(ar); 10545f1127ffSKalle Valo if (ret) 10555f1127ffSKalle Valo return ret; 10565f1127ffSKalle Valo 105765a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 10586bc36431SKalle Valo if (ret == 0) { 105965a8b4ccSKalle Valo ar->fw_api = 3; 106065a8b4ccSKalle Valo goto out; 106165a8b4ccSKalle Valo } 106265a8b4ccSKalle Valo 106365a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 106465a8b4ccSKalle Valo if (ret == 0) { 106565a8b4ccSKalle Valo ar->fw_api = 2; 106665a8b4ccSKalle Valo goto out; 10676bc36431SKalle Valo } 106850d41234SKalle Valo 106950d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 107050d41234SKalle Valo if (ret) 107150d41234SKalle Valo return ret; 107250d41234SKalle Valo 107365a8b4ccSKalle Valo ar->fw_api = 1; 107465a8b4ccSKalle Valo 107565a8b4ccSKalle Valo out: 107665a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 10776bc36431SKalle Valo 107850d41234SKalle Valo return 0; 107950d41234SKalle Valo } 108050d41234SKalle Valo 1081bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1082bdcd8170SKalle Valo { 1083bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 108431024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1085bdcd8170SKalle Valo int ret; 1086bdcd8170SKalle Valo 1087772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1088772c31eeSKalle Valo return -ENOENT; 1089bdcd8170SKalle Valo 109031024d99SKevin Fang /* 109131024d99SKevin Fang * Determine where in Target RAM to write Board Data. 109231024d99SKevin Fang * For AR6004, host determine Target RAM address for 109331024d99SKevin Fang * writing board data. 109431024d99SKevin Fang */ 10950d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 1096b0fc7c1aSKalle Valo board_address = ar->hw.board_addr; 109724fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data, 1098b0fc7c1aSKalle Valo board_address); 109931024d99SKevin Fang } else { 110080fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address); 110131024d99SKevin Fang } 110231024d99SKevin Fang 1103bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 110480fb2686SKalle Valo ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address); 1105bdcd8170SKalle Valo 110650e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 110750e2740bSKalle Valo board_ext_address == 0) { 1108bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1109bdcd8170SKalle Valo return -EINVAL; 1110bdcd8170SKalle Valo } 1111bdcd8170SKalle Valo 111231024d99SKevin Fang switch (ar->target_type) { 111331024d99SKevin Fang case TARGET_TYPE_AR6003: 111431024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 111531024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 1116fb1ac2efSPrasanna Kumar if (ar->fw_board_len > (board_data_size + board_ext_data_size)) 1117fb1ac2efSPrasanna Kumar board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2; 111831024d99SKevin Fang break; 111931024d99SKevin Fang case TARGET_TYPE_AR6004: 112031024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 112131024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 112231024d99SKevin Fang break; 112331024d99SKevin Fang default: 112431024d99SKevin Fang WARN_ON(1); 112531024d99SKevin Fang return -EINVAL; 112631024d99SKevin Fang break; 112731024d99SKevin Fang } 112831024d99SKevin Fang 112950e2740bSKalle Valo if (board_ext_address && 113050e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 113131024d99SKevin Fang 1132bdcd8170SKalle Valo /* write extended board data */ 11336bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11346bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11356bc36431SKalle Valo board_ext_address, board_ext_data_size); 11366bc36431SKalle Valo 1137bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 113831024d99SKevin Fang ar->fw_board + board_data_size, 113931024d99SKevin Fang board_ext_data_size); 1140bdcd8170SKalle Valo if (ret) { 1141bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1142bdcd8170SKalle Valo ret); 1143bdcd8170SKalle Valo return ret; 1144bdcd8170SKalle Valo } 1145bdcd8170SKalle Valo 1146bdcd8170SKalle Valo /* record that extended board data is initialized */ 114731024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 114831024d99SKevin Fang 114924fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param); 1150bdcd8170SKalle Valo } 1151bdcd8170SKalle Valo 115231024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1153bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1154bdcd8170SKalle Valo ret = -EINVAL; 1155bdcd8170SKalle Valo return ret; 1156bdcd8170SKalle Valo } 1157bdcd8170SKalle Valo 11586bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 11596bc36431SKalle Valo board_address, board_data_size); 11606bc36431SKalle Valo 1161bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 116231024d99SKevin Fang board_data_size); 1163bdcd8170SKalle Valo 1164bdcd8170SKalle Valo if (ret) { 1165bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1166bdcd8170SKalle Valo return ret; 1167bdcd8170SKalle Valo } 1168bdcd8170SKalle Valo 1169bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 117024fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1); 1171bdcd8170SKalle Valo 1172bdcd8170SKalle Valo return ret; 1173bdcd8170SKalle Valo } 1174bdcd8170SKalle Valo 1175bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1176bdcd8170SKalle Valo { 1177bdcd8170SKalle Valo u32 address, param; 1178bef26a7fSKalle Valo bool from_hw = false; 1179bdcd8170SKalle Valo int ret; 1180bdcd8170SKalle Valo 118150e2740bSKalle Valo if (ar->fw_otp == NULL) 118250e2740bSKalle Valo return 0; 1183bdcd8170SKalle Valo 1184a01ac414SKalle Valo address = ar->hw.app_load_addr; 1185bdcd8170SKalle Valo 1186ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 11876bc36431SKalle Valo ar->fw_otp_len); 11886bc36431SKalle Valo 1189bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1190bdcd8170SKalle Valo ar->fw_otp_len); 1191bdcd8170SKalle Valo if (ret) { 1192bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1193bdcd8170SKalle Valo return ret; 1194bdcd8170SKalle Valo } 1195bdcd8170SKalle Valo 1196639d0b89SKalle Valo /* read firmware start address */ 119780fb2686SKalle Valo ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address); 1198639d0b89SKalle Valo 1199639d0b89SKalle Valo if (ret) { 1200639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1201639d0b89SKalle Valo return ret; 1202639d0b89SKalle Valo } 1203639d0b89SKalle Valo 1204bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1205639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1206bef26a7fSKalle Valo from_hw = true; 1207bef26a7fSKalle Valo } 1208639d0b89SKalle Valo 1209bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1210bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 12116bc36431SKalle Valo ar->hw.app_start_override_addr); 12126bc36431SKalle Valo 1213bdcd8170SKalle Valo /* execute the OTP code */ 1214bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1215bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1216bdcd8170SKalle Valo param = 0; 1217bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1218bdcd8170SKalle Valo 1219bdcd8170SKalle Valo return ret; 1220bdcd8170SKalle Valo } 1221bdcd8170SKalle Valo 1222bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1223bdcd8170SKalle Valo { 1224bdcd8170SKalle Valo u32 address; 1225bdcd8170SKalle Valo int ret; 1226bdcd8170SKalle Valo 1227772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 122850e2740bSKalle Valo return 0; 1229bdcd8170SKalle Valo 1230a01ac414SKalle Valo address = ar->hw.app_load_addr; 1231bdcd8170SKalle Valo 1232ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12336bc36431SKalle Valo address, ar->fw_len); 12346bc36431SKalle Valo 1235bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1236bdcd8170SKalle Valo 1237bdcd8170SKalle Valo if (ret) { 1238bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1239bdcd8170SKalle Valo return ret; 1240bdcd8170SKalle Valo } 1241bdcd8170SKalle Valo 124231024d99SKevin Fang /* 124331024d99SKevin Fang * Set starting address for firmware 124431024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 124531024d99SKevin Fang */ 124631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1247a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1248bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 124931024d99SKevin Fang } 1250bdcd8170SKalle Valo return ret; 1251bdcd8170SKalle Valo } 1252bdcd8170SKalle Valo 1253bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1254bdcd8170SKalle Valo { 125524fc32b3SKalle Valo u32 address; 1256bdcd8170SKalle Valo int ret; 1257bdcd8170SKalle Valo 125850e2740bSKalle Valo if (ar->fw_patch == NULL) 125950e2740bSKalle Valo return 0; 1260bdcd8170SKalle Valo 1261a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1262bdcd8170SKalle Valo 1263ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 12646bc36431SKalle Valo address, ar->fw_patch_len); 12656bc36431SKalle Valo 1266bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1267bdcd8170SKalle Valo if (ret) { 1268bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1269bdcd8170SKalle Valo return ret; 1270bdcd8170SKalle Valo } 1271bdcd8170SKalle Valo 127224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address); 1273bdcd8170SKalle Valo 1274bdcd8170SKalle Valo return 0; 1275bdcd8170SKalle Valo } 1276bdcd8170SKalle Valo 1277cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar) 1278cd23c1c9SAlex Yang { 127924fc32b3SKalle Valo u32 address; 1280cd23c1c9SAlex Yang int ret; 1281cd23c1c9SAlex Yang 12825f1127ffSKalle Valo if (ar->testmode != 2) 1283cd23c1c9SAlex Yang return 0; 1284cd23c1c9SAlex Yang 1285cd23c1c9SAlex Yang if (ar->fw_testscript == NULL) 1286cd23c1c9SAlex Yang return 0; 1287cd23c1c9SAlex Yang 1288cd23c1c9SAlex Yang address = ar->hw.testscript_addr; 1289cd23c1c9SAlex Yang 1290cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1291cd23c1c9SAlex Yang address, ar->fw_testscript_len); 1292cd23c1c9SAlex Yang 1293cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1294cd23c1c9SAlex Yang ar->fw_testscript_len); 1295cd23c1c9SAlex Yang if (ret) { 1296cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret); 1297cd23c1c9SAlex Yang return ret; 1298cd23c1c9SAlex Yang } 1299cd23c1c9SAlex Yang 130024fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address); 130124fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096); 130224fc32b3SKalle Valo ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1); 1303cd23c1c9SAlex Yang 1304cd23c1c9SAlex Yang return 0; 1305cd23c1c9SAlex Yang } 1306cd23c1c9SAlex Yang 1307bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1308bdcd8170SKalle Valo { 1309bdcd8170SKalle Valo u32 param, options, sleep, address; 1310bdcd8170SKalle Valo int status = 0; 1311bdcd8170SKalle Valo 131231024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 131331024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1314bdcd8170SKalle Valo return -EINVAL; 1315bdcd8170SKalle Valo 1316bdcd8170SKalle Valo /* temporarily disable system sleep */ 1317bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1318bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1319bdcd8170SKalle Valo if (status) 1320bdcd8170SKalle Valo return status; 1321bdcd8170SKalle Valo 1322bdcd8170SKalle Valo options = param; 1323bdcd8170SKalle Valo 1324bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1325bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1326bdcd8170SKalle Valo if (status) 1327bdcd8170SKalle Valo return status; 1328bdcd8170SKalle Valo 1329bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1330bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1331bdcd8170SKalle Valo if (status) 1332bdcd8170SKalle Valo return status; 1333bdcd8170SKalle Valo 1334bdcd8170SKalle Valo sleep = param; 1335bdcd8170SKalle Valo 1336bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1337bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1338bdcd8170SKalle Valo if (status) 1339bdcd8170SKalle Valo return status; 1340bdcd8170SKalle Valo 1341bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1342bdcd8170SKalle Valo options, sleep); 1343bdcd8170SKalle Valo 1344bdcd8170SKalle Valo /* program analog PLL register */ 134531024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 134631024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1347bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1348bdcd8170SKalle Valo 0xF9104001); 134931024d99SKevin Fang 1350bdcd8170SKalle Valo if (status) 1351bdcd8170SKalle Valo return status; 1352bdcd8170SKalle Valo 1353bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1354bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1355bdcd8170SKalle Valo 1356bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1357bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1358bdcd8170SKalle Valo if (status) 1359bdcd8170SKalle Valo return status; 136031024d99SKevin Fang } 1361bdcd8170SKalle Valo 1362bdcd8170SKalle Valo param = 0; 1363bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1364bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1365bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1366bdcd8170SKalle Valo if (status) 1367bdcd8170SKalle Valo return status; 1368bdcd8170SKalle Valo 1369bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 13704480bb59SRaja Mani if (ar->version.target_ver == AR6003_HW_2_0_VERSION || 13714480bb59SRaja Mani ar->version.target_ver == AR6003_HW_2_1_1_VERSION) { 1372bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1373bdcd8170SKalle Valo 1374bdcd8170SKalle Valo param = 0x20; 1375bdcd8170SKalle Valo 1376bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1377bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1378bdcd8170SKalle Valo if (status) 1379bdcd8170SKalle Valo return status; 1380bdcd8170SKalle Valo 1381bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1382bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1383bdcd8170SKalle Valo if (status) 1384bdcd8170SKalle Valo return status; 1385bdcd8170SKalle Valo 1386bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1387bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1388bdcd8170SKalle Valo if (status) 1389bdcd8170SKalle Valo return status; 1390bdcd8170SKalle Valo 1391bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1392bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1393bdcd8170SKalle Valo if (status) 1394bdcd8170SKalle Valo return status; 1395bdcd8170SKalle Valo } 1396bdcd8170SKalle Valo 1397bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1398bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1399bdcd8170SKalle Valo if (status) 1400bdcd8170SKalle Valo return status; 1401bdcd8170SKalle Valo 1402bdcd8170SKalle Valo /* transfer One time Programmable data */ 1403bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1404bdcd8170SKalle Valo if (status) 1405bdcd8170SKalle Valo return status; 1406bdcd8170SKalle Valo 1407bdcd8170SKalle Valo /* Download Target firmware */ 1408bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1409bdcd8170SKalle Valo if (status) 1410bdcd8170SKalle Valo return status; 1411bdcd8170SKalle Valo 1412bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1413bdcd8170SKalle Valo if (status) 1414bdcd8170SKalle Valo return status; 1415bdcd8170SKalle Valo 1416cd23c1c9SAlex Yang /* Download the test script */ 1417cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar); 1418cd23c1c9SAlex Yang if (status) 1419cd23c1c9SAlex Yang return status; 1420cd23c1c9SAlex Yang 1421bdcd8170SKalle Valo /* Restore system sleep */ 1422bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1423bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1424bdcd8170SKalle Valo if (status) 1425bdcd8170SKalle Valo return status; 1426bdcd8170SKalle Valo 1427bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1428bdcd8170SKalle Valo param = options | 0x20; 1429bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1430bdcd8170SKalle Valo if (status) 1431bdcd8170SKalle Valo return status; 1432bdcd8170SKalle Valo 1433bdcd8170SKalle Valo return status; 1434bdcd8170SKalle Valo } 1435bdcd8170SKalle Valo 143645eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar) 1437a01ac414SKalle Valo { 14381b46dc04SKalle Valo const struct ath6kl_hw *uninitialized_var(hw); 1439856f4b31SKalle Valo int i; 1440bef26a7fSKalle Valo 1441856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1442856f4b31SKalle Valo hw = &hw_list[i]; 1443bef26a7fSKalle Valo 1444856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1445a01ac414SKalle Valo break; 1446856f4b31SKalle Valo } 1447856f4b31SKalle Valo 1448856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1449a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1450a01ac414SKalle Valo ar->version.target_ver); 1451a01ac414SKalle Valo return -EINVAL; 1452a01ac414SKalle Valo } 1453a01ac414SKalle Valo 1454856f4b31SKalle Valo ar->hw = *hw; 1455856f4b31SKalle Valo 14566bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14576bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 14586bc36431SKalle Valo ar->version.target_ver, ar->target_type, 14596bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 14606bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14616bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 14626bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 14636bc36431SKalle Valo ar->hw.reserved_ram_size); 146439586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 146539586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 146639586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 14676bc36431SKalle Valo 1468a01ac414SKalle Valo return 0; 1469a01ac414SKalle Valo } 1470a01ac414SKalle Valo 1471293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1472293badf4SKalle Valo { 1473293badf4SKalle Valo switch (type) { 1474293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1475293badf4SKalle Valo return "sdio"; 1476293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1477293badf4SKalle Valo return "usb"; 1478293badf4SKalle Valo } 1479293badf4SKalle Valo 1480293badf4SKalle Valo return NULL; 1481293badf4SKalle Valo } 1482293badf4SKalle Valo 14835fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 148420459ee2SKalle Valo { 148520459ee2SKalle Valo long timeleft; 148620459ee2SKalle Valo int ret, i; 148720459ee2SKalle Valo 14885fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 14895fe4dffbSKalle Valo 149020459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 149120459ee2SKalle Valo if (ret) 149220459ee2SKalle Valo return ret; 149320459ee2SKalle Valo 149420459ee2SKalle Valo ret = ath6kl_configure_target(ar); 149520459ee2SKalle Valo if (ret) 149620459ee2SKalle Valo goto err_power_off; 149720459ee2SKalle Valo 149820459ee2SKalle Valo ret = ath6kl_init_upload(ar); 149920459ee2SKalle Valo if (ret) 150020459ee2SKalle Valo goto err_power_off; 150120459ee2SKalle Valo 150220459ee2SKalle Valo /* Do we need to finish the BMI phase */ 150320459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 150420459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 150520459ee2SKalle Valo ret = -EIO; 150620459ee2SKalle Valo goto err_power_off; 150720459ee2SKalle Valo } 150820459ee2SKalle Valo 150920459ee2SKalle Valo /* 151020459ee2SKalle Valo * The reason we have to wait for the target here is that the 151120459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 151220459ee2SKalle Valo * size. 151320459ee2SKalle Valo */ 151420459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 151520459ee2SKalle Valo ret = -EIO; 151620459ee2SKalle Valo goto err_power_off; 151720459ee2SKalle Valo } 151820459ee2SKalle Valo 151920459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 152020459ee2SKalle Valo ret = -EIO; 152120459ee2SKalle Valo goto err_cleanup_scatter; 152220459ee2SKalle Valo } 152320459ee2SKalle Valo 152420459ee2SKalle Valo /* setup credit distribution */ 1525e76ac2bfSKalle Valo ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info); 152620459ee2SKalle Valo 152720459ee2SKalle Valo /* start HTC */ 152820459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 152920459ee2SKalle Valo if (ret) { 153020459ee2SKalle Valo /* FIXME: call this */ 153120459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 153220459ee2SKalle Valo goto err_cleanup_scatter; 153320459ee2SKalle Valo } 153420459ee2SKalle Valo 153520459ee2SKalle Valo /* Wait for Wmi event to be ready */ 153620459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 153720459ee2SKalle Valo test_bit(WMI_READY, 153820459ee2SKalle Valo &ar->flag), 153920459ee2SKalle Valo WMI_TIMEOUT); 154020459ee2SKalle Valo 154120459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 154220459ee2SKalle Valo 1543293badf4SKalle Valo 1544293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 154565a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1546293badf4SKalle Valo ar->hw.name, 1547293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1548293badf4SKalle Valo ar->wiphy->fw_version, 154965a8b4ccSKalle Valo ar->fw_api, 1550293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1551293badf4SKalle Valo } 1552293badf4SKalle Valo 155320459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 155420459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 155520459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 155620459ee2SKalle Valo ret = -EIO; 155720459ee2SKalle Valo goto err_htc_stop; 155820459ee2SKalle Valo } 155920459ee2SKalle Valo 156020459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 156120459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 156220459ee2SKalle Valo ret = -EIO; 156320459ee2SKalle Valo goto err_htc_stop; 156420459ee2SKalle Valo } 156520459ee2SKalle Valo 156620459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 156720459ee2SKalle Valo 156820459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 156920459ee2SKalle Valo /* FIXME: return error */ 157020459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 157120459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 157220459ee2SKalle Valo 157371f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 157420459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 157520459ee2SKalle Valo if (ret) 157620459ee2SKalle Valo goto err_htc_stop; 157720459ee2SKalle Valo } 157820459ee2SKalle Valo 157976a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 158076a9fbe2SKalle Valo 158120459ee2SKalle Valo return 0; 158220459ee2SKalle Valo 158320459ee2SKalle Valo err_htc_stop: 158420459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 158520459ee2SKalle Valo err_cleanup_scatter: 158620459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 158720459ee2SKalle Valo err_power_off: 158820459ee2SKalle Valo ath6kl_hif_power_off(ar); 158920459ee2SKalle Valo 159020459ee2SKalle Valo return ret; 159120459ee2SKalle Valo } 159220459ee2SKalle Valo 15935fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 15945fe4dffbSKalle Valo { 15955fe4dffbSKalle Valo int ret; 15965fe4dffbSKalle Valo 15975fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 15985fe4dffbSKalle Valo 15995fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 16005fe4dffbSKalle Valo 16015fe4dffbSKalle Valo ath6kl_hif_stop(ar); 16025fe4dffbSKalle Valo 16035fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 16045fe4dffbSKalle Valo 16055fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 16065fe4dffbSKalle Valo if (ret) 16075fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 16085fe4dffbSKalle Valo 160976a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 161076a9fbe2SKalle Valo 16115fe4dffbSKalle Valo return 0; 16125fe4dffbSKalle Valo } 16135fe4dffbSKalle Valo 1614c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ 161555055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 16166db8fa53SVasanthakumar Thiagarajan { 16176db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 16186db8fa53SVasanthakumar Thiagarajan bool discon_issued; 16196db8fa53SVasanthakumar Thiagarajan 16206db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 16216db8fa53SVasanthakumar Thiagarajan 16226db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 16236db8fa53SVasanthakumar Thiagarajan 16246db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 16256db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 16266db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 16276db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 16286db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 16296db8fa53SVasanthakumar Thiagarajan 16306db8fa53SVasanthakumar Thiagarajan if (discon_issued) 16316db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 16326db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 16336db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 16346db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 16356db8fa53SVasanthakumar Thiagarajan } 16366db8fa53SVasanthakumar Thiagarajan 16376db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 16386db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 16396db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 16406db8fa53SVasanthakumar Thiagarajan } 16416db8fa53SVasanthakumar Thiagarajan } 16426db8fa53SVasanthakumar Thiagarajan 1643bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1644bdcd8170SKalle Valo { 1645990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 16461d2a4456SVasanthakumar Thiagarajan int i; 1647bdcd8170SKalle Valo 1648bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1649bdcd8170SKalle Valo 1650bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1651bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1652bdcd8170SKalle Valo return; 1653bdcd8170SKalle Valo } 1654bdcd8170SKalle Valo 16551d2a4456SVasanthakumar Thiagarajan for (i = 0; i < AP_MAX_NUM_STA; i++) 16561d2a4456SVasanthakumar Thiagarajan aggr_reset_state(ar->sta_list[i].aggr_conn); 16571d2a4456SVasanthakumar Thiagarajan 165811f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1659990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1660990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 166111f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1662990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 166327929723SVasanthakumar Thiagarajan rtnl_lock(); 1664c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif); 166527929723SVasanthakumar Thiagarajan rtnl_unlock(); 166611f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1667990bd915SVasanthakumar Thiagarajan } 166811f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1669bdcd8170SKalle Valo 16706db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 16716db8fa53SVasanthakumar Thiagarajan 16726db8fa53SVasanthakumar Thiagarajan /* 16736db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 16746db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 16756db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 16766db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 16776db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 16786db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 16796db8fa53SVasanthakumar Thiagarajan * are collected. 16806db8fa53SVasanthakumar Thiagarajan */ 16816db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 16826db8fa53SVasanthakumar Thiagarajan 16836db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 16846db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 16856db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 16866db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1687bdcd8170SKalle Valo } 1688bdcd8170SKalle Valo 1689bdcd8170SKalle Valo /* 16906db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 16916db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1692bdcd8170SKalle Valo */ 16936db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 16946db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 16956db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1696bdcd8170SKalle Valo 16976db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1698e8ad9a06SVasanthakumar Thiagarajan 1699e8ad9a06SVasanthakumar Thiagarajan up(&ar->sem); 1700bdcd8170SKalle Valo } 1701d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx); 1702