1bdcd8170SKalle Valo 
2bdcd8170SKalle Valo /*
3bdcd8170SKalle Valo  * Copyright (c) 2011 Atheros Communications Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18c6efe578SStephen Rothwell #include <linux/moduleparam.h>
19f7830202SSangwook Lee #include <linux/errno.h>
20d6a434d6SKalle Valo #include <linux/export.h>
2192ecbff4SSam Leffler #include <linux/of.h>
22bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h>
23d6a434d6SKalle Valo 
24bdcd8170SKalle Valo #include "core.h"
25bdcd8170SKalle Valo #include "cfg80211.h"
26bdcd8170SKalle Valo #include "target.h"
27bdcd8170SKalle Valo #include "debug.h"
28bdcd8170SKalle Valo #include "hif-ops.h"
29bdcd8170SKalle Valo 
30003353b0SKalle Valo static unsigned int testmode;
31bdcd8170SKalle Valo 
32003353b0SKalle Valo module_param(testmode, uint, 0644);
33bdcd8170SKalle Valo 
34856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = {
35856f4b31SKalle Valo 	{
360d0192baSKalle Valo 		.id				= AR6003_HW_2_0_VERSION,
37293badf4SKalle Valo 		.name				= "ar6003 hw 2.0",
38856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57e884,
39856f4b31SKalle Valo 		.app_load_addr			= 0x543180,
40856f4b31SKalle Valo 		.board_ext_data_addr		= 0x57e500,
41856f4b31SKalle Valo 		.reserved_ram_size		= 6912,
4239586bf2SRyan Hsu 		.refclk_hz			= 26000000,
4339586bf2SRyan Hsu 		.uarttx_pin			= 8,
44856f4b31SKalle Valo 
45856f4b31SKalle Valo 		/* hw2.0 needs override address hardcoded */
46856f4b31SKalle Valo 		.app_start_override_addr	= 0x944C00,
47d1a9421dSKalle Valo 
48c0038972SKalle Valo 		.fw = {
49c0038972SKalle Valo 			.dir		= AR6003_HW_2_0_FW_DIR,
50c0038972SKalle Valo 			.otp		= AR6003_HW_2_0_OTP_FILE,
51d1a9421dSKalle Valo 			.fw		= AR6003_HW_2_0_FIRMWARE_FILE,
52c0038972SKalle Valo 			.tcmd		= AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
53c0038972SKalle Valo 			.patch		= AR6003_HW_2_0_PATCH_FILE,
54c0038972SKalle Valo 		},
55c0038972SKalle Valo 
56d1a9421dSKalle Valo 		.fw_board		= AR6003_HW_2_0_BOARD_DATA_FILE,
57d1a9421dSKalle Valo 		.fw_default_board	= AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
58856f4b31SKalle Valo 	},
59856f4b31SKalle Valo 	{
600d0192baSKalle Valo 		.id				= AR6003_HW_2_1_1_VERSION,
61293badf4SKalle Valo 		.name				= "ar6003 hw 2.1.1",
62856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57ff74,
63856f4b31SKalle Valo 		.app_load_addr			= 0x1234,
64856f4b31SKalle Valo 		.board_ext_data_addr		= 0x542330,
65856f4b31SKalle Valo 		.reserved_ram_size		= 512,
6639586bf2SRyan Hsu 		.refclk_hz			= 26000000,
6739586bf2SRyan Hsu 		.uarttx_pin			= 8,
68cd23c1c9SAlex Yang 		.testscript_addr		= 0x57ef74,
69d1a9421dSKalle Valo 
70c0038972SKalle Valo 		.fw = {
71c0038972SKalle Valo 			.dir		= AR6003_HW_2_1_1_FW_DIR,
72c0038972SKalle Valo 			.otp		= AR6003_HW_2_1_1_OTP_FILE,
73d1a9421dSKalle Valo 			.fw		= AR6003_HW_2_1_1_FIRMWARE_FILE,
74c0038972SKalle Valo 			.tcmd		= AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
75c0038972SKalle Valo 			.patch		= AR6003_HW_2_1_1_PATCH_FILE,
76cd23c1c9SAlex Yang 			.utf		= AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
77cd23c1c9SAlex Yang 			.testscript	= AR6003_HW_2_1_1_TESTSCRIPT_FILE,
78c0038972SKalle Valo 		},
79c0038972SKalle Valo 
80d1a9421dSKalle Valo 		.fw_board		= AR6003_HW_2_1_1_BOARD_DATA_FILE,
81d1a9421dSKalle Valo 		.fw_default_board	= AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
82856f4b31SKalle Valo 	},
83856f4b31SKalle Valo 	{
840d0192baSKalle Valo 		.id				= AR6004_HW_1_0_VERSION,
85293badf4SKalle Valo 		.name				= "ar6004 hw 1.0",
86856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57e884,
87856f4b31SKalle Valo 		.app_load_addr			= 0x1234,
88856f4b31SKalle Valo 		.board_ext_data_addr		= 0x437000,
89856f4b31SKalle Valo 		.reserved_ram_size		= 19456,
900d4d72bfSKalle Valo 		.board_addr			= 0x433900,
9139586bf2SRyan Hsu 		.refclk_hz			= 26000000,
9239586bf2SRyan Hsu 		.uarttx_pin			= 11,
93d1a9421dSKalle Valo 
94c0038972SKalle Valo 		.fw = {
95c0038972SKalle Valo 			.dir		= AR6004_HW_1_0_FW_DIR,
96d1a9421dSKalle Valo 			.fw		= AR6004_HW_1_0_FIRMWARE_FILE,
97c0038972SKalle Valo 		},
98c0038972SKalle Valo 
99d1a9421dSKalle Valo 		.fw_board		= AR6004_HW_1_0_BOARD_DATA_FILE,
100d1a9421dSKalle Valo 		.fw_default_board	= AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
101856f4b31SKalle Valo 	},
102856f4b31SKalle Valo 	{
1030d0192baSKalle Valo 		.id				= AR6004_HW_1_1_VERSION,
104293badf4SKalle Valo 		.name				= "ar6004 hw 1.1",
105856f4b31SKalle Valo 		.dataset_patch_addr		= 0x57e884,
106856f4b31SKalle Valo 		.app_load_addr			= 0x1234,
107856f4b31SKalle Valo 		.board_ext_data_addr		= 0x437000,
108856f4b31SKalle Valo 		.reserved_ram_size		= 11264,
1090d4d72bfSKalle Valo 		.board_addr			= 0x43d400,
11039586bf2SRyan Hsu 		.refclk_hz			= 40000000,
11139586bf2SRyan Hsu 		.uarttx_pin			= 11,
112d1a9421dSKalle Valo 
113c0038972SKalle Valo 		.fw = {
114c0038972SKalle Valo 			.dir		= AR6004_HW_1_1_FW_DIR,
115d1a9421dSKalle Valo 			.fw		= AR6004_HW_1_1_FIRMWARE_FILE,
116c0038972SKalle Valo 		},
117c0038972SKalle Valo 
118d1a9421dSKalle Valo 		.fw_board		= AR6004_HW_1_1_BOARD_DATA_FILE,
119d1a9421dSKalle Valo 		.fw_default_board	= AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
120856f4b31SKalle Valo 	},
121856f4b31SKalle Valo };
122856f4b31SKalle Valo 
123bdcd8170SKalle Valo /*
124bdcd8170SKalle Valo  * Include definitions here that can be used to tune the WLAN module
125bdcd8170SKalle Valo  * behavior. Different customers can tune the behavior as per their needs,
126bdcd8170SKalle Valo  * here.
127bdcd8170SKalle Valo  */
128bdcd8170SKalle Valo 
129bdcd8170SKalle Valo /*
130bdcd8170SKalle Valo  * This configuration item enable/disable keepalive support.
131bdcd8170SKalle Valo  * Keepalive support: In the absence of any data traffic to AP, null
132bdcd8170SKalle Valo  * frames will be sent to the AP at periodic interval, to keep the association
133bdcd8170SKalle Valo  * active. This configuration item defines the periodic interval.
134bdcd8170SKalle Valo  * Use value of zero to disable keepalive support
135bdcd8170SKalle Valo  * Default: 60 seconds
136bdcd8170SKalle Valo  */
137bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
138bdcd8170SKalle Valo 
139bdcd8170SKalle Valo /*
140bdcd8170SKalle Valo  * This configuration item sets the value of disconnect timeout
141bdcd8170SKalle Valo  * Firmware delays sending the disconnec event to the host for this
142bdcd8170SKalle Valo  * timeout after is gets disconnected from the current AP.
143bdcd8170SKalle Valo  * If the firmware successly roams within the disconnect timeout
144bdcd8170SKalle Valo  * it sends a new connect event
145bdcd8170SKalle Valo  */
146bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
147bdcd8170SKalle Valo 
148bdcd8170SKalle Valo 
149bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET    64
150bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size)
151bdcd8170SKalle Valo {
152bdcd8170SKalle Valo 	struct sk_buff *skb;
153bdcd8170SKalle Valo 	u16 reserved;
154bdcd8170SKalle Valo 
155bdcd8170SKalle Valo 	/* Add chacheline space at front and back of buffer */
156bdcd8170SKalle Valo 	reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
1571df94a85SVasanthakumar Thiagarajan 		   sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
158bdcd8170SKalle Valo 	skb = dev_alloc_skb(size + reserved);
159bdcd8170SKalle Valo 
160bdcd8170SKalle Valo 	if (skb)
161bdcd8170SKalle Valo 		skb_reserve(skb, reserved - L1_CACHE_BYTES);
162bdcd8170SKalle Valo 	return skb;
163bdcd8170SKalle Valo }
164bdcd8170SKalle Valo 
165e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif)
166bdcd8170SKalle Valo {
1673450334fSVasanthakumar Thiagarajan 	vif->ssid_len = 0;
1683450334fSVasanthakumar Thiagarajan 	memset(vif->ssid, 0, sizeof(vif->ssid));
1693450334fSVasanthakumar Thiagarajan 
1703450334fSVasanthakumar Thiagarajan 	vif->dot11_auth_mode = OPEN_AUTH;
1713450334fSVasanthakumar Thiagarajan 	vif->auth_mode = NONE_AUTH;
1723450334fSVasanthakumar Thiagarajan 	vif->prwise_crypto = NONE_CRYPT;
1733450334fSVasanthakumar Thiagarajan 	vif->prwise_crypto_len = 0;
1743450334fSVasanthakumar Thiagarajan 	vif->grp_crypto = NONE_CRYPT;
1753450334fSVasanthakumar Thiagarajan 	vif->grp_crypto_len = 0;
1766f2a73f9SVasanthakumar Thiagarajan 	memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
1778c8b65e3SVasanthakumar Thiagarajan 	memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
1788c8b65e3SVasanthakumar Thiagarajan 	memset(vif->bssid, 0, sizeof(vif->bssid));
179f74bac54SVasanthakumar Thiagarajan 	vif->bss_ch = 0;
180bdcd8170SKalle Valo }
181bdcd8170SKalle Valo 
182bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar)
183bdcd8170SKalle Valo {
184bdcd8170SKalle Valo 	u32 address, data;
185bdcd8170SKalle Valo 	struct host_app_area host_app_area;
186bdcd8170SKalle Valo 
187bdcd8170SKalle Valo 	/* Fetch the address of the host_app_area_s
188bdcd8170SKalle Valo 	 * instance in the host interest area */
189bdcd8170SKalle Valo 	address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
19031024d99SKevin Fang 	address = TARG_VTOP(ar->target_type, address);
191bdcd8170SKalle Valo 
192addb44beSKalle Valo 	if (ath6kl_diag_read32(ar, address, &data))
193bdcd8170SKalle Valo 		return -EIO;
194bdcd8170SKalle Valo 
19531024d99SKevin Fang 	address = TARG_VTOP(ar->target_type, data);
196cbf49a6fSKalle Valo 	host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
197addb44beSKalle Valo 	if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
198addb44beSKalle Valo 			      sizeof(struct host_app_area)))
199bdcd8170SKalle Valo 		return -EIO;
200bdcd8170SKalle Valo 
201bdcd8170SKalle Valo 	return 0;
202bdcd8170SKalle Valo }
203bdcd8170SKalle Valo 
204bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar,
205bdcd8170SKalle Valo 				  u8 ac,
206bdcd8170SKalle Valo 				  enum htc_endpoint_id ep)
207bdcd8170SKalle Valo {
208bdcd8170SKalle Valo 	ar->ac2ep_map[ac] = ep;
209bdcd8170SKalle Valo 	ar->ep2ac_map[ep] = ac;
210bdcd8170SKalle Valo }
211bdcd8170SKalle Valo 
212bdcd8170SKalle Valo /* connect to a service */
213bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar,
214bdcd8170SKalle Valo 				 struct htc_service_connect_req  *con_req,
215bdcd8170SKalle Valo 				 char *desc)
216bdcd8170SKalle Valo {
217bdcd8170SKalle Valo 	int status;
218bdcd8170SKalle Valo 	struct htc_service_connect_resp response;
219bdcd8170SKalle Valo 
220bdcd8170SKalle Valo 	memset(&response, 0, sizeof(response));
221bdcd8170SKalle Valo 
222ad226ec2SKalle Valo 	status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
223bdcd8170SKalle Valo 	if (status) {
224bdcd8170SKalle Valo 		ath6kl_err("failed to connect to %s service status:%d\n",
225bdcd8170SKalle Valo 			   desc, status);
226bdcd8170SKalle Valo 		return status;
227bdcd8170SKalle Valo 	}
228bdcd8170SKalle Valo 
229bdcd8170SKalle Valo 	switch (con_req->svc_id) {
230bdcd8170SKalle Valo 	case WMI_CONTROL_SVC:
231bdcd8170SKalle Valo 		if (test_bit(WMI_ENABLED, &ar->flag))
232bdcd8170SKalle Valo 			ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
233bdcd8170SKalle Valo 		ar->ctrl_ep = response.endpoint;
234bdcd8170SKalle Valo 		break;
235bdcd8170SKalle Valo 	case WMI_DATA_BE_SVC:
236bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
237bdcd8170SKalle Valo 		break;
238bdcd8170SKalle Valo 	case WMI_DATA_BK_SVC:
239bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
240bdcd8170SKalle Valo 		break;
241bdcd8170SKalle Valo 	case WMI_DATA_VI_SVC:
242bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
243bdcd8170SKalle Valo 		break;
244bdcd8170SKalle Valo 	case WMI_DATA_VO_SVC:
245bdcd8170SKalle Valo 		set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
246bdcd8170SKalle Valo 		break;
247bdcd8170SKalle Valo 	default:
248bdcd8170SKalle Valo 		ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
249bdcd8170SKalle Valo 		return -EINVAL;
250bdcd8170SKalle Valo 	}
251bdcd8170SKalle Valo 
252bdcd8170SKalle Valo 	return 0;
253bdcd8170SKalle Valo }
254bdcd8170SKalle Valo 
255bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar)
256bdcd8170SKalle Valo {
257bdcd8170SKalle Valo 	struct htc_service_connect_req connect;
258bdcd8170SKalle Valo 
259bdcd8170SKalle Valo 	memset(&connect, 0, sizeof(connect));
260bdcd8170SKalle Valo 
261bdcd8170SKalle Valo 	/* these fields are the same for all service endpoints */
262bdcd8170SKalle Valo 	connect.ep_cb.rx = ath6kl_rx;
263bdcd8170SKalle Valo 	connect.ep_cb.rx_refill = ath6kl_rx_refill;
264bdcd8170SKalle Valo 	connect.ep_cb.tx_full = ath6kl_tx_queue_full;
265bdcd8170SKalle Valo 
266bdcd8170SKalle Valo 	/*
267bdcd8170SKalle Valo 	 * Set the max queue depth so that our ath6kl_tx_queue_full handler
268bdcd8170SKalle Valo 	 * gets called.
269bdcd8170SKalle Valo 	*/
270bdcd8170SKalle Valo 	connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
271bdcd8170SKalle Valo 	connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
272bdcd8170SKalle Valo 	if (!connect.ep_cb.rx_refill_thresh)
273bdcd8170SKalle Valo 		connect.ep_cb.rx_refill_thresh++;
274bdcd8170SKalle Valo 
275bdcd8170SKalle Valo 	/* connect to control service */
276bdcd8170SKalle Valo 	connect.svc_id = WMI_CONTROL_SVC;
277bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
278bdcd8170SKalle Valo 		return -EIO;
279bdcd8170SKalle Valo 
280bdcd8170SKalle Valo 	connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
281bdcd8170SKalle Valo 
282bdcd8170SKalle Valo 	/*
283bdcd8170SKalle Valo 	 * Limit the HTC message size on the send path, although e can
284bdcd8170SKalle Valo 	 * receive A-MSDU frames of 4K, we will only send ethernet-sized
285bdcd8170SKalle Valo 	 * (802.3) frames on the send path.
286bdcd8170SKalle Valo 	 */
287bdcd8170SKalle Valo 	connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
288bdcd8170SKalle Valo 
289bdcd8170SKalle Valo 	/*
290bdcd8170SKalle Valo 	 * To reduce the amount of committed memory for larger A_MSDU
291bdcd8170SKalle Valo 	 * frames, use the recv-alloc threshold mechanism for larger
292bdcd8170SKalle Valo 	 * packets.
293bdcd8170SKalle Valo 	 */
294bdcd8170SKalle Valo 	connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
295bdcd8170SKalle Valo 	connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
296bdcd8170SKalle Valo 
297bdcd8170SKalle Valo 	/*
298bdcd8170SKalle Valo 	 * For the remaining data services set the connection flag to
299bdcd8170SKalle Valo 	 * reduce dribbling, if configured to do so.
300bdcd8170SKalle Valo 	 */
301bdcd8170SKalle Valo 	connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
302bdcd8170SKalle Valo 	connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
303bdcd8170SKalle Valo 	connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
304bdcd8170SKalle Valo 
305bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_BE_SVC;
306bdcd8170SKalle Valo 
307bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
308bdcd8170SKalle Valo 		return -EIO;
309bdcd8170SKalle Valo 
310bdcd8170SKalle Valo 	/* connect to back-ground map this to WMI LOW_PRI */
311bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_BK_SVC;
312bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
313bdcd8170SKalle Valo 		return -EIO;
314bdcd8170SKalle Valo 
315bdcd8170SKalle Valo 	/* connect to Video service, map this to to HI PRI */
316bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_VI_SVC;
317bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
318bdcd8170SKalle Valo 		return -EIO;
319bdcd8170SKalle Valo 
320bdcd8170SKalle Valo 	/*
321bdcd8170SKalle Valo 	 * Connect to VO service, this is currently not mapped to a WMI
322bdcd8170SKalle Valo 	 * priority stream due to historical reasons. WMI originally
323bdcd8170SKalle Valo 	 * defined 3 priorities over 3 mailboxes We can change this when
324bdcd8170SKalle Valo 	 * WMI is reworked so that priorities are not dependent on
325bdcd8170SKalle Valo 	 * mailboxes.
326bdcd8170SKalle Valo 	 */
327bdcd8170SKalle Valo 	connect.svc_id = WMI_DATA_VO_SVC;
328bdcd8170SKalle Valo 	if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
329bdcd8170SKalle Valo 		return -EIO;
330bdcd8170SKalle Valo 
331bdcd8170SKalle Valo 	return 0;
332bdcd8170SKalle Valo }
333bdcd8170SKalle Valo 
334e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif)
335bdcd8170SKalle Valo {
336e29f25f5SVasanthakumar Thiagarajan 	ath6kl_init_profile_info(vif);
3373450334fSVasanthakumar Thiagarajan 	vif->def_txkey_index = 0;
3386f2a73f9SVasanthakumar Thiagarajan 	memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
339f74bac54SVasanthakumar Thiagarajan 	vif->ch_hint = 0;
340bdcd8170SKalle Valo }
341bdcd8170SKalle Valo 
342bdcd8170SKalle Valo /*
343bdcd8170SKalle Valo  * Set HTC/Mbox operational parameters, this can only be called when the
344bdcd8170SKalle Valo  * target is in the BMI phase.
345bdcd8170SKalle Valo  */
346bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
347bdcd8170SKalle Valo 				 u8 htc_ctrl_buf)
348bdcd8170SKalle Valo {
349bdcd8170SKalle Valo 	int status;
350bdcd8170SKalle Valo 	u32 blk_size;
351bdcd8170SKalle Valo 
352bdcd8170SKalle Valo 	blk_size = ar->mbox_info.block_size;
353bdcd8170SKalle Valo 
354bdcd8170SKalle Valo 	if (htc_ctrl_buf)
355bdcd8170SKalle Valo 		blk_size |=  ((u32)htc_ctrl_buf) << 16;
356bdcd8170SKalle Valo 
357bdcd8170SKalle Valo 	/* set the host interest area for the block size */
358bdcd8170SKalle Valo 	status = ath6kl_bmi_write(ar,
359bdcd8170SKalle Valo 			ath6kl_get_hi_item_addr(ar,
360bdcd8170SKalle Valo 			HI_ITEM(hi_mbox_io_block_sz)),
361bdcd8170SKalle Valo 			(u8 *)&blk_size,
362bdcd8170SKalle Valo 			4);
363bdcd8170SKalle Valo 	if (status) {
364bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for IO block size failed\n");
365bdcd8170SKalle Valo 		goto out;
366bdcd8170SKalle Valo 	}
367bdcd8170SKalle Valo 
368bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
369bdcd8170SKalle Valo 		   blk_size,
370bdcd8170SKalle Valo 		   ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
371bdcd8170SKalle Valo 
372bdcd8170SKalle Valo 	if (mbox_isr_yield_val) {
373bdcd8170SKalle Valo 		/* set the host interest area for the mbox ISR yield limit */
374bdcd8170SKalle Valo 		status = ath6kl_bmi_write(ar,
375bdcd8170SKalle Valo 				ath6kl_get_hi_item_addr(ar,
376bdcd8170SKalle Valo 				HI_ITEM(hi_mbox_isr_yield_limit)),
377bdcd8170SKalle Valo 				(u8 *)&mbox_isr_yield_val,
378bdcd8170SKalle Valo 				4);
379bdcd8170SKalle Valo 		if (status) {
380bdcd8170SKalle Valo 			ath6kl_err("bmi_write_memory for yield limit failed\n");
381bdcd8170SKalle Valo 			goto out;
382bdcd8170SKalle Valo 		}
383bdcd8170SKalle Valo 	}
384bdcd8170SKalle Valo 
385bdcd8170SKalle Valo out:
386bdcd8170SKalle Valo 	return status;
387bdcd8170SKalle Valo }
388bdcd8170SKalle Valo 
3890ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
390bdcd8170SKalle Valo {
391bdcd8170SKalle Valo 	int status = 0;
3924dea08e0SJouni Malinen 	int ret;
393bdcd8170SKalle Valo 
394bdcd8170SKalle Valo 	/*
395bdcd8170SKalle Valo 	 * Configure the device for rx dot11 header rules. "0,0" are the
396bdcd8170SKalle Valo 	 * default values. Required if checksum offload is needed. Set
397bdcd8170SKalle Valo 	 * RxMetaVersion to 2.
398bdcd8170SKalle Valo 	 */
3990ce59445SVasanthakumar Thiagarajan 	if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
400bdcd8170SKalle Valo 					       ar->rx_meta_ver, 0, 0)) {
401bdcd8170SKalle Valo 		ath6kl_err("unable to set the rx frame format\n");
402bdcd8170SKalle Valo 		status = -EIO;
403bdcd8170SKalle Valo 	}
404bdcd8170SKalle Valo 
405bdcd8170SKalle Valo 	if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN)
4060ce59445SVasanthakumar Thiagarajan 		if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
407bdcd8170SKalle Valo 		     IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
408bdcd8170SKalle Valo 			ath6kl_err("unable to set power save fail event policy\n");
409bdcd8170SKalle Valo 			status = -EIO;
410bdcd8170SKalle Valo 		}
411bdcd8170SKalle Valo 
412bdcd8170SKalle Valo 	if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER))
4130ce59445SVasanthakumar Thiagarajan 		if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
414bdcd8170SKalle Valo 		     WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) {
415bdcd8170SKalle Valo 			ath6kl_err("unable to set barker preamble policy\n");
416bdcd8170SKalle Valo 			status = -EIO;
417bdcd8170SKalle Valo 		}
418bdcd8170SKalle Valo 
4190ce59445SVasanthakumar Thiagarajan 	if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
420bdcd8170SKalle Valo 			WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) {
421bdcd8170SKalle Valo 		ath6kl_err("unable to set keep alive interval\n");
422bdcd8170SKalle Valo 		status = -EIO;
423bdcd8170SKalle Valo 	}
424bdcd8170SKalle Valo 
4250ce59445SVasanthakumar Thiagarajan 	if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
426bdcd8170SKalle Valo 			WLAN_CONFIG_DISCONNECT_TIMEOUT)) {
427bdcd8170SKalle Valo 		ath6kl_err("unable to set disconnect timeout\n");
428bdcd8170SKalle Valo 		status = -EIO;
429bdcd8170SKalle Valo 	}
430bdcd8170SKalle Valo 
431bdcd8170SKalle Valo 	if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST))
4320ce59445SVasanthakumar Thiagarajan 		if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) {
433bdcd8170SKalle Valo 			ath6kl_err("unable to set txop bursting\n");
434bdcd8170SKalle Valo 			status = -EIO;
435bdcd8170SKalle Valo 		}
436bdcd8170SKalle Valo 
437b64de356SVasanthakumar Thiagarajan 	if (ar->p2p && (ar->vif_max == 1 || idx)) {
4380ce59445SVasanthakumar Thiagarajan 		ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
4396bbc7c35SJouni Malinen 					      P2P_FLAG_CAPABILITIES_REQ |
4404dea08e0SJouni Malinen 					      P2P_FLAG_MACADDR_REQ |
4414dea08e0SJouni Malinen 					      P2P_FLAG_HMODEL_REQ);
4424dea08e0SJouni Malinen 		if (ret) {
4434dea08e0SJouni Malinen 			ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
4446bbc7c35SJouni Malinen 				   "capabilities (%d) - assuming P2P not "
4456bbc7c35SJouni Malinen 				   "supported\n", ret);
4463db1cd5cSRusty Russell 			ar->p2p = false;
4476bbc7c35SJouni Malinen 		}
4486bbc7c35SJouni Malinen 	}
4496bbc7c35SJouni Malinen 
450b64de356SVasanthakumar Thiagarajan 	if (ar->p2p && (ar->vif_max == 1 || idx)) {
4516bbc7c35SJouni Malinen 		/* Enable Probe Request reporting for P2P */
4520ce59445SVasanthakumar Thiagarajan 		ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
4536bbc7c35SJouni Malinen 		if (ret) {
4546bbc7c35SJouni Malinen 			ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
4556bbc7c35SJouni Malinen 				   "Request reporting (%d)\n", ret);
4566bbc7c35SJouni Malinen 		}
4574dea08e0SJouni Malinen 	}
4584dea08e0SJouni Malinen 
459bdcd8170SKalle Valo 	return status;
460bdcd8170SKalle Valo }
461bdcd8170SKalle Valo 
462bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar)
463bdcd8170SKalle Valo {
464bdcd8170SKalle Valo 	u32 param, ram_reserved_size;
4653226f68aSVasanthakumar Thiagarajan 	u8 fw_iftype, fw_mode = 0, fw_submode = 0;
46639586bf2SRyan Hsu 	int i, status;
467bdcd8170SKalle Valo 
468f29af978SKalle Valo 	param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
469a10e2f2fSVasanthakumar Thiagarajan 	if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
470a10e2f2fSVasanthakumar Thiagarajan 			     HI_ITEM(hi_serial_enable)), (u8 *)&param, 4)) {
471a10e2f2fSVasanthakumar Thiagarajan 		ath6kl_err("bmi_write_memory for uart debug failed\n");
472a10e2f2fSVasanthakumar Thiagarajan 		return -EIO;
473a10e2f2fSVasanthakumar Thiagarajan 	}
474a10e2f2fSVasanthakumar Thiagarajan 
4757b85832dSVasanthakumar Thiagarajan 	/*
4767b85832dSVasanthakumar Thiagarajan 	 * Note: Even though the firmware interface type is
4777b85832dSVasanthakumar Thiagarajan 	 * chosen as BSS_STA for all three interfaces, can
4787b85832dSVasanthakumar Thiagarajan 	 * be configured to IBSS/AP as long as the fw submode
4797b85832dSVasanthakumar Thiagarajan 	 * remains normal mode (0 - AP, STA and IBSS). But
4807b85832dSVasanthakumar Thiagarajan 	 * due to an target assert in firmware only one interface is
4817b85832dSVasanthakumar Thiagarajan 	 * configured for now.
4827b85832dSVasanthakumar Thiagarajan 	 */
483dd3751f7SVasanthakumar Thiagarajan 	fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
484bdcd8170SKalle Valo 
48571f96ee6SKalle Valo 	for (i = 0; i < ar->vif_max; i++)
4867b85832dSVasanthakumar Thiagarajan 		fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
4877b85832dSVasanthakumar Thiagarajan 
4887b85832dSVasanthakumar Thiagarajan 	/*
4893226f68aSVasanthakumar Thiagarajan 	 * By default, submodes :
4903226f68aSVasanthakumar Thiagarajan 	 *		vif[0] - AP/STA/IBSS
4917b85832dSVasanthakumar Thiagarajan 	 *		vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
4927b85832dSVasanthakumar Thiagarajan 	 *		vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
4937b85832dSVasanthakumar Thiagarajan 	 */
4943226f68aSVasanthakumar Thiagarajan 
4953226f68aSVasanthakumar Thiagarajan 	for (i = 0; i < ar->max_norm_iface; i++)
4963226f68aSVasanthakumar Thiagarajan 		fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
4973226f68aSVasanthakumar Thiagarajan 			      (i * HI_OPTION_FW_SUBMODE_BITS);
4983226f68aSVasanthakumar Thiagarajan 
49971f96ee6SKalle Valo 	for (i = ar->max_norm_iface; i < ar->vif_max; i++)
5003226f68aSVasanthakumar Thiagarajan 		fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
5013226f68aSVasanthakumar Thiagarajan 			      (i * HI_OPTION_FW_SUBMODE_BITS);
5027b85832dSVasanthakumar Thiagarajan 
503b64de356SVasanthakumar Thiagarajan 	if (ar->p2p && ar->vif_max == 1)
5047b85832dSVasanthakumar Thiagarajan 		fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
5057b85832dSVasanthakumar Thiagarajan 
506bdcd8170SKalle Valo 	param = HTC_PROTOCOL_VERSION;
507bdcd8170SKalle Valo 	if (ath6kl_bmi_write(ar,
508bdcd8170SKalle Valo 			     ath6kl_get_hi_item_addr(ar,
509bdcd8170SKalle Valo 			     HI_ITEM(hi_app_host_interest)),
510bdcd8170SKalle Valo 			     (u8 *)&param, 4) != 0) {
511bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for htc version failed\n");
512bdcd8170SKalle Valo 		return -EIO;
513bdcd8170SKalle Valo 	}
514bdcd8170SKalle Valo 
515bdcd8170SKalle Valo 	/* set the firmware mode to STA/IBSS/AP */
516bdcd8170SKalle Valo 	param = 0;
517bdcd8170SKalle Valo 
518bdcd8170SKalle Valo 	if (ath6kl_bmi_read(ar,
519bdcd8170SKalle Valo 			    ath6kl_get_hi_item_addr(ar,
520bdcd8170SKalle Valo 			    HI_ITEM(hi_option_flag)),
521bdcd8170SKalle Valo 			    (u8 *)&param, 4) != 0) {
522bdcd8170SKalle Valo 		ath6kl_err("bmi_read_memory for setting fwmode failed\n");
523bdcd8170SKalle Valo 		return -EIO;
524bdcd8170SKalle Valo 	}
525bdcd8170SKalle Valo 
52671f96ee6SKalle Valo 	param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
5277b85832dSVasanthakumar Thiagarajan 	param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
5287b85832dSVasanthakumar Thiagarajan 	param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
5297b85832dSVasanthakumar Thiagarajan 
530bdcd8170SKalle Valo 	param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
531bdcd8170SKalle Valo 	param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
532bdcd8170SKalle Valo 
533bdcd8170SKalle Valo 	if (ath6kl_bmi_write(ar,
534bdcd8170SKalle Valo 			     ath6kl_get_hi_item_addr(ar,
535bdcd8170SKalle Valo 			     HI_ITEM(hi_option_flag)),
536bdcd8170SKalle Valo 			     (u8 *)&param,
537bdcd8170SKalle Valo 			     4) != 0) {
538bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for setting fwmode failed\n");
539bdcd8170SKalle Valo 		return -EIO;
540bdcd8170SKalle Valo 	}
541bdcd8170SKalle Valo 
542bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
543bdcd8170SKalle Valo 
544bdcd8170SKalle Valo 	/*
545bdcd8170SKalle Valo 	 * Hardcode the address use for the extended board data
546bdcd8170SKalle Valo 	 * Ideally this should be pre-allocate by the OS at boot time
547bdcd8170SKalle Valo 	 * But since it is a new feature and board data is loaded
548bdcd8170SKalle Valo 	 * at init time, we have to workaround this from host.
549bdcd8170SKalle Valo 	 * It is difficult to patch the firmware boot code,
550bdcd8170SKalle Valo 	 * but possible in theory.
551bdcd8170SKalle Valo 	 */
552bdcd8170SKalle Valo 
553991b27eaSKalle Valo 	param = ar->hw.board_ext_data_addr;
554991b27eaSKalle Valo 	ram_reserved_size = ar->hw.reserved_ram_size;
555bdcd8170SKalle Valo 
556991b27eaSKalle Valo 	if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
557bdcd8170SKalle Valo 					HI_ITEM(hi_board_ext_data)),
558bdcd8170SKalle Valo 			     (u8 *)&param, 4) != 0) {
559bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
560bdcd8170SKalle Valo 		return -EIO;
561bdcd8170SKalle Valo 	}
562991b27eaSKalle Valo 
563991b27eaSKalle Valo 	if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
564bdcd8170SKalle Valo 					HI_ITEM(hi_end_ram_reserve_sz)),
565bdcd8170SKalle Valo 			     (u8 *)&ram_reserved_size, 4) != 0) {
566bdcd8170SKalle Valo 		ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
567bdcd8170SKalle Valo 		return -EIO;
568bdcd8170SKalle Valo 	}
569bdcd8170SKalle Valo 
570bdcd8170SKalle Valo 	/* set the block size for the target */
571bdcd8170SKalle Valo 	if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
572bdcd8170SKalle Valo 		/* use default number of control buffers */
573bdcd8170SKalle Valo 		return -EIO;
574bdcd8170SKalle Valo 
57539586bf2SRyan Hsu 	/* Configure GPIO AR600x UART */
57639586bf2SRyan Hsu 	param = ar->hw.uarttx_pin;
57739586bf2SRyan Hsu 	status = ath6kl_bmi_write(ar,
57839586bf2SRyan Hsu 				ath6kl_get_hi_item_addr(ar,
57939586bf2SRyan Hsu 				HI_ITEM(hi_dbg_uart_txpin)),
58039586bf2SRyan Hsu 				(u8 *)&param, 4);
58139586bf2SRyan Hsu 	if (status)
58239586bf2SRyan Hsu 		return status;
58339586bf2SRyan Hsu 
58439586bf2SRyan Hsu 	/* Configure target refclk_hz */
58539586bf2SRyan Hsu 	param =  ar->hw.refclk_hz;
58639586bf2SRyan Hsu 	status = ath6kl_bmi_write(ar,
58739586bf2SRyan Hsu 				ath6kl_get_hi_item_addr(ar,
58839586bf2SRyan Hsu 				HI_ITEM(hi_refclk_hz)),
58939586bf2SRyan Hsu 				(u8 *)&param, 4);
59039586bf2SRyan Hsu 	if (status)
59139586bf2SRyan Hsu 		return status;
59239586bf2SRyan Hsu 
593bdcd8170SKalle Valo 	return 0;
594bdcd8170SKalle Valo }
595bdcd8170SKalle Valo 
596bdcd8170SKalle Valo /* firmware upload */
597bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
598bdcd8170SKalle Valo 			 u8 **fw, size_t *fw_len)
599bdcd8170SKalle Valo {
600bdcd8170SKalle Valo 	const struct firmware *fw_entry;
601bdcd8170SKalle Valo 	int ret;
602bdcd8170SKalle Valo 
603bdcd8170SKalle Valo 	ret = request_firmware(&fw_entry, filename, ar->dev);
604bdcd8170SKalle Valo 	if (ret)
605bdcd8170SKalle Valo 		return ret;
606bdcd8170SKalle Valo 
607bdcd8170SKalle Valo 	*fw_len = fw_entry->size;
608bdcd8170SKalle Valo 	*fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
609bdcd8170SKalle Valo 
610bdcd8170SKalle Valo 	if (*fw == NULL)
611bdcd8170SKalle Valo 		ret = -ENOMEM;
612bdcd8170SKalle Valo 
613bdcd8170SKalle Valo 	release_firmware(fw_entry);
614bdcd8170SKalle Valo 
615bdcd8170SKalle Valo 	return ret;
616bdcd8170SKalle Valo }
617bdcd8170SKalle Valo 
61892ecbff4SSam Leffler #ifdef CONFIG_OF
61992ecbff4SSam Leffler /*
62092ecbff4SSam Leffler  * Check the device tree for a board-id and use it to construct
62192ecbff4SSam Leffler  * the pathname to the firmware file.  Used (for now) to find a
62292ecbff4SSam Leffler  * fallback to the "bdata.bin" file--typically a symlink to the
62392ecbff4SSam Leffler  * appropriate board-specific file.
62492ecbff4SSam Leffler  */
62592ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar)
62692ecbff4SSam Leffler {
62792ecbff4SSam Leffler 	static const char *board_id_prop = "atheros,board-id";
62892ecbff4SSam Leffler 	struct device_node *node;
62992ecbff4SSam Leffler 	char board_filename[64];
63092ecbff4SSam Leffler 	const char *board_id;
63192ecbff4SSam Leffler 	int ret;
63292ecbff4SSam Leffler 
63392ecbff4SSam Leffler 	for_each_compatible_node(node, NULL, "atheros,ath6kl") {
63492ecbff4SSam Leffler 		board_id = of_get_property(node, board_id_prop, NULL);
63592ecbff4SSam Leffler 		if (board_id == NULL) {
63692ecbff4SSam Leffler 			ath6kl_warn("No \"%s\" property on %s node.\n",
63792ecbff4SSam Leffler 				    board_id_prop, node->name);
63892ecbff4SSam Leffler 			continue;
63992ecbff4SSam Leffler 		}
64092ecbff4SSam Leffler 		snprintf(board_filename, sizeof(board_filename),
641c0038972SKalle Valo 			 "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
64292ecbff4SSam Leffler 
64392ecbff4SSam Leffler 		ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
64492ecbff4SSam Leffler 				    &ar->fw_board_len);
64592ecbff4SSam Leffler 		if (ret) {
64692ecbff4SSam Leffler 			ath6kl_err("Failed to get DT board file %s: %d\n",
64792ecbff4SSam Leffler 				   board_filename, ret);
64892ecbff4SSam Leffler 			continue;
64992ecbff4SSam Leffler 		}
65092ecbff4SSam Leffler 		return true;
65192ecbff4SSam Leffler 	}
65292ecbff4SSam Leffler 	return false;
65392ecbff4SSam Leffler }
65492ecbff4SSam Leffler #else
65592ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar)
65692ecbff4SSam Leffler {
65792ecbff4SSam Leffler 	return false;
65892ecbff4SSam Leffler }
65992ecbff4SSam Leffler #endif /* CONFIG_OF */
66092ecbff4SSam Leffler 
661bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar)
662bdcd8170SKalle Valo {
663bdcd8170SKalle Valo 	const char *filename;
664bdcd8170SKalle Valo 	int ret;
665bdcd8170SKalle Valo 
666772c31eeSKalle Valo 	if (ar->fw_board != NULL)
667772c31eeSKalle Valo 		return 0;
668772c31eeSKalle Valo 
669d1a9421dSKalle Valo 	if (WARN_ON(ar->hw.fw_board == NULL))
670d1a9421dSKalle Valo 		return -EINVAL;
671d1a9421dSKalle Valo 
672d1a9421dSKalle Valo 	filename = ar->hw.fw_board;
673bdcd8170SKalle Valo 
674bdcd8170SKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
675bdcd8170SKalle Valo 			    &ar->fw_board_len);
676bdcd8170SKalle Valo 	if (ret == 0) {
677bdcd8170SKalle Valo 		/* managed to get proper board file */
678bdcd8170SKalle Valo 		return 0;
679bdcd8170SKalle Valo 	}
680bdcd8170SKalle Valo 
68192ecbff4SSam Leffler 	if (check_device_tree(ar)) {
68292ecbff4SSam Leffler 		/* got board file from device tree */
68392ecbff4SSam Leffler 		return 0;
68492ecbff4SSam Leffler 	}
68592ecbff4SSam Leffler 
686bdcd8170SKalle Valo 	/* there was no proper board file, try to use default instead */
687bdcd8170SKalle Valo 	ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
688bdcd8170SKalle Valo 		    filename, ret);
689bdcd8170SKalle Valo 
690d1a9421dSKalle Valo 	filename = ar->hw.fw_default_board;
691bdcd8170SKalle Valo 
692bdcd8170SKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
693bdcd8170SKalle Valo 			    &ar->fw_board_len);
694bdcd8170SKalle Valo 	if (ret) {
695bdcd8170SKalle Valo 		ath6kl_err("Failed to get default board file %s: %d\n",
696bdcd8170SKalle Valo 			   filename, ret);
697bdcd8170SKalle Valo 		return ret;
698bdcd8170SKalle Valo 	}
699bdcd8170SKalle Valo 
700bdcd8170SKalle Valo 	ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
701bdcd8170SKalle Valo 	ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
702bdcd8170SKalle Valo 
703bdcd8170SKalle Valo 	return 0;
704bdcd8170SKalle Valo }
705bdcd8170SKalle Valo 
706772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar)
707772c31eeSKalle Valo {
708c0038972SKalle Valo 	char filename[100];
709772c31eeSKalle Valo 	int ret;
710772c31eeSKalle Valo 
711772c31eeSKalle Valo 	if (ar->fw_otp != NULL)
712772c31eeSKalle Valo 		return 0;
713772c31eeSKalle Valo 
714c0038972SKalle Valo 	if (ar->hw.fw.otp == NULL) {
715d1a9421dSKalle Valo 		ath6kl_dbg(ATH6KL_DBG_BOOT,
716d1a9421dSKalle Valo 			   "no OTP file configured for this hw\n");
717772c31eeSKalle Valo 		return 0;
718772c31eeSKalle Valo 	}
719772c31eeSKalle Valo 
720c0038972SKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s",
721c0038972SKalle Valo 		 ar->hw.fw.dir, ar->hw.fw.otp);
722d1a9421dSKalle Valo 
723772c31eeSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
724772c31eeSKalle Valo 			    &ar->fw_otp_len);
725772c31eeSKalle Valo 	if (ret) {
726772c31eeSKalle Valo 		ath6kl_err("Failed to get OTP file %s: %d\n",
727772c31eeSKalle Valo 			   filename, ret);
728772c31eeSKalle Valo 		return ret;
729772c31eeSKalle Valo 	}
730772c31eeSKalle Valo 
731772c31eeSKalle Valo 	return 0;
732772c31eeSKalle Valo }
733772c31eeSKalle Valo 
734772c31eeSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar)
735772c31eeSKalle Valo {
736c0038972SKalle Valo 	char filename[100];
737772c31eeSKalle Valo 	int ret;
738772c31eeSKalle Valo 
739772c31eeSKalle Valo 	if (ar->fw != NULL)
740772c31eeSKalle Valo 		return 0;
741772c31eeSKalle Valo 
742772c31eeSKalle Valo 	if (testmode) {
743cd23c1c9SAlex Yang 		ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n",
744cd23c1c9SAlex Yang 				testmode);
745cd23c1c9SAlex Yang 		if (testmode == 2) {
746cd23c1c9SAlex Yang 			if (ar->hw.fw.utf == NULL) {
747cd23c1c9SAlex Yang 				ath6kl_warn("testmode 2 not supported\n");
748cd23c1c9SAlex Yang 				return -EOPNOTSUPP;
749cd23c1c9SAlex Yang 			}
750cd23c1c9SAlex Yang 
751cd23c1c9SAlex Yang 			snprintf(filename, sizeof(filename), "%s/%s",
752cd23c1c9SAlex Yang 				ar->hw.fw.dir, ar->hw.fw.utf);
753cd23c1c9SAlex Yang 		} else {
754c0038972SKalle Valo 			if (ar->hw.fw.tcmd == NULL) {
755cd23c1c9SAlex Yang 				ath6kl_warn("testmode 1 not supported\n");
756772c31eeSKalle Valo 				return -EOPNOTSUPP;
757772c31eeSKalle Valo 			}
758772c31eeSKalle Valo 
759c0038972SKalle Valo 			snprintf(filename, sizeof(filename), "%s/%s",
760c0038972SKalle Valo 				ar->hw.fw.dir, ar->hw.fw.tcmd);
761cd23c1c9SAlex Yang 		}
762772c31eeSKalle Valo 		set_bit(TESTMODE, &ar->flag);
763772c31eeSKalle Valo 
764772c31eeSKalle Valo 		goto get_fw;
765772c31eeSKalle Valo 	}
766772c31eeSKalle Valo 
767c0038972SKalle Valo 	/* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
768c0038972SKalle Valo 	if (WARN_ON(ar->hw.fw.fw == NULL))
769d1a9421dSKalle Valo 		return -EINVAL;
770d1a9421dSKalle Valo 
771c0038972SKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s",
772c0038972SKalle Valo 		 ar->hw.fw.dir, ar->hw.fw.fw);
773772c31eeSKalle Valo 
774772c31eeSKalle Valo get_fw:
775772c31eeSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
776772c31eeSKalle Valo 	if (ret) {
777772c31eeSKalle Valo 		ath6kl_err("Failed to get firmware file %s: %d\n",
778772c31eeSKalle Valo 			   filename, ret);
779772c31eeSKalle Valo 		return ret;
780772c31eeSKalle Valo 	}
781772c31eeSKalle Valo 
782772c31eeSKalle Valo 	return 0;
783772c31eeSKalle Valo }
784772c31eeSKalle Valo 
785772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar)
786772c31eeSKalle Valo {
787c0038972SKalle Valo 	char filename[100];
788772c31eeSKalle Valo 	int ret;
789772c31eeSKalle Valo 
790d1a9421dSKalle Valo 	if (ar->fw_patch != NULL)
791772c31eeSKalle Valo 		return 0;
792772c31eeSKalle Valo 
793c0038972SKalle Valo 	if (ar->hw.fw.patch == NULL)
794d1a9421dSKalle Valo 		return 0;
795d1a9421dSKalle Valo 
796c0038972SKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s",
797c0038972SKalle Valo 		 ar->hw.fw.dir, ar->hw.fw.patch);
798d1a9421dSKalle Valo 
799772c31eeSKalle Valo 	ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
800772c31eeSKalle Valo 			    &ar->fw_patch_len);
801772c31eeSKalle Valo 	if (ret) {
802772c31eeSKalle Valo 		ath6kl_err("Failed to get patch file %s: %d\n",
803772c31eeSKalle Valo 			   filename, ret);
804772c31eeSKalle Valo 		return ret;
805772c31eeSKalle Valo 	}
806772c31eeSKalle Valo 
807772c31eeSKalle Valo 	return 0;
808772c31eeSKalle Valo }
809772c31eeSKalle Valo 
810cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
811cd23c1c9SAlex Yang {
812cd23c1c9SAlex Yang 	char filename[100];
813cd23c1c9SAlex Yang 	int ret;
814cd23c1c9SAlex Yang 
815cd23c1c9SAlex Yang 	if (testmode != 2)
816cd23c1c9SAlex Yang 		return 0;
817cd23c1c9SAlex Yang 
818cd23c1c9SAlex Yang 	if (ar->fw_testscript != NULL)
819cd23c1c9SAlex Yang 		return 0;
820cd23c1c9SAlex Yang 
821cd23c1c9SAlex Yang 	if (ar->hw.fw.testscript == NULL)
822cd23c1c9SAlex Yang 		return 0;
823cd23c1c9SAlex Yang 
824cd23c1c9SAlex Yang 	snprintf(filename, sizeof(filename), "%s/%s",
825cd23c1c9SAlex Yang 		ar->hw.fw.dir, ar->hw.fw.testscript);
826cd23c1c9SAlex Yang 
827cd23c1c9SAlex Yang 	ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
828cd23c1c9SAlex Yang 				&ar->fw_testscript_len);
829cd23c1c9SAlex Yang 	if (ret) {
830cd23c1c9SAlex Yang 		ath6kl_err("Failed to get testscript file %s: %d\n",
831cd23c1c9SAlex Yang 			filename, ret);
832cd23c1c9SAlex Yang 		return ret;
833cd23c1c9SAlex Yang 	}
834cd23c1c9SAlex Yang 
835cd23c1c9SAlex Yang 	return 0;
836cd23c1c9SAlex Yang }
837cd23c1c9SAlex Yang 
83850d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
839772c31eeSKalle Valo {
840772c31eeSKalle Valo 	int ret;
841772c31eeSKalle Valo 
842772c31eeSKalle Valo 	ret = ath6kl_fetch_otp_file(ar);
843772c31eeSKalle Valo 	if (ret)
844772c31eeSKalle Valo 		return ret;
845772c31eeSKalle Valo 
846772c31eeSKalle Valo 	ret = ath6kl_fetch_fw_file(ar);
847772c31eeSKalle Valo 	if (ret)
848772c31eeSKalle Valo 		return ret;
849772c31eeSKalle Valo 
850772c31eeSKalle Valo 	ret = ath6kl_fetch_patch_file(ar);
851772c31eeSKalle Valo 	if (ret)
852772c31eeSKalle Valo 		return ret;
853772c31eeSKalle Valo 
854cd23c1c9SAlex Yang 	ret = ath6kl_fetch_testscript_file(ar);
855cd23c1c9SAlex Yang 	if (ret)
856cd23c1c9SAlex Yang 		return ret;
857cd23c1c9SAlex Yang 
858772c31eeSKalle Valo 	return 0;
859772c31eeSKalle Valo }
860bdcd8170SKalle Valo 
86165a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
86250d41234SKalle Valo {
86350d41234SKalle Valo 	size_t magic_len, len, ie_len;
86450d41234SKalle Valo 	const struct firmware *fw;
86550d41234SKalle Valo 	struct ath6kl_fw_ie *hdr;
866c0038972SKalle Valo 	char filename[100];
86750d41234SKalle Valo 	const u8 *data;
86897e0496dSKalle Valo 	int ret, ie_id, i, index, bit;
8698a137480SKalle Valo 	__le32 *val;
87050d41234SKalle Valo 
87165a8b4ccSKalle Valo 	snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
87250d41234SKalle Valo 
87350d41234SKalle Valo 	ret = request_firmware(&fw, filename, ar->dev);
87450d41234SKalle Valo 	if (ret)
87550d41234SKalle Valo 		return ret;
87650d41234SKalle Valo 
87750d41234SKalle Valo 	data = fw->data;
87850d41234SKalle Valo 	len = fw->size;
87950d41234SKalle Valo 
88050d41234SKalle Valo 	/* magic also includes the null byte, check that as well */
88150d41234SKalle Valo 	magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
88250d41234SKalle Valo 
88350d41234SKalle Valo 	if (len < magic_len) {
88450d41234SKalle Valo 		ret = -EINVAL;
88550d41234SKalle Valo 		goto out;
88650d41234SKalle Valo 	}
88750d41234SKalle Valo 
88850d41234SKalle Valo 	if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
88950d41234SKalle Valo 		ret = -EINVAL;
89050d41234SKalle Valo 		goto out;
89150d41234SKalle Valo 	}
89250d41234SKalle Valo 
89350d41234SKalle Valo 	len -= magic_len;
89450d41234SKalle Valo 	data += magic_len;
89550d41234SKalle Valo 
89650d41234SKalle Valo 	/* loop elements */
89750d41234SKalle Valo 	while (len > sizeof(struct ath6kl_fw_ie)) {
89850d41234SKalle Valo 		/* hdr is unaligned! */
89950d41234SKalle Valo 		hdr = (struct ath6kl_fw_ie *) data;
90050d41234SKalle Valo 
90150d41234SKalle Valo 		ie_id = le32_to_cpup(&hdr->id);
90250d41234SKalle Valo 		ie_len = le32_to_cpup(&hdr->len);
90350d41234SKalle Valo 
90450d41234SKalle Valo 		len -= sizeof(*hdr);
90550d41234SKalle Valo 		data += sizeof(*hdr);
90650d41234SKalle Valo 
90750d41234SKalle Valo 		if (len < ie_len) {
90850d41234SKalle Valo 			ret = -EINVAL;
90950d41234SKalle Valo 			goto out;
91050d41234SKalle Valo 		}
91150d41234SKalle Valo 
91250d41234SKalle Valo 		switch (ie_id) {
91350d41234SKalle Valo 		case ATH6KL_FW_IE_OTP_IMAGE:
914ef548626SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
9156bc36431SKalle Valo 				ie_len);
9166bc36431SKalle Valo 
91750d41234SKalle Valo 			ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
91850d41234SKalle Valo 
91950d41234SKalle Valo 			if (ar->fw_otp == NULL) {
92050d41234SKalle Valo 				ret = -ENOMEM;
92150d41234SKalle Valo 				goto out;
92250d41234SKalle Valo 			}
92350d41234SKalle Valo 
92450d41234SKalle Valo 			ar->fw_otp_len = ie_len;
92550d41234SKalle Valo 			break;
92650d41234SKalle Valo 		case ATH6KL_FW_IE_FW_IMAGE:
927ef548626SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
9286bc36431SKalle Valo 				ie_len);
9296bc36431SKalle Valo 
93050d41234SKalle Valo 			ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
93150d41234SKalle Valo 
93250d41234SKalle Valo 			if (ar->fw == NULL) {
93350d41234SKalle Valo 				ret = -ENOMEM;
93450d41234SKalle Valo 				goto out;
93550d41234SKalle Valo 			}
93650d41234SKalle Valo 
93750d41234SKalle Valo 			ar->fw_len = ie_len;
93850d41234SKalle Valo 			break;
93950d41234SKalle Valo 		case ATH6KL_FW_IE_PATCH_IMAGE:
940ef548626SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
9416bc36431SKalle Valo 				ie_len);
9426bc36431SKalle Valo 
94350d41234SKalle Valo 			ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
94450d41234SKalle Valo 
94550d41234SKalle Valo 			if (ar->fw_patch == NULL) {
94650d41234SKalle Valo 				ret = -ENOMEM;
94750d41234SKalle Valo 				goto out;
94850d41234SKalle Valo 			}
94950d41234SKalle Valo 
95050d41234SKalle Valo 			ar->fw_patch_len = ie_len;
95150d41234SKalle Valo 			break;
9528a137480SKalle Valo 		case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
9538a137480SKalle Valo 			val = (__le32 *) data;
9548a137480SKalle Valo 			ar->hw.reserved_ram_size = le32_to_cpup(val);
9556bc36431SKalle Valo 
9566bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
9576bc36431SKalle Valo 				   "found reserved ram size ie 0x%d\n",
9586bc36431SKalle Valo 				   ar->hw.reserved_ram_size);
9598a137480SKalle Valo 			break;
96097e0496dSKalle Valo 		case ATH6KL_FW_IE_CAPABILITIES:
961277d90f4SKalle Valo 			if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
962277d90f4SKalle Valo 				break;
963277d90f4SKalle Valo 
9646bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
965ef548626SKalle Valo 				   "found firmware capabilities ie (%zd B)\n",
9666bc36431SKalle Valo 				   ie_len);
9676bc36431SKalle Valo 
96897e0496dSKalle Valo 			for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
969277d90f4SKalle Valo 				index = i / 8;
97097e0496dSKalle Valo 				bit = i % 8;
97197e0496dSKalle Valo 
97297e0496dSKalle Valo 				if (data[index] & (1 << bit))
97397e0496dSKalle Valo 					__set_bit(i, ar->fw_capabilities);
97497e0496dSKalle Valo 			}
9756bc36431SKalle Valo 
9766bc36431SKalle Valo 			ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
9776bc36431SKalle Valo 					ar->fw_capabilities,
9786bc36431SKalle Valo 					sizeof(ar->fw_capabilities));
97997e0496dSKalle Valo 			break;
9801b4304daSKalle Valo 		case ATH6KL_FW_IE_PATCH_ADDR:
9811b4304daSKalle Valo 			if (ie_len != sizeof(*val))
9821b4304daSKalle Valo 				break;
9831b4304daSKalle Valo 
9841b4304daSKalle Valo 			val = (__le32 *) data;
9851b4304daSKalle Valo 			ar->hw.dataset_patch_addr = le32_to_cpup(val);
9866bc36431SKalle Valo 
9876bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
98803ef0250SKalle Valo 				   "found patch address ie 0x%x\n",
9896bc36431SKalle Valo 				   ar->hw.dataset_patch_addr);
9901b4304daSKalle Valo 			break;
99103ef0250SKalle Valo 		case ATH6KL_FW_IE_BOARD_ADDR:
99203ef0250SKalle Valo 			if (ie_len != sizeof(*val))
99303ef0250SKalle Valo 				break;
99403ef0250SKalle Valo 
99503ef0250SKalle Valo 			val = (__le32 *) data;
99603ef0250SKalle Valo 			ar->hw.board_addr = le32_to_cpup(val);
99703ef0250SKalle Valo 
99803ef0250SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
99903ef0250SKalle Valo 				   "found board address ie 0x%x\n",
100003ef0250SKalle Valo 				   ar->hw.board_addr);
100103ef0250SKalle Valo 			break;
1002368b1b0fSKalle Valo 		case ATH6KL_FW_IE_VIF_MAX:
1003368b1b0fSKalle Valo 			if (ie_len != sizeof(*val))
1004368b1b0fSKalle Valo 				break;
1005368b1b0fSKalle Valo 
1006368b1b0fSKalle Valo 			val = (__le32 *) data;
1007368b1b0fSKalle Valo 			ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
1008368b1b0fSKalle Valo 					    ATH6KL_VIF_MAX);
1009368b1b0fSKalle Valo 
1010f143379dSVasanthakumar Thiagarajan 			if (ar->vif_max > 1 && !ar->p2p)
1011f143379dSVasanthakumar Thiagarajan 				ar->max_norm_iface = 2;
1012f143379dSVasanthakumar Thiagarajan 
1013368b1b0fSKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT,
1014368b1b0fSKalle Valo 				   "found vif max ie %d\n", ar->vif_max);
1015368b1b0fSKalle Valo 			break;
101650d41234SKalle Valo 		default:
10176bc36431SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
101850d41234SKalle Valo 				   le32_to_cpup(&hdr->id));
101950d41234SKalle Valo 			break;
102050d41234SKalle Valo 		}
102150d41234SKalle Valo 
102250d41234SKalle Valo 		len -= ie_len;
102350d41234SKalle Valo 		data += ie_len;
102450d41234SKalle Valo 	};
102550d41234SKalle Valo 
102650d41234SKalle Valo 	ret = 0;
102750d41234SKalle Valo out:
102850d41234SKalle Valo 	release_firmware(fw);
102950d41234SKalle Valo 
103050d41234SKalle Valo 	return ret;
103150d41234SKalle Valo }
103250d41234SKalle Valo 
103345eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
103450d41234SKalle Valo {
103550d41234SKalle Valo 	int ret;
103650d41234SKalle Valo 
103750d41234SKalle Valo 	ret = ath6kl_fetch_board_file(ar);
103850d41234SKalle Valo 	if (ret)
103950d41234SKalle Valo 		return ret;
104050d41234SKalle Valo 
104165a8b4ccSKalle Valo 	ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
10426bc36431SKalle Valo 	if (ret == 0) {
104365a8b4ccSKalle Valo 		ar->fw_api = 3;
104465a8b4ccSKalle Valo 		goto out;
104565a8b4ccSKalle Valo 	}
104665a8b4ccSKalle Valo 
104765a8b4ccSKalle Valo 	ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
104865a8b4ccSKalle Valo 	if (ret == 0) {
104965a8b4ccSKalle Valo 		ar->fw_api = 2;
105065a8b4ccSKalle Valo 		goto out;
10516bc36431SKalle Valo 	}
105250d41234SKalle Valo 
105350d41234SKalle Valo 	ret = ath6kl_fetch_fw_api1(ar);
105450d41234SKalle Valo 	if (ret)
105550d41234SKalle Valo 		return ret;
105650d41234SKalle Valo 
105765a8b4ccSKalle Valo 	ar->fw_api = 1;
105865a8b4ccSKalle Valo 
105965a8b4ccSKalle Valo out:
106065a8b4ccSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
10616bc36431SKalle Valo 
106250d41234SKalle Valo 	return 0;
106350d41234SKalle Valo }
106450d41234SKalle Valo 
1065bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar)
1066bdcd8170SKalle Valo {
1067bdcd8170SKalle Valo 	u32 board_address, board_ext_address, param;
106831024d99SKevin Fang 	u32 board_data_size, board_ext_data_size;
1069bdcd8170SKalle Valo 	int ret;
1070bdcd8170SKalle Valo 
1071772c31eeSKalle Valo 	if (WARN_ON(ar->fw_board == NULL))
1072772c31eeSKalle Valo 		return -ENOENT;
1073bdcd8170SKalle Valo 
107431024d99SKevin Fang 	/*
107531024d99SKevin Fang 	 * Determine where in Target RAM to write Board Data.
107631024d99SKevin Fang 	 * For AR6004, host determine Target RAM address for
107731024d99SKevin Fang 	 * writing board data.
107831024d99SKevin Fang 	 */
10790d4d72bfSKalle Valo 	if (ar->hw.board_addr != 0) {
10800d4d72bfSKalle Valo 		board_address = ar->hw.board_addr;
108131024d99SKevin Fang 		ath6kl_bmi_write(ar,
108231024d99SKevin Fang 				ath6kl_get_hi_item_addr(ar,
108331024d99SKevin Fang 				HI_ITEM(hi_board_data)),
108431024d99SKevin Fang 				(u8 *) &board_address, 4);
108531024d99SKevin Fang 	} else {
1086bdcd8170SKalle Valo 		ath6kl_bmi_read(ar,
1087bdcd8170SKalle Valo 				ath6kl_get_hi_item_addr(ar,
1088bdcd8170SKalle Valo 				HI_ITEM(hi_board_data)),
1089bdcd8170SKalle Valo 				(u8 *) &board_address, 4);
109031024d99SKevin Fang 	}
109131024d99SKevin Fang 
1092bdcd8170SKalle Valo 	/* determine where in target ram to write extended board data */
1093bdcd8170SKalle Valo 	ath6kl_bmi_read(ar,
1094bdcd8170SKalle Valo 			ath6kl_get_hi_item_addr(ar,
1095bdcd8170SKalle Valo 			HI_ITEM(hi_board_ext_data)),
1096bdcd8170SKalle Valo 			(u8 *) &board_ext_address, 4);
1097bdcd8170SKalle Valo 
109850e2740bSKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003 &&
109950e2740bSKalle Valo 	    board_ext_address == 0) {
1100bdcd8170SKalle Valo 		ath6kl_err("Failed to get board file target address.\n");
1101bdcd8170SKalle Valo 		return -EINVAL;
1102bdcd8170SKalle Valo 	}
1103bdcd8170SKalle Valo 
110431024d99SKevin Fang 	switch (ar->target_type) {
110531024d99SKevin Fang 	case TARGET_TYPE_AR6003:
110631024d99SKevin Fang 		board_data_size = AR6003_BOARD_DATA_SZ;
110731024d99SKevin Fang 		board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
110831024d99SKevin Fang 		break;
110931024d99SKevin Fang 	case TARGET_TYPE_AR6004:
111031024d99SKevin Fang 		board_data_size = AR6004_BOARD_DATA_SZ;
111131024d99SKevin Fang 		board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
111231024d99SKevin Fang 		break;
111331024d99SKevin Fang 	default:
111431024d99SKevin Fang 		WARN_ON(1);
111531024d99SKevin Fang 		return -EINVAL;
111631024d99SKevin Fang 		break;
111731024d99SKevin Fang 	}
111831024d99SKevin Fang 
111950e2740bSKalle Valo 	if (board_ext_address &&
112050e2740bSKalle Valo 	    ar->fw_board_len == (board_data_size + board_ext_data_size)) {
112131024d99SKevin Fang 
1122bdcd8170SKalle Valo 		/* write extended board data */
11236bc36431SKalle Valo 		ath6kl_dbg(ATH6KL_DBG_BOOT,
11246bc36431SKalle Valo 			   "writing extended board data to 0x%x (%d B)\n",
11256bc36431SKalle Valo 			   board_ext_address, board_ext_data_size);
11266bc36431SKalle Valo 
1127bdcd8170SKalle Valo 		ret = ath6kl_bmi_write(ar, board_ext_address,
112831024d99SKevin Fang 				       ar->fw_board + board_data_size,
112931024d99SKevin Fang 				       board_ext_data_size);
1130bdcd8170SKalle Valo 		if (ret) {
1131bdcd8170SKalle Valo 			ath6kl_err("Failed to write extended board data: %d\n",
1132bdcd8170SKalle Valo 				   ret);
1133bdcd8170SKalle Valo 			return ret;
1134bdcd8170SKalle Valo 		}
1135bdcd8170SKalle Valo 
1136bdcd8170SKalle Valo 		/* record that extended board data is initialized */
113731024d99SKevin Fang 		param = (board_ext_data_size << 16) | 1;
113831024d99SKevin Fang 
1139bdcd8170SKalle Valo 		ath6kl_bmi_write(ar,
1140bdcd8170SKalle Valo 				 ath6kl_get_hi_item_addr(ar,
1141bdcd8170SKalle Valo 				 HI_ITEM(hi_board_ext_data_config)),
1142bdcd8170SKalle Valo 				 (unsigned char *) &param, 4);
1143bdcd8170SKalle Valo 	}
1144bdcd8170SKalle Valo 
114531024d99SKevin Fang 	if (ar->fw_board_len < board_data_size) {
1146bdcd8170SKalle Valo 		ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
1147bdcd8170SKalle Valo 		ret = -EINVAL;
1148bdcd8170SKalle Valo 		return ret;
1149bdcd8170SKalle Valo 	}
1150bdcd8170SKalle Valo 
11516bc36431SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
11526bc36431SKalle Valo 		   board_address, board_data_size);
11536bc36431SKalle Valo 
1154bdcd8170SKalle Valo 	ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
115531024d99SKevin Fang 			       board_data_size);
1156bdcd8170SKalle Valo 
1157bdcd8170SKalle Valo 	if (ret) {
1158bdcd8170SKalle Valo 		ath6kl_err("Board file bmi write failed: %d\n", ret);
1159bdcd8170SKalle Valo 		return ret;
1160bdcd8170SKalle Valo 	}
1161bdcd8170SKalle Valo 
1162bdcd8170SKalle Valo 	/* record the fact that Board Data IS initialized */
1163bdcd8170SKalle Valo 	param = 1;
1164bdcd8170SKalle Valo 	ath6kl_bmi_write(ar,
1165bdcd8170SKalle Valo 			 ath6kl_get_hi_item_addr(ar,
1166bdcd8170SKalle Valo 			 HI_ITEM(hi_board_data_initialized)),
1167bdcd8170SKalle Valo 			 (u8 *)&param, 4);
1168bdcd8170SKalle Valo 
1169bdcd8170SKalle Valo 	return ret;
1170bdcd8170SKalle Valo }
1171bdcd8170SKalle Valo 
1172bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar)
1173bdcd8170SKalle Valo {
1174bdcd8170SKalle Valo 	u32 address, param;
1175bef26a7fSKalle Valo 	bool from_hw = false;
1176bdcd8170SKalle Valo 	int ret;
1177bdcd8170SKalle Valo 
117850e2740bSKalle Valo 	if (ar->fw_otp == NULL)
117950e2740bSKalle Valo 		return 0;
1180bdcd8170SKalle Valo 
1181a01ac414SKalle Valo 	address = ar->hw.app_load_addr;
1182bdcd8170SKalle Valo 
1183ef548626SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
11846bc36431SKalle Valo 		   ar->fw_otp_len);
11856bc36431SKalle Valo 
1186bdcd8170SKalle Valo 	ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
1187bdcd8170SKalle Valo 				       ar->fw_otp_len);
1188bdcd8170SKalle Valo 	if (ret) {
1189bdcd8170SKalle Valo 		ath6kl_err("Failed to upload OTP file: %d\n", ret);
1190bdcd8170SKalle Valo 		return ret;
1191bdcd8170SKalle Valo 	}
1192bdcd8170SKalle Valo 
1193639d0b89SKalle Valo 	/* read firmware start address */
1194639d0b89SKalle Valo 	ret = ath6kl_bmi_read(ar,
1195639d0b89SKalle Valo 			      ath6kl_get_hi_item_addr(ar,
1196639d0b89SKalle Valo 						      HI_ITEM(hi_app_start)),
1197639d0b89SKalle Valo 			      (u8 *) &address, sizeof(address));
1198639d0b89SKalle Valo 
1199639d0b89SKalle Valo 	if (ret) {
1200639d0b89SKalle Valo 		ath6kl_err("Failed to read hi_app_start: %d\n", ret);
1201639d0b89SKalle Valo 		return ret;
1202639d0b89SKalle Valo 	}
1203639d0b89SKalle Valo 
1204bef26a7fSKalle Valo 	if (ar->hw.app_start_override_addr == 0) {
1205639d0b89SKalle Valo 		ar->hw.app_start_override_addr = address;
1206bef26a7fSKalle Valo 		from_hw = true;
1207bef26a7fSKalle Valo 	}
1208639d0b89SKalle Valo 
1209bef26a7fSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
1210bef26a7fSKalle Valo 		   from_hw ? " (from hw)" : "",
12116bc36431SKalle Valo 		   ar->hw.app_start_override_addr);
12126bc36431SKalle Valo 
1213bdcd8170SKalle Valo 	/* execute the OTP code */
1214bef26a7fSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
1215bef26a7fSKalle Valo 		   ar->hw.app_start_override_addr);
1216bdcd8170SKalle Valo 	param = 0;
1217bef26a7fSKalle Valo 	ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
1218bdcd8170SKalle Valo 
1219bdcd8170SKalle Valo 	return ret;
1220bdcd8170SKalle Valo }
1221bdcd8170SKalle Valo 
1222bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar)
1223bdcd8170SKalle Valo {
1224bdcd8170SKalle Valo 	u32 address;
1225bdcd8170SKalle Valo 	int ret;
1226bdcd8170SKalle Valo 
1227772c31eeSKalle Valo 	if (WARN_ON(ar->fw == NULL))
122850e2740bSKalle Valo 		return 0;
1229bdcd8170SKalle Valo 
1230a01ac414SKalle Valo 	address = ar->hw.app_load_addr;
1231bdcd8170SKalle Valo 
1232ef548626SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
12336bc36431SKalle Valo 		   address, ar->fw_len);
12346bc36431SKalle Valo 
1235bdcd8170SKalle Valo 	ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
1236bdcd8170SKalle Valo 
1237bdcd8170SKalle Valo 	if (ret) {
1238bdcd8170SKalle Valo 		ath6kl_err("Failed to write firmware: %d\n", ret);
1239bdcd8170SKalle Valo 		return ret;
1240bdcd8170SKalle Valo 	}
1241bdcd8170SKalle Valo 
124231024d99SKevin Fang 	/*
124331024d99SKevin Fang 	 * Set starting address for firmware
124431024d99SKevin Fang 	 * Don't need to setup app_start override addr on AR6004
124531024d99SKevin Fang 	 */
124631024d99SKevin Fang 	if (ar->target_type != TARGET_TYPE_AR6004) {
1247a01ac414SKalle Valo 		address = ar->hw.app_start_override_addr;
1248bdcd8170SKalle Valo 		ath6kl_bmi_set_app_start(ar, address);
124931024d99SKevin Fang 	}
1250bdcd8170SKalle Valo 	return ret;
1251bdcd8170SKalle Valo }
1252bdcd8170SKalle Valo 
1253bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar)
1254bdcd8170SKalle Valo {
1255bdcd8170SKalle Valo 	u32 address, param;
1256bdcd8170SKalle Valo 	int ret;
1257bdcd8170SKalle Valo 
125850e2740bSKalle Valo 	if (ar->fw_patch == NULL)
125950e2740bSKalle Valo 		return 0;
1260bdcd8170SKalle Valo 
1261a01ac414SKalle Valo 	address = ar->hw.dataset_patch_addr;
1262bdcd8170SKalle Valo 
1263ef548626SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
12646bc36431SKalle Valo 		   address, ar->fw_patch_len);
12656bc36431SKalle Valo 
1266bdcd8170SKalle Valo 	ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
1267bdcd8170SKalle Valo 	if (ret) {
1268bdcd8170SKalle Valo 		ath6kl_err("Failed to write patch file: %d\n", ret);
1269bdcd8170SKalle Valo 		return ret;
1270bdcd8170SKalle Valo 	}
1271bdcd8170SKalle Valo 
1272bdcd8170SKalle Valo 	param = address;
1273bdcd8170SKalle Valo 	ath6kl_bmi_write(ar,
1274bdcd8170SKalle Valo 			 ath6kl_get_hi_item_addr(ar,
1275bdcd8170SKalle Valo 			 HI_ITEM(hi_dset_list_head)),
1276bdcd8170SKalle Valo 			 (unsigned char *) &param, 4);
1277bdcd8170SKalle Valo 
1278bdcd8170SKalle Valo 	return 0;
1279bdcd8170SKalle Valo }
1280bdcd8170SKalle Valo 
1281cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar)
1282cd23c1c9SAlex Yang {
1283cd23c1c9SAlex Yang 	u32 address, param;
1284cd23c1c9SAlex Yang 	int ret;
1285cd23c1c9SAlex Yang 
1286cd23c1c9SAlex Yang 	if (testmode != 2)
1287cd23c1c9SAlex Yang 		return 0;
1288cd23c1c9SAlex Yang 
1289cd23c1c9SAlex Yang 	if (ar->fw_testscript == NULL)
1290cd23c1c9SAlex Yang 		return 0;
1291cd23c1c9SAlex Yang 
1292cd23c1c9SAlex Yang 	address = ar->hw.testscript_addr;
1293cd23c1c9SAlex Yang 
1294cd23c1c9SAlex Yang 	ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
1295cd23c1c9SAlex Yang 		address, ar->fw_testscript_len);
1296cd23c1c9SAlex Yang 
1297cd23c1c9SAlex Yang 	ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
1298cd23c1c9SAlex Yang 		ar->fw_testscript_len);
1299cd23c1c9SAlex Yang 	if (ret) {
1300cd23c1c9SAlex Yang 		ath6kl_err("Failed to write testscript file: %d\n", ret);
1301cd23c1c9SAlex Yang 		return ret;
1302cd23c1c9SAlex Yang 	}
1303cd23c1c9SAlex Yang 
1304cd23c1c9SAlex Yang 	param = address;
1305cd23c1c9SAlex Yang 	ath6kl_bmi_write(ar,
1306cd23c1c9SAlex Yang 			ath6kl_get_hi_item_addr(ar,
1307cd23c1c9SAlex Yang 			HI_ITEM(hi_ota_testscript)),
1308cd23c1c9SAlex Yang 			(unsigned char *) &param, 4);
1309cd23c1c9SAlex Yang 
1310cd23c1c9SAlex Yang 	param = 4096;
1311cd23c1c9SAlex Yang 	ath6kl_bmi_write(ar,
1312cd23c1c9SAlex Yang 			ath6kl_get_hi_item_addr(ar,
1313cd23c1c9SAlex Yang 			HI_ITEM(hi_end_ram_reserve_sz)),
1314cd23c1c9SAlex Yang 			(unsigned char *) &param, 4);
1315cd23c1c9SAlex Yang 
1316cd23c1c9SAlex Yang 	param = 1;
1317cd23c1c9SAlex Yang 	ath6kl_bmi_write(ar,
1318cd23c1c9SAlex Yang 			ath6kl_get_hi_item_addr(ar,
1319cd23c1c9SAlex Yang 			HI_ITEM(hi_test_apps_related)),
1320cd23c1c9SAlex Yang 			(unsigned char *) &param, 4);
1321cd23c1c9SAlex Yang 
1322cd23c1c9SAlex Yang 	return 0;
1323cd23c1c9SAlex Yang }
1324cd23c1c9SAlex Yang 
1325bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar)
1326bdcd8170SKalle Valo {
1327bdcd8170SKalle Valo 	u32 param, options, sleep, address;
1328bdcd8170SKalle Valo 	int status = 0;
1329bdcd8170SKalle Valo 
133031024d99SKevin Fang 	if (ar->target_type != TARGET_TYPE_AR6003 &&
133131024d99SKevin Fang 		ar->target_type != TARGET_TYPE_AR6004)
1332bdcd8170SKalle Valo 		return -EINVAL;
1333bdcd8170SKalle Valo 
1334bdcd8170SKalle Valo 	/* temporarily disable system sleep */
1335bdcd8170SKalle Valo 	address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1336bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_read(ar, address, &param);
1337bdcd8170SKalle Valo 	if (status)
1338bdcd8170SKalle Valo 		return status;
1339bdcd8170SKalle Valo 
1340bdcd8170SKalle Valo 	options = param;
1341bdcd8170SKalle Valo 
1342bdcd8170SKalle Valo 	param |= ATH6KL_OPTION_SLEEP_DISABLE;
1343bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1344bdcd8170SKalle Valo 	if (status)
1345bdcd8170SKalle Valo 		return status;
1346bdcd8170SKalle Valo 
1347bdcd8170SKalle Valo 	address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1348bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_read(ar, address, &param);
1349bdcd8170SKalle Valo 	if (status)
1350bdcd8170SKalle Valo 		return status;
1351bdcd8170SKalle Valo 
1352bdcd8170SKalle Valo 	sleep = param;
1353bdcd8170SKalle Valo 
1354bdcd8170SKalle Valo 	param |= SM(SYSTEM_SLEEP_DISABLE, 1);
1355bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1356bdcd8170SKalle Valo 	if (status)
1357bdcd8170SKalle Valo 		return status;
1358bdcd8170SKalle Valo 
1359bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
1360bdcd8170SKalle Valo 		   options, sleep);
1361bdcd8170SKalle Valo 
1362bdcd8170SKalle Valo 	/* program analog PLL register */
136331024d99SKevin Fang 	/* no need to control 40/44MHz clock on AR6004 */
136431024d99SKevin Fang 	if (ar->target_type != TARGET_TYPE_AR6004) {
1365bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
1366bdcd8170SKalle Valo 					      0xF9104001);
136731024d99SKevin Fang 
1368bdcd8170SKalle Valo 		if (status)
1369bdcd8170SKalle Valo 			return status;
1370bdcd8170SKalle Valo 
1371bdcd8170SKalle Valo 		/* Run at 80/88MHz by default */
1372bdcd8170SKalle Valo 		param = SM(CPU_CLOCK_STANDARD, 1);
1373bdcd8170SKalle Valo 
1374bdcd8170SKalle Valo 		address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
1375bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1376bdcd8170SKalle Valo 		if (status)
1377bdcd8170SKalle Valo 			return status;
137831024d99SKevin Fang 	}
1379bdcd8170SKalle Valo 
1380bdcd8170SKalle Valo 	param = 0;
1381bdcd8170SKalle Valo 	address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
1382bdcd8170SKalle Valo 	param = SM(LPO_CAL_ENABLE, 1);
1383bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1384bdcd8170SKalle Valo 	if (status)
1385bdcd8170SKalle Valo 		return status;
1386bdcd8170SKalle Valo 
1387bdcd8170SKalle Valo 	/* WAR to avoid SDIO CRC err */
13880d0192baSKalle Valo 	if (ar->version.target_ver == AR6003_HW_2_0_VERSION) {
1389bdcd8170SKalle Valo 		ath6kl_err("temporary war to avoid sdio crc error\n");
1390bdcd8170SKalle Valo 
1391bdcd8170SKalle Valo 		param = 0x20;
1392bdcd8170SKalle Valo 
1393bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
1394bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1395bdcd8170SKalle Valo 		if (status)
1396bdcd8170SKalle Valo 			return status;
1397bdcd8170SKalle Valo 
1398bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
1399bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1400bdcd8170SKalle Valo 		if (status)
1401bdcd8170SKalle Valo 			return status;
1402bdcd8170SKalle Valo 
1403bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
1404bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1405bdcd8170SKalle Valo 		if (status)
1406bdcd8170SKalle Valo 			return status;
1407bdcd8170SKalle Valo 
1408bdcd8170SKalle Valo 		address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
1409bdcd8170SKalle Valo 		status = ath6kl_bmi_reg_write(ar, address, param);
1410bdcd8170SKalle Valo 		if (status)
1411bdcd8170SKalle Valo 			return status;
1412bdcd8170SKalle Valo 	}
1413bdcd8170SKalle Valo 
1414bdcd8170SKalle Valo 	/* write EEPROM data to Target RAM */
1415bdcd8170SKalle Valo 	status = ath6kl_upload_board_file(ar);
1416bdcd8170SKalle Valo 	if (status)
1417bdcd8170SKalle Valo 		return status;
1418bdcd8170SKalle Valo 
1419bdcd8170SKalle Valo 	/* transfer One time Programmable data */
1420bdcd8170SKalle Valo 	status = ath6kl_upload_otp(ar);
1421bdcd8170SKalle Valo 	if (status)
1422bdcd8170SKalle Valo 		return status;
1423bdcd8170SKalle Valo 
1424bdcd8170SKalle Valo 	/* Download Target firmware */
1425bdcd8170SKalle Valo 	status = ath6kl_upload_firmware(ar);
1426bdcd8170SKalle Valo 	if (status)
1427bdcd8170SKalle Valo 		return status;
1428bdcd8170SKalle Valo 
1429bdcd8170SKalle Valo 	status = ath6kl_upload_patch(ar);
1430bdcd8170SKalle Valo 	if (status)
1431bdcd8170SKalle Valo 		return status;
1432bdcd8170SKalle Valo 
1433cd23c1c9SAlex Yang 	/* Download the test script */
1434cd23c1c9SAlex Yang 	status = ath6kl_upload_testscript(ar);
1435cd23c1c9SAlex Yang 	if (status)
1436cd23c1c9SAlex Yang 		return status;
1437cd23c1c9SAlex Yang 
1438bdcd8170SKalle Valo 	/* Restore system sleep */
1439bdcd8170SKalle Valo 	address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1440bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, sleep);
1441bdcd8170SKalle Valo 	if (status)
1442bdcd8170SKalle Valo 		return status;
1443bdcd8170SKalle Valo 
1444bdcd8170SKalle Valo 	address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1445bdcd8170SKalle Valo 	param = options | 0x20;
1446bdcd8170SKalle Valo 	status = ath6kl_bmi_reg_write(ar, address, param);
1447bdcd8170SKalle Valo 	if (status)
1448bdcd8170SKalle Valo 		return status;
1449bdcd8170SKalle Valo 
1450bdcd8170SKalle Valo 	return status;
1451bdcd8170SKalle Valo }
1452bdcd8170SKalle Valo 
145345eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar)
1454a01ac414SKalle Valo {
1455856f4b31SKalle Valo 	const struct ath6kl_hw *hw;
1456856f4b31SKalle Valo 	int i;
1457bef26a7fSKalle Valo 
1458856f4b31SKalle Valo 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
1459856f4b31SKalle Valo 		hw = &hw_list[i];
1460bef26a7fSKalle Valo 
1461856f4b31SKalle Valo 		if (hw->id == ar->version.target_ver)
1462a01ac414SKalle Valo 			break;
1463856f4b31SKalle Valo 	}
1464856f4b31SKalle Valo 
1465856f4b31SKalle Valo 	if (i == ARRAY_SIZE(hw_list)) {
1466a01ac414SKalle Valo 		ath6kl_err("Unsupported hardware version: 0x%x\n",
1467a01ac414SKalle Valo 			   ar->version.target_ver);
1468a01ac414SKalle Valo 		return -EINVAL;
1469a01ac414SKalle Valo 	}
1470a01ac414SKalle Valo 
1471856f4b31SKalle Valo 	ar->hw = *hw;
1472856f4b31SKalle Valo 
14736bc36431SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT,
14746bc36431SKalle Valo 		   "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
14756bc36431SKalle Valo 		   ar->version.target_ver, ar->target_type,
14766bc36431SKalle Valo 		   ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
14776bc36431SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT,
14786bc36431SKalle Valo 		   "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
14796bc36431SKalle Valo 		   ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
14806bc36431SKalle Valo 		   ar->hw.reserved_ram_size);
148139586bf2SRyan Hsu 	ath6kl_dbg(ATH6KL_DBG_BOOT,
148239586bf2SRyan Hsu 		   "refclk_hz %d uarttx_pin %d",
148339586bf2SRyan Hsu 		   ar->hw.refclk_hz, ar->hw.uarttx_pin);
14846bc36431SKalle Valo 
1485a01ac414SKalle Valo 	return 0;
1486a01ac414SKalle Valo }
1487a01ac414SKalle Valo 
1488293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
1489293badf4SKalle Valo {
1490293badf4SKalle Valo 	switch (type) {
1491293badf4SKalle Valo 	case ATH6KL_HIF_TYPE_SDIO:
1492293badf4SKalle Valo 		return "sdio";
1493293badf4SKalle Valo 	case ATH6KL_HIF_TYPE_USB:
1494293badf4SKalle Valo 		return "usb";
1495293badf4SKalle Valo 	}
1496293badf4SKalle Valo 
1497293badf4SKalle Valo 	return NULL;
1498293badf4SKalle Valo }
1499293badf4SKalle Valo 
15005fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar)
150120459ee2SKalle Valo {
150220459ee2SKalle Valo 	long timeleft;
150320459ee2SKalle Valo 	int ret, i;
150420459ee2SKalle Valo 
15055fe4dffbSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
15065fe4dffbSKalle Valo 
150720459ee2SKalle Valo 	ret = ath6kl_hif_power_on(ar);
150820459ee2SKalle Valo 	if (ret)
150920459ee2SKalle Valo 		return ret;
151020459ee2SKalle Valo 
151120459ee2SKalle Valo 	ret = ath6kl_configure_target(ar);
151220459ee2SKalle Valo 	if (ret)
151320459ee2SKalle Valo 		goto err_power_off;
151420459ee2SKalle Valo 
151520459ee2SKalle Valo 	ret = ath6kl_init_upload(ar);
151620459ee2SKalle Valo 	if (ret)
151720459ee2SKalle Valo 		goto err_power_off;
151820459ee2SKalle Valo 
151920459ee2SKalle Valo 	/* Do we need to finish the BMI phase */
152020459ee2SKalle Valo 	/* FIXME: return error from ath6kl_bmi_done() */
152120459ee2SKalle Valo 	if (ath6kl_bmi_done(ar)) {
152220459ee2SKalle Valo 		ret = -EIO;
152320459ee2SKalle Valo 		goto err_power_off;
152420459ee2SKalle Valo 	}
152520459ee2SKalle Valo 
152620459ee2SKalle Valo 	/*
152720459ee2SKalle Valo 	 * The reason we have to wait for the target here is that the
152820459ee2SKalle Valo 	 * driver layer has to init BMI in order to set the host block
152920459ee2SKalle Valo 	 * size.
153020459ee2SKalle Valo 	 */
153120459ee2SKalle Valo 	if (ath6kl_htc_wait_target(ar->htc_target)) {
153220459ee2SKalle Valo 		ret = -EIO;
153320459ee2SKalle Valo 		goto err_power_off;
153420459ee2SKalle Valo 	}
153520459ee2SKalle Valo 
153620459ee2SKalle Valo 	if (ath6kl_init_service_ep(ar)) {
153720459ee2SKalle Valo 		ret = -EIO;
153820459ee2SKalle Valo 		goto err_cleanup_scatter;
153920459ee2SKalle Valo 	}
154020459ee2SKalle Valo 
154120459ee2SKalle Valo 	/* setup credit distribution */
154220459ee2SKalle Valo 	ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
154320459ee2SKalle Valo 
154420459ee2SKalle Valo 	/* start HTC */
154520459ee2SKalle Valo 	ret = ath6kl_htc_start(ar->htc_target);
154620459ee2SKalle Valo 	if (ret) {
154720459ee2SKalle Valo 		/* FIXME: call this */
154820459ee2SKalle Valo 		ath6kl_cookie_cleanup(ar);
154920459ee2SKalle Valo 		goto err_cleanup_scatter;
155020459ee2SKalle Valo 	}
155120459ee2SKalle Valo 
155220459ee2SKalle Valo 	/* Wait for Wmi event to be ready */
155320459ee2SKalle Valo 	timeleft = wait_event_interruptible_timeout(ar->event_wq,
155420459ee2SKalle Valo 						    test_bit(WMI_READY,
155520459ee2SKalle Valo 							     &ar->flag),
155620459ee2SKalle Valo 						    WMI_TIMEOUT);
155720459ee2SKalle Valo 
155820459ee2SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
155920459ee2SKalle Valo 
1560293badf4SKalle Valo 
1561293badf4SKalle Valo 	if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
156265a8b4ccSKalle Valo 		ath6kl_info("%s %s fw %s api %d%s\n",
1563293badf4SKalle Valo 			    ar->hw.name,
1564293badf4SKalle Valo 			    ath6kl_init_get_hif_name(ar->hif_type),
1565293badf4SKalle Valo 			    ar->wiphy->fw_version,
156665a8b4ccSKalle Valo 			    ar->fw_api,
1567293badf4SKalle Valo 			    test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
1568293badf4SKalle Valo 	}
1569293badf4SKalle Valo 
157020459ee2SKalle Valo 	if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
157120459ee2SKalle Valo 		ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
157220459ee2SKalle Valo 			   ATH6KL_ABI_VERSION, ar->version.abi_ver);
157320459ee2SKalle Valo 		ret = -EIO;
157420459ee2SKalle Valo 		goto err_htc_stop;
157520459ee2SKalle Valo 	}
157620459ee2SKalle Valo 
157720459ee2SKalle Valo 	if (!timeleft || signal_pending(current)) {
157820459ee2SKalle Valo 		ath6kl_err("wmi is not ready or wait was interrupted\n");
157920459ee2SKalle Valo 		ret = -EIO;
158020459ee2SKalle Valo 		goto err_htc_stop;
158120459ee2SKalle Valo 	}
158220459ee2SKalle Valo 
158320459ee2SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
158420459ee2SKalle Valo 
158520459ee2SKalle Valo 	/* communicate the wmi protocol verision to the target */
158620459ee2SKalle Valo 	/* FIXME: return error */
158720459ee2SKalle Valo 	if ((ath6kl_set_host_app_area(ar)) != 0)
158820459ee2SKalle Valo 		ath6kl_err("unable to set the host app area\n");
158920459ee2SKalle Valo 
159071f96ee6SKalle Valo 	for (i = 0; i < ar->vif_max; i++) {
159120459ee2SKalle Valo 		ret = ath6kl_target_config_wlan_params(ar, i);
159220459ee2SKalle Valo 		if (ret)
159320459ee2SKalle Valo 			goto err_htc_stop;
159420459ee2SKalle Valo 	}
159520459ee2SKalle Valo 
159676a9fbe2SKalle Valo 	ar->state = ATH6KL_STATE_ON;
159776a9fbe2SKalle Valo 
159820459ee2SKalle Valo 	return 0;
159920459ee2SKalle Valo 
160020459ee2SKalle Valo err_htc_stop:
160120459ee2SKalle Valo 	ath6kl_htc_stop(ar->htc_target);
160220459ee2SKalle Valo err_cleanup_scatter:
160320459ee2SKalle Valo 	ath6kl_hif_cleanup_scatter(ar);
160420459ee2SKalle Valo err_power_off:
160520459ee2SKalle Valo 	ath6kl_hif_power_off(ar);
160620459ee2SKalle Valo 
160720459ee2SKalle Valo 	return ret;
160820459ee2SKalle Valo }
160920459ee2SKalle Valo 
16105fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar)
16115fe4dffbSKalle Valo {
16125fe4dffbSKalle Valo 	int ret;
16135fe4dffbSKalle Valo 
16145fe4dffbSKalle Valo 	ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
16155fe4dffbSKalle Valo 
16165fe4dffbSKalle Valo 	ath6kl_htc_stop(ar->htc_target);
16175fe4dffbSKalle Valo 
16185fe4dffbSKalle Valo 	ath6kl_hif_stop(ar);
16195fe4dffbSKalle Valo 
16205fe4dffbSKalle Valo 	ath6kl_bmi_reset(ar);
16215fe4dffbSKalle Valo 
16225fe4dffbSKalle Valo 	ret = ath6kl_hif_power_off(ar);
16235fe4dffbSKalle Valo 	if (ret)
16245fe4dffbSKalle Valo 		ath6kl_warn("failed to power off hif: %d\n", ret);
16255fe4dffbSKalle Valo 
162676a9fbe2SKalle Valo 	ar->state = ATH6KL_STATE_OFF;
162776a9fbe2SKalle Valo 
16285fe4dffbSKalle Valo 	return 0;
16295fe4dffbSKalle Valo }
16305fe4dffbSKalle Valo 
1631c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
163255055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
16336db8fa53SVasanthakumar Thiagarajan {
16346db8fa53SVasanthakumar Thiagarajan 	static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
16356db8fa53SVasanthakumar Thiagarajan 	bool discon_issued;
16366db8fa53SVasanthakumar Thiagarajan 
16376db8fa53SVasanthakumar Thiagarajan 	netif_stop_queue(vif->ndev);
16386db8fa53SVasanthakumar Thiagarajan 
16396db8fa53SVasanthakumar Thiagarajan 	clear_bit(WLAN_ENABLED, &vif->flags);
16406db8fa53SVasanthakumar Thiagarajan 
16416db8fa53SVasanthakumar Thiagarajan 	if (wmi_ready) {
16426db8fa53SVasanthakumar Thiagarajan 		discon_issued = test_bit(CONNECTED, &vif->flags) ||
16436db8fa53SVasanthakumar Thiagarajan 				test_bit(CONNECT_PEND, &vif->flags);
16446db8fa53SVasanthakumar Thiagarajan 		ath6kl_disconnect(vif);
16456db8fa53SVasanthakumar Thiagarajan 		del_timer(&vif->disconnect_timer);
16466db8fa53SVasanthakumar Thiagarajan 
16476db8fa53SVasanthakumar Thiagarajan 		if (discon_issued)
16486db8fa53SVasanthakumar Thiagarajan 			ath6kl_disconnect_event(vif, DISCONNECT_CMD,
16496db8fa53SVasanthakumar Thiagarajan 						(vif->nw_type & AP_NETWORK) ?
16506db8fa53SVasanthakumar Thiagarajan 						bcast_mac : vif->bssid,
16516db8fa53SVasanthakumar Thiagarajan 						0, NULL, 0);
16526db8fa53SVasanthakumar Thiagarajan 	}
16536db8fa53SVasanthakumar Thiagarajan 
16546db8fa53SVasanthakumar Thiagarajan 	if (vif->scan_req) {
16556db8fa53SVasanthakumar Thiagarajan 		cfg80211_scan_done(vif->scan_req, true);
16566db8fa53SVasanthakumar Thiagarajan 		vif->scan_req = NULL;
16576db8fa53SVasanthakumar Thiagarajan 	}
16586db8fa53SVasanthakumar Thiagarajan }
16596db8fa53SVasanthakumar Thiagarajan 
1660bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar)
1661bdcd8170SKalle Valo {
1662990bd915SVasanthakumar Thiagarajan 	struct ath6kl_vif *vif, *tmp_vif;
16631d2a4456SVasanthakumar Thiagarajan 	int i;
1664bdcd8170SKalle Valo 
1665bdcd8170SKalle Valo 	set_bit(DESTROY_IN_PROGRESS, &ar->flag);
1666bdcd8170SKalle Valo 
1667bdcd8170SKalle Valo 	if (down_interruptible(&ar->sem)) {
1668bdcd8170SKalle Valo 		ath6kl_err("down_interruptible failed\n");
1669bdcd8170SKalle Valo 		return;
1670bdcd8170SKalle Valo 	}
1671bdcd8170SKalle Valo 
16721d2a4456SVasanthakumar Thiagarajan 	for (i = 0; i < AP_MAX_NUM_STA; i++)
16731d2a4456SVasanthakumar Thiagarajan 		aggr_reset_state(ar->sta_list[i].aggr_conn);
16741d2a4456SVasanthakumar Thiagarajan 
167511f6e40dSVasanthakumar Thiagarajan 	spin_lock_bh(&ar->list_lock);
1676990bd915SVasanthakumar Thiagarajan 	list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
1677990bd915SVasanthakumar Thiagarajan 		list_del(&vif->list);
167811f6e40dSVasanthakumar Thiagarajan 		spin_unlock_bh(&ar->list_lock);
1679990bd915SVasanthakumar Thiagarajan 		ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
168027929723SVasanthakumar Thiagarajan 		rtnl_lock();
1681c25889e8SKalle Valo 		ath6kl_cfg80211_vif_cleanup(vif);
168227929723SVasanthakumar Thiagarajan 		rtnl_unlock();
168311f6e40dSVasanthakumar Thiagarajan 		spin_lock_bh(&ar->list_lock);
1684990bd915SVasanthakumar Thiagarajan 	}
168511f6e40dSVasanthakumar Thiagarajan 	spin_unlock_bh(&ar->list_lock);
1686bdcd8170SKalle Valo 
16876db8fa53SVasanthakumar Thiagarajan 	clear_bit(WMI_READY, &ar->flag);
16886db8fa53SVasanthakumar Thiagarajan 
16896db8fa53SVasanthakumar Thiagarajan 	/*
16906db8fa53SVasanthakumar Thiagarajan 	 * After wmi_shudown all WMI events will be dropped. We
16916db8fa53SVasanthakumar Thiagarajan 	 * need to cleanup the buffers allocated in AP mode and
16926db8fa53SVasanthakumar Thiagarajan 	 * give disconnect notification to stack, which usually
16936db8fa53SVasanthakumar Thiagarajan 	 * happens in the disconnect_event. Simulate the disconnect
16946db8fa53SVasanthakumar Thiagarajan 	 * event by calling the function directly. Sometimes
16956db8fa53SVasanthakumar Thiagarajan 	 * disconnect_event will be received when the debug logs
16966db8fa53SVasanthakumar Thiagarajan 	 * are collected.
16976db8fa53SVasanthakumar Thiagarajan 	 */
16986db8fa53SVasanthakumar Thiagarajan 	ath6kl_wmi_shutdown(ar->wmi);
16996db8fa53SVasanthakumar Thiagarajan 
17006db8fa53SVasanthakumar Thiagarajan 	clear_bit(WMI_ENABLED, &ar->flag);
17016db8fa53SVasanthakumar Thiagarajan 	if (ar->htc_target) {
17026db8fa53SVasanthakumar Thiagarajan 		ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
17036db8fa53SVasanthakumar Thiagarajan 		ath6kl_htc_stop(ar->htc_target);
1704bdcd8170SKalle Valo 	}
1705bdcd8170SKalle Valo 
1706bdcd8170SKalle Valo 	/*
17076db8fa53SVasanthakumar Thiagarajan 	 * Try to reset the device if we can. The driver may have been
17086db8fa53SVasanthakumar Thiagarajan 	 * configure NOT to reset the target during a debug session.
1709bdcd8170SKalle Valo 	 */
17106db8fa53SVasanthakumar Thiagarajan 	ath6kl_dbg(ATH6KL_DBG_TRC,
17116db8fa53SVasanthakumar Thiagarajan 			"attempting to reset target on instance destroy\n");
17126db8fa53SVasanthakumar Thiagarajan 	ath6kl_reset_device(ar, ar->target_type, true, true);
1713bdcd8170SKalle Valo 
17146db8fa53SVasanthakumar Thiagarajan 	clear_bit(WLAN_ENABLED, &ar->flag);
1715bdcd8170SKalle Valo }
1716d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx);
1717