1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 41b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 5bdcd8170SKalle Valo * 6bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 7bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 8bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 9bdcd8170SKalle Valo * 10bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17bdcd8170SKalle Valo */ 18bdcd8170SKalle Valo 19c6efe578SStephen Rothwell #include <linux/moduleparam.h> 20f7830202SSangwook Lee #include <linux/errno.h> 21d6a434d6SKalle Valo #include <linux/export.h> 2292ecbff4SSam Leffler #include <linux/of.h> 23bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 24d6a434d6SKalle Valo 25bdcd8170SKalle Valo #include "core.h" 26bdcd8170SKalle Valo #include "cfg80211.h" 27bdcd8170SKalle Valo #include "target.h" 28bdcd8170SKalle Valo #include "debug.h" 29bdcd8170SKalle Valo #include "hif-ops.h" 30bdcd8170SKalle Valo 31856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 32856f4b31SKalle Valo { 330d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 34293badf4SKalle Valo .name = "ar6003 hw 2.0", 35856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 36856f4b31SKalle Valo .app_load_addr = 0x543180, 37856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 38856f4b31SKalle Valo .reserved_ram_size = 6912, 3939586bf2SRyan Hsu .refclk_hz = 26000000, 4039586bf2SRyan Hsu .uarttx_pin = 8, 41856f4b31SKalle Valo 42856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 43856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 44d1a9421dSKalle Valo 45c0038972SKalle Valo .fw = { 46c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 47c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 48d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 49c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 50c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 51c0038972SKalle Valo }, 52c0038972SKalle Valo 53d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 54d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 55856f4b31SKalle Valo }, 56856f4b31SKalle Valo { 570d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 58293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 59856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 60856f4b31SKalle Valo .app_load_addr = 0x1234, 61856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 62856f4b31SKalle Valo .reserved_ram_size = 512, 6339586bf2SRyan Hsu .refclk_hz = 26000000, 6439586bf2SRyan Hsu .uarttx_pin = 8, 65cd23c1c9SAlex Yang .testscript_addr = 0x57ef74, 66d1a9421dSKalle Valo 67c0038972SKalle Valo .fw = { 68c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 69c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 70d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 71c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 72c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 73cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, 74cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, 75c0038972SKalle Valo }, 76c0038972SKalle Valo 77d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 78d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 79856f4b31SKalle Valo }, 80856f4b31SKalle Valo { 810d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 82293badf4SKalle Valo .name = "ar6004 hw 1.0", 83856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 84856f4b31SKalle Valo .app_load_addr = 0x1234, 85856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 86856f4b31SKalle Valo .reserved_ram_size = 19456, 870d4d72bfSKalle Valo .board_addr = 0x433900, 8839586bf2SRyan Hsu .refclk_hz = 26000000, 8939586bf2SRyan Hsu .uarttx_pin = 11, 90d1a9421dSKalle Valo 91c0038972SKalle Valo .fw = { 92c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 93d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 94c0038972SKalle Valo }, 95c0038972SKalle Valo 96d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 97d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 98856f4b31SKalle Valo }, 99856f4b31SKalle Valo { 1000d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 101293badf4SKalle Valo .name = "ar6004 hw 1.1", 102856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 103856f4b31SKalle Valo .app_load_addr = 0x1234, 104856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 105856f4b31SKalle Valo .reserved_ram_size = 11264, 1060d4d72bfSKalle Valo .board_addr = 0x43d400, 10739586bf2SRyan Hsu .refclk_hz = 40000000, 10839586bf2SRyan Hsu .uarttx_pin = 11, 109d1a9421dSKalle Valo 110c0038972SKalle Valo .fw = { 111c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 112d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 113c0038972SKalle Valo }, 114c0038972SKalle Valo 115d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 116d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 117856f4b31SKalle Valo }, 118856f4b31SKalle Valo }; 119856f4b31SKalle Valo 120bdcd8170SKalle Valo /* 121bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 122bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 123bdcd8170SKalle Valo * here. 124bdcd8170SKalle Valo */ 125bdcd8170SKalle Valo 126bdcd8170SKalle Valo /* 127bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 128bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 129bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 130bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 131bdcd8170SKalle Valo * Use value of zero to disable keepalive support 132bdcd8170SKalle Valo * Default: 60 seconds 133bdcd8170SKalle Valo */ 134bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 135bdcd8170SKalle Valo 136bdcd8170SKalle Valo /* 137bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 138bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 139bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 140bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 141bdcd8170SKalle Valo * it sends a new connect event 142bdcd8170SKalle Valo */ 143bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 144bdcd8170SKalle Valo 145bdcd8170SKalle Valo 146bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 147bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 148bdcd8170SKalle Valo { 149bdcd8170SKalle Valo struct sk_buff *skb; 150bdcd8170SKalle Valo u16 reserved; 151bdcd8170SKalle Valo 152bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 153bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 1541df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 155bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 156bdcd8170SKalle Valo 157bdcd8170SKalle Valo if (skb) 158bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 159bdcd8170SKalle Valo return skb; 160bdcd8170SKalle Valo } 161bdcd8170SKalle Valo 162e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 163bdcd8170SKalle Valo { 1643450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 1653450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 1663450334fSVasanthakumar Thiagarajan 1673450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 1683450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 1693450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 1703450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 1713450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 1723450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 1736f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 1748c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 1758c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 176f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 177bdcd8170SKalle Valo } 178bdcd8170SKalle Valo 179bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 180bdcd8170SKalle Valo { 181bdcd8170SKalle Valo u32 address, data; 182bdcd8170SKalle Valo struct host_app_area host_app_area; 183bdcd8170SKalle Valo 184bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 185bdcd8170SKalle Valo * instance in the host interest area */ 186bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 18731024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 188bdcd8170SKalle Valo 189addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 190bdcd8170SKalle Valo return -EIO; 191bdcd8170SKalle Valo 19231024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 193cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 194addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 195addb44beSKalle Valo sizeof(struct host_app_area))) 196bdcd8170SKalle Valo return -EIO; 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo return 0; 199bdcd8170SKalle Valo } 200bdcd8170SKalle Valo 201bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 202bdcd8170SKalle Valo u8 ac, 203bdcd8170SKalle Valo enum htc_endpoint_id ep) 204bdcd8170SKalle Valo { 205bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 206bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 207bdcd8170SKalle Valo } 208bdcd8170SKalle Valo 209bdcd8170SKalle Valo /* connect to a service */ 210bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 211bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 212bdcd8170SKalle Valo char *desc) 213bdcd8170SKalle Valo { 214bdcd8170SKalle Valo int status; 215bdcd8170SKalle Valo struct htc_service_connect_resp response; 216bdcd8170SKalle Valo 217bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 218bdcd8170SKalle Valo 219ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 220bdcd8170SKalle Valo if (status) { 221bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 222bdcd8170SKalle Valo desc, status); 223bdcd8170SKalle Valo return status; 224bdcd8170SKalle Valo } 225bdcd8170SKalle Valo 226bdcd8170SKalle Valo switch (con_req->svc_id) { 227bdcd8170SKalle Valo case WMI_CONTROL_SVC: 228bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 229bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 230bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 231bdcd8170SKalle Valo break; 232bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 233bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 234bdcd8170SKalle Valo break; 235bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 236bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 237bdcd8170SKalle Valo break; 238bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 239bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 240bdcd8170SKalle Valo break; 241bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 242bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 243bdcd8170SKalle Valo break; 244bdcd8170SKalle Valo default: 245bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 246bdcd8170SKalle Valo return -EINVAL; 247bdcd8170SKalle Valo } 248bdcd8170SKalle Valo 249bdcd8170SKalle Valo return 0; 250bdcd8170SKalle Valo } 251bdcd8170SKalle Valo 252bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 253bdcd8170SKalle Valo { 254bdcd8170SKalle Valo struct htc_service_connect_req connect; 255bdcd8170SKalle Valo 256bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 257bdcd8170SKalle Valo 258bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 259bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 260bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 261bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo /* 264bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 265bdcd8170SKalle Valo * gets called. 266bdcd8170SKalle Valo */ 267bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 268bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 269bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 270bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 271bdcd8170SKalle Valo 272bdcd8170SKalle Valo /* connect to control service */ 273bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 274bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 275bdcd8170SKalle Valo return -EIO; 276bdcd8170SKalle Valo 277bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 278bdcd8170SKalle Valo 279bdcd8170SKalle Valo /* 280bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 281bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 282bdcd8170SKalle Valo * (802.3) frames on the send path. 283bdcd8170SKalle Valo */ 284bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 285bdcd8170SKalle Valo 286bdcd8170SKalle Valo /* 287bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 288bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 289bdcd8170SKalle Valo * packets. 290bdcd8170SKalle Valo */ 291bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 292bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 293bdcd8170SKalle Valo 294bdcd8170SKalle Valo /* 295bdcd8170SKalle Valo * For the remaining data services set the connection flag to 296bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 297bdcd8170SKalle Valo */ 298bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 299bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 300bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 301bdcd8170SKalle Valo 302bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 303bdcd8170SKalle Valo 304bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 305bdcd8170SKalle Valo return -EIO; 306bdcd8170SKalle Valo 307bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 308bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 309bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 310bdcd8170SKalle Valo return -EIO; 311bdcd8170SKalle Valo 312bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 313bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 314bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 315bdcd8170SKalle Valo return -EIO; 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo /* 318bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 319bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 320bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 321bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 322bdcd8170SKalle Valo * mailboxes. 323bdcd8170SKalle Valo */ 324bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 325bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 326bdcd8170SKalle Valo return -EIO; 327bdcd8170SKalle Valo 328bdcd8170SKalle Valo return 0; 329bdcd8170SKalle Valo } 330bdcd8170SKalle Valo 331e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 332bdcd8170SKalle Valo { 333e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3343450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3356f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 336f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 337bdcd8170SKalle Valo } 338bdcd8170SKalle Valo 339bdcd8170SKalle Valo /* 340bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 341bdcd8170SKalle Valo * target is in the BMI phase. 342bdcd8170SKalle Valo */ 343bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 344bdcd8170SKalle Valo u8 htc_ctrl_buf) 345bdcd8170SKalle Valo { 346bdcd8170SKalle Valo int status; 347bdcd8170SKalle Valo u32 blk_size; 348bdcd8170SKalle Valo 349bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 350bdcd8170SKalle Valo 351bdcd8170SKalle Valo if (htc_ctrl_buf) 352bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 353bdcd8170SKalle Valo 354bdcd8170SKalle Valo /* set the host interest area for the block size */ 355bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 356bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 357bdcd8170SKalle Valo HI_ITEM(hi_mbox_io_block_sz)), 358bdcd8170SKalle Valo (u8 *)&blk_size, 359bdcd8170SKalle Valo 4); 360bdcd8170SKalle Valo if (status) { 361bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 362bdcd8170SKalle Valo goto out; 363bdcd8170SKalle Valo } 364bdcd8170SKalle Valo 365bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 366bdcd8170SKalle Valo blk_size, 367bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 368bdcd8170SKalle Valo 369bdcd8170SKalle Valo if (mbox_isr_yield_val) { 370bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 371bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 372bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 373bdcd8170SKalle Valo HI_ITEM(hi_mbox_isr_yield_limit)), 374bdcd8170SKalle Valo (u8 *)&mbox_isr_yield_val, 375bdcd8170SKalle Valo 4); 376bdcd8170SKalle Valo if (status) { 377bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 378bdcd8170SKalle Valo goto out; 379bdcd8170SKalle Valo } 380bdcd8170SKalle Valo } 381bdcd8170SKalle Valo 382bdcd8170SKalle Valo out: 383bdcd8170SKalle Valo return status; 384bdcd8170SKalle Valo } 385bdcd8170SKalle Valo 3860ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 387bdcd8170SKalle Valo { 388bdcd8170SKalle Valo int status = 0; 3894dea08e0SJouni Malinen int ret; 390bdcd8170SKalle Valo 391bdcd8170SKalle Valo /* 392bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 393bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 394bdcd8170SKalle Valo * RxMetaVersion to 2. 395bdcd8170SKalle Valo */ 3960ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 397bdcd8170SKalle Valo ar->rx_meta_ver, 0, 0)) { 398bdcd8170SKalle Valo ath6kl_err("unable to set the rx frame format\n"); 399bdcd8170SKalle Valo status = -EIO; 400bdcd8170SKalle Valo } 401bdcd8170SKalle Valo 402bdcd8170SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) 4030ce59445SVasanthakumar Thiagarajan if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 404bdcd8170SKalle Valo IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) { 405bdcd8170SKalle Valo ath6kl_err("unable to set power save fail event policy\n"); 406bdcd8170SKalle Valo status = -EIO; 407bdcd8170SKalle Valo } 408bdcd8170SKalle Valo 409bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) 4100ce59445SVasanthakumar Thiagarajan if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 411bdcd8170SKalle Valo WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) { 412bdcd8170SKalle Valo ath6kl_err("unable to set barker preamble policy\n"); 413bdcd8170SKalle Valo status = -EIO; 414bdcd8170SKalle Valo } 415bdcd8170SKalle Valo 4160ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 417bdcd8170SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) { 418bdcd8170SKalle Valo ath6kl_err("unable to set keep alive interval\n"); 419bdcd8170SKalle Valo status = -EIO; 420bdcd8170SKalle Valo } 421bdcd8170SKalle Valo 4220ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 423bdcd8170SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT)) { 424bdcd8170SKalle Valo ath6kl_err("unable to set disconnect timeout\n"); 425bdcd8170SKalle Valo status = -EIO; 426bdcd8170SKalle Valo } 427bdcd8170SKalle Valo 428bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) 4290ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) { 430bdcd8170SKalle Valo ath6kl_err("unable to set txop bursting\n"); 431bdcd8170SKalle Valo status = -EIO; 432bdcd8170SKalle Valo } 433bdcd8170SKalle Valo 434b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4350ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4366bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4374dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4384dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4394dea08e0SJouni Malinen if (ret) { 4404dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4416bbc7c35SJouni Malinen "capabilities (%d) - assuming P2P not " 4426bbc7c35SJouni Malinen "supported\n", ret); 4433db1cd5cSRusty Russell ar->p2p = false; 4446bbc7c35SJouni Malinen } 4456bbc7c35SJouni Malinen } 4466bbc7c35SJouni Malinen 447b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4486bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 4490ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 4506bbc7c35SJouni Malinen if (ret) { 4516bbc7c35SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " 4526bbc7c35SJouni Malinen "Request reporting (%d)\n", ret); 4536bbc7c35SJouni Malinen } 4544dea08e0SJouni Malinen } 4554dea08e0SJouni Malinen 456bdcd8170SKalle Valo return status; 457bdcd8170SKalle Valo } 458bdcd8170SKalle Valo 459bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 460bdcd8170SKalle Valo { 461bdcd8170SKalle Valo u32 param, ram_reserved_size; 4623226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 46339586bf2SRyan Hsu int i, status; 464bdcd8170SKalle Valo 465f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 466a10e2f2fSVasanthakumar Thiagarajan if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 467a10e2f2fSVasanthakumar Thiagarajan HI_ITEM(hi_serial_enable)), (u8 *)¶m, 4)) { 468a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 469a10e2f2fSVasanthakumar Thiagarajan return -EIO; 470a10e2f2fSVasanthakumar Thiagarajan } 471a10e2f2fSVasanthakumar Thiagarajan 4727b85832dSVasanthakumar Thiagarajan /* 4737b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 4747b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 4757b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 4767b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 4777b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 4787b85832dSVasanthakumar Thiagarajan * configured for now. 4797b85832dSVasanthakumar Thiagarajan */ 480dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 481bdcd8170SKalle Valo 48271f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 4837b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 4847b85832dSVasanthakumar Thiagarajan 4857b85832dSVasanthakumar Thiagarajan /* 4863226f68aSVasanthakumar Thiagarajan * By default, submodes : 4873226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 4887b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 4897b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 4907b85832dSVasanthakumar Thiagarajan */ 4913226f68aSVasanthakumar Thiagarajan 4923226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 4933226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 4943226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 4953226f68aSVasanthakumar Thiagarajan 49671f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 4973226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 4983226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 4997b85832dSVasanthakumar Thiagarajan 500b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5017b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5027b85832dSVasanthakumar Thiagarajan 503bdcd8170SKalle Valo param = HTC_PROTOCOL_VERSION; 504bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 505bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 506bdcd8170SKalle Valo HI_ITEM(hi_app_host_interest)), 507bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 508bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 509bdcd8170SKalle Valo return -EIO; 510bdcd8170SKalle Valo } 511bdcd8170SKalle Valo 512bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 513bdcd8170SKalle Valo param = 0; 514bdcd8170SKalle Valo 515bdcd8170SKalle Valo if (ath6kl_bmi_read(ar, 516bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 517bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 518bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 519bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 520bdcd8170SKalle Valo return -EIO; 521bdcd8170SKalle Valo } 522bdcd8170SKalle Valo 52371f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5247b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5257b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5267b85832dSVasanthakumar Thiagarajan 527bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 528bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 529bdcd8170SKalle Valo 530bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 531bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 532bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 533bdcd8170SKalle Valo (u8 *)¶m, 534bdcd8170SKalle Valo 4) != 0) { 535bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 536bdcd8170SKalle Valo return -EIO; 537bdcd8170SKalle Valo } 538bdcd8170SKalle Valo 539bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 540bdcd8170SKalle Valo 541bdcd8170SKalle Valo /* 542bdcd8170SKalle Valo * Hardcode the address use for the extended board data 543bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 544bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 545bdcd8170SKalle Valo * at init time, we have to workaround this from host. 546bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 547bdcd8170SKalle Valo * but possible in theory. 548bdcd8170SKalle Valo */ 549bdcd8170SKalle Valo 550991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 551991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 552bdcd8170SKalle Valo 553991b27eaSKalle Valo if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 554bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 555bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 556bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 557bdcd8170SKalle Valo return -EIO; 558bdcd8170SKalle Valo } 559991b27eaSKalle Valo 560991b27eaSKalle Valo if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 561bdcd8170SKalle Valo HI_ITEM(hi_end_ram_reserve_sz)), 562bdcd8170SKalle Valo (u8 *)&ram_reserved_size, 4) != 0) { 563bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 564bdcd8170SKalle Valo return -EIO; 565bdcd8170SKalle Valo } 566bdcd8170SKalle Valo 567bdcd8170SKalle Valo /* set the block size for the target */ 568bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 569bdcd8170SKalle Valo /* use default number of control buffers */ 570bdcd8170SKalle Valo return -EIO; 571bdcd8170SKalle Valo 57239586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 57339586bf2SRyan Hsu param = ar->hw.uarttx_pin; 57439586bf2SRyan Hsu status = ath6kl_bmi_write(ar, 57539586bf2SRyan Hsu ath6kl_get_hi_item_addr(ar, 57639586bf2SRyan Hsu HI_ITEM(hi_dbg_uart_txpin)), 57739586bf2SRyan Hsu (u8 *)¶m, 4); 57839586bf2SRyan Hsu if (status) 57939586bf2SRyan Hsu return status; 58039586bf2SRyan Hsu 58139586bf2SRyan Hsu /* Configure target refclk_hz */ 58239586bf2SRyan Hsu param = ar->hw.refclk_hz; 58339586bf2SRyan Hsu status = ath6kl_bmi_write(ar, 58439586bf2SRyan Hsu ath6kl_get_hi_item_addr(ar, 58539586bf2SRyan Hsu HI_ITEM(hi_refclk_hz)), 58639586bf2SRyan Hsu (u8 *)¶m, 4); 58739586bf2SRyan Hsu if (status) 58839586bf2SRyan Hsu return status; 58939586bf2SRyan Hsu 590bdcd8170SKalle Valo return 0; 591bdcd8170SKalle Valo } 592bdcd8170SKalle Valo 593bdcd8170SKalle Valo /* firmware upload */ 594bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 595bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 596bdcd8170SKalle Valo { 597bdcd8170SKalle Valo const struct firmware *fw_entry; 598bdcd8170SKalle Valo int ret; 599bdcd8170SKalle Valo 600bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 601bdcd8170SKalle Valo if (ret) 602bdcd8170SKalle Valo return ret; 603bdcd8170SKalle Valo 604bdcd8170SKalle Valo *fw_len = fw_entry->size; 605bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 606bdcd8170SKalle Valo 607bdcd8170SKalle Valo if (*fw == NULL) 608bdcd8170SKalle Valo ret = -ENOMEM; 609bdcd8170SKalle Valo 610bdcd8170SKalle Valo release_firmware(fw_entry); 611bdcd8170SKalle Valo 612bdcd8170SKalle Valo return ret; 613bdcd8170SKalle Valo } 614bdcd8170SKalle Valo 61592ecbff4SSam Leffler #ifdef CONFIG_OF 61692ecbff4SSam Leffler /* 61792ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 61892ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 61992ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 62092ecbff4SSam Leffler * appropriate board-specific file. 62192ecbff4SSam Leffler */ 62292ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 62392ecbff4SSam Leffler { 62492ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 62592ecbff4SSam Leffler struct device_node *node; 62692ecbff4SSam Leffler char board_filename[64]; 62792ecbff4SSam Leffler const char *board_id; 62892ecbff4SSam Leffler int ret; 62992ecbff4SSam Leffler 63092ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 63192ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 63292ecbff4SSam Leffler if (board_id == NULL) { 63392ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 63492ecbff4SSam Leffler board_id_prop, node->name); 63592ecbff4SSam Leffler continue; 63692ecbff4SSam Leffler } 63792ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 638c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 63992ecbff4SSam Leffler 64092ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 64192ecbff4SSam Leffler &ar->fw_board_len); 64292ecbff4SSam Leffler if (ret) { 64392ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 64492ecbff4SSam Leffler board_filename, ret); 64592ecbff4SSam Leffler continue; 64692ecbff4SSam Leffler } 64792ecbff4SSam Leffler return true; 64892ecbff4SSam Leffler } 64992ecbff4SSam Leffler return false; 65092ecbff4SSam Leffler } 65192ecbff4SSam Leffler #else 65292ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 65392ecbff4SSam Leffler { 65492ecbff4SSam Leffler return false; 65592ecbff4SSam Leffler } 65692ecbff4SSam Leffler #endif /* CONFIG_OF */ 65792ecbff4SSam Leffler 658bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 659bdcd8170SKalle Valo { 660bdcd8170SKalle Valo const char *filename; 661bdcd8170SKalle Valo int ret; 662bdcd8170SKalle Valo 663772c31eeSKalle Valo if (ar->fw_board != NULL) 664772c31eeSKalle Valo return 0; 665772c31eeSKalle Valo 666d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 667d1a9421dSKalle Valo return -EINVAL; 668d1a9421dSKalle Valo 669d1a9421dSKalle Valo filename = ar->hw.fw_board; 670bdcd8170SKalle Valo 671bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 672bdcd8170SKalle Valo &ar->fw_board_len); 673bdcd8170SKalle Valo if (ret == 0) { 674bdcd8170SKalle Valo /* managed to get proper board file */ 675bdcd8170SKalle Valo return 0; 676bdcd8170SKalle Valo } 677bdcd8170SKalle Valo 67892ecbff4SSam Leffler if (check_device_tree(ar)) { 67992ecbff4SSam Leffler /* got board file from device tree */ 68092ecbff4SSam Leffler return 0; 68192ecbff4SSam Leffler } 68292ecbff4SSam Leffler 683bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 684bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 685bdcd8170SKalle Valo filename, ret); 686bdcd8170SKalle Valo 687d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 688bdcd8170SKalle Valo 689bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 690bdcd8170SKalle Valo &ar->fw_board_len); 691bdcd8170SKalle Valo if (ret) { 692bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 693bdcd8170SKalle Valo filename, ret); 694bdcd8170SKalle Valo return ret; 695bdcd8170SKalle Valo } 696bdcd8170SKalle Valo 697bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 698bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 699bdcd8170SKalle Valo 700bdcd8170SKalle Valo return 0; 701bdcd8170SKalle Valo } 702bdcd8170SKalle Valo 703772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 704772c31eeSKalle Valo { 705c0038972SKalle Valo char filename[100]; 706772c31eeSKalle Valo int ret; 707772c31eeSKalle Valo 708772c31eeSKalle Valo if (ar->fw_otp != NULL) 709772c31eeSKalle Valo return 0; 710772c31eeSKalle Valo 711c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 712d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 713d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 714772c31eeSKalle Valo return 0; 715772c31eeSKalle Valo } 716772c31eeSKalle Valo 717c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 718c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 719d1a9421dSKalle Valo 720772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 721772c31eeSKalle Valo &ar->fw_otp_len); 722772c31eeSKalle Valo if (ret) { 723772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 724772c31eeSKalle Valo filename, ret); 725772c31eeSKalle Valo return ret; 726772c31eeSKalle Valo } 727772c31eeSKalle Valo 728772c31eeSKalle Valo return 0; 729772c31eeSKalle Valo } 730772c31eeSKalle Valo 7315f1127ffSKalle Valo static int ath6kl_fetch_testmode_file(struct ath6kl *ar) 732772c31eeSKalle Valo { 733c0038972SKalle Valo char filename[100]; 734772c31eeSKalle Valo int ret; 735772c31eeSKalle Valo 7365f1127ffSKalle Valo if (ar->testmode == 0) 737772c31eeSKalle Valo return 0; 738772c31eeSKalle Valo 7395f1127ffSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode); 7405f1127ffSKalle Valo 7415f1127ffSKalle Valo if (ar->testmode == 2) { 742cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) { 743cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n"); 744cd23c1c9SAlex Yang return -EOPNOTSUPP; 745cd23c1c9SAlex Yang } 746cd23c1c9SAlex Yang 747cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 748cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf); 749cd23c1c9SAlex Yang } else { 750c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 751cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n"); 752772c31eeSKalle Valo return -EOPNOTSUPP; 753772c31eeSKalle Valo } 754772c31eeSKalle Valo 755c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 756c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 757cd23c1c9SAlex Yang } 7585f1127ffSKalle Valo 759772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 760772c31eeSKalle Valo 7615f1127ffSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 7625f1127ffSKalle Valo if (ret) { 7635f1127ffSKalle Valo ath6kl_err("Failed to get testmode %d firmware file %s: %d\n", 7645f1127ffSKalle Valo ar->testmode, filename, ret); 7655f1127ffSKalle Valo return ret; 766772c31eeSKalle Valo } 767772c31eeSKalle Valo 7685f1127ffSKalle Valo return 0; 7695f1127ffSKalle Valo } 7705f1127ffSKalle Valo 7715f1127ffSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 7725f1127ffSKalle Valo { 7735f1127ffSKalle Valo char filename[100]; 7745f1127ffSKalle Valo int ret; 7755f1127ffSKalle Valo 7765f1127ffSKalle Valo if (ar->fw != NULL) 7775f1127ffSKalle Valo return 0; 7785f1127ffSKalle Valo 779c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 780c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 781d1a9421dSKalle Valo return -EINVAL; 782d1a9421dSKalle Valo 783c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 784c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 785772c31eeSKalle Valo 786772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 787772c31eeSKalle Valo if (ret) { 788772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 789772c31eeSKalle Valo filename, ret); 790772c31eeSKalle Valo return ret; 791772c31eeSKalle Valo } 792772c31eeSKalle Valo 793772c31eeSKalle Valo return 0; 794772c31eeSKalle Valo } 795772c31eeSKalle Valo 796772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 797772c31eeSKalle Valo { 798c0038972SKalle Valo char filename[100]; 799772c31eeSKalle Valo int ret; 800772c31eeSKalle Valo 801d1a9421dSKalle Valo if (ar->fw_patch != NULL) 802772c31eeSKalle Valo return 0; 803772c31eeSKalle Valo 804c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 805d1a9421dSKalle Valo return 0; 806d1a9421dSKalle Valo 807c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 808c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 809d1a9421dSKalle Valo 810772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 811772c31eeSKalle Valo &ar->fw_patch_len); 812772c31eeSKalle Valo if (ret) { 813772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 814772c31eeSKalle Valo filename, ret); 815772c31eeSKalle Valo return ret; 816772c31eeSKalle Valo } 817772c31eeSKalle Valo 818772c31eeSKalle Valo return 0; 819772c31eeSKalle Valo } 820772c31eeSKalle Valo 821cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar) 822cd23c1c9SAlex Yang { 823cd23c1c9SAlex Yang char filename[100]; 824cd23c1c9SAlex Yang int ret; 825cd23c1c9SAlex Yang 8265f1127ffSKalle Valo if (ar->testmode != 2) 827cd23c1c9SAlex Yang return 0; 828cd23c1c9SAlex Yang 829cd23c1c9SAlex Yang if (ar->fw_testscript != NULL) 830cd23c1c9SAlex Yang return 0; 831cd23c1c9SAlex Yang 832cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL) 833cd23c1c9SAlex Yang return 0; 834cd23c1c9SAlex Yang 835cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 836cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript); 837cd23c1c9SAlex Yang 838cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 839cd23c1c9SAlex Yang &ar->fw_testscript_len); 840cd23c1c9SAlex Yang if (ret) { 841cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n", 842cd23c1c9SAlex Yang filename, ret); 843cd23c1c9SAlex Yang return ret; 844cd23c1c9SAlex Yang } 845cd23c1c9SAlex Yang 846cd23c1c9SAlex Yang return 0; 847cd23c1c9SAlex Yang } 848cd23c1c9SAlex Yang 84950d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 850772c31eeSKalle Valo { 851772c31eeSKalle Valo int ret; 852772c31eeSKalle Valo 853772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 854772c31eeSKalle Valo if (ret) 855772c31eeSKalle Valo return ret; 856772c31eeSKalle Valo 857772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 858772c31eeSKalle Valo if (ret) 859772c31eeSKalle Valo return ret; 860772c31eeSKalle Valo 861772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 862772c31eeSKalle Valo if (ret) 863772c31eeSKalle Valo return ret; 864772c31eeSKalle Valo 865cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar); 866cd23c1c9SAlex Yang if (ret) 867cd23c1c9SAlex Yang return ret; 868cd23c1c9SAlex Yang 869772c31eeSKalle Valo return 0; 870772c31eeSKalle Valo } 871bdcd8170SKalle Valo 87265a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 87350d41234SKalle Valo { 87450d41234SKalle Valo size_t magic_len, len, ie_len; 87550d41234SKalle Valo const struct firmware *fw; 87650d41234SKalle Valo struct ath6kl_fw_ie *hdr; 877c0038972SKalle Valo char filename[100]; 87850d41234SKalle Valo const u8 *data; 87997e0496dSKalle Valo int ret, ie_id, i, index, bit; 8808a137480SKalle Valo __le32 *val; 88150d41234SKalle Valo 88265a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 88350d41234SKalle Valo 88450d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 88550d41234SKalle Valo if (ret) 88650d41234SKalle Valo return ret; 88750d41234SKalle Valo 88850d41234SKalle Valo data = fw->data; 88950d41234SKalle Valo len = fw->size; 89050d41234SKalle Valo 89150d41234SKalle Valo /* magic also includes the null byte, check that as well */ 89250d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 89350d41234SKalle Valo 89450d41234SKalle Valo if (len < magic_len) { 89550d41234SKalle Valo ret = -EINVAL; 89650d41234SKalle Valo goto out; 89750d41234SKalle Valo } 89850d41234SKalle Valo 89950d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 90050d41234SKalle Valo ret = -EINVAL; 90150d41234SKalle Valo goto out; 90250d41234SKalle Valo } 90350d41234SKalle Valo 90450d41234SKalle Valo len -= magic_len; 90550d41234SKalle Valo data += magic_len; 90650d41234SKalle Valo 90750d41234SKalle Valo /* loop elements */ 90850d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 90950d41234SKalle Valo /* hdr is unaligned! */ 91050d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 91150d41234SKalle Valo 91250d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 91350d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 91450d41234SKalle Valo 91550d41234SKalle Valo len -= sizeof(*hdr); 91650d41234SKalle Valo data += sizeof(*hdr); 91750d41234SKalle Valo 91850d41234SKalle Valo if (len < ie_len) { 91950d41234SKalle Valo ret = -EINVAL; 92050d41234SKalle Valo goto out; 92150d41234SKalle Valo } 92250d41234SKalle Valo 92350d41234SKalle Valo switch (ie_id) { 92450d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 925ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9266bc36431SKalle Valo ie_len); 9276bc36431SKalle Valo 92850d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 92950d41234SKalle Valo 93050d41234SKalle Valo if (ar->fw_otp == NULL) { 93150d41234SKalle Valo ret = -ENOMEM; 93250d41234SKalle Valo goto out; 93350d41234SKalle Valo } 93450d41234SKalle Valo 93550d41234SKalle Valo ar->fw_otp_len = ie_len; 93650d41234SKalle Valo break; 93750d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 938ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9396bc36431SKalle Valo ie_len); 9406bc36431SKalle Valo 9415f1127ffSKalle Valo /* in testmode we already might have a fw file */ 9425f1127ffSKalle Valo if (ar->fw != NULL) 9435f1127ffSKalle Valo break; 9445f1127ffSKalle Valo 94550d41234SKalle Valo ar->fw = kmemdup(data, ie_len, GFP_KERNEL); 94650d41234SKalle Valo 94750d41234SKalle Valo if (ar->fw == NULL) { 94850d41234SKalle Valo ret = -ENOMEM; 94950d41234SKalle Valo goto out; 95050d41234SKalle Valo } 95150d41234SKalle Valo 95250d41234SKalle Valo ar->fw_len = ie_len; 95350d41234SKalle Valo break; 95450d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 955ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 9566bc36431SKalle Valo ie_len); 9576bc36431SKalle Valo 95850d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 95950d41234SKalle Valo 96050d41234SKalle Valo if (ar->fw_patch == NULL) { 96150d41234SKalle Valo ret = -ENOMEM; 96250d41234SKalle Valo goto out; 96350d41234SKalle Valo } 96450d41234SKalle Valo 96550d41234SKalle Valo ar->fw_patch_len = ie_len; 96650d41234SKalle Valo break; 9678a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 9688a137480SKalle Valo val = (__le32 *) data; 9698a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 9706bc36431SKalle Valo 9716bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 9726bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 9736bc36431SKalle Valo ar->hw.reserved_ram_size); 9748a137480SKalle Valo break; 97597e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 976277d90f4SKalle Valo if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) 977277d90f4SKalle Valo break; 978277d90f4SKalle Valo 9796bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 980ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 9816bc36431SKalle Valo ie_len); 9826bc36431SKalle Valo 98397e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 984277d90f4SKalle Valo index = i / 8; 98597e0496dSKalle Valo bit = i % 8; 98697e0496dSKalle Valo 98797e0496dSKalle Valo if (data[index] & (1 << bit)) 98897e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 98997e0496dSKalle Valo } 9906bc36431SKalle Valo 9916bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 9926bc36431SKalle Valo ar->fw_capabilities, 9936bc36431SKalle Valo sizeof(ar->fw_capabilities)); 99497e0496dSKalle Valo break; 9951b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 9961b4304daSKalle Valo if (ie_len != sizeof(*val)) 9971b4304daSKalle Valo break; 9981b4304daSKalle Valo 9991b4304daSKalle Valo val = (__le32 *) data; 10001b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 10016bc36431SKalle Valo 10026bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 100303ef0250SKalle Valo "found patch address ie 0x%x\n", 10046bc36431SKalle Valo ar->hw.dataset_patch_addr); 10051b4304daSKalle Valo break; 100603ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 100703ef0250SKalle Valo if (ie_len != sizeof(*val)) 100803ef0250SKalle Valo break; 100903ef0250SKalle Valo 101003ef0250SKalle Valo val = (__le32 *) data; 101103ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 101203ef0250SKalle Valo 101303ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 101403ef0250SKalle Valo "found board address ie 0x%x\n", 101503ef0250SKalle Valo ar->hw.board_addr); 101603ef0250SKalle Valo break; 1017368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 1018368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 1019368b1b0fSKalle Valo break; 1020368b1b0fSKalle Valo 1021368b1b0fSKalle Valo val = (__le32 *) data; 1022368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 1023368b1b0fSKalle Valo ATH6KL_VIF_MAX); 1024368b1b0fSKalle Valo 1025f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 1026f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1027f143379dSVasanthakumar Thiagarajan 1028368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1029368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1030368b1b0fSKalle Valo break; 103150d41234SKalle Valo default: 10326bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 103350d41234SKalle Valo le32_to_cpup(&hdr->id)); 103450d41234SKalle Valo break; 103550d41234SKalle Valo } 103650d41234SKalle Valo 103750d41234SKalle Valo len -= ie_len; 103850d41234SKalle Valo data += ie_len; 103950d41234SKalle Valo }; 104050d41234SKalle Valo 104150d41234SKalle Valo ret = 0; 104250d41234SKalle Valo out: 104350d41234SKalle Valo release_firmware(fw); 104450d41234SKalle Valo 104550d41234SKalle Valo return ret; 104650d41234SKalle Valo } 104750d41234SKalle Valo 104845eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar) 104950d41234SKalle Valo { 105050d41234SKalle Valo int ret; 105150d41234SKalle Valo 105250d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 105350d41234SKalle Valo if (ret) 105450d41234SKalle Valo return ret; 105550d41234SKalle Valo 10565f1127ffSKalle Valo ret = ath6kl_fetch_testmode_file(ar); 10575f1127ffSKalle Valo if (ret) 10585f1127ffSKalle Valo return ret; 10595f1127ffSKalle Valo 106065a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 10616bc36431SKalle Valo if (ret == 0) { 106265a8b4ccSKalle Valo ar->fw_api = 3; 106365a8b4ccSKalle Valo goto out; 106465a8b4ccSKalle Valo } 106565a8b4ccSKalle Valo 106665a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 106765a8b4ccSKalle Valo if (ret == 0) { 106865a8b4ccSKalle Valo ar->fw_api = 2; 106965a8b4ccSKalle Valo goto out; 10706bc36431SKalle Valo } 107150d41234SKalle Valo 107250d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 107350d41234SKalle Valo if (ret) 107450d41234SKalle Valo return ret; 107550d41234SKalle Valo 107665a8b4ccSKalle Valo ar->fw_api = 1; 107765a8b4ccSKalle Valo 107865a8b4ccSKalle Valo out: 107965a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 10806bc36431SKalle Valo 108150d41234SKalle Valo return 0; 108250d41234SKalle Valo } 108350d41234SKalle Valo 1084bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1085bdcd8170SKalle Valo { 1086bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 108731024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1088bdcd8170SKalle Valo int ret; 1089bdcd8170SKalle Valo 1090772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1091772c31eeSKalle Valo return -ENOENT; 1092bdcd8170SKalle Valo 109331024d99SKevin Fang /* 109431024d99SKevin Fang * Determine where in Target RAM to write Board Data. 109531024d99SKevin Fang * For AR6004, host determine Target RAM address for 109631024d99SKevin Fang * writing board data. 109731024d99SKevin Fang */ 10980d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 10990d4d72bfSKalle Valo board_address = ar->hw.board_addr; 110031024d99SKevin Fang ath6kl_bmi_write(ar, 110131024d99SKevin Fang ath6kl_get_hi_item_addr(ar, 110231024d99SKevin Fang HI_ITEM(hi_board_data)), 110331024d99SKevin Fang (u8 *) &board_address, 4); 110431024d99SKevin Fang } else { 1105bdcd8170SKalle Valo ath6kl_bmi_read(ar, 1106bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1107bdcd8170SKalle Valo HI_ITEM(hi_board_data)), 1108bdcd8170SKalle Valo (u8 *) &board_address, 4); 110931024d99SKevin Fang } 111031024d99SKevin Fang 1111bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 1112bdcd8170SKalle Valo ath6kl_bmi_read(ar, 1113bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1114bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 1115bdcd8170SKalle Valo (u8 *) &board_ext_address, 4); 1116bdcd8170SKalle Valo 111750e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 111850e2740bSKalle Valo board_ext_address == 0) { 1119bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1120bdcd8170SKalle Valo return -EINVAL; 1121bdcd8170SKalle Valo } 1122bdcd8170SKalle Valo 112331024d99SKevin Fang switch (ar->target_type) { 112431024d99SKevin Fang case TARGET_TYPE_AR6003: 112531024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 112631024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 112731024d99SKevin Fang break; 112831024d99SKevin Fang case TARGET_TYPE_AR6004: 112931024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 113031024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 113131024d99SKevin Fang break; 113231024d99SKevin Fang default: 113331024d99SKevin Fang WARN_ON(1); 113431024d99SKevin Fang return -EINVAL; 113531024d99SKevin Fang break; 113631024d99SKevin Fang } 113731024d99SKevin Fang 113850e2740bSKalle Valo if (board_ext_address && 113950e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 114031024d99SKevin Fang 1141bdcd8170SKalle Valo /* write extended board data */ 11426bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11436bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11446bc36431SKalle Valo board_ext_address, board_ext_data_size); 11456bc36431SKalle Valo 1146bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 114731024d99SKevin Fang ar->fw_board + board_data_size, 114831024d99SKevin Fang board_ext_data_size); 1149bdcd8170SKalle Valo if (ret) { 1150bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1151bdcd8170SKalle Valo ret); 1152bdcd8170SKalle Valo return ret; 1153bdcd8170SKalle Valo } 1154bdcd8170SKalle Valo 1155bdcd8170SKalle Valo /* record that extended board data is initialized */ 115631024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 115731024d99SKevin Fang 1158bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1159bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1160bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data_config)), 1161bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 1162bdcd8170SKalle Valo } 1163bdcd8170SKalle Valo 116431024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1165bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1166bdcd8170SKalle Valo ret = -EINVAL; 1167bdcd8170SKalle Valo return ret; 1168bdcd8170SKalle Valo } 1169bdcd8170SKalle Valo 11706bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 11716bc36431SKalle Valo board_address, board_data_size); 11726bc36431SKalle Valo 1173bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 117431024d99SKevin Fang board_data_size); 1175bdcd8170SKalle Valo 1176bdcd8170SKalle Valo if (ret) { 1177bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1178bdcd8170SKalle Valo return ret; 1179bdcd8170SKalle Valo } 1180bdcd8170SKalle Valo 1181bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 1182bdcd8170SKalle Valo param = 1; 1183bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1184bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1185bdcd8170SKalle Valo HI_ITEM(hi_board_data_initialized)), 1186bdcd8170SKalle Valo (u8 *)¶m, 4); 1187bdcd8170SKalle Valo 1188bdcd8170SKalle Valo return ret; 1189bdcd8170SKalle Valo } 1190bdcd8170SKalle Valo 1191bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1192bdcd8170SKalle Valo { 1193bdcd8170SKalle Valo u32 address, param; 1194bef26a7fSKalle Valo bool from_hw = false; 1195bdcd8170SKalle Valo int ret; 1196bdcd8170SKalle Valo 119750e2740bSKalle Valo if (ar->fw_otp == NULL) 119850e2740bSKalle Valo return 0; 1199bdcd8170SKalle Valo 1200a01ac414SKalle Valo address = ar->hw.app_load_addr; 1201bdcd8170SKalle Valo 1202ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 12036bc36431SKalle Valo ar->fw_otp_len); 12046bc36431SKalle Valo 1205bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1206bdcd8170SKalle Valo ar->fw_otp_len); 1207bdcd8170SKalle Valo if (ret) { 1208bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1209bdcd8170SKalle Valo return ret; 1210bdcd8170SKalle Valo } 1211bdcd8170SKalle Valo 1212639d0b89SKalle Valo /* read firmware start address */ 1213639d0b89SKalle Valo ret = ath6kl_bmi_read(ar, 1214639d0b89SKalle Valo ath6kl_get_hi_item_addr(ar, 1215639d0b89SKalle Valo HI_ITEM(hi_app_start)), 1216639d0b89SKalle Valo (u8 *) &address, sizeof(address)); 1217639d0b89SKalle Valo 1218639d0b89SKalle Valo if (ret) { 1219639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1220639d0b89SKalle Valo return ret; 1221639d0b89SKalle Valo } 1222639d0b89SKalle Valo 1223bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1224639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1225bef26a7fSKalle Valo from_hw = true; 1226bef26a7fSKalle Valo } 1227639d0b89SKalle Valo 1228bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1229bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 12306bc36431SKalle Valo ar->hw.app_start_override_addr); 12316bc36431SKalle Valo 1232bdcd8170SKalle Valo /* execute the OTP code */ 1233bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1234bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1235bdcd8170SKalle Valo param = 0; 1236bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1237bdcd8170SKalle Valo 1238bdcd8170SKalle Valo return ret; 1239bdcd8170SKalle Valo } 1240bdcd8170SKalle Valo 1241bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1242bdcd8170SKalle Valo { 1243bdcd8170SKalle Valo u32 address; 1244bdcd8170SKalle Valo int ret; 1245bdcd8170SKalle Valo 1246772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 124750e2740bSKalle Valo return 0; 1248bdcd8170SKalle Valo 1249a01ac414SKalle Valo address = ar->hw.app_load_addr; 1250bdcd8170SKalle Valo 1251ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12526bc36431SKalle Valo address, ar->fw_len); 12536bc36431SKalle Valo 1254bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1255bdcd8170SKalle Valo 1256bdcd8170SKalle Valo if (ret) { 1257bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1258bdcd8170SKalle Valo return ret; 1259bdcd8170SKalle Valo } 1260bdcd8170SKalle Valo 126131024d99SKevin Fang /* 126231024d99SKevin Fang * Set starting address for firmware 126331024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 126431024d99SKevin Fang */ 126531024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1266a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1267bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 126831024d99SKevin Fang } 1269bdcd8170SKalle Valo return ret; 1270bdcd8170SKalle Valo } 1271bdcd8170SKalle Valo 1272bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1273bdcd8170SKalle Valo { 1274bdcd8170SKalle Valo u32 address, param; 1275bdcd8170SKalle Valo int ret; 1276bdcd8170SKalle Valo 127750e2740bSKalle Valo if (ar->fw_patch == NULL) 127850e2740bSKalle Valo return 0; 1279bdcd8170SKalle Valo 1280a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1281bdcd8170SKalle Valo 1282ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 12836bc36431SKalle Valo address, ar->fw_patch_len); 12846bc36431SKalle Valo 1285bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1286bdcd8170SKalle Valo if (ret) { 1287bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1288bdcd8170SKalle Valo return ret; 1289bdcd8170SKalle Valo } 1290bdcd8170SKalle Valo 1291bdcd8170SKalle Valo param = address; 1292bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1293bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1294bdcd8170SKalle Valo HI_ITEM(hi_dset_list_head)), 1295bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 1296bdcd8170SKalle Valo 1297bdcd8170SKalle Valo return 0; 1298bdcd8170SKalle Valo } 1299bdcd8170SKalle Valo 1300cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar) 1301cd23c1c9SAlex Yang { 1302cd23c1c9SAlex Yang u32 address, param; 1303cd23c1c9SAlex Yang int ret; 1304cd23c1c9SAlex Yang 13055f1127ffSKalle Valo if (ar->testmode != 2) 1306cd23c1c9SAlex Yang return 0; 1307cd23c1c9SAlex Yang 1308cd23c1c9SAlex Yang if (ar->fw_testscript == NULL) 1309cd23c1c9SAlex Yang return 0; 1310cd23c1c9SAlex Yang 1311cd23c1c9SAlex Yang address = ar->hw.testscript_addr; 1312cd23c1c9SAlex Yang 1313cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1314cd23c1c9SAlex Yang address, ar->fw_testscript_len); 1315cd23c1c9SAlex Yang 1316cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1317cd23c1c9SAlex Yang ar->fw_testscript_len); 1318cd23c1c9SAlex Yang if (ret) { 1319cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret); 1320cd23c1c9SAlex Yang return ret; 1321cd23c1c9SAlex Yang } 1322cd23c1c9SAlex Yang 1323cd23c1c9SAlex Yang param = address; 1324cd23c1c9SAlex Yang ath6kl_bmi_write(ar, 1325cd23c1c9SAlex Yang ath6kl_get_hi_item_addr(ar, 1326cd23c1c9SAlex Yang HI_ITEM(hi_ota_testscript)), 1327cd23c1c9SAlex Yang (unsigned char *) ¶m, 4); 1328cd23c1c9SAlex Yang 1329cd23c1c9SAlex Yang param = 4096; 1330cd23c1c9SAlex Yang ath6kl_bmi_write(ar, 1331cd23c1c9SAlex Yang ath6kl_get_hi_item_addr(ar, 1332cd23c1c9SAlex Yang HI_ITEM(hi_end_ram_reserve_sz)), 1333cd23c1c9SAlex Yang (unsigned char *) ¶m, 4); 1334cd23c1c9SAlex Yang 1335cd23c1c9SAlex Yang param = 1; 1336cd23c1c9SAlex Yang ath6kl_bmi_write(ar, 1337cd23c1c9SAlex Yang ath6kl_get_hi_item_addr(ar, 1338cd23c1c9SAlex Yang HI_ITEM(hi_test_apps_related)), 1339cd23c1c9SAlex Yang (unsigned char *) ¶m, 4); 1340cd23c1c9SAlex Yang 1341cd23c1c9SAlex Yang return 0; 1342cd23c1c9SAlex Yang } 1343cd23c1c9SAlex Yang 1344bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1345bdcd8170SKalle Valo { 1346bdcd8170SKalle Valo u32 param, options, sleep, address; 1347bdcd8170SKalle Valo int status = 0; 1348bdcd8170SKalle Valo 134931024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 135031024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1351bdcd8170SKalle Valo return -EINVAL; 1352bdcd8170SKalle Valo 1353bdcd8170SKalle Valo /* temporarily disable system sleep */ 1354bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1355bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1356bdcd8170SKalle Valo if (status) 1357bdcd8170SKalle Valo return status; 1358bdcd8170SKalle Valo 1359bdcd8170SKalle Valo options = param; 1360bdcd8170SKalle Valo 1361bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1362bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1363bdcd8170SKalle Valo if (status) 1364bdcd8170SKalle Valo return status; 1365bdcd8170SKalle Valo 1366bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1367bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1368bdcd8170SKalle Valo if (status) 1369bdcd8170SKalle Valo return status; 1370bdcd8170SKalle Valo 1371bdcd8170SKalle Valo sleep = param; 1372bdcd8170SKalle Valo 1373bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1374bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1375bdcd8170SKalle Valo if (status) 1376bdcd8170SKalle Valo return status; 1377bdcd8170SKalle Valo 1378bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1379bdcd8170SKalle Valo options, sleep); 1380bdcd8170SKalle Valo 1381bdcd8170SKalle Valo /* program analog PLL register */ 138231024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 138331024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1384bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1385bdcd8170SKalle Valo 0xF9104001); 138631024d99SKevin Fang 1387bdcd8170SKalle Valo if (status) 1388bdcd8170SKalle Valo return status; 1389bdcd8170SKalle Valo 1390bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1391bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1392bdcd8170SKalle Valo 1393bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1394bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1395bdcd8170SKalle Valo if (status) 1396bdcd8170SKalle Valo return status; 139731024d99SKevin Fang } 1398bdcd8170SKalle Valo 1399bdcd8170SKalle Valo param = 0; 1400bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1401bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1402bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1403bdcd8170SKalle Valo if (status) 1404bdcd8170SKalle Valo return status; 1405bdcd8170SKalle Valo 1406bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 14070d0192baSKalle Valo if (ar->version.target_ver == AR6003_HW_2_0_VERSION) { 1408bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1409bdcd8170SKalle Valo 1410bdcd8170SKalle Valo param = 0x20; 1411bdcd8170SKalle Valo 1412bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1413bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1414bdcd8170SKalle Valo if (status) 1415bdcd8170SKalle Valo return status; 1416bdcd8170SKalle Valo 1417bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1418bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1419bdcd8170SKalle Valo if (status) 1420bdcd8170SKalle Valo return status; 1421bdcd8170SKalle Valo 1422bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1423bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1424bdcd8170SKalle Valo if (status) 1425bdcd8170SKalle Valo return status; 1426bdcd8170SKalle Valo 1427bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1428bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1429bdcd8170SKalle Valo if (status) 1430bdcd8170SKalle Valo return status; 1431bdcd8170SKalle Valo } 1432bdcd8170SKalle Valo 1433bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1434bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1435bdcd8170SKalle Valo if (status) 1436bdcd8170SKalle Valo return status; 1437bdcd8170SKalle Valo 1438bdcd8170SKalle Valo /* transfer One time Programmable data */ 1439bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1440bdcd8170SKalle Valo if (status) 1441bdcd8170SKalle Valo return status; 1442bdcd8170SKalle Valo 1443bdcd8170SKalle Valo /* Download Target firmware */ 1444bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1445bdcd8170SKalle Valo if (status) 1446bdcd8170SKalle Valo return status; 1447bdcd8170SKalle Valo 1448bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1449bdcd8170SKalle Valo if (status) 1450bdcd8170SKalle Valo return status; 1451bdcd8170SKalle Valo 1452cd23c1c9SAlex Yang /* Download the test script */ 1453cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar); 1454cd23c1c9SAlex Yang if (status) 1455cd23c1c9SAlex Yang return status; 1456cd23c1c9SAlex Yang 1457bdcd8170SKalle Valo /* Restore system sleep */ 1458bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1459bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1460bdcd8170SKalle Valo if (status) 1461bdcd8170SKalle Valo return status; 1462bdcd8170SKalle Valo 1463bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1464bdcd8170SKalle Valo param = options | 0x20; 1465bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1466bdcd8170SKalle Valo if (status) 1467bdcd8170SKalle Valo return status; 1468bdcd8170SKalle Valo 1469bdcd8170SKalle Valo return status; 1470bdcd8170SKalle Valo } 1471bdcd8170SKalle Valo 147245eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar) 1473a01ac414SKalle Valo { 14741b46dc04SKalle Valo const struct ath6kl_hw *uninitialized_var(hw); 1475856f4b31SKalle Valo int i; 1476bef26a7fSKalle Valo 1477856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1478856f4b31SKalle Valo hw = &hw_list[i]; 1479bef26a7fSKalle Valo 1480856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1481a01ac414SKalle Valo break; 1482856f4b31SKalle Valo } 1483856f4b31SKalle Valo 1484856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1485a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1486a01ac414SKalle Valo ar->version.target_ver); 1487a01ac414SKalle Valo return -EINVAL; 1488a01ac414SKalle Valo } 1489a01ac414SKalle Valo 1490856f4b31SKalle Valo ar->hw = *hw; 1491856f4b31SKalle Valo 14926bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14936bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 14946bc36431SKalle Valo ar->version.target_ver, ar->target_type, 14956bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 14966bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14976bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 14986bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 14996bc36431SKalle Valo ar->hw.reserved_ram_size); 150039586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 150139586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 150239586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 15036bc36431SKalle Valo 1504a01ac414SKalle Valo return 0; 1505a01ac414SKalle Valo } 1506a01ac414SKalle Valo 1507293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1508293badf4SKalle Valo { 1509293badf4SKalle Valo switch (type) { 1510293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1511293badf4SKalle Valo return "sdio"; 1512293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1513293badf4SKalle Valo return "usb"; 1514293badf4SKalle Valo } 1515293badf4SKalle Valo 1516293badf4SKalle Valo return NULL; 1517293badf4SKalle Valo } 1518293badf4SKalle Valo 15195fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 152020459ee2SKalle Valo { 152120459ee2SKalle Valo long timeleft; 152220459ee2SKalle Valo int ret, i; 152320459ee2SKalle Valo 15245fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 15255fe4dffbSKalle Valo 152620459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 152720459ee2SKalle Valo if (ret) 152820459ee2SKalle Valo return ret; 152920459ee2SKalle Valo 153020459ee2SKalle Valo ret = ath6kl_configure_target(ar); 153120459ee2SKalle Valo if (ret) 153220459ee2SKalle Valo goto err_power_off; 153320459ee2SKalle Valo 153420459ee2SKalle Valo ret = ath6kl_init_upload(ar); 153520459ee2SKalle Valo if (ret) 153620459ee2SKalle Valo goto err_power_off; 153720459ee2SKalle Valo 153820459ee2SKalle Valo /* Do we need to finish the BMI phase */ 153920459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 154020459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 154120459ee2SKalle Valo ret = -EIO; 154220459ee2SKalle Valo goto err_power_off; 154320459ee2SKalle Valo } 154420459ee2SKalle Valo 154520459ee2SKalle Valo /* 154620459ee2SKalle Valo * The reason we have to wait for the target here is that the 154720459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 154820459ee2SKalle Valo * size. 154920459ee2SKalle Valo */ 155020459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 155120459ee2SKalle Valo ret = -EIO; 155220459ee2SKalle Valo goto err_power_off; 155320459ee2SKalle Valo } 155420459ee2SKalle Valo 155520459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 155620459ee2SKalle Valo ret = -EIO; 155720459ee2SKalle Valo goto err_cleanup_scatter; 155820459ee2SKalle Valo } 155920459ee2SKalle Valo 156020459ee2SKalle Valo /* setup credit distribution */ 156120459ee2SKalle Valo ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info); 156220459ee2SKalle Valo 156320459ee2SKalle Valo /* start HTC */ 156420459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 156520459ee2SKalle Valo if (ret) { 156620459ee2SKalle Valo /* FIXME: call this */ 156720459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 156820459ee2SKalle Valo goto err_cleanup_scatter; 156920459ee2SKalle Valo } 157020459ee2SKalle Valo 157120459ee2SKalle Valo /* Wait for Wmi event to be ready */ 157220459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 157320459ee2SKalle Valo test_bit(WMI_READY, 157420459ee2SKalle Valo &ar->flag), 157520459ee2SKalle Valo WMI_TIMEOUT); 157620459ee2SKalle Valo 157720459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 157820459ee2SKalle Valo 1579293badf4SKalle Valo 1580293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 158165a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1582293badf4SKalle Valo ar->hw.name, 1583293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1584293badf4SKalle Valo ar->wiphy->fw_version, 158565a8b4ccSKalle Valo ar->fw_api, 1586293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1587293badf4SKalle Valo } 1588293badf4SKalle Valo 158920459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 159020459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 159120459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 159220459ee2SKalle Valo ret = -EIO; 159320459ee2SKalle Valo goto err_htc_stop; 159420459ee2SKalle Valo } 159520459ee2SKalle Valo 159620459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 159720459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 159820459ee2SKalle Valo ret = -EIO; 159920459ee2SKalle Valo goto err_htc_stop; 160020459ee2SKalle Valo } 160120459ee2SKalle Valo 160220459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 160320459ee2SKalle Valo 160420459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 160520459ee2SKalle Valo /* FIXME: return error */ 160620459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 160720459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 160820459ee2SKalle Valo 160971f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 161020459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 161120459ee2SKalle Valo if (ret) 161220459ee2SKalle Valo goto err_htc_stop; 161320459ee2SKalle Valo } 161420459ee2SKalle Valo 161576a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 161676a9fbe2SKalle Valo 161720459ee2SKalle Valo return 0; 161820459ee2SKalle Valo 161920459ee2SKalle Valo err_htc_stop: 162020459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 162120459ee2SKalle Valo err_cleanup_scatter: 162220459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 162320459ee2SKalle Valo err_power_off: 162420459ee2SKalle Valo ath6kl_hif_power_off(ar); 162520459ee2SKalle Valo 162620459ee2SKalle Valo return ret; 162720459ee2SKalle Valo } 162820459ee2SKalle Valo 16295fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 16305fe4dffbSKalle Valo { 16315fe4dffbSKalle Valo int ret; 16325fe4dffbSKalle Valo 16335fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 16345fe4dffbSKalle Valo 16355fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 16365fe4dffbSKalle Valo 16375fe4dffbSKalle Valo ath6kl_hif_stop(ar); 16385fe4dffbSKalle Valo 16395fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 16405fe4dffbSKalle Valo 16415fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 16425fe4dffbSKalle Valo if (ret) 16435fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 16445fe4dffbSKalle Valo 164576a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 164676a9fbe2SKalle Valo 16475fe4dffbSKalle Valo return 0; 16485fe4dffbSKalle Valo } 16495fe4dffbSKalle Valo 1650c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ 165155055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 16526db8fa53SVasanthakumar Thiagarajan { 16536db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 16546db8fa53SVasanthakumar Thiagarajan bool discon_issued; 16556db8fa53SVasanthakumar Thiagarajan 16566db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 16576db8fa53SVasanthakumar Thiagarajan 16586db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 16596db8fa53SVasanthakumar Thiagarajan 16606db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 16616db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 16626db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 16636db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 16646db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 16656db8fa53SVasanthakumar Thiagarajan 16666db8fa53SVasanthakumar Thiagarajan if (discon_issued) 16676db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 16686db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 16696db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 16706db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 16716db8fa53SVasanthakumar Thiagarajan } 16726db8fa53SVasanthakumar Thiagarajan 16736db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 16746db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 16756db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 16766db8fa53SVasanthakumar Thiagarajan } 16776db8fa53SVasanthakumar Thiagarajan } 16786db8fa53SVasanthakumar Thiagarajan 1679bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1680bdcd8170SKalle Valo { 1681990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 16821d2a4456SVasanthakumar Thiagarajan int i; 1683bdcd8170SKalle Valo 1684bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1685bdcd8170SKalle Valo 1686bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1687bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1688bdcd8170SKalle Valo return; 1689bdcd8170SKalle Valo } 1690bdcd8170SKalle Valo 16911d2a4456SVasanthakumar Thiagarajan for (i = 0; i < AP_MAX_NUM_STA; i++) 16921d2a4456SVasanthakumar Thiagarajan aggr_reset_state(ar->sta_list[i].aggr_conn); 16931d2a4456SVasanthakumar Thiagarajan 169411f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1695990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1696990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 169711f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1698990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 169927929723SVasanthakumar Thiagarajan rtnl_lock(); 1700c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif); 170127929723SVasanthakumar Thiagarajan rtnl_unlock(); 170211f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1703990bd915SVasanthakumar Thiagarajan } 170411f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1705bdcd8170SKalle Valo 17066db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 17076db8fa53SVasanthakumar Thiagarajan 17086db8fa53SVasanthakumar Thiagarajan /* 17096db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 17106db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 17116db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 17126db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 17136db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 17146db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 17156db8fa53SVasanthakumar Thiagarajan * are collected. 17166db8fa53SVasanthakumar Thiagarajan */ 17176db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 17186db8fa53SVasanthakumar Thiagarajan 17196db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 17206db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 17216db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 17226db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1723bdcd8170SKalle Valo } 1724bdcd8170SKalle Valo 1725bdcd8170SKalle Valo /* 17266db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 17276db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1728bdcd8170SKalle Valo */ 17296db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 17306db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 17316db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1732bdcd8170SKalle Valo 17336db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1734bdcd8170SKalle Valo } 1735d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_stop_txrx); 1736