1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #ifndef HIF_H 18bdcd8170SKalle Valo #define HIF_H 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo #include "common.h" 21bdcd8170SKalle Valo #include "core.h" 22bdcd8170SKalle Valo 23bdcd8170SKalle Valo #include <linux/scatterlist.h> 24bdcd8170SKalle Valo 25bdcd8170SKalle Valo #define BUS_REQUEST_MAX_NUM 64 26bdcd8170SKalle Valo #define HIF_MBOX_BLOCK_SIZE 128 27bdcd8170SKalle Valo #define HIF_MBOX0_BLOCK_SIZE 1 28bdcd8170SKalle Valo 29bdcd8170SKalle Valo #define HIF_DMA_BUFFER_SIZE (32 * 1024) 30bdcd8170SKalle Valo #define CMD53_FIXED_ADDRESS 1 31bdcd8170SKalle Valo #define CMD53_INCR_ADDRESS 2 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo #define MAX_SCATTER_REQUESTS 4 34bdcd8170SKalle Valo #define MAX_SCATTER_ENTRIES_PER_REQ 16 35bdcd8170SKalle Valo #define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024) 36bdcd8170SKalle Valo 37bdcd8170SKalle Valo #define MANUFACTURER_ID_AR6003_BASE 0x300 38bdcd8170SKalle Valo /* SDIO manufacturer ID and Codes */ 39bdcd8170SKalle Valo #define MANUFACTURER_ID_ATH6KL_BASE_MASK 0xFF00 40bdcd8170SKalle Valo #define MANUFACTURER_CODE 0x271 /* Atheros */ 41bdcd8170SKalle Valo 42bdcd8170SKalle Valo /* Mailbox address in SDIO address space */ 43bdcd8170SKalle Valo #define HIF_MBOX_BASE_ADDR 0x800 44bdcd8170SKalle Valo #define HIF_MBOX_WIDTH 0x800 45bdcd8170SKalle Valo 46bdcd8170SKalle Valo #define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1) 47bdcd8170SKalle Valo 48bdcd8170SKalle Valo /* version 1 of the chip has only a 12K extended mbox range */ 49bdcd8170SKalle Valo #define HIF_MBOX0_EXT_BASE_ADDR 0x4000 50bdcd8170SKalle Valo #define HIF_MBOX0_EXT_WIDTH (12*1024) 51bdcd8170SKalle Valo 52bdcd8170SKalle Valo /* GMBOX addresses */ 53bdcd8170SKalle Valo #define HIF_GMBOX_BASE_ADDR 0x7000 54bdcd8170SKalle Valo #define HIF_GMBOX_WIDTH 0x4000 55bdcd8170SKalle Valo 56bdcd8170SKalle Valo /* interrupt mode register */ 57bdcd8170SKalle Valo #define CCCR_SDIO_IRQ_MODE_REG 0xF0 58bdcd8170SKalle Valo 59bdcd8170SKalle Valo /* mode to enable special 4-bit interrupt assertion without clock */ 60bdcd8170SKalle Valo #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) 61bdcd8170SKalle Valo 622e1cb23cSKalle Valo /* HTC runs over mailbox 0 */ 632e1cb23cSKalle Valo #define HTC_MAILBOX 0 642e1cb23cSKalle Valo 652e1cb23cSKalle Valo #define ATH6KL_TARGET_DEBUG_INTR_MASK 0x01 662e1cb23cSKalle Valo 672e1cb23cSKalle Valo /* FIXME: are these duplicates with MAX_SCATTER_ values in hif.h? */ 682e1cb23cSKalle Valo #define ATH6KL_SCATTER_ENTRIES_PER_REQ 16 692e1cb23cSKalle Valo #define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER (16 * 1024) 702e1cb23cSKalle Valo #define ATH6KL_SCATTER_REQS 4 712e1cb23cSKalle Valo 72d60e8ab6SKalle Valo #define ATH6KL_HIF_COMMUNICATION_TIMEOUT 1000 73d60e8ab6SKalle Valo 74bdcd8170SKalle Valo struct bus_request { 75bdcd8170SKalle Valo struct list_head list; 76bdcd8170SKalle Valo 77bdcd8170SKalle Valo /* request data */ 78bdcd8170SKalle Valo u32 address; 79bdcd8170SKalle Valo 80bdcd8170SKalle Valo u8 *buffer; 81bdcd8170SKalle Valo u32 length; 82bdcd8170SKalle Valo u32 request; 83bdcd8170SKalle Valo struct htc_packet *packet; 84bdcd8170SKalle Valo int status; 85bdcd8170SKalle Valo 86bdcd8170SKalle Valo /* this is a scatter request */ 87bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 88bdcd8170SKalle Valo }; 89bdcd8170SKalle Valo 90bdcd8170SKalle Valo /* direction of transfer (read/write) */ 91bdcd8170SKalle Valo #define HIF_READ 0x00000001 92bdcd8170SKalle Valo #define HIF_WRITE 0x00000002 93bdcd8170SKalle Valo #define HIF_DIR_MASK (HIF_READ | HIF_WRITE) 94bdcd8170SKalle Valo 95bdcd8170SKalle Valo /* 96bdcd8170SKalle Valo * emode - This indicates the whether the command is to be executed in a 97bdcd8170SKalle Valo * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ 98bdcd8170SKalle Valo * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been 99bdcd8170SKalle Valo * implemented using the asynchronous mode allowing the the bus 100bdcd8170SKalle Valo * driver to indicate the completion of operation through the 101bdcd8170SKalle Valo * registered callback routine. The requirement primarily comes 102bdcd8170SKalle Valo * from the contexts these operations get called from (a driver's 103bdcd8170SKalle Valo * transmit context or the ISR context in case of receive). 104bdcd8170SKalle Valo * Support for both of these modes is essential. 105bdcd8170SKalle Valo */ 106bdcd8170SKalle Valo #define HIF_SYNCHRONOUS 0x00000010 107bdcd8170SKalle Valo #define HIF_ASYNCHRONOUS 0x00000020 108bdcd8170SKalle Valo #define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) 109bdcd8170SKalle Valo 110bdcd8170SKalle Valo /* 111bdcd8170SKalle Valo * dmode - An interface may support different kinds of commands based on 112bdcd8170SKalle Valo * the tradeoff between the amount of data it can carry and the 113bdcd8170SKalle Valo * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ 114bdcd8170SKalle Valo * HIF_BLOCK_BASIS). In case of latter, the data is rounded off 115bdcd8170SKalle Valo * to the nearest block size by padding. The size of the block is 116bdcd8170SKalle Valo * configurable at compile time using the HIF_BLOCK_SIZE and is 117bdcd8170SKalle Valo * negotiated with the target during initialization after the 118bdcd8170SKalle Valo * ATH6KL interrupts are enabled. 119bdcd8170SKalle Valo */ 120bdcd8170SKalle Valo #define HIF_BYTE_BASIS 0x00000040 121bdcd8170SKalle Valo #define HIF_BLOCK_BASIS 0x00000080 122bdcd8170SKalle Valo #define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) 123bdcd8170SKalle Valo 124bdcd8170SKalle Valo /* 125bdcd8170SKalle Valo * amode - This indicates if the address has to be incremented on ATH6KL 126bdcd8170SKalle Valo * after every read/write operation (HIF?FIXED_ADDRESS/ 127bdcd8170SKalle Valo * HIF_INCREMENTAL_ADDRESS). 128bdcd8170SKalle Valo */ 129bdcd8170SKalle Valo #define HIF_FIXED_ADDRESS 0x00000100 130bdcd8170SKalle Valo #define HIF_INCREMENTAL_ADDRESS 0x00000200 131bdcd8170SKalle Valo #define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) 132bdcd8170SKalle Valo 133bdcd8170SKalle Valo #define HIF_WR_ASYNC_BYTE_INC \ 134bdcd8170SKalle Valo (HIF_WRITE | HIF_ASYNCHRONOUS | \ 135bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) 136bdcd8170SKalle Valo 137bdcd8170SKalle Valo #define HIF_WR_ASYNC_BLOCK_INC \ 138bdcd8170SKalle Valo (HIF_WRITE | HIF_ASYNCHRONOUS | \ 139bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) 140bdcd8170SKalle Valo 141bdcd8170SKalle Valo #define HIF_WR_SYNC_BYTE_FIX \ 142bdcd8170SKalle Valo (HIF_WRITE | HIF_SYNCHRONOUS | \ 143bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) 144bdcd8170SKalle Valo 145bdcd8170SKalle Valo #define HIF_WR_SYNC_BYTE_INC \ 146bdcd8170SKalle Valo (HIF_WRITE | HIF_SYNCHRONOUS | \ 147bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) 148bdcd8170SKalle Valo 149bdcd8170SKalle Valo #define HIF_WR_SYNC_BLOCK_INC \ 150bdcd8170SKalle Valo (HIF_WRITE | HIF_SYNCHRONOUS | \ 151bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) 152bdcd8170SKalle Valo 153bdcd8170SKalle Valo #define HIF_RD_SYNC_BYTE_INC \ 154bdcd8170SKalle Valo (HIF_READ | HIF_SYNCHRONOUS | \ 155bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) 156bdcd8170SKalle Valo 157bdcd8170SKalle Valo #define HIF_RD_SYNC_BYTE_FIX \ 158bdcd8170SKalle Valo (HIF_READ | HIF_SYNCHRONOUS | \ 159bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) 160bdcd8170SKalle Valo 161bdcd8170SKalle Valo #define HIF_RD_ASYNC_BLOCK_FIX \ 162bdcd8170SKalle Valo (HIF_READ | HIF_ASYNCHRONOUS | \ 163bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) 164bdcd8170SKalle Valo 165bdcd8170SKalle Valo #define HIF_RD_SYNC_BLOCK_FIX \ 166bdcd8170SKalle Valo (HIF_READ | HIF_SYNCHRONOUS | \ 167bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) 168bdcd8170SKalle Valo 169bdcd8170SKalle Valo struct hif_scatter_item { 170bdcd8170SKalle Valo u8 *buf; 171bdcd8170SKalle Valo int len; 172bdcd8170SKalle Valo struct htc_packet *packet; 173bdcd8170SKalle Valo }; 174bdcd8170SKalle Valo 175bdcd8170SKalle Valo struct hif_scatter_req { 176bdcd8170SKalle Valo struct list_head list; 177bdcd8170SKalle Valo /* address for the read/write operation */ 178bdcd8170SKalle Valo u32 addr; 179bdcd8170SKalle Valo 180bdcd8170SKalle Valo /* request flags */ 181bdcd8170SKalle Valo u32 req; 182bdcd8170SKalle Valo 183bdcd8170SKalle Valo /* total length of entire transfer */ 184bdcd8170SKalle Valo u32 len; 185bdcd8170SKalle Valo 1864a005c3eSVasanthakumar Thiagarajan bool virt_scat; 1874a005c3eSVasanthakumar Thiagarajan 188e041c7f9SVasanthakumar Thiagarajan void (*complete) (struct htc_target *, struct hif_scatter_req *); 189bdcd8170SKalle Valo int status; 190bdcd8170SKalle Valo int scat_entries; 191bdcd8170SKalle Valo 192d4df7890SVasanthakumar Thiagarajan struct bus_request *busrequest; 193d4df7890SVasanthakumar Thiagarajan struct scatterlist *sgentries; 194bdcd8170SKalle Valo 195bdcd8170SKalle Valo /* bounce buffer for upper layers to copy to/from */ 196bdcd8170SKalle Valo u8 *virt_dma_buf; 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo struct hif_scatter_item scat_list[1]; 199bdcd8170SKalle Valo }; 200bdcd8170SKalle Valo 2012e1cb23cSKalle Valo struct ath6kl_irq_proc_registers { 2022e1cb23cSKalle Valo u8 host_int_status; 2032e1cb23cSKalle Valo u8 cpu_int_status; 2042e1cb23cSKalle Valo u8 error_int_status; 2052e1cb23cSKalle Valo u8 counter_int_status; 2062e1cb23cSKalle Valo u8 mbox_frame; 2072e1cb23cSKalle Valo u8 rx_lkahd_valid; 2082e1cb23cSKalle Valo u8 host_int_status2; 2092e1cb23cSKalle Valo u8 gmbox_rx_avail; 2102e1cb23cSKalle Valo __le32 rx_lkahd[2]; 2112e1cb23cSKalle Valo __le32 rx_gmbox_lkahd_alias[2]; 2122e1cb23cSKalle Valo } __packed; 2132e1cb23cSKalle Valo 2142e1cb23cSKalle Valo struct ath6kl_irq_enable_reg { 2152e1cb23cSKalle Valo u8 int_status_en; 2162e1cb23cSKalle Valo u8 cpu_int_status_en; 2172e1cb23cSKalle Valo u8 err_int_status_en; 2182e1cb23cSKalle Valo u8 cntr_int_status_en; 2192e1cb23cSKalle Valo } __packed; 2202e1cb23cSKalle Valo 2212e1cb23cSKalle Valo struct ath6kl_device { 2222e1cb23cSKalle Valo spinlock_t lock; 2232e1cb23cSKalle Valo struct ath6kl_irq_proc_registers irq_proc_reg; 2242e1cb23cSKalle Valo struct ath6kl_irq_enable_reg irq_en_reg; 2252e1cb23cSKalle Valo struct htc_target *htc_cnxt; 2262e1cb23cSKalle Valo struct ath6kl *ar; 2272e1cb23cSKalle Valo }; 2282e1cb23cSKalle Valo 229bdcd8170SKalle Valo struct ath6kl_hif_ops { 230bdcd8170SKalle Valo int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf, 231bdcd8170SKalle Valo u32 len, u32 request); 232bdcd8170SKalle Valo int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer, 233bdcd8170SKalle Valo u32 length, u32 request, struct htc_packet *packet); 234bdcd8170SKalle Valo 235bdcd8170SKalle Valo void (*irq_enable)(struct ath6kl *ar); 236bdcd8170SKalle Valo void (*irq_disable)(struct ath6kl *ar); 237bdcd8170SKalle Valo 238bdcd8170SKalle Valo struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar); 239bdcd8170SKalle Valo void (*scatter_req_add)(struct ath6kl *ar, 240bdcd8170SKalle Valo struct hif_scatter_req *s_req); 24150745af7SVasanthakumar Thiagarajan int (*enable_scatter)(struct ath6kl *ar); 242f74a7361SVasanthakumar Thiagarajan int (*scat_req_rw) (struct ath6kl *ar, 243f74a7361SVasanthakumar Thiagarajan struct hif_scatter_req *scat_req); 244bdcd8170SKalle Valo void (*cleanup_scatter)(struct ath6kl *ar); 2450f60e9f4SRaja Mani int (*suspend)(struct ath6kl *ar, struct cfg80211_wowlan *wow); 246aa6cffc1SChilam Ng int (*resume)(struct ath6kl *ar); 24766b693c3SKalle Valo int (*bmi_read)(struct ath6kl *ar, u8 *buf, u32 len); 24866b693c3SKalle Valo int (*bmi_write)(struct ath6kl *ar, u8 *buf, u32 len); 249b2e75698SKalle Valo int (*power_on)(struct ath6kl *ar); 250b2e75698SKalle Valo int (*power_off)(struct ath6kl *ar); 25132a07e44SKalle Valo void (*stop)(struct ath6kl *ar); 252bdcd8170SKalle Valo }; 253bdcd8170SKalle Valo 2542e1cb23cSKalle Valo int ath6kl_hif_setup(struct ath6kl_device *dev); 2552e1cb23cSKalle Valo int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev); 2562e1cb23cSKalle Valo int ath6kl_hif_mask_intrs(struct ath6kl_device *dev); 2572e1cb23cSKalle Valo int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, 2582e1cb23cSKalle Valo u32 *lk_ahd, int timeout); 2592e1cb23cSKalle Valo int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx); 2602e1cb23cSKalle Valo int ath6kl_hif_disable_intrs(struct ath6kl_device *dev); 2612e1cb23cSKalle Valo 2622e1cb23cSKalle Valo int ath6kl_hif_rw_comp_handler(void *context, int status); 2632e1cb23cSKalle Valo int ath6kl_hif_intr_bh_handler(struct ath6kl *ar); 2642e1cb23cSKalle Valo 2652e1cb23cSKalle Valo /* Scatter Function and Definitions */ 2662e1cb23cSKalle Valo int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, 2672e1cb23cSKalle Valo struct hif_scatter_req *scat_req, bool read); 2682e1cb23cSKalle Valo 269bdcd8170SKalle Valo #endif 270