1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #ifndef HIF_H 18bdcd8170SKalle Valo #define HIF_H 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo #include "common.h" 21bdcd8170SKalle Valo #include "core.h" 22bdcd8170SKalle Valo 23bdcd8170SKalle Valo #include <linux/scatterlist.h> 24bdcd8170SKalle Valo 25bdcd8170SKalle Valo #define BUS_REQUEST_MAX_NUM 64 26bdcd8170SKalle Valo #define HIF_MBOX_BLOCK_SIZE 128 27bdcd8170SKalle Valo #define HIF_MBOX0_BLOCK_SIZE 1 28bdcd8170SKalle Valo 29bdcd8170SKalle Valo #define HIF_DMA_BUFFER_SIZE (32 * 1024) 30bdcd8170SKalle Valo #define CMD53_FIXED_ADDRESS 1 31bdcd8170SKalle Valo #define CMD53_INCR_ADDRESS 2 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo #define MAX_SCATTER_REQUESTS 4 34bdcd8170SKalle Valo #define MAX_SCATTER_ENTRIES_PER_REQ 16 35bdcd8170SKalle Valo #define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024) 36bdcd8170SKalle Valo 37bdcd8170SKalle Valo #define MANUFACTURER_ID_AR6003_BASE 0x300 38bdcd8170SKalle Valo /* SDIO manufacturer ID and Codes */ 39bdcd8170SKalle Valo #define MANUFACTURER_ID_ATH6KL_BASE_MASK 0xFF00 40bdcd8170SKalle Valo #define MANUFACTURER_CODE 0x271 /* Atheros */ 41bdcd8170SKalle Valo 42bdcd8170SKalle Valo /* Mailbox address in SDIO address space */ 43bdcd8170SKalle Valo #define HIF_MBOX_BASE_ADDR 0x800 44bdcd8170SKalle Valo #define HIF_MBOX_WIDTH 0x800 45bdcd8170SKalle Valo 46bdcd8170SKalle Valo #define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1) 47bdcd8170SKalle Valo 48bdcd8170SKalle Valo /* version 1 of the chip has only a 12K extended mbox range */ 49bdcd8170SKalle Valo #define HIF_MBOX0_EXT_BASE_ADDR 0x4000 50bdcd8170SKalle Valo #define HIF_MBOX0_EXT_WIDTH (12*1024) 51bdcd8170SKalle Valo 52bdcd8170SKalle Valo /* GMBOX addresses */ 53bdcd8170SKalle Valo #define HIF_GMBOX_BASE_ADDR 0x7000 54bdcd8170SKalle Valo #define HIF_GMBOX_WIDTH 0x4000 55bdcd8170SKalle Valo 56bdcd8170SKalle Valo /* interrupt mode register */ 57bdcd8170SKalle Valo #define CCCR_SDIO_IRQ_MODE_REG 0xF0 58bdcd8170SKalle Valo 59bdcd8170SKalle Valo /* mode to enable special 4-bit interrupt assertion without clock */ 60bdcd8170SKalle Valo #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo struct bus_request { 63bdcd8170SKalle Valo struct list_head list; 64bdcd8170SKalle Valo 65bdcd8170SKalle Valo /* request data */ 66bdcd8170SKalle Valo u32 address; 67bdcd8170SKalle Valo 68bdcd8170SKalle Valo u8 *buffer; 69bdcd8170SKalle Valo u32 length; 70bdcd8170SKalle Valo u32 request; 71bdcd8170SKalle Valo struct htc_packet *packet; 72bdcd8170SKalle Valo int status; 73bdcd8170SKalle Valo 74bdcd8170SKalle Valo /* this is a scatter request */ 75bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 76bdcd8170SKalle Valo }; 77bdcd8170SKalle Valo 78bdcd8170SKalle Valo /* direction of transfer (read/write) */ 79bdcd8170SKalle Valo #define HIF_READ 0x00000001 80bdcd8170SKalle Valo #define HIF_WRITE 0x00000002 81bdcd8170SKalle Valo #define HIF_DIR_MASK (HIF_READ | HIF_WRITE) 82bdcd8170SKalle Valo 83bdcd8170SKalle Valo /* 84bdcd8170SKalle Valo * emode - This indicates the whether the command is to be executed in a 85bdcd8170SKalle Valo * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ 86bdcd8170SKalle Valo * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been 87bdcd8170SKalle Valo * implemented using the asynchronous mode allowing the the bus 88bdcd8170SKalle Valo * driver to indicate the completion of operation through the 89bdcd8170SKalle Valo * registered callback routine. The requirement primarily comes 90bdcd8170SKalle Valo * from the contexts these operations get called from (a driver's 91bdcd8170SKalle Valo * transmit context or the ISR context in case of receive). 92bdcd8170SKalle Valo * Support for both of these modes is essential. 93bdcd8170SKalle Valo */ 94bdcd8170SKalle Valo #define HIF_SYNCHRONOUS 0x00000010 95bdcd8170SKalle Valo #define HIF_ASYNCHRONOUS 0x00000020 96bdcd8170SKalle Valo #define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) 97bdcd8170SKalle Valo 98bdcd8170SKalle Valo /* 99bdcd8170SKalle Valo * dmode - An interface may support different kinds of commands based on 100bdcd8170SKalle Valo * the tradeoff between the amount of data it can carry and the 101bdcd8170SKalle Valo * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ 102bdcd8170SKalle Valo * HIF_BLOCK_BASIS). In case of latter, the data is rounded off 103bdcd8170SKalle Valo * to the nearest block size by padding. The size of the block is 104bdcd8170SKalle Valo * configurable at compile time using the HIF_BLOCK_SIZE and is 105bdcd8170SKalle Valo * negotiated with the target during initialization after the 106bdcd8170SKalle Valo * ATH6KL interrupts are enabled. 107bdcd8170SKalle Valo */ 108bdcd8170SKalle Valo #define HIF_BYTE_BASIS 0x00000040 109bdcd8170SKalle Valo #define HIF_BLOCK_BASIS 0x00000080 110bdcd8170SKalle Valo #define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) 111bdcd8170SKalle Valo 112bdcd8170SKalle Valo /* 113bdcd8170SKalle Valo * amode - This indicates if the address has to be incremented on ATH6KL 114bdcd8170SKalle Valo * after every read/write operation (HIF?FIXED_ADDRESS/ 115bdcd8170SKalle Valo * HIF_INCREMENTAL_ADDRESS). 116bdcd8170SKalle Valo */ 117bdcd8170SKalle Valo #define HIF_FIXED_ADDRESS 0x00000100 118bdcd8170SKalle Valo #define HIF_INCREMENTAL_ADDRESS 0x00000200 119bdcd8170SKalle Valo #define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) 120bdcd8170SKalle Valo 121bdcd8170SKalle Valo #define HIF_WR_ASYNC_BYTE_INC \ 122bdcd8170SKalle Valo (HIF_WRITE | HIF_ASYNCHRONOUS | \ 123bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) 124bdcd8170SKalle Valo 125bdcd8170SKalle Valo #define HIF_WR_ASYNC_BLOCK_INC \ 126bdcd8170SKalle Valo (HIF_WRITE | HIF_ASYNCHRONOUS | \ 127bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) 128bdcd8170SKalle Valo 129bdcd8170SKalle Valo #define HIF_WR_SYNC_BYTE_FIX \ 130bdcd8170SKalle Valo (HIF_WRITE | HIF_SYNCHRONOUS | \ 131bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) 132bdcd8170SKalle Valo 133bdcd8170SKalle Valo #define HIF_WR_SYNC_BYTE_INC \ 134bdcd8170SKalle Valo (HIF_WRITE | HIF_SYNCHRONOUS | \ 135bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) 136bdcd8170SKalle Valo 137bdcd8170SKalle Valo #define HIF_WR_SYNC_BLOCK_INC \ 138bdcd8170SKalle Valo (HIF_WRITE | HIF_SYNCHRONOUS | \ 139bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) 140bdcd8170SKalle Valo 141bdcd8170SKalle Valo #define HIF_RD_SYNC_BYTE_INC \ 142bdcd8170SKalle Valo (HIF_READ | HIF_SYNCHRONOUS | \ 143bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) 144bdcd8170SKalle Valo 145bdcd8170SKalle Valo #define HIF_RD_SYNC_BYTE_FIX \ 146bdcd8170SKalle Valo (HIF_READ | HIF_SYNCHRONOUS | \ 147bdcd8170SKalle Valo HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) 148bdcd8170SKalle Valo 149bdcd8170SKalle Valo #define HIF_RD_ASYNC_BLOCK_FIX \ 150bdcd8170SKalle Valo (HIF_READ | HIF_ASYNCHRONOUS | \ 151bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) 152bdcd8170SKalle Valo 153bdcd8170SKalle Valo #define HIF_RD_SYNC_BLOCK_FIX \ 154bdcd8170SKalle Valo (HIF_READ | HIF_SYNCHRONOUS | \ 155bdcd8170SKalle Valo HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) 156bdcd8170SKalle Valo 157bdcd8170SKalle Valo struct hif_scatter_item { 158bdcd8170SKalle Valo u8 *buf; 159bdcd8170SKalle Valo int len; 160bdcd8170SKalle Valo struct htc_packet *packet; 161bdcd8170SKalle Valo }; 162bdcd8170SKalle Valo 163bdcd8170SKalle Valo struct hif_scatter_req { 164bdcd8170SKalle Valo struct list_head list; 165bdcd8170SKalle Valo /* address for the read/write operation */ 166bdcd8170SKalle Valo u32 addr; 167bdcd8170SKalle Valo 168bdcd8170SKalle Valo /* request flags */ 169bdcd8170SKalle Valo u32 req; 170bdcd8170SKalle Valo 171bdcd8170SKalle Valo /* total length of entire transfer */ 172bdcd8170SKalle Valo u32 len; 173bdcd8170SKalle Valo 1744a005c3eSVasanthakumar Thiagarajan bool virt_scat; 1754a005c3eSVasanthakumar Thiagarajan 176e041c7f9SVasanthakumar Thiagarajan void (*complete) (struct htc_target *, struct hif_scatter_req *); 177bdcd8170SKalle Valo int status; 178bdcd8170SKalle Valo int scat_entries; 179bdcd8170SKalle Valo 180d4df7890SVasanthakumar Thiagarajan struct bus_request *busrequest; 181d4df7890SVasanthakumar Thiagarajan struct scatterlist *sgentries; 182bdcd8170SKalle Valo 183bdcd8170SKalle Valo /* bounce buffer for upper layers to copy to/from */ 184bdcd8170SKalle Valo u8 *virt_dma_buf; 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo struct hif_scatter_item scat_list[1]; 187bdcd8170SKalle Valo }; 188bdcd8170SKalle Valo 189bdcd8170SKalle Valo struct ath6kl_hif_ops { 190bdcd8170SKalle Valo int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf, 191bdcd8170SKalle Valo u32 len, u32 request); 192bdcd8170SKalle Valo int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer, 193bdcd8170SKalle Valo u32 length, u32 request, struct htc_packet *packet); 194bdcd8170SKalle Valo 195bdcd8170SKalle Valo void (*irq_enable)(struct ath6kl *ar); 196bdcd8170SKalle Valo void (*irq_disable)(struct ath6kl *ar); 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar); 199bdcd8170SKalle Valo void (*scatter_req_add)(struct ath6kl *ar, 200bdcd8170SKalle Valo struct hif_scatter_req *s_req); 20150745af7SVasanthakumar Thiagarajan int (*enable_scatter)(struct ath6kl *ar); 202f74a7361SVasanthakumar Thiagarajan int (*scat_req_rw) (struct ath6kl *ar, 203f74a7361SVasanthakumar Thiagarajan struct hif_scatter_req *scat_req); 204bdcd8170SKalle Valo void (*cleanup_scatter)(struct ath6kl *ar); 205bdcd8170SKalle Valo }; 206bdcd8170SKalle Valo 207bdcd8170SKalle Valo #endif 208