1 /* 2 * Copyright (c) 2007-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #include "hif.h" 17 18 #include "core.h" 19 #include "target.h" 20 #include "hif-ops.h" 21 #include "debug.h" 22 23 #define MAILBOX_FOR_BLOCK_SIZE 1 24 25 #define ATH6KL_TIME_QUANTUM 10 /* in ms */ 26 27 static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req, 28 bool from_dma) 29 { 30 u8 *buf; 31 int i; 32 33 buf = req->virt_dma_buf; 34 35 for (i = 0; i < req->scat_entries; i++) { 36 37 if (from_dma) 38 memcpy(req->scat_list[i].buf, buf, 39 req->scat_list[i].len); 40 else 41 memcpy(buf, req->scat_list[i].buf, 42 req->scat_list[i].len); 43 44 buf += req->scat_list[i].len; 45 } 46 47 return 0; 48 } 49 50 int ath6kl_hif_rw_comp_handler(void *context, int status) 51 { 52 struct htc_packet *packet = context; 53 54 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n", 55 packet, status); 56 57 packet->status = status; 58 packet->completion(packet->context, packet); 59 60 return 0; 61 } 62 #define REG_DUMP_COUNT_AR6003 60 63 #define REGISTER_DUMP_LEN_MAX 60 64 65 static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar) 66 { 67 __le32 regdump_val[REGISTER_DUMP_LEN_MAX]; 68 u32 i, address, regdump_addr = 0; 69 int ret; 70 71 if (ar->target_type != TARGET_TYPE_AR6003) 72 return; 73 74 /* the reg dump pointer is copied to the host interest area */ 75 address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state)); 76 address = TARG_VTOP(ar->target_type, address); 77 78 /* read RAM location through diagnostic window */ 79 ret = ath6kl_diag_read32(ar, address, ®dump_addr); 80 81 if (ret || !regdump_addr) { 82 ath6kl_warn("failed to get ptr to register dump area: %d\n", 83 ret); 84 return; 85 } 86 87 ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n", 88 regdump_addr); 89 regdump_addr = TARG_VTOP(ar->target_type, regdump_addr); 90 91 /* fetch register dump data */ 92 ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0], 93 REG_DUMP_COUNT_AR6003 * (sizeof(u32))); 94 if (ret) { 95 ath6kl_warn("failed to get register dump: %d\n", ret); 96 return; 97 } 98 99 ath6kl_info("crash dump:\n"); 100 ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version, 101 ar->wiphy->fw_version); 102 103 BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4); 104 105 for (i = 0; i < REG_DUMP_COUNT_AR6003 / 4; i++) { 106 ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n", 107 4 * i, 108 le32_to_cpu(regdump_val[i]), 109 le32_to_cpu(regdump_val[i + 1]), 110 le32_to_cpu(regdump_val[i + 2]), 111 le32_to_cpu(regdump_val[i + 3])); 112 } 113 114 } 115 116 static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev) 117 { 118 u32 dummy; 119 int ret; 120 121 ath6kl_warn("firmware crashed\n"); 122 123 /* 124 * read counter to clear the interrupt, the debug error interrupt is 125 * counter 0. 126 */ 127 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, 128 (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC); 129 if (ret) 130 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret); 131 132 ath6kl_hif_dump_fw_crash(dev->ar); 133 134 return ret; 135 } 136 137 /* mailbox recv message polling */ 138 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd, 139 int timeout) 140 { 141 struct ath6kl_irq_proc_registers *rg; 142 int status = 0, i; 143 u8 htc_mbox = 1 << HTC_MAILBOX; 144 145 for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { 146 /* this is the standard HIF way, load the reg table */ 147 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 148 (u8 *) &dev->irq_proc_reg, 149 sizeof(dev->irq_proc_reg), 150 HIF_RD_SYNC_BYTE_INC); 151 152 if (status) { 153 ath6kl_err("failed to read reg table\n"); 154 return status; 155 } 156 157 /* check for MBOX data and valid lookahead */ 158 if (dev->irq_proc_reg.host_int_status & htc_mbox) { 159 if (dev->irq_proc_reg.rx_lkahd_valid & 160 htc_mbox) { 161 /* 162 * Mailbox has a message and the look ahead 163 * is valid. 164 */ 165 rg = &dev->irq_proc_reg; 166 *lk_ahd = 167 le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 168 break; 169 } 170 } 171 172 /* delay a little */ 173 mdelay(ATH6KL_TIME_QUANTUM); 174 ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i); 175 } 176 177 if (i == 0) { 178 ath6kl_err("timeout waiting for recv message\n"); 179 status = -ETIME; 180 /* check if the target asserted */ 181 if (dev->irq_proc_reg.counter_int_status & 182 ATH6KL_TARGET_DEBUG_INTR_MASK) 183 /* 184 * Target failure handler will be called in case of 185 * an assert. 186 */ 187 ath6kl_hif_proc_dbg_intr(dev); 188 } 189 190 return status; 191 } 192 193 /* 194 * Disable packet reception (used in case the host runs out of buffers) 195 * using the interrupt enable registers through the host I/F 196 */ 197 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx) 198 { 199 struct ath6kl_irq_enable_reg regs; 200 int status = 0; 201 202 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n", 203 enable_rx ? "enable" : "disable"); 204 205 /* take the lock to protect interrupt enable shadows */ 206 spin_lock_bh(&dev->lock); 207 208 if (enable_rx) 209 dev->irq_en_reg.int_status_en |= 210 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 211 else 212 dev->irq_en_reg.int_status_en &= 213 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 214 215 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 216 217 spin_unlock_bh(&dev->lock); 218 219 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 220 ®s.int_status_en, 221 sizeof(struct ath6kl_irq_enable_reg), 222 HIF_WR_SYNC_BYTE_INC); 223 224 return status; 225 } 226 227 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, 228 struct hif_scatter_req *scat_req, bool read) 229 { 230 int status = 0; 231 232 if (read) { 233 scat_req->req = HIF_RD_SYNC_BLOCK_FIX; 234 scat_req->addr = dev->ar->mbox_info.htc_addr; 235 } else { 236 scat_req->req = HIF_WR_ASYNC_BLOCK_INC; 237 238 scat_req->addr = 239 (scat_req->len > HIF_MBOX_WIDTH) ? 240 dev->ar->mbox_info.htc_ext_addr : 241 dev->ar->mbox_info.htc_addr; 242 } 243 244 ath6kl_dbg(ATH6KL_DBG_HIF, 245 "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n", 246 scat_req->scat_entries, scat_req->len, 247 scat_req->addr, !read ? "async" : "sync", 248 (read) ? "rd" : "wr"); 249 250 if (!read && scat_req->virt_scat) { 251 status = ath6kl_hif_cp_scat_dma_buf(scat_req, false); 252 if (status) { 253 scat_req->status = status; 254 scat_req->complete(dev->ar->htc_target, scat_req); 255 return 0; 256 } 257 } 258 259 status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); 260 261 if (read) { 262 /* in sync mode, we can touch the scatter request */ 263 scat_req->status = status; 264 if (!status && scat_req->virt_scat) 265 scat_req->status = 266 ath6kl_hif_cp_scat_dma_buf(scat_req, true); 267 } 268 269 return status; 270 } 271 272 static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev) 273 { 274 u8 counter_int_status; 275 276 ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n"); 277 278 counter_int_status = dev->irq_proc_reg.counter_int_status & 279 dev->irq_en_reg.cntr_int_status_en; 280 281 ath6kl_dbg(ATH6KL_DBG_IRQ, 282 "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", 283 counter_int_status); 284 285 /* 286 * NOTE: other modules like GMBOX may use the counter interrupt for 287 * credit flow control on other counters, we only need to check for 288 * the debug assertion counter interrupt. 289 */ 290 if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK) 291 return ath6kl_hif_proc_dbg_intr(dev); 292 293 return 0; 294 } 295 296 static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev) 297 { 298 int status; 299 u8 error_int_status; 300 u8 reg_buf[4]; 301 302 ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n"); 303 304 error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; 305 if (!error_int_status) { 306 WARN_ON(1); 307 return -EIO; 308 } 309 310 ath6kl_dbg(ATH6KL_DBG_IRQ, 311 "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", 312 error_int_status); 313 314 if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) 315 ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n"); 316 317 if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) 318 ath6kl_err("rx underflow\n"); 319 320 if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) 321 ath6kl_err("tx overflow\n"); 322 323 /* Clear the interrupt */ 324 dev->irq_proc_reg.error_int_status &= ~error_int_status; 325 326 /* set W1C value to clear the interrupt, this hits the register first */ 327 reg_buf[0] = error_int_status; 328 reg_buf[1] = 0; 329 reg_buf[2] = 0; 330 reg_buf[3] = 0; 331 332 status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, 333 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 334 335 if (status) 336 WARN_ON(1); 337 338 return status; 339 } 340 341 static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev) 342 { 343 int status; 344 u8 cpu_int_status; 345 u8 reg_buf[4]; 346 347 ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n"); 348 349 cpu_int_status = dev->irq_proc_reg.cpu_int_status & 350 dev->irq_en_reg.cpu_int_status_en; 351 if (!cpu_int_status) { 352 WARN_ON(1); 353 return -EIO; 354 } 355 356 ath6kl_dbg(ATH6KL_DBG_IRQ, 357 "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", 358 cpu_int_status); 359 360 /* Clear the interrupt */ 361 dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; 362 363 /* 364 * Set up the register transfer buffer to hit the register 4 times , 365 * this is done to make the access 4-byte aligned to mitigate issues 366 * with host bus interconnects that restrict bus transfer lengths to 367 * be a multiple of 4-bytes. 368 */ 369 370 /* set W1C value to clear the interrupt, this hits the register first */ 371 reg_buf[0] = cpu_int_status; 372 /* the remaining are set to zero which have no-effect */ 373 reg_buf[1] = 0; 374 reg_buf[2] = 0; 375 reg_buf[3] = 0; 376 377 status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, 378 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 379 380 if (status) 381 WARN_ON(1); 382 383 return status; 384 } 385 386 /* process pending interrupts synchronously */ 387 static int proc_pending_irqs(struct ath6kl_device *dev, bool *done) 388 { 389 struct ath6kl_irq_proc_registers *rg; 390 int status = 0; 391 u8 host_int_status = 0; 392 u32 lk_ahd = 0; 393 u8 htc_mbox = 1 << HTC_MAILBOX; 394 395 ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev); 396 397 /* 398 * NOTE: HIF implementation guarantees that the context of this 399 * call allows us to perform SYNCHRONOUS I/O, that is we can block, 400 * sleep or call any API that can block or switch thread/task 401 * contexts. This is a fully schedulable context. 402 */ 403 404 /* 405 * Process pending intr only when int_status_en is clear, it may 406 * result in unnecessary bus transaction otherwise. Target may be 407 * unresponsive at the time. 408 */ 409 if (dev->irq_en_reg.int_status_en) { 410 /* 411 * Read the first 28 bytes of the HTC register table. This 412 * will yield us the value of different int status 413 * registers and the lookahead registers. 414 * 415 * length = sizeof(int_status) + sizeof(cpu_int_status) 416 * + sizeof(error_int_status) + 417 * sizeof(counter_int_status) + 418 * sizeof(mbox_frame) + sizeof(rx_lkahd_valid) 419 * + sizeof(hole) + sizeof(rx_lkahd) + 420 * sizeof(int_status_en) + 421 * sizeof(cpu_int_status_en) + 422 * sizeof(err_int_status_en) + 423 * sizeof(cntr_int_status_en); 424 */ 425 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 426 (u8 *) &dev->irq_proc_reg, 427 sizeof(dev->irq_proc_reg), 428 HIF_RD_SYNC_BYTE_INC); 429 if (status) 430 goto out; 431 432 if (AR_DBG_LVL_CHECK(ATH6KL_DBG_IRQ)) 433 ath6kl_dump_registers(dev, &dev->irq_proc_reg, 434 &dev->irq_en_reg); 435 436 /* Update only those registers that are enabled */ 437 host_int_status = dev->irq_proc_reg.host_int_status & 438 dev->irq_en_reg.int_status_en; 439 440 /* Look at mbox status */ 441 if (host_int_status & htc_mbox) { 442 /* 443 * Mask out pending mbox value, we use "lookAhead as 444 * the real flag for mbox processing. 445 */ 446 host_int_status &= ~htc_mbox; 447 if (dev->irq_proc_reg.rx_lkahd_valid & 448 htc_mbox) { 449 rg = &dev->irq_proc_reg; 450 lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 451 if (!lk_ahd) 452 ath6kl_err("lookAhead is zero!\n"); 453 } 454 } 455 } 456 457 if (!host_int_status && !lk_ahd) { 458 *done = true; 459 goto out; 460 } 461 462 if (lk_ahd) { 463 int fetched = 0; 464 465 ath6kl_dbg(ATH6KL_DBG_IRQ, 466 "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd); 467 /* 468 * Mailbox Interrupt, the HTC layer may issue async 469 * requests to empty the mailbox. When emptying the recv 470 * mailbox we use the async handler above called from the 471 * completion routine of the callers read request. This can 472 * improve performance by reducing context switching when 473 * we rapidly pull packets. 474 */ 475 status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, 476 lk_ahd, &fetched); 477 if (status) 478 goto out; 479 480 if (!fetched) 481 /* 482 * HTC could not pull any messages out due to lack 483 * of resources. 484 */ 485 dev->htc_cnxt->chk_irq_status_cnt = 0; 486 } 487 488 /* now handle the rest of them */ 489 ath6kl_dbg(ATH6KL_DBG_IRQ, 490 "valid interrupt source(s) for other interrupts: 0x%x\n", 491 host_int_status); 492 493 if (MS(HOST_INT_STATUS_CPU, host_int_status)) { 494 /* CPU Interrupt */ 495 status = ath6kl_hif_proc_cpu_intr(dev); 496 if (status) 497 goto out; 498 } 499 500 if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { 501 /* Error Interrupt */ 502 status = ath6kl_hif_proc_err_intr(dev); 503 if (status) 504 goto out; 505 } 506 507 if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) 508 /* Counter Interrupt */ 509 status = ath6kl_hif_proc_counter_intr(dev); 510 511 out: 512 /* 513 * An optimization to bypass reading the IRQ status registers 514 * unecessarily which can re-wake the target, if upper layers 515 * determine that we are in a low-throughput mode, we can rely on 516 * taking another interrupt rather than re-checking the status 517 * registers which can re-wake the target. 518 * 519 * NOTE : for host interfaces that makes use of detecting pending 520 * mbox messages at hif can not use this optimization due to 521 * possible side effects, SPI requires the host to drain all 522 * messages from the mailbox before exiting the ISR routine. 523 */ 524 525 ath6kl_dbg(ATH6KL_DBG_IRQ, 526 "bypassing irq status re-check, forcing done\n"); 527 528 if (!dev->htc_cnxt->chk_irq_status_cnt) 529 *done = true; 530 531 ath6kl_dbg(ATH6KL_DBG_IRQ, 532 "proc_pending_irqs: (done:%d, status=%d\n", *done, status); 533 534 return status; 535 } 536 537 /* interrupt handler, kicks off all interrupt processing */ 538 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar) 539 { 540 struct ath6kl_device *dev = ar->htc_target->dev; 541 unsigned long timeout; 542 int status = 0; 543 bool done = false; 544 545 /* 546 * Reset counter used to flag a re-scan of IRQ status registers on 547 * the target. 548 */ 549 dev->htc_cnxt->chk_irq_status_cnt = 0; 550 551 /* 552 * IRQ processing is synchronous, interrupt status registers can be 553 * re-read. 554 */ 555 timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT); 556 while (time_before(jiffies, timeout) && !done) { 557 status = proc_pending_irqs(dev, &done); 558 if (status) 559 break; 560 } 561 562 return status; 563 } 564 565 static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev) 566 { 567 struct ath6kl_irq_enable_reg regs; 568 int status; 569 570 spin_lock_bh(&dev->lock); 571 572 /* Enable all but ATH6KL CPU interrupts */ 573 dev->irq_en_reg.int_status_en = 574 SM(INT_STATUS_ENABLE_ERROR, 0x01) | 575 SM(INT_STATUS_ENABLE_CPU, 0x01) | 576 SM(INT_STATUS_ENABLE_COUNTER, 0x01); 577 578 /* 579 * NOTE: There are some cases where HIF can do detection of 580 * pending mbox messages which is disabled now. 581 */ 582 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 583 584 /* Set up the CPU Interrupt status Register */ 585 dev->irq_en_reg.cpu_int_status_en = 0; 586 587 /* Set up the Error Interrupt status Register */ 588 dev->irq_en_reg.err_int_status_en = 589 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | 590 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); 591 592 /* 593 * Enable Counter interrupt status register to get fatal errors for 594 * debugging. 595 */ 596 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, 597 ATH6KL_TARGET_DEBUG_INTR_MASK); 598 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 599 600 spin_unlock_bh(&dev->lock); 601 602 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 603 ®s.int_status_en, sizeof(regs), 604 HIF_WR_SYNC_BYTE_INC); 605 606 if (status) 607 ath6kl_err("failed to update interrupt ctl reg err: %d\n", 608 status); 609 610 return status; 611 } 612 613 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev) 614 { 615 struct ath6kl_irq_enable_reg regs; 616 617 spin_lock_bh(&dev->lock); 618 /* Disable all interrupts */ 619 dev->irq_en_reg.int_status_en = 0; 620 dev->irq_en_reg.cpu_int_status_en = 0; 621 dev->irq_en_reg.err_int_status_en = 0; 622 dev->irq_en_reg.cntr_int_status_en = 0; 623 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 624 spin_unlock_bh(&dev->lock); 625 626 return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 627 ®s.int_status_en, sizeof(regs), 628 HIF_WR_SYNC_BYTE_INC); 629 } 630 631 /* enable device interrupts */ 632 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev) 633 { 634 int status = 0; 635 636 /* 637 * Make sure interrupt are disabled before unmasking at the HIF 638 * layer. The rationale here is that between device insertion 639 * (where we clear the interrupts the first time) and when HTC 640 * is finally ready to handle interrupts, other software can perform 641 * target "soft" resets. The ATH6KL interrupt enables reset back to an 642 * "enabled" state when this happens. 643 */ 644 ath6kl_hif_disable_intrs(dev); 645 646 /* unmask the host controller interrupts */ 647 ath6kl_hif_irq_enable(dev->ar); 648 status = ath6kl_hif_enable_intrs(dev); 649 650 return status; 651 } 652 653 /* disable all device interrupts */ 654 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev) 655 { 656 /* 657 * Mask the interrupt at the HIF layer to avoid any stray interrupt 658 * taken while we zero out our shadow registers in 659 * ath6kl_hif_disable_intrs(). 660 */ 661 ath6kl_hif_irq_disable(dev->ar); 662 663 return ath6kl_hif_disable_intrs(dev); 664 } 665 666 int ath6kl_hif_setup(struct ath6kl_device *dev) 667 { 668 int status = 0; 669 670 spin_lock_init(&dev->lock); 671 672 /* 673 * NOTE: we actually get the block size of a mailbox other than 0, 674 * for SDIO the block size on mailbox 0 is artificially set to 1. 675 * So we use the block size that is set for the other 3 mailboxes. 676 */ 677 dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; 678 679 /* must be a power of 2 */ 680 if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { 681 WARN_ON(1); 682 status = -EINVAL; 683 goto fail_setup; 684 } 685 686 /* assemble mask, used for padding to a block */ 687 dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; 688 689 ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n", 690 dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); 691 692 /* usb doesn't support enabling interrupts */ 693 /* FIXME: remove check once USB support is implemented */ 694 if (dev->ar->hif_type == ATH6KL_HIF_TYPE_USB) 695 return 0; 696 697 status = ath6kl_hif_disable_intrs(dev); 698 699 fail_setup: 700 return status; 701 702 } 703