1 /* 2 * Copyright (c) 2007-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include "hif.h" 18 19 #include <linux/export.h> 20 21 #include "core.h" 22 #include "target.h" 23 #include "hif-ops.h" 24 #include "debug.h" 25 26 #define MAILBOX_FOR_BLOCK_SIZE 1 27 28 #define ATH6KL_TIME_QUANTUM 10 /* in ms */ 29 30 static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req, 31 bool from_dma) 32 { 33 u8 *buf; 34 int i; 35 36 buf = req->virt_dma_buf; 37 38 for (i = 0; i < req->scat_entries; i++) { 39 40 if (from_dma) 41 memcpy(req->scat_list[i].buf, buf, 42 req->scat_list[i].len); 43 else 44 memcpy(buf, req->scat_list[i].buf, 45 req->scat_list[i].len); 46 47 buf += req->scat_list[i].len; 48 } 49 50 return 0; 51 } 52 53 int ath6kl_hif_rw_comp_handler(void *context, int status) 54 { 55 struct htc_packet *packet = context; 56 57 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n", 58 packet, status); 59 60 packet->status = status; 61 packet->completion(packet->context, packet); 62 63 return 0; 64 } 65 EXPORT_SYMBOL(ath6kl_hif_rw_comp_handler); 66 67 #define REG_DUMP_COUNT_AR6003 60 68 #define REGISTER_DUMP_LEN_MAX 60 69 70 static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar) 71 { 72 __le32 regdump_val[REGISTER_DUMP_LEN_MAX]; 73 u32 i, address, regdump_addr = 0; 74 int ret; 75 76 if (ar->target_type != TARGET_TYPE_AR6003) 77 return; 78 79 /* the reg dump pointer is copied to the host interest area */ 80 address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state)); 81 address = TARG_VTOP(ar->target_type, address); 82 83 /* read RAM location through diagnostic window */ 84 ret = ath6kl_diag_read32(ar, address, ®dump_addr); 85 86 if (ret || !regdump_addr) { 87 ath6kl_warn("failed to get ptr to register dump area: %d\n", 88 ret); 89 return; 90 } 91 92 ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n", 93 regdump_addr); 94 regdump_addr = TARG_VTOP(ar->target_type, regdump_addr); 95 96 /* fetch register dump data */ 97 ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0], 98 REG_DUMP_COUNT_AR6003 * (sizeof(u32))); 99 if (ret) { 100 ath6kl_warn("failed to get register dump: %d\n", ret); 101 return; 102 } 103 104 ath6kl_info("crash dump:\n"); 105 ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version, 106 ar->wiphy->fw_version); 107 108 BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4); 109 110 for (i = 0; i < REG_DUMP_COUNT_AR6003; i += 4) { 111 ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n", 112 i, 113 le32_to_cpu(regdump_val[i]), 114 le32_to_cpu(regdump_val[i + 1]), 115 le32_to_cpu(regdump_val[i + 2]), 116 le32_to_cpu(regdump_val[i + 3])); 117 } 118 119 } 120 121 static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev) 122 { 123 u32 dummy; 124 int ret; 125 126 ath6kl_warn("firmware crashed\n"); 127 128 /* 129 * read counter to clear the interrupt, the debug error interrupt is 130 * counter 0. 131 */ 132 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, 133 (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC); 134 if (ret) 135 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret); 136 137 ath6kl_hif_dump_fw_crash(dev->ar); 138 ath6kl_read_fwlogs(dev->ar); 139 ath6kl_recovery_err_notify(dev->ar, ATH6KL_FW_ASSERT); 140 141 return ret; 142 } 143 144 /* mailbox recv message polling */ 145 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd, 146 int timeout) 147 { 148 struct ath6kl_irq_proc_registers *rg; 149 int status = 0, i; 150 u8 htc_mbox = 1 << HTC_MAILBOX; 151 152 for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { 153 /* this is the standard HIF way, load the reg table */ 154 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 155 (u8 *) &dev->irq_proc_reg, 156 sizeof(dev->irq_proc_reg), 157 HIF_RD_SYNC_BYTE_INC); 158 159 if (status) { 160 ath6kl_err("failed to read reg table\n"); 161 return status; 162 } 163 164 /* check for MBOX data and valid lookahead */ 165 if (dev->irq_proc_reg.host_int_status & htc_mbox) { 166 if (dev->irq_proc_reg.rx_lkahd_valid & 167 htc_mbox) { 168 /* 169 * Mailbox has a message and the look ahead 170 * is valid. 171 */ 172 rg = &dev->irq_proc_reg; 173 *lk_ahd = 174 le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 175 break; 176 } 177 } 178 179 /* delay a little */ 180 mdelay(ATH6KL_TIME_QUANTUM); 181 ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i); 182 } 183 184 if (i == 0) { 185 ath6kl_err("timeout waiting for recv message\n"); 186 status = -ETIME; 187 /* check if the target asserted */ 188 if (dev->irq_proc_reg.counter_int_status & 189 ATH6KL_TARGET_DEBUG_INTR_MASK) 190 /* 191 * Target failure handler will be called in case of 192 * an assert. 193 */ 194 ath6kl_hif_proc_dbg_intr(dev); 195 } 196 197 return status; 198 } 199 200 /* 201 * Disable packet reception (used in case the host runs out of buffers) 202 * using the interrupt enable registers through the host I/F 203 */ 204 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx) 205 { 206 struct ath6kl_irq_enable_reg regs; 207 int status = 0; 208 209 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n", 210 enable_rx ? "enable" : "disable"); 211 212 /* take the lock to protect interrupt enable shadows */ 213 spin_lock_bh(&dev->lock); 214 215 if (enable_rx) 216 dev->irq_en_reg.int_status_en |= 217 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 218 else 219 dev->irq_en_reg.int_status_en &= 220 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 221 222 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 223 224 spin_unlock_bh(&dev->lock); 225 226 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 227 ®s.int_status_en, 228 sizeof(struct ath6kl_irq_enable_reg), 229 HIF_WR_SYNC_BYTE_INC); 230 231 return status; 232 } 233 234 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, 235 struct hif_scatter_req *scat_req, bool read) 236 { 237 int status = 0; 238 239 if (read) { 240 scat_req->req = HIF_RD_SYNC_BLOCK_FIX; 241 scat_req->addr = dev->ar->mbox_info.htc_addr; 242 } else { 243 scat_req->req = HIF_WR_ASYNC_BLOCK_INC; 244 245 scat_req->addr = 246 (scat_req->len > HIF_MBOX_WIDTH) ? 247 dev->ar->mbox_info.htc_ext_addr : 248 dev->ar->mbox_info.htc_addr; 249 } 250 251 ath6kl_dbg(ATH6KL_DBG_HIF, 252 "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n", 253 scat_req->scat_entries, scat_req->len, 254 scat_req->addr, !read ? "async" : "sync", 255 (read) ? "rd" : "wr"); 256 257 if (!read && scat_req->virt_scat) { 258 status = ath6kl_hif_cp_scat_dma_buf(scat_req, false); 259 if (status) { 260 scat_req->status = status; 261 scat_req->complete(dev->ar->htc_target, scat_req); 262 return 0; 263 } 264 } 265 266 status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); 267 268 if (read) { 269 /* in sync mode, we can touch the scatter request */ 270 scat_req->status = status; 271 if (!status && scat_req->virt_scat) 272 scat_req->status = 273 ath6kl_hif_cp_scat_dma_buf(scat_req, true); 274 } 275 276 return status; 277 } 278 279 static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev) 280 { 281 u8 counter_int_status; 282 283 ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n"); 284 285 counter_int_status = dev->irq_proc_reg.counter_int_status & 286 dev->irq_en_reg.cntr_int_status_en; 287 288 ath6kl_dbg(ATH6KL_DBG_IRQ, 289 "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", 290 counter_int_status); 291 292 /* 293 * NOTE: other modules like GMBOX may use the counter interrupt for 294 * credit flow control on other counters, we only need to check for 295 * the debug assertion counter interrupt. 296 */ 297 if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK) 298 return ath6kl_hif_proc_dbg_intr(dev); 299 300 return 0; 301 } 302 303 static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev) 304 { 305 int status; 306 u8 error_int_status; 307 u8 reg_buf[4]; 308 309 ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n"); 310 311 error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; 312 if (!error_int_status) { 313 WARN_ON(1); 314 return -EIO; 315 } 316 317 ath6kl_dbg(ATH6KL_DBG_IRQ, 318 "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", 319 error_int_status); 320 321 if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) 322 ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n"); 323 324 if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) 325 ath6kl_err("rx underflow\n"); 326 327 if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) 328 ath6kl_err("tx overflow\n"); 329 330 /* Clear the interrupt */ 331 dev->irq_proc_reg.error_int_status &= ~error_int_status; 332 333 /* set W1C value to clear the interrupt, this hits the register first */ 334 reg_buf[0] = error_int_status; 335 reg_buf[1] = 0; 336 reg_buf[2] = 0; 337 reg_buf[3] = 0; 338 339 status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, 340 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 341 342 if (status) 343 WARN_ON(1); 344 345 return status; 346 } 347 348 static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev) 349 { 350 int status; 351 u8 cpu_int_status; 352 u8 reg_buf[4]; 353 354 ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n"); 355 356 cpu_int_status = dev->irq_proc_reg.cpu_int_status & 357 dev->irq_en_reg.cpu_int_status_en; 358 if (!cpu_int_status) { 359 WARN_ON(1); 360 return -EIO; 361 } 362 363 ath6kl_dbg(ATH6KL_DBG_IRQ, 364 "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", 365 cpu_int_status); 366 367 /* Clear the interrupt */ 368 dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; 369 370 /* 371 * Set up the register transfer buffer to hit the register 4 times , 372 * this is done to make the access 4-byte aligned to mitigate issues 373 * with host bus interconnects that restrict bus transfer lengths to 374 * be a multiple of 4-bytes. 375 */ 376 377 /* set W1C value to clear the interrupt, this hits the register first */ 378 reg_buf[0] = cpu_int_status; 379 /* the remaining are set to zero which have no-effect */ 380 reg_buf[1] = 0; 381 reg_buf[2] = 0; 382 reg_buf[3] = 0; 383 384 status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, 385 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 386 387 if (status) 388 WARN_ON(1); 389 390 return status; 391 } 392 393 /* process pending interrupts synchronously */ 394 static int proc_pending_irqs(struct ath6kl_device *dev, bool *done) 395 { 396 struct ath6kl_irq_proc_registers *rg; 397 int status = 0; 398 u8 host_int_status = 0; 399 u32 lk_ahd = 0; 400 u8 htc_mbox = 1 << HTC_MAILBOX; 401 402 ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev); 403 404 /* 405 * NOTE: HIF implementation guarantees that the context of this 406 * call allows us to perform SYNCHRONOUS I/O, that is we can block, 407 * sleep or call any API that can block or switch thread/task 408 * contexts. This is a fully schedulable context. 409 */ 410 411 /* 412 * Process pending intr only when int_status_en is clear, it may 413 * result in unnecessary bus transaction otherwise. Target may be 414 * unresponsive at the time. 415 */ 416 if (dev->irq_en_reg.int_status_en) { 417 /* 418 * Read the first 28 bytes of the HTC register table. This 419 * will yield us the value of different int status 420 * registers and the lookahead registers. 421 * 422 * length = sizeof(int_status) + sizeof(cpu_int_status) 423 * + sizeof(error_int_status) + 424 * sizeof(counter_int_status) + 425 * sizeof(mbox_frame) + sizeof(rx_lkahd_valid) 426 * + sizeof(hole) + sizeof(rx_lkahd) + 427 * sizeof(int_status_en) + 428 * sizeof(cpu_int_status_en) + 429 * sizeof(err_int_status_en) + 430 * sizeof(cntr_int_status_en); 431 */ 432 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 433 (u8 *) &dev->irq_proc_reg, 434 sizeof(dev->irq_proc_reg), 435 HIF_RD_SYNC_BYTE_INC); 436 if (status) 437 goto out; 438 439 ath6kl_dump_registers(dev, &dev->irq_proc_reg, 440 &dev->irq_en_reg); 441 442 /* Update only those registers that are enabled */ 443 host_int_status = dev->irq_proc_reg.host_int_status & 444 dev->irq_en_reg.int_status_en; 445 446 /* Look at mbox status */ 447 if (host_int_status & htc_mbox) { 448 /* 449 * Mask out pending mbox value, we use "lookAhead as 450 * the real flag for mbox processing. 451 */ 452 host_int_status &= ~htc_mbox; 453 if (dev->irq_proc_reg.rx_lkahd_valid & 454 htc_mbox) { 455 rg = &dev->irq_proc_reg; 456 lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 457 if (!lk_ahd) 458 ath6kl_err("lookAhead is zero!\n"); 459 } 460 } 461 } 462 463 if (!host_int_status && !lk_ahd) { 464 *done = true; 465 goto out; 466 } 467 468 if (lk_ahd) { 469 int fetched = 0; 470 471 ath6kl_dbg(ATH6KL_DBG_IRQ, 472 "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd); 473 /* 474 * Mailbox Interrupt, the HTC layer may issue async 475 * requests to empty the mailbox. When emptying the recv 476 * mailbox we use the async handler above called from the 477 * completion routine of the callers read request. This can 478 * improve performance by reducing context switching when 479 * we rapidly pull packets. 480 */ 481 status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, 482 lk_ahd, &fetched); 483 if (status) 484 goto out; 485 486 if (!fetched) 487 /* 488 * HTC could not pull any messages out due to lack 489 * of resources. 490 */ 491 dev->htc_cnxt->chk_irq_status_cnt = 0; 492 } 493 494 /* now handle the rest of them */ 495 ath6kl_dbg(ATH6KL_DBG_IRQ, 496 "valid interrupt source(s) for other interrupts: 0x%x\n", 497 host_int_status); 498 499 if (MS(HOST_INT_STATUS_CPU, host_int_status)) { 500 /* CPU Interrupt */ 501 status = ath6kl_hif_proc_cpu_intr(dev); 502 if (status) 503 goto out; 504 } 505 506 if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { 507 /* Error Interrupt */ 508 status = ath6kl_hif_proc_err_intr(dev); 509 if (status) 510 goto out; 511 } 512 513 if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) 514 /* Counter Interrupt */ 515 status = ath6kl_hif_proc_counter_intr(dev); 516 517 out: 518 /* 519 * An optimization to bypass reading the IRQ status registers 520 * unecessarily which can re-wake the target, if upper layers 521 * determine that we are in a low-throughput mode, we can rely on 522 * taking another interrupt rather than re-checking the status 523 * registers which can re-wake the target. 524 * 525 * NOTE : for host interfaces that makes use of detecting pending 526 * mbox messages at hif can not use this optimization due to 527 * possible side effects, SPI requires the host to drain all 528 * messages from the mailbox before exiting the ISR routine. 529 */ 530 531 ath6kl_dbg(ATH6KL_DBG_IRQ, 532 "bypassing irq status re-check, forcing done\n"); 533 534 if (!dev->htc_cnxt->chk_irq_status_cnt) 535 *done = true; 536 537 ath6kl_dbg(ATH6KL_DBG_IRQ, 538 "proc_pending_irqs: (done:%d, status=%d\n", *done, status); 539 540 return status; 541 } 542 543 /* interrupt handler, kicks off all interrupt processing */ 544 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar) 545 { 546 struct ath6kl_device *dev = ar->htc_target->dev; 547 unsigned long timeout; 548 int status = 0; 549 bool done = false; 550 551 /* 552 * Reset counter used to flag a re-scan of IRQ status registers on 553 * the target. 554 */ 555 dev->htc_cnxt->chk_irq_status_cnt = 0; 556 557 /* 558 * IRQ processing is synchronous, interrupt status registers can be 559 * re-read. 560 */ 561 timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT); 562 while (time_before(jiffies, timeout) && !done) { 563 status = proc_pending_irqs(dev, &done); 564 if (status) 565 break; 566 } 567 568 return status; 569 } 570 EXPORT_SYMBOL(ath6kl_hif_intr_bh_handler); 571 572 static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev) 573 { 574 struct ath6kl_irq_enable_reg regs; 575 int status; 576 577 spin_lock_bh(&dev->lock); 578 579 /* Enable all but ATH6KL CPU interrupts */ 580 dev->irq_en_reg.int_status_en = 581 SM(INT_STATUS_ENABLE_ERROR, 0x01) | 582 SM(INT_STATUS_ENABLE_CPU, 0x01) | 583 SM(INT_STATUS_ENABLE_COUNTER, 0x01); 584 585 /* 586 * NOTE: There are some cases where HIF can do detection of 587 * pending mbox messages which is disabled now. 588 */ 589 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 590 591 /* Set up the CPU Interrupt status Register */ 592 dev->irq_en_reg.cpu_int_status_en = 0; 593 594 /* Set up the Error Interrupt status Register */ 595 dev->irq_en_reg.err_int_status_en = 596 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | 597 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); 598 599 /* 600 * Enable Counter interrupt status register to get fatal errors for 601 * debugging. 602 */ 603 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, 604 ATH6KL_TARGET_DEBUG_INTR_MASK); 605 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 606 607 spin_unlock_bh(&dev->lock); 608 609 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 610 ®s.int_status_en, sizeof(regs), 611 HIF_WR_SYNC_BYTE_INC); 612 613 if (status) 614 ath6kl_err("failed to update interrupt ctl reg err: %d\n", 615 status); 616 617 return status; 618 } 619 620 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev) 621 { 622 struct ath6kl_irq_enable_reg regs; 623 624 spin_lock_bh(&dev->lock); 625 /* Disable all interrupts */ 626 dev->irq_en_reg.int_status_en = 0; 627 dev->irq_en_reg.cpu_int_status_en = 0; 628 dev->irq_en_reg.err_int_status_en = 0; 629 dev->irq_en_reg.cntr_int_status_en = 0; 630 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 631 spin_unlock_bh(&dev->lock); 632 633 return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 634 ®s.int_status_en, sizeof(regs), 635 HIF_WR_SYNC_BYTE_INC); 636 } 637 638 /* enable device interrupts */ 639 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev) 640 { 641 int status = 0; 642 643 /* 644 * Make sure interrupt are disabled before unmasking at the HIF 645 * layer. The rationale here is that between device insertion 646 * (where we clear the interrupts the first time) and when HTC 647 * is finally ready to handle interrupts, other software can perform 648 * target "soft" resets. The ATH6KL interrupt enables reset back to an 649 * "enabled" state when this happens. 650 */ 651 ath6kl_hif_disable_intrs(dev); 652 653 /* unmask the host controller interrupts */ 654 ath6kl_hif_irq_enable(dev->ar); 655 status = ath6kl_hif_enable_intrs(dev); 656 657 return status; 658 } 659 660 /* disable all device interrupts */ 661 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev) 662 { 663 /* 664 * Mask the interrupt at the HIF layer to avoid any stray interrupt 665 * taken while we zero out our shadow registers in 666 * ath6kl_hif_disable_intrs(). 667 */ 668 ath6kl_hif_irq_disable(dev->ar); 669 670 return ath6kl_hif_disable_intrs(dev); 671 } 672 673 int ath6kl_hif_setup(struct ath6kl_device *dev) 674 { 675 int status = 0; 676 677 spin_lock_init(&dev->lock); 678 679 /* 680 * NOTE: we actually get the block size of a mailbox other than 0, 681 * for SDIO the block size on mailbox 0 is artificially set to 1. 682 * So we use the block size that is set for the other 3 mailboxes. 683 */ 684 dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; 685 686 /* must be a power of 2 */ 687 if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { 688 WARN_ON(1); 689 status = -EINVAL; 690 goto fail_setup; 691 } 692 693 /* assemble mask, used for padding to a block */ 694 dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; 695 696 ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n", 697 dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); 698 699 status = ath6kl_hif_disable_intrs(dev); 700 701 fail_setup: 702 return status; 703 704 } 705