1 /* 2 * Copyright (c) 2007-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include "hif.h" 18 19 #include <linux/export.h> 20 21 #include "core.h" 22 #include "target.h" 23 #include "hif-ops.h" 24 #include "debug.h" 25 26 #define MAILBOX_FOR_BLOCK_SIZE 1 27 28 #define ATH6KL_TIME_QUANTUM 10 /* in ms */ 29 30 static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req, 31 bool from_dma) 32 { 33 u8 *buf; 34 int i; 35 36 buf = req->virt_dma_buf; 37 38 for (i = 0; i < req->scat_entries; i++) { 39 40 if (from_dma) 41 memcpy(req->scat_list[i].buf, buf, 42 req->scat_list[i].len); 43 else 44 memcpy(buf, req->scat_list[i].buf, 45 req->scat_list[i].len); 46 47 buf += req->scat_list[i].len; 48 } 49 50 return 0; 51 } 52 53 int ath6kl_hif_rw_comp_handler(void *context, int status) 54 { 55 struct htc_packet *packet = context; 56 57 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n", 58 packet, status); 59 60 packet->status = status; 61 packet->completion(packet->context, packet); 62 63 return 0; 64 } 65 EXPORT_SYMBOL(ath6kl_hif_rw_comp_handler); 66 67 #define REG_DUMP_COUNT_AR6003 60 68 #define REGISTER_DUMP_LEN_MAX 60 69 70 static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar) 71 { 72 __le32 regdump_val[REGISTER_DUMP_LEN_MAX]; 73 u32 i, address, regdump_addr = 0; 74 int ret; 75 76 if (ar->target_type != TARGET_TYPE_AR6003) 77 return; 78 79 /* the reg dump pointer is copied to the host interest area */ 80 address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state)); 81 address = TARG_VTOP(ar->target_type, address); 82 83 /* read RAM location through diagnostic window */ 84 ret = ath6kl_diag_read32(ar, address, ®dump_addr); 85 86 if (ret || !regdump_addr) { 87 ath6kl_warn("failed to get ptr to register dump area: %d\n", 88 ret); 89 return; 90 } 91 92 ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n", 93 regdump_addr); 94 regdump_addr = TARG_VTOP(ar->target_type, regdump_addr); 95 96 /* fetch register dump data */ 97 ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0], 98 REG_DUMP_COUNT_AR6003 * (sizeof(u32))); 99 if (ret) { 100 ath6kl_warn("failed to get register dump: %d\n", ret); 101 return; 102 } 103 104 ath6kl_info("crash dump:\n"); 105 ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version, 106 ar->wiphy->fw_version); 107 108 BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4); 109 110 for (i = 0; i < REG_DUMP_COUNT_AR6003; i += 4) { 111 ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n", 112 i, 113 le32_to_cpu(regdump_val[i]), 114 le32_to_cpu(regdump_val[i + 1]), 115 le32_to_cpu(regdump_val[i + 2]), 116 le32_to_cpu(regdump_val[i + 3])); 117 } 118 119 } 120 121 static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev) 122 { 123 u32 dummy; 124 int ret; 125 126 ath6kl_warn("firmware crashed\n"); 127 128 /* 129 * read counter to clear the interrupt, the debug error interrupt is 130 * counter 0. 131 */ 132 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, 133 (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC); 134 if (ret) 135 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret); 136 137 ath6kl_hif_dump_fw_crash(dev->ar); 138 ath6kl_read_fwlogs(dev->ar); 139 140 return ret; 141 } 142 143 /* mailbox recv message polling */ 144 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd, 145 int timeout) 146 { 147 struct ath6kl_irq_proc_registers *rg; 148 int status = 0, i; 149 u8 htc_mbox = 1 << HTC_MAILBOX; 150 151 for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { 152 /* this is the standard HIF way, load the reg table */ 153 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 154 (u8 *) &dev->irq_proc_reg, 155 sizeof(dev->irq_proc_reg), 156 HIF_RD_SYNC_BYTE_INC); 157 158 if (status) { 159 ath6kl_err("failed to read reg table\n"); 160 return status; 161 } 162 163 /* check for MBOX data and valid lookahead */ 164 if (dev->irq_proc_reg.host_int_status & htc_mbox) { 165 if (dev->irq_proc_reg.rx_lkahd_valid & 166 htc_mbox) { 167 /* 168 * Mailbox has a message and the look ahead 169 * is valid. 170 */ 171 rg = &dev->irq_proc_reg; 172 *lk_ahd = 173 le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 174 break; 175 } 176 } 177 178 /* delay a little */ 179 mdelay(ATH6KL_TIME_QUANTUM); 180 ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i); 181 } 182 183 if (i == 0) { 184 ath6kl_err("timeout waiting for recv message\n"); 185 status = -ETIME; 186 /* check if the target asserted */ 187 if (dev->irq_proc_reg.counter_int_status & 188 ATH6KL_TARGET_DEBUG_INTR_MASK) 189 /* 190 * Target failure handler will be called in case of 191 * an assert. 192 */ 193 ath6kl_hif_proc_dbg_intr(dev); 194 } 195 196 return status; 197 } 198 199 /* 200 * Disable packet reception (used in case the host runs out of buffers) 201 * using the interrupt enable registers through the host I/F 202 */ 203 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx) 204 { 205 struct ath6kl_irq_enable_reg regs; 206 int status = 0; 207 208 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n", 209 enable_rx ? "enable" : "disable"); 210 211 /* take the lock to protect interrupt enable shadows */ 212 spin_lock_bh(&dev->lock); 213 214 if (enable_rx) 215 dev->irq_en_reg.int_status_en |= 216 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 217 else 218 dev->irq_en_reg.int_status_en &= 219 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 220 221 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 222 223 spin_unlock_bh(&dev->lock); 224 225 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 226 ®s.int_status_en, 227 sizeof(struct ath6kl_irq_enable_reg), 228 HIF_WR_SYNC_BYTE_INC); 229 230 return status; 231 } 232 233 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, 234 struct hif_scatter_req *scat_req, bool read) 235 { 236 int status = 0; 237 238 if (read) { 239 scat_req->req = HIF_RD_SYNC_BLOCK_FIX; 240 scat_req->addr = dev->ar->mbox_info.htc_addr; 241 } else { 242 scat_req->req = HIF_WR_ASYNC_BLOCK_INC; 243 244 scat_req->addr = 245 (scat_req->len > HIF_MBOX_WIDTH) ? 246 dev->ar->mbox_info.htc_ext_addr : 247 dev->ar->mbox_info.htc_addr; 248 } 249 250 ath6kl_dbg(ATH6KL_DBG_HIF, 251 "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n", 252 scat_req->scat_entries, scat_req->len, 253 scat_req->addr, !read ? "async" : "sync", 254 (read) ? "rd" : "wr"); 255 256 if (!read && scat_req->virt_scat) { 257 status = ath6kl_hif_cp_scat_dma_buf(scat_req, false); 258 if (status) { 259 scat_req->status = status; 260 scat_req->complete(dev->ar->htc_target, scat_req); 261 return 0; 262 } 263 } 264 265 status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); 266 267 if (read) { 268 /* in sync mode, we can touch the scatter request */ 269 scat_req->status = status; 270 if (!status && scat_req->virt_scat) 271 scat_req->status = 272 ath6kl_hif_cp_scat_dma_buf(scat_req, true); 273 } 274 275 return status; 276 } 277 278 static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev) 279 { 280 u8 counter_int_status; 281 282 ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n"); 283 284 counter_int_status = dev->irq_proc_reg.counter_int_status & 285 dev->irq_en_reg.cntr_int_status_en; 286 287 ath6kl_dbg(ATH6KL_DBG_IRQ, 288 "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", 289 counter_int_status); 290 291 /* 292 * NOTE: other modules like GMBOX may use the counter interrupt for 293 * credit flow control on other counters, we only need to check for 294 * the debug assertion counter interrupt. 295 */ 296 if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK) 297 return ath6kl_hif_proc_dbg_intr(dev); 298 299 return 0; 300 } 301 302 static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev) 303 { 304 int status; 305 u8 error_int_status; 306 u8 reg_buf[4]; 307 308 ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n"); 309 310 error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; 311 if (!error_int_status) { 312 WARN_ON(1); 313 return -EIO; 314 } 315 316 ath6kl_dbg(ATH6KL_DBG_IRQ, 317 "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", 318 error_int_status); 319 320 if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) 321 ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n"); 322 323 if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) 324 ath6kl_err("rx underflow\n"); 325 326 if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) 327 ath6kl_err("tx overflow\n"); 328 329 /* Clear the interrupt */ 330 dev->irq_proc_reg.error_int_status &= ~error_int_status; 331 332 /* set W1C value to clear the interrupt, this hits the register first */ 333 reg_buf[0] = error_int_status; 334 reg_buf[1] = 0; 335 reg_buf[2] = 0; 336 reg_buf[3] = 0; 337 338 status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, 339 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 340 341 if (status) 342 WARN_ON(1); 343 344 return status; 345 } 346 347 static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev) 348 { 349 int status; 350 u8 cpu_int_status; 351 u8 reg_buf[4]; 352 353 ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n"); 354 355 cpu_int_status = dev->irq_proc_reg.cpu_int_status & 356 dev->irq_en_reg.cpu_int_status_en; 357 if (!cpu_int_status) { 358 WARN_ON(1); 359 return -EIO; 360 } 361 362 ath6kl_dbg(ATH6KL_DBG_IRQ, 363 "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", 364 cpu_int_status); 365 366 /* Clear the interrupt */ 367 dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; 368 369 /* 370 * Set up the register transfer buffer to hit the register 4 times , 371 * this is done to make the access 4-byte aligned to mitigate issues 372 * with host bus interconnects that restrict bus transfer lengths to 373 * be a multiple of 4-bytes. 374 */ 375 376 /* set W1C value to clear the interrupt, this hits the register first */ 377 reg_buf[0] = cpu_int_status; 378 /* the remaining are set to zero which have no-effect */ 379 reg_buf[1] = 0; 380 reg_buf[2] = 0; 381 reg_buf[3] = 0; 382 383 status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, 384 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 385 386 if (status) 387 WARN_ON(1); 388 389 return status; 390 } 391 392 /* process pending interrupts synchronously */ 393 static int proc_pending_irqs(struct ath6kl_device *dev, bool *done) 394 { 395 struct ath6kl_irq_proc_registers *rg; 396 int status = 0; 397 u8 host_int_status = 0; 398 u32 lk_ahd = 0; 399 u8 htc_mbox = 1 << HTC_MAILBOX; 400 401 ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev); 402 403 /* 404 * NOTE: HIF implementation guarantees that the context of this 405 * call allows us to perform SYNCHRONOUS I/O, that is we can block, 406 * sleep or call any API that can block or switch thread/task 407 * contexts. This is a fully schedulable context. 408 */ 409 410 /* 411 * Process pending intr only when int_status_en is clear, it may 412 * result in unnecessary bus transaction otherwise. Target may be 413 * unresponsive at the time. 414 */ 415 if (dev->irq_en_reg.int_status_en) { 416 /* 417 * Read the first 28 bytes of the HTC register table. This 418 * will yield us the value of different int status 419 * registers and the lookahead registers. 420 * 421 * length = sizeof(int_status) + sizeof(cpu_int_status) 422 * + sizeof(error_int_status) + 423 * sizeof(counter_int_status) + 424 * sizeof(mbox_frame) + sizeof(rx_lkahd_valid) 425 * + sizeof(hole) + sizeof(rx_lkahd) + 426 * sizeof(int_status_en) + 427 * sizeof(cpu_int_status_en) + 428 * sizeof(err_int_status_en) + 429 * sizeof(cntr_int_status_en); 430 */ 431 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 432 (u8 *) &dev->irq_proc_reg, 433 sizeof(dev->irq_proc_reg), 434 HIF_RD_SYNC_BYTE_INC); 435 if (status) 436 goto out; 437 438 ath6kl_dump_registers(dev, &dev->irq_proc_reg, 439 &dev->irq_en_reg); 440 441 /* Update only those registers that are enabled */ 442 host_int_status = dev->irq_proc_reg.host_int_status & 443 dev->irq_en_reg.int_status_en; 444 445 /* Look at mbox status */ 446 if (host_int_status & htc_mbox) { 447 /* 448 * Mask out pending mbox value, we use "lookAhead as 449 * the real flag for mbox processing. 450 */ 451 host_int_status &= ~htc_mbox; 452 if (dev->irq_proc_reg.rx_lkahd_valid & 453 htc_mbox) { 454 rg = &dev->irq_proc_reg; 455 lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 456 if (!lk_ahd) 457 ath6kl_err("lookAhead is zero!\n"); 458 } 459 } 460 } 461 462 if (!host_int_status && !lk_ahd) { 463 *done = true; 464 goto out; 465 } 466 467 if (lk_ahd) { 468 int fetched = 0; 469 470 ath6kl_dbg(ATH6KL_DBG_IRQ, 471 "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd); 472 /* 473 * Mailbox Interrupt, the HTC layer may issue async 474 * requests to empty the mailbox. When emptying the recv 475 * mailbox we use the async handler above called from the 476 * completion routine of the callers read request. This can 477 * improve performance by reducing context switching when 478 * we rapidly pull packets. 479 */ 480 status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, 481 lk_ahd, &fetched); 482 if (status) 483 goto out; 484 485 if (!fetched) 486 /* 487 * HTC could not pull any messages out due to lack 488 * of resources. 489 */ 490 dev->htc_cnxt->chk_irq_status_cnt = 0; 491 } 492 493 /* now handle the rest of them */ 494 ath6kl_dbg(ATH6KL_DBG_IRQ, 495 "valid interrupt source(s) for other interrupts: 0x%x\n", 496 host_int_status); 497 498 if (MS(HOST_INT_STATUS_CPU, host_int_status)) { 499 /* CPU Interrupt */ 500 status = ath6kl_hif_proc_cpu_intr(dev); 501 if (status) 502 goto out; 503 } 504 505 if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { 506 /* Error Interrupt */ 507 status = ath6kl_hif_proc_err_intr(dev); 508 if (status) 509 goto out; 510 } 511 512 if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) 513 /* Counter Interrupt */ 514 status = ath6kl_hif_proc_counter_intr(dev); 515 516 out: 517 /* 518 * An optimization to bypass reading the IRQ status registers 519 * unecessarily which can re-wake the target, if upper layers 520 * determine that we are in a low-throughput mode, we can rely on 521 * taking another interrupt rather than re-checking the status 522 * registers which can re-wake the target. 523 * 524 * NOTE : for host interfaces that makes use of detecting pending 525 * mbox messages at hif can not use this optimization due to 526 * possible side effects, SPI requires the host to drain all 527 * messages from the mailbox before exiting the ISR routine. 528 */ 529 530 ath6kl_dbg(ATH6KL_DBG_IRQ, 531 "bypassing irq status re-check, forcing done\n"); 532 533 if (!dev->htc_cnxt->chk_irq_status_cnt) 534 *done = true; 535 536 ath6kl_dbg(ATH6KL_DBG_IRQ, 537 "proc_pending_irqs: (done:%d, status=%d\n", *done, status); 538 539 return status; 540 } 541 542 /* interrupt handler, kicks off all interrupt processing */ 543 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar) 544 { 545 struct ath6kl_device *dev = ar->htc_target->dev; 546 unsigned long timeout; 547 int status = 0; 548 bool done = false; 549 550 /* 551 * Reset counter used to flag a re-scan of IRQ status registers on 552 * the target. 553 */ 554 dev->htc_cnxt->chk_irq_status_cnt = 0; 555 556 /* 557 * IRQ processing is synchronous, interrupt status registers can be 558 * re-read. 559 */ 560 timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT); 561 while (time_before(jiffies, timeout) && !done) { 562 status = proc_pending_irqs(dev, &done); 563 if (status) 564 break; 565 } 566 567 return status; 568 } 569 EXPORT_SYMBOL(ath6kl_hif_intr_bh_handler); 570 571 static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev) 572 { 573 struct ath6kl_irq_enable_reg regs; 574 int status; 575 576 spin_lock_bh(&dev->lock); 577 578 /* Enable all but ATH6KL CPU interrupts */ 579 dev->irq_en_reg.int_status_en = 580 SM(INT_STATUS_ENABLE_ERROR, 0x01) | 581 SM(INT_STATUS_ENABLE_CPU, 0x01) | 582 SM(INT_STATUS_ENABLE_COUNTER, 0x01); 583 584 /* 585 * NOTE: There are some cases where HIF can do detection of 586 * pending mbox messages which is disabled now. 587 */ 588 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 589 590 /* Set up the CPU Interrupt status Register */ 591 dev->irq_en_reg.cpu_int_status_en = 0; 592 593 /* Set up the Error Interrupt status Register */ 594 dev->irq_en_reg.err_int_status_en = 595 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | 596 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); 597 598 /* 599 * Enable Counter interrupt status register to get fatal errors for 600 * debugging. 601 */ 602 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, 603 ATH6KL_TARGET_DEBUG_INTR_MASK); 604 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 605 606 spin_unlock_bh(&dev->lock); 607 608 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 609 ®s.int_status_en, sizeof(regs), 610 HIF_WR_SYNC_BYTE_INC); 611 612 if (status) 613 ath6kl_err("failed to update interrupt ctl reg err: %d\n", 614 status); 615 616 return status; 617 } 618 619 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev) 620 { 621 struct ath6kl_irq_enable_reg regs; 622 623 spin_lock_bh(&dev->lock); 624 /* Disable all interrupts */ 625 dev->irq_en_reg.int_status_en = 0; 626 dev->irq_en_reg.cpu_int_status_en = 0; 627 dev->irq_en_reg.err_int_status_en = 0; 628 dev->irq_en_reg.cntr_int_status_en = 0; 629 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 630 spin_unlock_bh(&dev->lock); 631 632 return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 633 ®s.int_status_en, sizeof(regs), 634 HIF_WR_SYNC_BYTE_INC); 635 } 636 637 /* enable device interrupts */ 638 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev) 639 { 640 int status = 0; 641 642 /* 643 * Make sure interrupt are disabled before unmasking at the HIF 644 * layer. The rationale here is that between device insertion 645 * (where we clear the interrupts the first time) and when HTC 646 * is finally ready to handle interrupts, other software can perform 647 * target "soft" resets. The ATH6KL interrupt enables reset back to an 648 * "enabled" state when this happens. 649 */ 650 ath6kl_hif_disable_intrs(dev); 651 652 /* unmask the host controller interrupts */ 653 ath6kl_hif_irq_enable(dev->ar); 654 status = ath6kl_hif_enable_intrs(dev); 655 656 return status; 657 } 658 659 /* disable all device interrupts */ 660 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev) 661 { 662 /* 663 * Mask the interrupt at the HIF layer to avoid any stray interrupt 664 * taken while we zero out our shadow registers in 665 * ath6kl_hif_disable_intrs(). 666 */ 667 ath6kl_hif_irq_disable(dev->ar); 668 669 return ath6kl_hif_disable_intrs(dev); 670 } 671 672 int ath6kl_hif_setup(struct ath6kl_device *dev) 673 { 674 int status = 0; 675 676 spin_lock_init(&dev->lock); 677 678 /* 679 * NOTE: we actually get the block size of a mailbox other than 0, 680 * for SDIO the block size on mailbox 0 is artificially set to 1. 681 * So we use the block size that is set for the other 3 mailboxes. 682 */ 683 dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; 684 685 /* must be a power of 2 */ 686 if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { 687 WARN_ON(1); 688 status = -EINVAL; 689 goto fail_setup; 690 } 691 692 /* assemble mask, used for padding to a block */ 693 dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; 694 695 ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n", 696 dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); 697 698 /* usb doesn't support enabling interrupts */ 699 /* FIXME: remove check once USB support is implemented */ 700 if (dev->ar->hif_type == ATH6KL_HIF_TYPE_USB) 701 return 0; 702 703 status = ath6kl_hif_disable_intrs(dev); 704 705 fail_setup: 706 return status; 707 708 } 709