18e8ddb2bSKalle Valo /* 28e8ddb2bSKalle Valo * Copyright (c) 2007-2011 Atheros Communications Inc. 38e8ddb2bSKalle Valo * 48e8ddb2bSKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 58e8ddb2bSKalle Valo * purpose with or without fee is hereby granted, provided that the above 68e8ddb2bSKalle Valo * copyright notice and this permission notice appear in all copies. 78e8ddb2bSKalle Valo * 88e8ddb2bSKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98e8ddb2bSKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 108e8ddb2bSKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 118e8ddb2bSKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 128e8ddb2bSKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 138e8ddb2bSKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 148e8ddb2bSKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 158e8ddb2bSKalle Valo */ 162e1cb23cSKalle Valo #include "hif.h" 178e8ddb2bSKalle Valo 188e8ddb2bSKalle Valo #include "core.h" 198e8ddb2bSKalle Valo #include "target.h" 208e8ddb2bSKalle Valo #include "hif-ops.h" 218e8ddb2bSKalle Valo #include "debug.h" 228e8ddb2bSKalle Valo 238e8ddb2bSKalle Valo #define MAILBOX_FOR_BLOCK_SIZE 1 248e8ddb2bSKalle Valo 258e8ddb2bSKalle Valo #define ATH6KL_TIME_QUANTUM 10 /* in ms */ 268e8ddb2bSKalle Valo 278e8ddb2bSKalle Valo static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req, 288e8ddb2bSKalle Valo bool from_dma) 298e8ddb2bSKalle Valo { 308e8ddb2bSKalle Valo u8 *buf; 318e8ddb2bSKalle Valo int i; 328e8ddb2bSKalle Valo 338e8ddb2bSKalle Valo buf = req->virt_dma_buf; 348e8ddb2bSKalle Valo 358e8ddb2bSKalle Valo for (i = 0; i < req->scat_entries; i++) { 368e8ddb2bSKalle Valo 378e8ddb2bSKalle Valo if (from_dma) 388e8ddb2bSKalle Valo memcpy(req->scat_list[i].buf, buf, 398e8ddb2bSKalle Valo req->scat_list[i].len); 408e8ddb2bSKalle Valo else 418e8ddb2bSKalle Valo memcpy(buf, req->scat_list[i].buf, 428e8ddb2bSKalle Valo req->scat_list[i].len); 438e8ddb2bSKalle Valo 448e8ddb2bSKalle Valo buf += req->scat_list[i].len; 458e8ddb2bSKalle Valo } 468e8ddb2bSKalle Valo 478e8ddb2bSKalle Valo return 0; 488e8ddb2bSKalle Valo } 498e8ddb2bSKalle Valo 508e8ddb2bSKalle Valo int ath6kl_hif_rw_comp_handler(void *context, int status) 518e8ddb2bSKalle Valo { 528e8ddb2bSKalle Valo struct htc_packet *packet = context; 538e8ddb2bSKalle Valo 5483973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n", 558e8ddb2bSKalle Valo packet, status); 568e8ddb2bSKalle Valo 578e8ddb2bSKalle Valo packet->status = status; 588e8ddb2bSKalle Valo packet->completion(packet->context, packet); 598e8ddb2bSKalle Valo 608e8ddb2bSKalle Valo return 0; 618e8ddb2bSKalle Valo } 628e8ddb2bSKalle Valo 638e8ddb2bSKalle Valo static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev) 648e8ddb2bSKalle Valo { 658e8ddb2bSKalle Valo u32 dummy; 668e8ddb2bSKalle Valo int status; 678e8ddb2bSKalle Valo 688e8ddb2bSKalle Valo ath6kl_err("target debug interrupt\n"); 698e8ddb2bSKalle Valo 708e8ddb2bSKalle Valo ath6kl_target_failure(dev->ar); 718e8ddb2bSKalle Valo 728e8ddb2bSKalle Valo /* 738e8ddb2bSKalle Valo * read counter to clear the interrupt, the debug error interrupt is 748e8ddb2bSKalle Valo * counter 0. 758e8ddb2bSKalle Valo */ 768e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, 778e8ddb2bSKalle Valo (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC); 788e8ddb2bSKalle Valo if (status) 798e8ddb2bSKalle Valo WARN_ON(1); 808e8ddb2bSKalle Valo 818e8ddb2bSKalle Valo return status; 828e8ddb2bSKalle Valo } 838e8ddb2bSKalle Valo 848e8ddb2bSKalle Valo /* mailbox recv message polling */ 858e8ddb2bSKalle Valo int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd, 868e8ddb2bSKalle Valo int timeout) 878e8ddb2bSKalle Valo { 888e8ddb2bSKalle Valo struct ath6kl_irq_proc_registers *rg; 898e8ddb2bSKalle Valo int status = 0, i; 908e8ddb2bSKalle Valo u8 htc_mbox = 1 << HTC_MAILBOX; 918e8ddb2bSKalle Valo 928e8ddb2bSKalle Valo for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { 938e8ddb2bSKalle Valo /* this is the standard HIF way, load the reg table */ 948e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 958e8ddb2bSKalle Valo (u8 *) &dev->irq_proc_reg, 968e8ddb2bSKalle Valo sizeof(dev->irq_proc_reg), 978e8ddb2bSKalle Valo HIF_RD_SYNC_BYTE_INC); 988e8ddb2bSKalle Valo 998e8ddb2bSKalle Valo if (status) { 1008e8ddb2bSKalle Valo ath6kl_err("failed to read reg table\n"); 1018e8ddb2bSKalle Valo return status; 1028e8ddb2bSKalle Valo } 1038e8ddb2bSKalle Valo 1048e8ddb2bSKalle Valo /* check for MBOX data and valid lookahead */ 1058e8ddb2bSKalle Valo if (dev->irq_proc_reg.host_int_status & htc_mbox) { 1068e8ddb2bSKalle Valo if (dev->irq_proc_reg.rx_lkahd_valid & 1078e8ddb2bSKalle Valo htc_mbox) { 1088e8ddb2bSKalle Valo /* 1098e8ddb2bSKalle Valo * Mailbox has a message and the look ahead 1108e8ddb2bSKalle Valo * is valid. 1118e8ddb2bSKalle Valo */ 1128e8ddb2bSKalle Valo rg = &dev->irq_proc_reg; 1138e8ddb2bSKalle Valo *lk_ahd = 1148e8ddb2bSKalle Valo le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 1158e8ddb2bSKalle Valo break; 1168e8ddb2bSKalle Valo } 1178e8ddb2bSKalle Valo } 1188e8ddb2bSKalle Valo 1198e8ddb2bSKalle Valo /* delay a little */ 1208e8ddb2bSKalle Valo mdelay(ATH6KL_TIME_QUANTUM); 12183973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i); 1228e8ddb2bSKalle Valo } 1238e8ddb2bSKalle Valo 1248e8ddb2bSKalle Valo if (i == 0) { 1258e8ddb2bSKalle Valo ath6kl_err("timeout waiting for recv message\n"); 1268e8ddb2bSKalle Valo status = -ETIME; 1278e8ddb2bSKalle Valo /* check if the target asserted */ 1288e8ddb2bSKalle Valo if (dev->irq_proc_reg.counter_int_status & 1298e8ddb2bSKalle Valo ATH6KL_TARGET_DEBUG_INTR_MASK) 1308e8ddb2bSKalle Valo /* 1318e8ddb2bSKalle Valo * Target failure handler will be called in case of 1328e8ddb2bSKalle Valo * an assert. 1338e8ddb2bSKalle Valo */ 1348e8ddb2bSKalle Valo ath6kl_hif_proc_dbg_intr(dev); 1358e8ddb2bSKalle Valo } 1368e8ddb2bSKalle Valo 1378e8ddb2bSKalle Valo return status; 1388e8ddb2bSKalle Valo } 1398e8ddb2bSKalle Valo 1408e8ddb2bSKalle Valo /* 1418e8ddb2bSKalle Valo * Disable packet reception (used in case the host runs out of buffers) 1428e8ddb2bSKalle Valo * using the interrupt enable registers through the host I/F 1438e8ddb2bSKalle Valo */ 1448e8ddb2bSKalle Valo int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx) 1458e8ddb2bSKalle Valo { 1468e8ddb2bSKalle Valo struct ath6kl_irq_enable_reg regs; 1478e8ddb2bSKalle Valo int status = 0; 1488e8ddb2bSKalle Valo 14983973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n", 15083973e03SKalle Valo enable_rx ? "enable" : "disable"); 15183973e03SKalle Valo 1528e8ddb2bSKalle Valo /* take the lock to protect interrupt enable shadows */ 1538e8ddb2bSKalle Valo spin_lock_bh(&dev->lock); 1548e8ddb2bSKalle Valo 1558e8ddb2bSKalle Valo if (enable_rx) 1568e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en |= 1578e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 1588e8ddb2bSKalle Valo else 1598e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en &= 1608e8ddb2bSKalle Valo ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 1618e8ddb2bSKalle Valo 1628e8ddb2bSKalle Valo memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 1638e8ddb2bSKalle Valo 1648e8ddb2bSKalle Valo spin_unlock_bh(&dev->lock); 1658e8ddb2bSKalle Valo 1668e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 1678e8ddb2bSKalle Valo ®s.int_status_en, 1688e8ddb2bSKalle Valo sizeof(struct ath6kl_irq_enable_reg), 1698e8ddb2bSKalle Valo HIF_WR_SYNC_BYTE_INC); 1708e8ddb2bSKalle Valo 1718e8ddb2bSKalle Valo return status; 1728e8ddb2bSKalle Valo } 1738e8ddb2bSKalle Valo 1748e8ddb2bSKalle Valo int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, 1758e8ddb2bSKalle Valo struct hif_scatter_req *scat_req, bool read) 1768e8ddb2bSKalle Valo { 1778e8ddb2bSKalle Valo int status = 0; 1788e8ddb2bSKalle Valo 1798e8ddb2bSKalle Valo if (read) { 1808e8ddb2bSKalle Valo scat_req->req = HIF_RD_SYNC_BLOCK_FIX; 1818e8ddb2bSKalle Valo scat_req->addr = dev->ar->mbox_info.htc_addr; 1828e8ddb2bSKalle Valo } else { 1838e8ddb2bSKalle Valo scat_req->req = HIF_WR_ASYNC_BLOCK_INC; 1848e8ddb2bSKalle Valo 1858e8ddb2bSKalle Valo scat_req->addr = 1868e8ddb2bSKalle Valo (scat_req->len > HIF_MBOX_WIDTH) ? 1878e8ddb2bSKalle Valo dev->ar->mbox_info.htc_ext_addr : 1888e8ddb2bSKalle Valo dev->ar->mbox_info.htc_addr; 1898e8ddb2bSKalle Valo } 1908e8ddb2bSKalle Valo 19183973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, 19283973e03SKalle Valo "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n", 1938e8ddb2bSKalle Valo scat_req->scat_entries, scat_req->len, 1948e8ddb2bSKalle Valo scat_req->addr, !read ? "async" : "sync", 1958e8ddb2bSKalle Valo (read) ? "rd" : "wr"); 1968e8ddb2bSKalle Valo 1978e8ddb2bSKalle Valo if (!read && scat_req->virt_scat) { 1988e8ddb2bSKalle Valo status = ath6kl_hif_cp_scat_dma_buf(scat_req, false); 1998e8ddb2bSKalle Valo if (status) { 2008e8ddb2bSKalle Valo scat_req->status = status; 2018e8ddb2bSKalle Valo scat_req->complete(dev->ar->htc_target, scat_req); 2028e8ddb2bSKalle Valo return 0; 2038e8ddb2bSKalle Valo } 2048e8ddb2bSKalle Valo } 2058e8ddb2bSKalle Valo 2068e8ddb2bSKalle Valo status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); 2078e8ddb2bSKalle Valo 2088e8ddb2bSKalle Valo if (read) { 2098e8ddb2bSKalle Valo /* in sync mode, we can touch the scatter request */ 2108e8ddb2bSKalle Valo scat_req->status = status; 2118e8ddb2bSKalle Valo if (!status && scat_req->virt_scat) 2128e8ddb2bSKalle Valo scat_req->status = 2138e8ddb2bSKalle Valo ath6kl_hif_cp_scat_dma_buf(scat_req, true); 2148e8ddb2bSKalle Valo } 2158e8ddb2bSKalle Valo 2168e8ddb2bSKalle Valo return status; 2178e8ddb2bSKalle Valo } 2188e8ddb2bSKalle Valo 2198e8ddb2bSKalle Valo static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev) 2208e8ddb2bSKalle Valo { 2218e8ddb2bSKalle Valo u8 counter_int_status; 2228e8ddb2bSKalle Valo 2238e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n"); 2248e8ddb2bSKalle Valo 2258e8ddb2bSKalle Valo counter_int_status = dev->irq_proc_reg.counter_int_status & 2268e8ddb2bSKalle Valo dev->irq_en_reg.cntr_int_status_en; 2278e8ddb2bSKalle Valo 2288e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 2298e8ddb2bSKalle Valo "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", 2308e8ddb2bSKalle Valo counter_int_status); 2318e8ddb2bSKalle Valo 2328e8ddb2bSKalle Valo /* 2338e8ddb2bSKalle Valo * NOTE: other modules like GMBOX may use the counter interrupt for 2348e8ddb2bSKalle Valo * credit flow control on other counters, we only need to check for 2358e8ddb2bSKalle Valo * the debug assertion counter interrupt. 2368e8ddb2bSKalle Valo */ 2378e8ddb2bSKalle Valo if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK) 2388e8ddb2bSKalle Valo return ath6kl_hif_proc_dbg_intr(dev); 2398e8ddb2bSKalle Valo 2408e8ddb2bSKalle Valo return 0; 2418e8ddb2bSKalle Valo } 2428e8ddb2bSKalle Valo 2438e8ddb2bSKalle Valo static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev) 2448e8ddb2bSKalle Valo { 2458e8ddb2bSKalle Valo int status; 2468e8ddb2bSKalle Valo u8 error_int_status; 2478e8ddb2bSKalle Valo u8 reg_buf[4]; 2488e8ddb2bSKalle Valo 2498e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n"); 2508e8ddb2bSKalle Valo 2518e8ddb2bSKalle Valo error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; 2528e8ddb2bSKalle Valo if (!error_int_status) { 2538e8ddb2bSKalle Valo WARN_ON(1); 2548e8ddb2bSKalle Valo return -EIO; 2558e8ddb2bSKalle Valo } 2568e8ddb2bSKalle Valo 2578e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 2588e8ddb2bSKalle Valo "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", 2598e8ddb2bSKalle Valo error_int_status); 2608e8ddb2bSKalle Valo 2618e8ddb2bSKalle Valo if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) 2628e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n"); 2638e8ddb2bSKalle Valo 2648e8ddb2bSKalle Valo if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) 2658e8ddb2bSKalle Valo ath6kl_err("rx underflow\n"); 2668e8ddb2bSKalle Valo 2678e8ddb2bSKalle Valo if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) 2688e8ddb2bSKalle Valo ath6kl_err("tx overflow\n"); 2698e8ddb2bSKalle Valo 2708e8ddb2bSKalle Valo /* Clear the interrupt */ 2718e8ddb2bSKalle Valo dev->irq_proc_reg.error_int_status &= ~error_int_status; 2728e8ddb2bSKalle Valo 2738e8ddb2bSKalle Valo /* set W1C value to clear the interrupt, this hits the register first */ 2748e8ddb2bSKalle Valo reg_buf[0] = error_int_status; 2758e8ddb2bSKalle Valo reg_buf[1] = 0; 2768e8ddb2bSKalle Valo reg_buf[2] = 0; 2778e8ddb2bSKalle Valo reg_buf[3] = 0; 2788e8ddb2bSKalle Valo 2798e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, 2808e8ddb2bSKalle Valo reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 2818e8ddb2bSKalle Valo 2828e8ddb2bSKalle Valo if (status) 2838e8ddb2bSKalle Valo WARN_ON(1); 2848e8ddb2bSKalle Valo 2858e8ddb2bSKalle Valo return status; 2868e8ddb2bSKalle Valo } 2878e8ddb2bSKalle Valo 2888e8ddb2bSKalle Valo static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev) 2898e8ddb2bSKalle Valo { 2908e8ddb2bSKalle Valo int status; 2918e8ddb2bSKalle Valo u8 cpu_int_status; 2928e8ddb2bSKalle Valo u8 reg_buf[4]; 2938e8ddb2bSKalle Valo 2948e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n"); 2958e8ddb2bSKalle Valo 2968e8ddb2bSKalle Valo cpu_int_status = dev->irq_proc_reg.cpu_int_status & 2978e8ddb2bSKalle Valo dev->irq_en_reg.cpu_int_status_en; 2988e8ddb2bSKalle Valo if (!cpu_int_status) { 2998e8ddb2bSKalle Valo WARN_ON(1); 3008e8ddb2bSKalle Valo return -EIO; 3018e8ddb2bSKalle Valo } 3028e8ddb2bSKalle Valo 3038e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 3048e8ddb2bSKalle Valo "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", 3058e8ddb2bSKalle Valo cpu_int_status); 3068e8ddb2bSKalle Valo 3078e8ddb2bSKalle Valo /* Clear the interrupt */ 3088e8ddb2bSKalle Valo dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; 3098e8ddb2bSKalle Valo 3108e8ddb2bSKalle Valo /* 3118e8ddb2bSKalle Valo * Set up the register transfer buffer to hit the register 4 times , 3128e8ddb2bSKalle Valo * this is done to make the access 4-byte aligned to mitigate issues 3138e8ddb2bSKalle Valo * with host bus interconnects that restrict bus transfer lengths to 3148e8ddb2bSKalle Valo * be a multiple of 4-bytes. 3158e8ddb2bSKalle Valo */ 3168e8ddb2bSKalle Valo 3178e8ddb2bSKalle Valo /* set W1C value to clear the interrupt, this hits the register first */ 3188e8ddb2bSKalle Valo reg_buf[0] = cpu_int_status; 3198e8ddb2bSKalle Valo /* the remaining are set to zero which have no-effect */ 3208e8ddb2bSKalle Valo reg_buf[1] = 0; 3218e8ddb2bSKalle Valo reg_buf[2] = 0; 3228e8ddb2bSKalle Valo reg_buf[3] = 0; 3238e8ddb2bSKalle Valo 3248e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, 3258e8ddb2bSKalle Valo reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 3268e8ddb2bSKalle Valo 3278e8ddb2bSKalle Valo if (status) 3288e8ddb2bSKalle Valo WARN_ON(1); 3298e8ddb2bSKalle Valo 3308e8ddb2bSKalle Valo return status; 3318e8ddb2bSKalle Valo } 3328e8ddb2bSKalle Valo 3338e8ddb2bSKalle Valo /* process pending interrupts synchronously */ 3348e8ddb2bSKalle Valo static int proc_pending_irqs(struct ath6kl_device *dev, bool *done) 3358e8ddb2bSKalle Valo { 3368e8ddb2bSKalle Valo struct ath6kl_irq_proc_registers *rg; 3378e8ddb2bSKalle Valo int status = 0; 3388e8ddb2bSKalle Valo u8 host_int_status = 0; 3398e8ddb2bSKalle Valo u32 lk_ahd = 0; 3408e8ddb2bSKalle Valo u8 htc_mbox = 1 << HTC_MAILBOX; 3418e8ddb2bSKalle Valo 3428e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev); 3438e8ddb2bSKalle Valo 3448e8ddb2bSKalle Valo /* 3458e8ddb2bSKalle Valo * NOTE: HIF implementation guarantees that the context of this 3468e8ddb2bSKalle Valo * call allows us to perform SYNCHRONOUS I/O, that is we can block, 3478e8ddb2bSKalle Valo * sleep or call any API that can block or switch thread/task 3488e8ddb2bSKalle Valo * contexts. This is a fully schedulable context. 3498e8ddb2bSKalle Valo */ 3508e8ddb2bSKalle Valo 3518e8ddb2bSKalle Valo /* 3528e8ddb2bSKalle Valo * Process pending intr only when int_status_en is clear, it may 3538e8ddb2bSKalle Valo * result in unnecessary bus transaction otherwise. Target may be 3548e8ddb2bSKalle Valo * unresponsive at the time. 3558e8ddb2bSKalle Valo */ 3568e8ddb2bSKalle Valo if (dev->irq_en_reg.int_status_en) { 3578e8ddb2bSKalle Valo /* 3588e8ddb2bSKalle Valo * Read the first 28 bytes of the HTC register table. This 3598e8ddb2bSKalle Valo * will yield us the value of different int status 3608e8ddb2bSKalle Valo * registers and the lookahead registers. 3618e8ddb2bSKalle Valo * 3628e8ddb2bSKalle Valo * length = sizeof(int_status) + sizeof(cpu_int_status) 3638e8ddb2bSKalle Valo * + sizeof(error_int_status) + 3648e8ddb2bSKalle Valo * sizeof(counter_int_status) + 3658e8ddb2bSKalle Valo * sizeof(mbox_frame) + sizeof(rx_lkahd_valid) 3668e8ddb2bSKalle Valo * + sizeof(hole) + sizeof(rx_lkahd) + 3678e8ddb2bSKalle Valo * sizeof(int_status_en) + 3688e8ddb2bSKalle Valo * sizeof(cpu_int_status_en) + 3698e8ddb2bSKalle Valo * sizeof(err_int_status_en) + 3708e8ddb2bSKalle Valo * sizeof(cntr_int_status_en); 3718e8ddb2bSKalle Valo */ 3728e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 3738e8ddb2bSKalle Valo (u8 *) &dev->irq_proc_reg, 3748e8ddb2bSKalle Valo sizeof(dev->irq_proc_reg), 3758e8ddb2bSKalle Valo HIF_RD_SYNC_BYTE_INC); 3768e8ddb2bSKalle Valo if (status) 3778e8ddb2bSKalle Valo goto out; 3788e8ddb2bSKalle Valo 3798e8ddb2bSKalle Valo if (AR_DBG_LVL_CHECK(ATH6KL_DBG_IRQ)) 3808e8ddb2bSKalle Valo ath6kl_dump_registers(dev, &dev->irq_proc_reg, 3818e8ddb2bSKalle Valo &dev->irq_en_reg); 3828e8ddb2bSKalle Valo 3838e8ddb2bSKalle Valo /* Update only those registers that are enabled */ 3848e8ddb2bSKalle Valo host_int_status = dev->irq_proc_reg.host_int_status & 3858e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en; 3868e8ddb2bSKalle Valo 3878e8ddb2bSKalle Valo /* Look at mbox status */ 3888e8ddb2bSKalle Valo if (host_int_status & htc_mbox) { 3898e8ddb2bSKalle Valo /* 3908e8ddb2bSKalle Valo * Mask out pending mbox value, we use "lookAhead as 3918e8ddb2bSKalle Valo * the real flag for mbox processing. 3928e8ddb2bSKalle Valo */ 3938e8ddb2bSKalle Valo host_int_status &= ~htc_mbox; 3948e8ddb2bSKalle Valo if (dev->irq_proc_reg.rx_lkahd_valid & 3958e8ddb2bSKalle Valo htc_mbox) { 3968e8ddb2bSKalle Valo rg = &dev->irq_proc_reg; 3978e8ddb2bSKalle Valo lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 3988e8ddb2bSKalle Valo if (!lk_ahd) 3998e8ddb2bSKalle Valo ath6kl_err("lookAhead is zero!\n"); 4008e8ddb2bSKalle Valo } 4018e8ddb2bSKalle Valo } 4028e8ddb2bSKalle Valo } 4038e8ddb2bSKalle Valo 4048e8ddb2bSKalle Valo if (!host_int_status && !lk_ahd) { 4058e8ddb2bSKalle Valo *done = true; 4068e8ddb2bSKalle Valo goto out; 4078e8ddb2bSKalle Valo } 4088e8ddb2bSKalle Valo 4098e8ddb2bSKalle Valo if (lk_ahd) { 4108e8ddb2bSKalle Valo int fetched = 0; 4118e8ddb2bSKalle Valo 4128e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 4138e8ddb2bSKalle Valo "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd); 4148e8ddb2bSKalle Valo /* 4158e8ddb2bSKalle Valo * Mailbox Interrupt, the HTC layer may issue async 4168e8ddb2bSKalle Valo * requests to empty the mailbox. When emptying the recv 4178e8ddb2bSKalle Valo * mailbox we use the async handler above called from the 4188e8ddb2bSKalle Valo * completion routine of the callers read request. This can 4198e8ddb2bSKalle Valo * improve performance by reducing context switching when 4208e8ddb2bSKalle Valo * we rapidly pull packets. 4218e8ddb2bSKalle Valo */ 4228e8ddb2bSKalle Valo status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, 4238e8ddb2bSKalle Valo lk_ahd, &fetched); 4248e8ddb2bSKalle Valo if (status) 4258e8ddb2bSKalle Valo goto out; 4268e8ddb2bSKalle Valo 4278e8ddb2bSKalle Valo if (!fetched) 4288e8ddb2bSKalle Valo /* 4298e8ddb2bSKalle Valo * HTC could not pull any messages out due to lack 4308e8ddb2bSKalle Valo * of resources. 4318e8ddb2bSKalle Valo */ 4328e8ddb2bSKalle Valo dev->htc_cnxt->chk_irq_status_cnt = 0; 4338e8ddb2bSKalle Valo } 4348e8ddb2bSKalle Valo 4358e8ddb2bSKalle Valo /* now handle the rest of them */ 4368e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 4378e8ddb2bSKalle Valo "valid interrupt source(s) for other interrupts: 0x%x\n", 4388e8ddb2bSKalle Valo host_int_status); 4398e8ddb2bSKalle Valo 4408e8ddb2bSKalle Valo if (MS(HOST_INT_STATUS_CPU, host_int_status)) { 4418e8ddb2bSKalle Valo /* CPU Interrupt */ 4428e8ddb2bSKalle Valo status = ath6kl_hif_proc_cpu_intr(dev); 4438e8ddb2bSKalle Valo if (status) 4448e8ddb2bSKalle Valo goto out; 4458e8ddb2bSKalle Valo } 4468e8ddb2bSKalle Valo 4478e8ddb2bSKalle Valo if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { 4488e8ddb2bSKalle Valo /* Error Interrupt */ 4498e8ddb2bSKalle Valo status = ath6kl_hif_proc_err_intr(dev); 4508e8ddb2bSKalle Valo if (status) 4518e8ddb2bSKalle Valo goto out; 4528e8ddb2bSKalle Valo } 4538e8ddb2bSKalle Valo 4548e8ddb2bSKalle Valo if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) 4558e8ddb2bSKalle Valo /* Counter Interrupt */ 4568e8ddb2bSKalle Valo status = ath6kl_hif_proc_counter_intr(dev); 4578e8ddb2bSKalle Valo 4588e8ddb2bSKalle Valo out: 4598e8ddb2bSKalle Valo /* 4608e8ddb2bSKalle Valo * An optimization to bypass reading the IRQ status registers 4618e8ddb2bSKalle Valo * unecessarily which can re-wake the target, if upper layers 4628e8ddb2bSKalle Valo * determine that we are in a low-throughput mode, we can rely on 4638e8ddb2bSKalle Valo * taking another interrupt rather than re-checking the status 4648e8ddb2bSKalle Valo * registers which can re-wake the target. 4658e8ddb2bSKalle Valo * 4668e8ddb2bSKalle Valo * NOTE : for host interfaces that makes use of detecting pending 4678e8ddb2bSKalle Valo * mbox messages at hif can not use this optimization due to 4688e8ddb2bSKalle Valo * possible side effects, SPI requires the host to drain all 4698e8ddb2bSKalle Valo * messages from the mailbox before exiting the ISR routine. 4708e8ddb2bSKalle Valo */ 4718e8ddb2bSKalle Valo 4728e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 4738e8ddb2bSKalle Valo "bypassing irq status re-check, forcing done\n"); 4748e8ddb2bSKalle Valo 4758e8ddb2bSKalle Valo if (!dev->htc_cnxt->chk_irq_status_cnt) 4768e8ddb2bSKalle Valo *done = true; 4778e8ddb2bSKalle Valo 4788e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, 4798e8ddb2bSKalle Valo "proc_pending_irqs: (done:%d, status=%d\n", *done, status); 4808e8ddb2bSKalle Valo 4818e8ddb2bSKalle Valo return status; 4828e8ddb2bSKalle Valo } 4838e8ddb2bSKalle Valo 4848e8ddb2bSKalle Valo /* interrupt handler, kicks off all interrupt processing */ 4858e8ddb2bSKalle Valo int ath6kl_hif_intr_bh_handler(struct ath6kl *ar) 4868e8ddb2bSKalle Valo { 4878e8ddb2bSKalle Valo struct ath6kl_device *dev = ar->htc_target->dev; 488d60e8ab6SKalle Valo unsigned long timeout; 4898e8ddb2bSKalle Valo int status = 0; 4908e8ddb2bSKalle Valo bool done = false; 4918e8ddb2bSKalle Valo 4928e8ddb2bSKalle Valo /* 4938e8ddb2bSKalle Valo * Reset counter used to flag a re-scan of IRQ status registers on 4948e8ddb2bSKalle Valo * the target. 4958e8ddb2bSKalle Valo */ 4968e8ddb2bSKalle Valo dev->htc_cnxt->chk_irq_status_cnt = 0; 4978e8ddb2bSKalle Valo 4988e8ddb2bSKalle Valo /* 4998e8ddb2bSKalle Valo * IRQ processing is synchronous, interrupt status registers can be 5008e8ddb2bSKalle Valo * re-read. 5018e8ddb2bSKalle Valo */ 502d60e8ab6SKalle Valo timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT); 503d60e8ab6SKalle Valo while (time_before(jiffies, timeout) && !done) { 5048e8ddb2bSKalle Valo status = proc_pending_irqs(dev, &done); 5058e8ddb2bSKalle Valo if (status) 5068e8ddb2bSKalle Valo break; 5078e8ddb2bSKalle Valo } 5088e8ddb2bSKalle Valo 5098e8ddb2bSKalle Valo return status; 5108e8ddb2bSKalle Valo } 5118e8ddb2bSKalle Valo 5128e8ddb2bSKalle Valo static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev) 5138e8ddb2bSKalle Valo { 5148e8ddb2bSKalle Valo struct ath6kl_irq_enable_reg regs; 5158e8ddb2bSKalle Valo int status; 5168e8ddb2bSKalle Valo 5178e8ddb2bSKalle Valo spin_lock_bh(&dev->lock); 5188e8ddb2bSKalle Valo 5198e8ddb2bSKalle Valo /* Enable all but ATH6KL CPU interrupts */ 5208e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en = 5218e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_ERROR, 0x01) | 5228e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_CPU, 0x01) | 5238e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_COUNTER, 0x01); 5248e8ddb2bSKalle Valo 5258e8ddb2bSKalle Valo /* 5268e8ddb2bSKalle Valo * NOTE: There are some cases where HIF can do detection of 5278e8ddb2bSKalle Valo * pending mbox messages which is disabled now. 5288e8ddb2bSKalle Valo */ 5298e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 5308e8ddb2bSKalle Valo 5318e8ddb2bSKalle Valo /* Set up the CPU Interrupt status Register */ 5328e8ddb2bSKalle Valo dev->irq_en_reg.cpu_int_status_en = 0; 5338e8ddb2bSKalle Valo 5348e8ddb2bSKalle Valo /* Set up the Error Interrupt status Register */ 5358e8ddb2bSKalle Valo dev->irq_en_reg.err_int_status_en = 5368e8ddb2bSKalle Valo SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | 5378e8ddb2bSKalle Valo SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); 5388e8ddb2bSKalle Valo 5398e8ddb2bSKalle Valo /* 5408e8ddb2bSKalle Valo * Enable Counter interrupt status register to get fatal errors for 5418e8ddb2bSKalle Valo * debugging. 5428e8ddb2bSKalle Valo */ 5438e8ddb2bSKalle Valo dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, 5448e8ddb2bSKalle Valo ATH6KL_TARGET_DEBUG_INTR_MASK); 5458e8ddb2bSKalle Valo memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 5468e8ddb2bSKalle Valo 5478e8ddb2bSKalle Valo spin_unlock_bh(&dev->lock); 5488e8ddb2bSKalle Valo 5498e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 5508e8ddb2bSKalle Valo ®s.int_status_en, sizeof(regs), 5518e8ddb2bSKalle Valo HIF_WR_SYNC_BYTE_INC); 5528e8ddb2bSKalle Valo 5538e8ddb2bSKalle Valo if (status) 5548e8ddb2bSKalle Valo ath6kl_err("failed to update interrupt ctl reg err: %d\n", 5558e8ddb2bSKalle Valo status); 5568e8ddb2bSKalle Valo 5578e8ddb2bSKalle Valo return status; 5588e8ddb2bSKalle Valo } 5598e8ddb2bSKalle Valo 5608e8ddb2bSKalle Valo int ath6kl_hif_disable_intrs(struct ath6kl_device *dev) 5618e8ddb2bSKalle Valo { 5628e8ddb2bSKalle Valo struct ath6kl_irq_enable_reg regs; 5638e8ddb2bSKalle Valo 5648e8ddb2bSKalle Valo spin_lock_bh(&dev->lock); 5658e8ddb2bSKalle Valo /* Disable all interrupts */ 5668e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en = 0; 5678e8ddb2bSKalle Valo dev->irq_en_reg.cpu_int_status_en = 0; 5688e8ddb2bSKalle Valo dev->irq_en_reg.err_int_status_en = 0; 5698e8ddb2bSKalle Valo dev->irq_en_reg.cntr_int_status_en = 0; 5708e8ddb2bSKalle Valo memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 5718e8ddb2bSKalle Valo spin_unlock_bh(&dev->lock); 5728e8ddb2bSKalle Valo 5738e8ddb2bSKalle Valo return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 5748e8ddb2bSKalle Valo ®s.int_status_en, sizeof(regs), 5758e8ddb2bSKalle Valo HIF_WR_SYNC_BYTE_INC); 5768e8ddb2bSKalle Valo } 5778e8ddb2bSKalle Valo 5788e8ddb2bSKalle Valo /* enable device interrupts */ 5798e8ddb2bSKalle Valo int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev) 5808e8ddb2bSKalle Valo { 5818e8ddb2bSKalle Valo int status = 0; 5828e8ddb2bSKalle Valo 5838e8ddb2bSKalle Valo /* 5848e8ddb2bSKalle Valo * Make sure interrupt are disabled before unmasking at the HIF 5858e8ddb2bSKalle Valo * layer. The rationale here is that between device insertion 5868e8ddb2bSKalle Valo * (where we clear the interrupts the first time) and when HTC 5878e8ddb2bSKalle Valo * is finally ready to handle interrupts, other software can perform 5888e8ddb2bSKalle Valo * target "soft" resets. The ATH6KL interrupt enables reset back to an 5898e8ddb2bSKalle Valo * "enabled" state when this happens. 5908e8ddb2bSKalle Valo */ 5918e8ddb2bSKalle Valo ath6kl_hif_disable_intrs(dev); 5928e8ddb2bSKalle Valo 5938e8ddb2bSKalle Valo /* unmask the host controller interrupts */ 5948e8ddb2bSKalle Valo ath6kl_hif_irq_enable(dev->ar); 5958e8ddb2bSKalle Valo status = ath6kl_hif_enable_intrs(dev); 5968e8ddb2bSKalle Valo 5978e8ddb2bSKalle Valo return status; 5988e8ddb2bSKalle Valo } 5998e8ddb2bSKalle Valo 6008e8ddb2bSKalle Valo /* disable all device interrupts */ 6018e8ddb2bSKalle Valo int ath6kl_hif_mask_intrs(struct ath6kl_device *dev) 6028e8ddb2bSKalle Valo { 6038e8ddb2bSKalle Valo /* 6048e8ddb2bSKalle Valo * Mask the interrupt at the HIF layer to avoid any stray interrupt 6058e8ddb2bSKalle Valo * taken while we zero out our shadow registers in 6068e8ddb2bSKalle Valo * ath6kl_hif_disable_intrs(). 6078e8ddb2bSKalle Valo */ 6088e8ddb2bSKalle Valo ath6kl_hif_irq_disable(dev->ar); 6098e8ddb2bSKalle Valo 6108e8ddb2bSKalle Valo return ath6kl_hif_disable_intrs(dev); 6118e8ddb2bSKalle Valo } 6128e8ddb2bSKalle Valo 6138e8ddb2bSKalle Valo int ath6kl_hif_setup(struct ath6kl_device *dev) 6148e8ddb2bSKalle Valo { 6158e8ddb2bSKalle Valo int status = 0; 6168e8ddb2bSKalle Valo 6178e8ddb2bSKalle Valo spin_lock_init(&dev->lock); 6188e8ddb2bSKalle Valo 6198e8ddb2bSKalle Valo /* 6208e8ddb2bSKalle Valo * NOTE: we actually get the block size of a mailbox other than 0, 6218e8ddb2bSKalle Valo * for SDIO the block size on mailbox 0 is artificially set to 1. 6228e8ddb2bSKalle Valo * So we use the block size that is set for the other 3 mailboxes. 6238e8ddb2bSKalle Valo */ 6248e8ddb2bSKalle Valo dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; 6258e8ddb2bSKalle Valo 6268e8ddb2bSKalle Valo /* must be a power of 2 */ 6278e8ddb2bSKalle Valo if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { 6288e8ddb2bSKalle Valo WARN_ON(1); 6298e8ddb2bSKalle Valo status = -EINVAL; 6308e8ddb2bSKalle Valo goto fail_setup; 6318e8ddb2bSKalle Valo } 6328e8ddb2bSKalle Valo 6338e8ddb2bSKalle Valo /* assemble mask, used for padding to a block */ 6348e8ddb2bSKalle Valo dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; 6358e8ddb2bSKalle Valo 63683973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n", 6378e8ddb2bSKalle Valo dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); 6388e8ddb2bSKalle Valo 6398e8ddb2bSKalle Valo status = ath6kl_hif_disable_intrs(dev); 6408e8ddb2bSKalle Valo 6418e8ddb2bSKalle Valo fail_setup: 6428e8ddb2bSKalle Valo return status; 6438e8ddb2bSKalle Valo 6448e8ddb2bSKalle Valo } 645