18e8ddb2bSKalle Valo /*
28e8ddb2bSKalle Valo * Copyright (c) 2007-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
48e8ddb2bSKalle Valo *
58e8ddb2bSKalle Valo * Permission to use, copy, modify, and/or distribute this software for any
68e8ddb2bSKalle Valo * purpose with or without fee is hereby granted, provided that the above
78e8ddb2bSKalle Valo * copyright notice and this permission notice appear in all copies.
88e8ddb2bSKalle Valo *
98e8ddb2bSKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
108e8ddb2bSKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
118e8ddb2bSKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
128e8ddb2bSKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
138e8ddb2bSKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
148e8ddb2bSKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
158e8ddb2bSKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
168e8ddb2bSKalle Valo */
172e1cb23cSKalle Valo #include "hif.h"
188e8ddb2bSKalle Valo
19d6a434d6SKalle Valo #include <linux/export.h>
20d6a434d6SKalle Valo
218e8ddb2bSKalle Valo #include "core.h"
228e8ddb2bSKalle Valo #include "target.h"
238e8ddb2bSKalle Valo #include "hif-ops.h"
248e8ddb2bSKalle Valo #include "debug.h"
25d57f093aSKalle Valo #include "trace.h"
268e8ddb2bSKalle Valo
278e8ddb2bSKalle Valo #define MAILBOX_FOR_BLOCK_SIZE 1
288e8ddb2bSKalle Valo
298e8ddb2bSKalle Valo #define ATH6KL_TIME_QUANTUM 10 /* in ms */
308e8ddb2bSKalle Valo
ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req * req,bool from_dma)318e8ddb2bSKalle Valo static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req,
328e8ddb2bSKalle Valo bool from_dma)
338e8ddb2bSKalle Valo {
348e8ddb2bSKalle Valo u8 *buf;
358e8ddb2bSKalle Valo int i;
368e8ddb2bSKalle Valo
378e8ddb2bSKalle Valo buf = req->virt_dma_buf;
388e8ddb2bSKalle Valo
398e8ddb2bSKalle Valo for (i = 0; i < req->scat_entries; i++) {
408e8ddb2bSKalle Valo if (from_dma)
418e8ddb2bSKalle Valo memcpy(req->scat_list[i].buf, buf,
428e8ddb2bSKalle Valo req->scat_list[i].len);
438e8ddb2bSKalle Valo else
448e8ddb2bSKalle Valo memcpy(buf, req->scat_list[i].buf,
458e8ddb2bSKalle Valo req->scat_list[i].len);
468e8ddb2bSKalle Valo
478e8ddb2bSKalle Valo buf += req->scat_list[i].len;
488e8ddb2bSKalle Valo }
498e8ddb2bSKalle Valo
508e8ddb2bSKalle Valo return 0;
518e8ddb2bSKalle Valo }
528e8ddb2bSKalle Valo
ath6kl_hif_rw_comp_handler(void * context,int status)538e8ddb2bSKalle Valo int ath6kl_hif_rw_comp_handler(void *context, int status)
548e8ddb2bSKalle Valo {
558e8ddb2bSKalle Valo struct htc_packet *packet = context;
568e8ddb2bSKalle Valo
5783973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n",
588e8ddb2bSKalle Valo packet, status);
598e8ddb2bSKalle Valo
608e8ddb2bSKalle Valo packet->status = status;
618e8ddb2bSKalle Valo packet->completion(packet->context, packet);
628e8ddb2bSKalle Valo
638e8ddb2bSKalle Valo return 0;
648e8ddb2bSKalle Valo }
65d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_hif_rw_comp_handler);
66d6a434d6SKalle Valo
67f3fa6314SDan Kephart #define REGISTER_DUMP_COUNT 60
686250aac6SKalle Valo #define REGISTER_DUMP_LEN_MAX 60
696250aac6SKalle Valo
ath6kl_hif_dump_fw_crash(struct ath6kl * ar)706250aac6SKalle Valo static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar)
716250aac6SKalle Valo {
726250aac6SKalle Valo __le32 regdump_val[REGISTER_DUMP_LEN_MAX];
736250aac6SKalle Valo u32 i, address, regdump_addr = 0;
746250aac6SKalle Valo int ret;
756250aac6SKalle Valo
766250aac6SKalle Valo /* the reg dump pointer is copied to the host interest area */
776250aac6SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state));
786250aac6SKalle Valo address = TARG_VTOP(ar->target_type, address);
796250aac6SKalle Valo
806250aac6SKalle Valo /* read RAM location through diagnostic window */
816250aac6SKalle Valo ret = ath6kl_diag_read32(ar, address, ®dump_addr);
826250aac6SKalle Valo
836250aac6SKalle Valo if (ret || !regdump_addr) {
846250aac6SKalle Valo ath6kl_warn("failed to get ptr to register dump area: %d\n",
856250aac6SKalle Valo ret);
866250aac6SKalle Valo return;
876250aac6SKalle Valo }
886250aac6SKalle Valo
896250aac6SKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n",
906250aac6SKalle Valo regdump_addr);
916250aac6SKalle Valo regdump_addr = TARG_VTOP(ar->target_type, regdump_addr);
926250aac6SKalle Valo
936250aac6SKalle Valo /* fetch register dump data */
946250aac6SKalle Valo ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0],
95f3fa6314SDan Kephart REGISTER_DUMP_COUNT * (sizeof(u32)));
966250aac6SKalle Valo if (ret) {
976250aac6SKalle Valo ath6kl_warn("failed to get register dump: %d\n", ret);
986250aac6SKalle Valo return;
996250aac6SKalle Valo }
1006250aac6SKalle Valo
1016250aac6SKalle Valo ath6kl_info("crash dump:\n");
1026250aac6SKalle Valo ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version,
1036250aac6SKalle Valo ar->wiphy->fw_version);
1046250aac6SKalle Valo
105f3fa6314SDan Kephart BUILD_BUG_ON(REGISTER_DUMP_COUNT % 4);
1066250aac6SKalle Valo
107f3fa6314SDan Kephart for (i = 0; i < REGISTER_DUMP_COUNT; i += 4) {
1086250aac6SKalle Valo ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n",
1093b96d49aSNaveen Gangadharan i,
1106250aac6SKalle Valo le32_to_cpu(regdump_val[i]),
1116250aac6SKalle Valo le32_to_cpu(regdump_val[i + 1]),
1126250aac6SKalle Valo le32_to_cpu(regdump_val[i + 2]),
1136250aac6SKalle Valo le32_to_cpu(regdump_val[i + 3]));
1146250aac6SKalle Valo }
1156250aac6SKalle Valo }
1168e8ddb2bSKalle Valo
ath6kl_hif_proc_dbg_intr(struct ath6kl_device * dev)1178e8ddb2bSKalle Valo static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev)
1188e8ddb2bSKalle Valo {
1198e8ddb2bSKalle Valo u32 dummy;
1206250aac6SKalle Valo int ret;
1218e8ddb2bSKalle Valo
1226250aac6SKalle Valo ath6kl_warn("firmware crashed\n");
1238e8ddb2bSKalle Valo
1248e8ddb2bSKalle Valo /*
1258e8ddb2bSKalle Valo * read counter to clear the interrupt, the debug error interrupt is
1268e8ddb2bSKalle Valo * counter 0.
1278e8ddb2bSKalle Valo */
1286250aac6SKalle Valo ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS,
1298e8ddb2bSKalle Valo (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC);
1306250aac6SKalle Valo if (ret)
1316250aac6SKalle Valo ath6kl_warn("Failed to clear debug interrupt: %d\n", ret);
1328e8ddb2bSKalle Valo
1336250aac6SKalle Valo ath6kl_hif_dump_fw_crash(dev->ar);
134af840ba7SEtay Luz ath6kl_read_fwlogs(dev->ar);
13584caf800SVasanthakumar Thiagarajan ath6kl_recovery_err_notify(dev->ar, ATH6KL_FW_ASSERT);
1366250aac6SKalle Valo
1376250aac6SKalle Valo return ret;
1388e8ddb2bSKalle Valo }
1398e8ddb2bSKalle Valo
1408e8ddb2bSKalle Valo /* mailbox recv message polling */
ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device * dev,u32 * lk_ahd,int timeout)1418e8ddb2bSKalle Valo int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
1428e8ddb2bSKalle Valo int timeout)
1438e8ddb2bSKalle Valo {
1448e8ddb2bSKalle Valo struct ath6kl_irq_proc_registers *rg;
1458e8ddb2bSKalle Valo int status = 0, i;
1468e8ddb2bSKalle Valo u8 htc_mbox = 1 << HTC_MAILBOX;
1478e8ddb2bSKalle Valo
1488e8ddb2bSKalle Valo for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) {
1498e8ddb2bSKalle Valo /* this is the standard HIF way, load the reg table */
1508e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS,
1518e8ddb2bSKalle Valo (u8 *) &dev->irq_proc_reg,
1528e8ddb2bSKalle Valo sizeof(dev->irq_proc_reg),
1538e8ddb2bSKalle Valo HIF_RD_SYNC_BYTE_INC);
1548e8ddb2bSKalle Valo
1558e8ddb2bSKalle Valo if (status) {
1568e8ddb2bSKalle Valo ath6kl_err("failed to read reg table\n");
1578e8ddb2bSKalle Valo return status;
1588e8ddb2bSKalle Valo }
1598e8ddb2bSKalle Valo
1608e8ddb2bSKalle Valo /* check for MBOX data and valid lookahead */
1618e8ddb2bSKalle Valo if (dev->irq_proc_reg.host_int_status & htc_mbox) {
1628e8ddb2bSKalle Valo if (dev->irq_proc_reg.rx_lkahd_valid &
1638e8ddb2bSKalle Valo htc_mbox) {
1648e8ddb2bSKalle Valo /*
1658e8ddb2bSKalle Valo * Mailbox has a message and the look ahead
1668e8ddb2bSKalle Valo * is valid.
1678e8ddb2bSKalle Valo */
1688e8ddb2bSKalle Valo rg = &dev->irq_proc_reg;
1698e8ddb2bSKalle Valo *lk_ahd =
1708e8ddb2bSKalle Valo le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]);
1718e8ddb2bSKalle Valo break;
1728e8ddb2bSKalle Valo }
1738e8ddb2bSKalle Valo }
1748e8ddb2bSKalle Valo
1758e8ddb2bSKalle Valo /* delay a little */
1768e8ddb2bSKalle Valo mdelay(ATH6KL_TIME_QUANTUM);
17783973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i);
1788e8ddb2bSKalle Valo }
1798e8ddb2bSKalle Valo
1808e8ddb2bSKalle Valo if (i == 0) {
1818e8ddb2bSKalle Valo ath6kl_err("timeout waiting for recv message\n");
1828e8ddb2bSKalle Valo status = -ETIME;
1838e8ddb2bSKalle Valo /* check if the target asserted */
1848e8ddb2bSKalle Valo if (dev->irq_proc_reg.counter_int_status &
1858e8ddb2bSKalle Valo ATH6KL_TARGET_DEBUG_INTR_MASK)
1868e8ddb2bSKalle Valo /*
1878e8ddb2bSKalle Valo * Target failure handler will be called in case of
1888e8ddb2bSKalle Valo * an assert.
1898e8ddb2bSKalle Valo */
1908e8ddb2bSKalle Valo ath6kl_hif_proc_dbg_intr(dev);
1918e8ddb2bSKalle Valo }
1928e8ddb2bSKalle Valo
1938e8ddb2bSKalle Valo return status;
1948e8ddb2bSKalle Valo }
1958e8ddb2bSKalle Valo
1968e8ddb2bSKalle Valo /*
1978e8ddb2bSKalle Valo * Disable packet reception (used in case the host runs out of buffers)
1988e8ddb2bSKalle Valo * using the interrupt enable registers through the host I/F
1998e8ddb2bSKalle Valo */
ath6kl_hif_rx_control(struct ath6kl_device * dev,bool enable_rx)2008e8ddb2bSKalle Valo int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx)
2018e8ddb2bSKalle Valo {
2028e8ddb2bSKalle Valo struct ath6kl_irq_enable_reg regs;
2038e8ddb2bSKalle Valo int status = 0;
2048e8ddb2bSKalle Valo
20583973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n",
20683973e03SKalle Valo enable_rx ? "enable" : "disable");
20783973e03SKalle Valo
2088e8ddb2bSKalle Valo /* take the lock to protect interrupt enable shadows */
2098e8ddb2bSKalle Valo spin_lock_bh(&dev->lock);
2108e8ddb2bSKalle Valo
2118e8ddb2bSKalle Valo if (enable_rx)
2128e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en |=
2138e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
2148e8ddb2bSKalle Valo else
2158e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en &=
2168e8ddb2bSKalle Valo ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
2178e8ddb2bSKalle Valo
2188e8ddb2bSKalle Valo memcpy(®s, &dev->irq_en_reg, sizeof(regs));
2198e8ddb2bSKalle Valo
2208e8ddb2bSKalle Valo spin_unlock_bh(&dev->lock);
2218e8ddb2bSKalle Valo
2228e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS,
2238e8ddb2bSKalle Valo ®s.int_status_en,
2248e8ddb2bSKalle Valo sizeof(struct ath6kl_irq_enable_reg),
2258e8ddb2bSKalle Valo HIF_WR_SYNC_BYTE_INC);
2268e8ddb2bSKalle Valo
2278e8ddb2bSKalle Valo return status;
2288e8ddb2bSKalle Valo }
2298e8ddb2bSKalle Valo
ath6kl_hif_submit_scat_req(struct ath6kl_device * dev,struct hif_scatter_req * scat_req,bool read)2308e8ddb2bSKalle Valo int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
2318e8ddb2bSKalle Valo struct hif_scatter_req *scat_req, bool read)
2328e8ddb2bSKalle Valo {
2338e8ddb2bSKalle Valo int status = 0;
2348e8ddb2bSKalle Valo
2358e8ddb2bSKalle Valo if (read) {
2368e8ddb2bSKalle Valo scat_req->req = HIF_RD_SYNC_BLOCK_FIX;
2378e8ddb2bSKalle Valo scat_req->addr = dev->ar->mbox_info.htc_addr;
2388e8ddb2bSKalle Valo } else {
2398e8ddb2bSKalle Valo scat_req->req = HIF_WR_ASYNC_BLOCK_INC;
2408e8ddb2bSKalle Valo
2418e8ddb2bSKalle Valo scat_req->addr =
2428e8ddb2bSKalle Valo (scat_req->len > HIF_MBOX_WIDTH) ?
2438e8ddb2bSKalle Valo dev->ar->mbox_info.htc_ext_addr :
2448e8ddb2bSKalle Valo dev->ar->mbox_info.htc_addr;
2458e8ddb2bSKalle Valo }
2468e8ddb2bSKalle Valo
24783973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF,
24883973e03SKalle Valo "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n",
2498e8ddb2bSKalle Valo scat_req->scat_entries, scat_req->len,
2508e8ddb2bSKalle Valo scat_req->addr, !read ? "async" : "sync",
2518e8ddb2bSKalle Valo (read) ? "rd" : "wr");
2528e8ddb2bSKalle Valo
2538e8ddb2bSKalle Valo if (!read && scat_req->virt_scat) {
2548e8ddb2bSKalle Valo status = ath6kl_hif_cp_scat_dma_buf(scat_req, false);
2558e8ddb2bSKalle Valo if (status) {
2568e8ddb2bSKalle Valo scat_req->status = status;
2578e8ddb2bSKalle Valo scat_req->complete(dev->ar->htc_target, scat_req);
2588e8ddb2bSKalle Valo return 0;
2598e8ddb2bSKalle Valo }
2608e8ddb2bSKalle Valo }
2618e8ddb2bSKalle Valo
2628e8ddb2bSKalle Valo status = ath6kl_hif_scat_req_rw(dev->ar, scat_req);
2638e8ddb2bSKalle Valo
2648e8ddb2bSKalle Valo if (read) {
2658e8ddb2bSKalle Valo /* in sync mode, we can touch the scatter request */
2668e8ddb2bSKalle Valo scat_req->status = status;
2678e8ddb2bSKalle Valo if (!status && scat_req->virt_scat)
2688e8ddb2bSKalle Valo scat_req->status =
2698e8ddb2bSKalle Valo ath6kl_hif_cp_scat_dma_buf(scat_req, true);
2708e8ddb2bSKalle Valo }
2718e8ddb2bSKalle Valo
2728e8ddb2bSKalle Valo return status;
2738e8ddb2bSKalle Valo }
2748e8ddb2bSKalle Valo
ath6kl_hif_proc_counter_intr(struct ath6kl_device * dev)2758e8ddb2bSKalle Valo static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev)
2768e8ddb2bSKalle Valo {
2778e8ddb2bSKalle Valo u8 counter_int_status;
2788e8ddb2bSKalle Valo
2798e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n");
2808e8ddb2bSKalle Valo
2818e8ddb2bSKalle Valo counter_int_status = dev->irq_proc_reg.counter_int_status &
2828e8ddb2bSKalle Valo dev->irq_en_reg.cntr_int_status_en;
2838e8ddb2bSKalle Valo
2848e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
2858e8ddb2bSKalle Valo "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
2868e8ddb2bSKalle Valo counter_int_status);
2878e8ddb2bSKalle Valo
2888e8ddb2bSKalle Valo /*
2898e8ddb2bSKalle Valo * NOTE: other modules like GMBOX may use the counter interrupt for
2908e8ddb2bSKalle Valo * credit flow control on other counters, we only need to check for
2918e8ddb2bSKalle Valo * the debug assertion counter interrupt.
2928e8ddb2bSKalle Valo */
2938e8ddb2bSKalle Valo if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK)
2948e8ddb2bSKalle Valo return ath6kl_hif_proc_dbg_intr(dev);
2958e8ddb2bSKalle Valo
2968e8ddb2bSKalle Valo return 0;
2978e8ddb2bSKalle Valo }
2988e8ddb2bSKalle Valo
ath6kl_hif_proc_err_intr(struct ath6kl_device * dev)2998e8ddb2bSKalle Valo static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev)
3008e8ddb2bSKalle Valo {
3018e8ddb2bSKalle Valo int status;
3028e8ddb2bSKalle Valo u8 error_int_status;
3038e8ddb2bSKalle Valo u8 reg_buf[4];
3048e8ddb2bSKalle Valo
3058e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n");
3068e8ddb2bSKalle Valo
3078e8ddb2bSKalle Valo error_int_status = dev->irq_proc_reg.error_int_status & 0x0F;
3088e8ddb2bSKalle Valo if (!error_int_status) {
3098e8ddb2bSKalle Valo WARN_ON(1);
3108e8ddb2bSKalle Valo return -EIO;
3118e8ddb2bSKalle Valo }
3128e8ddb2bSKalle Valo
3138e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
3148e8ddb2bSKalle Valo "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
3158e8ddb2bSKalle Valo error_int_status);
3168e8ddb2bSKalle Valo
3178e8ddb2bSKalle Valo if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status))
3188e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n");
3198e8ddb2bSKalle Valo
3208e8ddb2bSKalle Valo if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status))
3218e8ddb2bSKalle Valo ath6kl_err("rx underflow\n");
3228e8ddb2bSKalle Valo
3238e8ddb2bSKalle Valo if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status))
3248e8ddb2bSKalle Valo ath6kl_err("tx overflow\n");
3258e8ddb2bSKalle Valo
3268e8ddb2bSKalle Valo /* Clear the interrupt */
3278e8ddb2bSKalle Valo dev->irq_proc_reg.error_int_status &= ~error_int_status;
3288e8ddb2bSKalle Valo
3298e8ddb2bSKalle Valo /* set W1C value to clear the interrupt, this hits the register first */
3308e8ddb2bSKalle Valo reg_buf[0] = error_int_status;
3318e8ddb2bSKalle Valo reg_buf[1] = 0;
3328e8ddb2bSKalle Valo reg_buf[2] = 0;
3338e8ddb2bSKalle Valo reg_buf[3] = 0;
3348e8ddb2bSKalle Valo
3358e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS,
3368e8ddb2bSKalle Valo reg_buf, 4, HIF_WR_SYNC_BYTE_FIX);
3378e8ddb2bSKalle Valo
338f3ec3bf5SJulia Lawall WARN_ON(status);
3398e8ddb2bSKalle Valo
3408e8ddb2bSKalle Valo return status;
3418e8ddb2bSKalle Valo }
3428e8ddb2bSKalle Valo
ath6kl_hif_proc_cpu_intr(struct ath6kl_device * dev)3438e8ddb2bSKalle Valo static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev)
3448e8ddb2bSKalle Valo {
3458e8ddb2bSKalle Valo int status;
3468e8ddb2bSKalle Valo u8 cpu_int_status;
3478e8ddb2bSKalle Valo u8 reg_buf[4];
3488e8ddb2bSKalle Valo
3498e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n");
3508e8ddb2bSKalle Valo
3518e8ddb2bSKalle Valo cpu_int_status = dev->irq_proc_reg.cpu_int_status &
3528e8ddb2bSKalle Valo dev->irq_en_reg.cpu_int_status_en;
3538e8ddb2bSKalle Valo if (!cpu_int_status) {
3548e8ddb2bSKalle Valo WARN_ON(1);
3558e8ddb2bSKalle Valo return -EIO;
3568e8ddb2bSKalle Valo }
3578e8ddb2bSKalle Valo
3588e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
3598e8ddb2bSKalle Valo "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
3608e8ddb2bSKalle Valo cpu_int_status);
3618e8ddb2bSKalle Valo
3628e8ddb2bSKalle Valo /* Clear the interrupt */
3638e8ddb2bSKalle Valo dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status;
3648e8ddb2bSKalle Valo
3658e8ddb2bSKalle Valo /*
3668e8ddb2bSKalle Valo * Set up the register transfer buffer to hit the register 4 times ,
3678e8ddb2bSKalle Valo * this is done to make the access 4-byte aligned to mitigate issues
3688e8ddb2bSKalle Valo * with host bus interconnects that restrict bus transfer lengths to
3698e8ddb2bSKalle Valo * be a multiple of 4-bytes.
3708e8ddb2bSKalle Valo */
3718e8ddb2bSKalle Valo
3728e8ddb2bSKalle Valo /* set W1C value to clear the interrupt, this hits the register first */
3738e8ddb2bSKalle Valo reg_buf[0] = cpu_int_status;
3748e8ddb2bSKalle Valo /* the remaining are set to zero which have no-effect */
3758e8ddb2bSKalle Valo reg_buf[1] = 0;
3768e8ddb2bSKalle Valo reg_buf[2] = 0;
3778e8ddb2bSKalle Valo reg_buf[3] = 0;
3788e8ddb2bSKalle Valo
3798e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS,
3808e8ddb2bSKalle Valo reg_buf, 4, HIF_WR_SYNC_BYTE_FIX);
3818e8ddb2bSKalle Valo
382f3ec3bf5SJulia Lawall WARN_ON(status);
3838e8ddb2bSKalle Valo
3848e8ddb2bSKalle Valo return status;
3858e8ddb2bSKalle Valo }
3868e8ddb2bSKalle Valo
3878e8ddb2bSKalle Valo /* process pending interrupts synchronously */
proc_pending_irqs(struct ath6kl_device * dev,bool * done)3888e8ddb2bSKalle Valo static int proc_pending_irqs(struct ath6kl_device *dev, bool *done)
3898e8ddb2bSKalle Valo {
3908e8ddb2bSKalle Valo struct ath6kl_irq_proc_registers *rg;
3918e8ddb2bSKalle Valo int status = 0;
3928e8ddb2bSKalle Valo u8 host_int_status = 0;
3938e8ddb2bSKalle Valo u32 lk_ahd = 0;
3948e8ddb2bSKalle Valo u8 htc_mbox = 1 << HTC_MAILBOX;
3958e8ddb2bSKalle Valo
3968e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev);
3978e8ddb2bSKalle Valo
3988e8ddb2bSKalle Valo /*
3998e8ddb2bSKalle Valo * NOTE: HIF implementation guarantees that the context of this
4008e8ddb2bSKalle Valo * call allows us to perform SYNCHRONOUS I/O, that is we can block,
4018e8ddb2bSKalle Valo * sleep or call any API that can block or switch thread/task
4028e8ddb2bSKalle Valo * contexts. This is a fully schedulable context.
4038e8ddb2bSKalle Valo */
4048e8ddb2bSKalle Valo
4058e8ddb2bSKalle Valo /*
4068e8ddb2bSKalle Valo * Process pending intr only when int_status_en is clear, it may
4078e8ddb2bSKalle Valo * result in unnecessary bus transaction otherwise. Target may be
4088e8ddb2bSKalle Valo * unresponsive at the time.
4098e8ddb2bSKalle Valo */
4108e8ddb2bSKalle Valo if (dev->irq_en_reg.int_status_en) {
4118e8ddb2bSKalle Valo /*
4128e8ddb2bSKalle Valo * Read the first 28 bytes of the HTC register table. This
4138e8ddb2bSKalle Valo * will yield us the value of different int status
4148e8ddb2bSKalle Valo * registers and the lookahead registers.
4158e8ddb2bSKalle Valo *
4168e8ddb2bSKalle Valo * length = sizeof(int_status) + sizeof(cpu_int_status)
4178e8ddb2bSKalle Valo * + sizeof(error_int_status) +
4188e8ddb2bSKalle Valo * sizeof(counter_int_status) +
4198e8ddb2bSKalle Valo * sizeof(mbox_frame) + sizeof(rx_lkahd_valid)
4208e8ddb2bSKalle Valo * + sizeof(hole) + sizeof(rx_lkahd) +
4218e8ddb2bSKalle Valo * sizeof(int_status_en) +
4228e8ddb2bSKalle Valo * sizeof(cpu_int_status_en) +
4238e8ddb2bSKalle Valo * sizeof(err_int_status_en) +
4248e8ddb2bSKalle Valo * sizeof(cntr_int_status_en);
4258e8ddb2bSKalle Valo */
4268e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS,
4278e8ddb2bSKalle Valo (u8 *) &dev->irq_proc_reg,
4288e8ddb2bSKalle Valo sizeof(dev->irq_proc_reg),
4298e8ddb2bSKalle Valo HIF_RD_SYNC_BYTE_INC);
4308e8ddb2bSKalle Valo if (status)
4318e8ddb2bSKalle Valo goto out;
4328e8ddb2bSKalle Valo
4338e8ddb2bSKalle Valo ath6kl_dump_registers(dev, &dev->irq_proc_reg,
4348e8ddb2bSKalle Valo &dev->irq_en_reg);
435d57f093aSKalle Valo trace_ath6kl_sdio_irq(&dev->irq_en_reg,
436d57f093aSKalle Valo sizeof(dev->irq_en_reg));
4378e8ddb2bSKalle Valo
4388e8ddb2bSKalle Valo /* Update only those registers that are enabled */
4398e8ddb2bSKalle Valo host_int_status = dev->irq_proc_reg.host_int_status &
4408e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en;
4418e8ddb2bSKalle Valo
4428e8ddb2bSKalle Valo /* Look at mbox status */
4438e8ddb2bSKalle Valo if (host_int_status & htc_mbox) {
4448e8ddb2bSKalle Valo /*
4458e8ddb2bSKalle Valo * Mask out pending mbox value, we use "lookAhead as
4468e8ddb2bSKalle Valo * the real flag for mbox processing.
4478e8ddb2bSKalle Valo */
4488e8ddb2bSKalle Valo host_int_status &= ~htc_mbox;
4498e8ddb2bSKalle Valo if (dev->irq_proc_reg.rx_lkahd_valid &
4508e8ddb2bSKalle Valo htc_mbox) {
4518e8ddb2bSKalle Valo rg = &dev->irq_proc_reg;
4528e8ddb2bSKalle Valo lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]);
4538e8ddb2bSKalle Valo if (!lk_ahd)
4548e8ddb2bSKalle Valo ath6kl_err("lookAhead is zero!\n");
4558e8ddb2bSKalle Valo }
4568e8ddb2bSKalle Valo }
4578e8ddb2bSKalle Valo }
4588e8ddb2bSKalle Valo
4598e8ddb2bSKalle Valo if (!host_int_status && !lk_ahd) {
4608e8ddb2bSKalle Valo *done = true;
4618e8ddb2bSKalle Valo goto out;
4628e8ddb2bSKalle Valo }
4638e8ddb2bSKalle Valo
4648e8ddb2bSKalle Valo if (lk_ahd) {
4658e8ddb2bSKalle Valo int fetched = 0;
4668e8ddb2bSKalle Valo
4678e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
4688e8ddb2bSKalle Valo "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd);
4698e8ddb2bSKalle Valo /*
4708e8ddb2bSKalle Valo * Mailbox Interrupt, the HTC layer may issue async
4718e8ddb2bSKalle Valo * requests to empty the mailbox. When emptying the recv
4728e8ddb2bSKalle Valo * mailbox we use the async handler above called from the
4738e8ddb2bSKalle Valo * completion routine of the callers read request. This can
4748e8ddb2bSKalle Valo * improve performance by reducing context switching when
4758e8ddb2bSKalle Valo * we rapidly pull packets.
4768e8ddb2bSKalle Valo */
4778e8ddb2bSKalle Valo status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt,
4788e8ddb2bSKalle Valo lk_ahd, &fetched);
4798e8ddb2bSKalle Valo if (status)
4808e8ddb2bSKalle Valo goto out;
4818e8ddb2bSKalle Valo
4828e8ddb2bSKalle Valo if (!fetched)
4838e8ddb2bSKalle Valo /*
4848e8ddb2bSKalle Valo * HTC could not pull any messages out due to lack
4858e8ddb2bSKalle Valo * of resources.
4868e8ddb2bSKalle Valo */
4878e8ddb2bSKalle Valo dev->htc_cnxt->chk_irq_status_cnt = 0;
4888e8ddb2bSKalle Valo }
4898e8ddb2bSKalle Valo
4908e8ddb2bSKalle Valo /* now handle the rest of them */
4918e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
4928e8ddb2bSKalle Valo "valid interrupt source(s) for other interrupts: 0x%x\n",
4938e8ddb2bSKalle Valo host_int_status);
4948e8ddb2bSKalle Valo
4958e8ddb2bSKalle Valo if (MS(HOST_INT_STATUS_CPU, host_int_status)) {
4968e8ddb2bSKalle Valo /* CPU Interrupt */
4978e8ddb2bSKalle Valo status = ath6kl_hif_proc_cpu_intr(dev);
4988e8ddb2bSKalle Valo if (status)
4998e8ddb2bSKalle Valo goto out;
5008e8ddb2bSKalle Valo }
5018e8ddb2bSKalle Valo
5028e8ddb2bSKalle Valo if (MS(HOST_INT_STATUS_ERROR, host_int_status)) {
5038e8ddb2bSKalle Valo /* Error Interrupt */
5048e8ddb2bSKalle Valo status = ath6kl_hif_proc_err_intr(dev);
5058e8ddb2bSKalle Valo if (status)
5068e8ddb2bSKalle Valo goto out;
5078e8ddb2bSKalle Valo }
5088e8ddb2bSKalle Valo
5098e8ddb2bSKalle Valo if (MS(HOST_INT_STATUS_COUNTER, host_int_status))
5108e8ddb2bSKalle Valo /* Counter Interrupt */
5118e8ddb2bSKalle Valo status = ath6kl_hif_proc_counter_intr(dev);
5128e8ddb2bSKalle Valo
5138e8ddb2bSKalle Valo out:
5148e8ddb2bSKalle Valo /*
5158e8ddb2bSKalle Valo * An optimization to bypass reading the IRQ status registers
5168e8ddb2bSKalle Valo * unecessarily which can re-wake the target, if upper layers
5178e8ddb2bSKalle Valo * determine that we are in a low-throughput mode, we can rely on
5188e8ddb2bSKalle Valo * taking another interrupt rather than re-checking the status
5198e8ddb2bSKalle Valo * registers which can re-wake the target.
5208e8ddb2bSKalle Valo *
5218e8ddb2bSKalle Valo * NOTE : for host interfaces that makes use of detecting pending
5228e8ddb2bSKalle Valo * mbox messages at hif can not use this optimization due to
5238e8ddb2bSKalle Valo * possible side effects, SPI requires the host to drain all
5248e8ddb2bSKalle Valo * messages from the mailbox before exiting the ISR routine.
5258e8ddb2bSKalle Valo */
5268e8ddb2bSKalle Valo
5278e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
5288e8ddb2bSKalle Valo "bypassing irq status re-check, forcing done\n");
5298e8ddb2bSKalle Valo
5308e8ddb2bSKalle Valo if (!dev->htc_cnxt->chk_irq_status_cnt)
5318e8ddb2bSKalle Valo *done = true;
5328e8ddb2bSKalle Valo
5338e8ddb2bSKalle Valo ath6kl_dbg(ATH6KL_DBG_IRQ,
5348e8ddb2bSKalle Valo "proc_pending_irqs: (done:%d, status=%d\n", *done, status);
5358e8ddb2bSKalle Valo
5368e8ddb2bSKalle Valo return status;
5378e8ddb2bSKalle Valo }
5388e8ddb2bSKalle Valo
5398e8ddb2bSKalle Valo /* interrupt handler, kicks off all interrupt processing */
ath6kl_hif_intr_bh_handler(struct ath6kl * ar)5408e8ddb2bSKalle Valo int ath6kl_hif_intr_bh_handler(struct ath6kl *ar)
5418e8ddb2bSKalle Valo {
5428e8ddb2bSKalle Valo struct ath6kl_device *dev = ar->htc_target->dev;
543d60e8ab6SKalle Valo unsigned long timeout;
5448e8ddb2bSKalle Valo int status = 0;
5458e8ddb2bSKalle Valo bool done = false;
5468e8ddb2bSKalle Valo
5478e8ddb2bSKalle Valo /*
5488e8ddb2bSKalle Valo * Reset counter used to flag a re-scan of IRQ status registers on
5498e8ddb2bSKalle Valo * the target.
5508e8ddb2bSKalle Valo */
5518e8ddb2bSKalle Valo dev->htc_cnxt->chk_irq_status_cnt = 0;
5528e8ddb2bSKalle Valo
5538e8ddb2bSKalle Valo /*
5548e8ddb2bSKalle Valo * IRQ processing is synchronous, interrupt status registers can be
5558e8ddb2bSKalle Valo * re-read.
5568e8ddb2bSKalle Valo */
557d60e8ab6SKalle Valo timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT);
558d60e8ab6SKalle Valo while (time_before(jiffies, timeout) && !done) {
5598e8ddb2bSKalle Valo status = proc_pending_irqs(dev, &done);
5608e8ddb2bSKalle Valo if (status)
5618e8ddb2bSKalle Valo break;
5628e8ddb2bSKalle Valo }
5638e8ddb2bSKalle Valo
5648e8ddb2bSKalle Valo return status;
5658e8ddb2bSKalle Valo }
566d6a434d6SKalle Valo EXPORT_SYMBOL(ath6kl_hif_intr_bh_handler);
5678e8ddb2bSKalle Valo
ath6kl_hif_enable_intrs(struct ath6kl_device * dev)5688e8ddb2bSKalle Valo static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev)
5698e8ddb2bSKalle Valo {
5708e8ddb2bSKalle Valo struct ath6kl_irq_enable_reg regs;
5718e8ddb2bSKalle Valo int status;
5728e8ddb2bSKalle Valo
5738e8ddb2bSKalle Valo spin_lock_bh(&dev->lock);
5748e8ddb2bSKalle Valo
5758e8ddb2bSKalle Valo /* Enable all but ATH6KL CPU interrupts */
5768e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en =
5778e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_ERROR, 0x01) |
5788e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_CPU, 0x01) |
5798e8ddb2bSKalle Valo SM(INT_STATUS_ENABLE_COUNTER, 0x01);
5808e8ddb2bSKalle Valo
5818e8ddb2bSKalle Valo /*
5828e8ddb2bSKalle Valo * NOTE: There are some cases where HIF can do detection of
5838e8ddb2bSKalle Valo * pending mbox messages which is disabled now.
5848e8ddb2bSKalle Valo */
5858e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
5868e8ddb2bSKalle Valo
5878e8ddb2bSKalle Valo /* Set up the CPU Interrupt status Register */
5888e8ddb2bSKalle Valo dev->irq_en_reg.cpu_int_status_en = 0;
5898e8ddb2bSKalle Valo
5908e8ddb2bSKalle Valo /* Set up the Error Interrupt status Register */
5918e8ddb2bSKalle Valo dev->irq_en_reg.err_int_status_en =
5928e8ddb2bSKalle Valo SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) |
5938e8ddb2bSKalle Valo SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1);
5948e8ddb2bSKalle Valo
5958e8ddb2bSKalle Valo /*
5968e8ddb2bSKalle Valo * Enable Counter interrupt status register to get fatal errors for
5978e8ddb2bSKalle Valo * debugging.
5988e8ddb2bSKalle Valo */
5998e8ddb2bSKalle Valo dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT,
6008e8ddb2bSKalle Valo ATH6KL_TARGET_DEBUG_INTR_MASK);
6018e8ddb2bSKalle Valo memcpy(®s, &dev->irq_en_reg, sizeof(regs));
6028e8ddb2bSKalle Valo
6038e8ddb2bSKalle Valo spin_unlock_bh(&dev->lock);
6048e8ddb2bSKalle Valo
6058e8ddb2bSKalle Valo status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS,
6068e8ddb2bSKalle Valo ®s.int_status_en, sizeof(regs),
6078e8ddb2bSKalle Valo HIF_WR_SYNC_BYTE_INC);
6088e8ddb2bSKalle Valo
6098e8ddb2bSKalle Valo if (status)
6108e8ddb2bSKalle Valo ath6kl_err("failed to update interrupt ctl reg err: %d\n",
6118e8ddb2bSKalle Valo status);
6128e8ddb2bSKalle Valo
6138e8ddb2bSKalle Valo return status;
6148e8ddb2bSKalle Valo }
6158e8ddb2bSKalle Valo
ath6kl_hif_disable_intrs(struct ath6kl_device * dev)6168e8ddb2bSKalle Valo int ath6kl_hif_disable_intrs(struct ath6kl_device *dev)
6178e8ddb2bSKalle Valo {
6188e8ddb2bSKalle Valo struct ath6kl_irq_enable_reg regs;
6198e8ddb2bSKalle Valo
6208e8ddb2bSKalle Valo spin_lock_bh(&dev->lock);
6218e8ddb2bSKalle Valo /* Disable all interrupts */
6228e8ddb2bSKalle Valo dev->irq_en_reg.int_status_en = 0;
6238e8ddb2bSKalle Valo dev->irq_en_reg.cpu_int_status_en = 0;
6248e8ddb2bSKalle Valo dev->irq_en_reg.err_int_status_en = 0;
6258e8ddb2bSKalle Valo dev->irq_en_reg.cntr_int_status_en = 0;
6268e8ddb2bSKalle Valo memcpy(®s, &dev->irq_en_reg, sizeof(regs));
6278e8ddb2bSKalle Valo spin_unlock_bh(&dev->lock);
6288e8ddb2bSKalle Valo
6298e8ddb2bSKalle Valo return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS,
6308e8ddb2bSKalle Valo ®s.int_status_en, sizeof(regs),
6318e8ddb2bSKalle Valo HIF_WR_SYNC_BYTE_INC);
6328e8ddb2bSKalle Valo }
6338e8ddb2bSKalle Valo
6348e8ddb2bSKalle Valo /* enable device interrupts */
ath6kl_hif_unmask_intrs(struct ath6kl_device * dev)6358e8ddb2bSKalle Valo int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev)
6368e8ddb2bSKalle Valo {
6378e8ddb2bSKalle Valo int status = 0;
6388e8ddb2bSKalle Valo
6398e8ddb2bSKalle Valo /*
6408e8ddb2bSKalle Valo * Make sure interrupt are disabled before unmasking at the HIF
6418e8ddb2bSKalle Valo * layer. The rationale here is that between device insertion
6428e8ddb2bSKalle Valo * (where we clear the interrupts the first time) and when HTC
6438e8ddb2bSKalle Valo * is finally ready to handle interrupts, other software can perform
6448e8ddb2bSKalle Valo * target "soft" resets. The ATH6KL interrupt enables reset back to an
6458e8ddb2bSKalle Valo * "enabled" state when this happens.
6468e8ddb2bSKalle Valo */
6478e8ddb2bSKalle Valo ath6kl_hif_disable_intrs(dev);
6488e8ddb2bSKalle Valo
6498e8ddb2bSKalle Valo /* unmask the host controller interrupts */
6508e8ddb2bSKalle Valo ath6kl_hif_irq_enable(dev->ar);
6518e8ddb2bSKalle Valo status = ath6kl_hif_enable_intrs(dev);
6528e8ddb2bSKalle Valo
6538e8ddb2bSKalle Valo return status;
6548e8ddb2bSKalle Valo }
6558e8ddb2bSKalle Valo
6568e8ddb2bSKalle Valo /* disable all device interrupts */
ath6kl_hif_mask_intrs(struct ath6kl_device * dev)6578e8ddb2bSKalle Valo int ath6kl_hif_mask_intrs(struct ath6kl_device *dev)
6588e8ddb2bSKalle Valo {
6598e8ddb2bSKalle Valo /*
6608e8ddb2bSKalle Valo * Mask the interrupt at the HIF layer to avoid any stray interrupt
6618e8ddb2bSKalle Valo * taken while we zero out our shadow registers in
6628e8ddb2bSKalle Valo * ath6kl_hif_disable_intrs().
6638e8ddb2bSKalle Valo */
6648e8ddb2bSKalle Valo ath6kl_hif_irq_disable(dev->ar);
6658e8ddb2bSKalle Valo
6668e8ddb2bSKalle Valo return ath6kl_hif_disable_intrs(dev);
6678e8ddb2bSKalle Valo }
6688e8ddb2bSKalle Valo
ath6kl_hif_setup(struct ath6kl_device * dev)6698e8ddb2bSKalle Valo int ath6kl_hif_setup(struct ath6kl_device *dev)
6708e8ddb2bSKalle Valo {
6718e8ddb2bSKalle Valo int status = 0;
6728e8ddb2bSKalle Valo
6738e8ddb2bSKalle Valo spin_lock_init(&dev->lock);
6748e8ddb2bSKalle Valo
6758e8ddb2bSKalle Valo /*
6768e8ddb2bSKalle Valo * NOTE: we actually get the block size of a mailbox other than 0,
6778e8ddb2bSKalle Valo * for SDIO the block size on mailbox 0 is artificially set to 1.
6788e8ddb2bSKalle Valo * So we use the block size that is set for the other 3 mailboxes.
6798e8ddb2bSKalle Valo */
6808e8ddb2bSKalle Valo dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size;
6818e8ddb2bSKalle Valo
6828e8ddb2bSKalle Valo /* must be a power of 2 */
6838e8ddb2bSKalle Valo if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) {
6848e8ddb2bSKalle Valo WARN_ON(1);
6858e8ddb2bSKalle Valo status = -EINVAL;
6868e8ddb2bSKalle Valo goto fail_setup;
6878e8ddb2bSKalle Valo }
6888e8ddb2bSKalle Valo
6898e8ddb2bSKalle Valo /* assemble mask, used for padding to a block */
6908e8ddb2bSKalle Valo dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1;
6918e8ddb2bSKalle Valo
69283973e03SKalle Valo ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n",
6938e8ddb2bSKalle Valo dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr);
6948e8ddb2bSKalle Valo
6958e8ddb2bSKalle Valo status = ath6kl_hif_disable_intrs(dev);
6968e8ddb2bSKalle Valo
6978e8ddb2bSKalle Valo fail_setup:
6988e8ddb2bSKalle Valo return status;
6998e8ddb2bSKalle Valo }
700