1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef CORE_H 19bdcd8170SKalle Valo #define CORE_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #include <linux/etherdevice.h> 22bdcd8170SKalle Valo #include <linux/rtnetlink.h> 23bdcd8170SKalle Valo #include <linux/firmware.h> 24bdcd8170SKalle Valo #include <linux/sched.h> 25bdf5396bSKalle Valo #include <linux/circ_buf.h> 26bdcd8170SKalle Valo #include <net/cfg80211.h> 27bdcd8170SKalle Valo #include "htc.h" 28bdcd8170SKalle Valo #include "wmi.h" 29bdcd8170SKalle Valo #include "bmi.h" 30bc07ddb2SKalle Valo #include "target.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define MAX_ATH6KL 1 33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 46bdcd8170SKalle Valo #define MAX_NODE_NUM 15 47bdcd8170SKalle Valo 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 51c1762a3fSThirumalai Pachamuthu 521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 541df94a85SVasanthakumar Thiagarajan 55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 58bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 59bdcd8170SKalle Valo 60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 638232736dSSujith Manoharan #define A_DEFAULT_LISTEN_INTERVAL 1 /* beacon intervals */ 64bdcd8170SKalle Valo #define A_MAX_WOW_LISTEN_INTERVAL 1000 65bdcd8170SKalle Valo 6650d41234SKalle Valo /* includes also the null byte */ 6750d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6850d41234SKalle Valo 6950d41234SKalle Valo enum ath6kl_fw_ie_type { 7050d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7150d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7250d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7350d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7450d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 758a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7697e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 771b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7803ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 79368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 8050d41234SKalle Valo }; 8150d41234SKalle Valo 8297e0496dSKalle Valo enum ath6kl_fw_capability { 8397e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8410509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8597e0496dSKalle Valo 863ca9d1fcSAarthi Thiruvengadam /* 873ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 883ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 893ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 903ca9d1fcSAarthi Thiruvengadam */ 913ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 923ca9d1fcSAarthi Thiruvengadam 9397e0496dSKalle Valo /* this needs to be last */ 9497e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 9597e0496dSKalle Valo }; 9697e0496dSKalle Valo 9797e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 9897e0496dSKalle Valo 9950d41234SKalle Valo struct ath6kl_fw_ie { 10050d41234SKalle Valo __le32 id; 10150d41234SKalle Valo __le32 len; 10250d41234SKalle Valo u8 data[0]; 10350d41234SKalle Valo }; 10450d41234SKalle Valo 105c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 10665a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 107c0038972SKalle Valo 108bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1090d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 110bdcd8170SKalle Valo 111bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1120d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1130d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 114c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 115c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 116c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 117c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 118c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1190d0192baSKalle Valo #define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin" 1200d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1210d0192baSKalle Valo "ath6k/AR6003/hw2.0/bdata.SD31.bin" 122bdcd8170SKalle Valo 123bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1240d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 125c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 126c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 127c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 128c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 129cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 130cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 131c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1320d0192baSKalle Valo #define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin" 1330d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 134bdcd8170SKalle Valo "ath6k/AR6003/hw2.1.1/bdata.SD31.bin" 135bdcd8170SKalle Valo 13631024d99SKevin Fang /* AR6004 1.0 definitions */ 1370d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 138c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 139c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 1400d0192baSKalle Valo #define AR6004_HW_1_0_BOARD_DATA_FILE "ath6k/AR6004/hw1.0/bdata.bin" 1410d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 142d5720e59SKalle Valo "ath6k/AR6004/hw1.0/bdata.DB132.bin" 143d5720e59SKalle Valo 144d5720e59SKalle Valo /* AR6004 1.1 definitions */ 1450d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 146c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 147c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 1480d0192baSKalle Valo #define AR6004_HW_1_1_BOARD_DATA_FILE "ath6k/AR6004/hw1.1/bdata.bin" 1490d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 150d5720e59SKalle Valo "ath6k/AR6004/hw1.1/bdata.DB132.bin" 15131024d99SKevin Fang 152bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 153bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 154bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 155bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 156c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 157c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 158bdcd8170SKalle Valo 159bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 160bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 161bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 162bdcd8170SKalle Valo 163bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 164bdcd8170SKalle Valo 165bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 166bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 167bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 168bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 169bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 170bdcd8170SKalle Valo 171bdcd8170SKalle Valo #define NUM_OF_TIDS 8 172bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 173bdcd8170SKalle Valo 174bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 175bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 176bdcd8170SKalle Valo 177bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 178bdcd8170SKalle Valo 179bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 180bdcd8170SKalle Valo 181bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT 400 /* in ms */ 182bdcd8170SKalle Valo 183bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 184bdcd8170SKalle Valo 185bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 186bdcd8170SKalle Valo 187bdcd8170SKalle Valo /* configuration lags */ 188bdcd8170SKalle Valo /* 189bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 190bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 191bdcd8170SKalle Valo * sending (Re)Assoc req. 192bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 193bdcd8170SKalle Valo * module state transition failure events which happen during 194bdcd8170SKalle Valo * scan, to the host. 195bdcd8170SKalle Valo */ 196bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 197bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 198bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 199bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 200e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG BIT(4) 201bdcd8170SKalle Valo 202bdcd8170SKalle Valo enum wlan_low_pwr_state { 203bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 204bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 205bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 206bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 207bdcd8170SKalle Valo }; 208bdcd8170SKalle Valo 209bdcd8170SKalle Valo enum sme_state { 210bdcd8170SKalle Valo SME_DISCONNECTED, 211bdcd8170SKalle Valo SME_CONNECTING, 212bdcd8170SKalle Valo SME_CONNECTED 213bdcd8170SKalle Valo }; 214bdcd8170SKalle Valo 215bdcd8170SKalle Valo struct skb_hold_q { 216bdcd8170SKalle Valo struct sk_buff *skb; 217bdcd8170SKalle Valo bool is_amsdu; 218bdcd8170SKalle Valo u16 seq_no; 219bdcd8170SKalle Valo }; 220bdcd8170SKalle Valo 221bdcd8170SKalle Valo struct rxtid { 222bdcd8170SKalle Valo bool aggr; 223bdcd8170SKalle Valo bool progress; 224bdcd8170SKalle Valo bool timer_mon; 225bdcd8170SKalle Valo u16 win_sz; 226bdcd8170SKalle Valo u16 seq_next; 227bdcd8170SKalle Valo u32 hold_q_sz; 228bdcd8170SKalle Valo struct skb_hold_q *hold_q; 229bdcd8170SKalle Valo struct sk_buff_head q; 230bdcd8170SKalle Valo spinlock_t lock; 231bdcd8170SKalle Valo }; 232bdcd8170SKalle Valo 233bdcd8170SKalle Valo struct rxtid_stats { 234bdcd8170SKalle Valo u32 num_into_aggr; 235bdcd8170SKalle Valo u32 num_dups; 236bdcd8170SKalle Valo u32 num_oow; 237bdcd8170SKalle Valo u32 num_mpdu; 238bdcd8170SKalle Valo u32 num_amsdu; 239bdcd8170SKalle Valo u32 num_delivered; 240bdcd8170SKalle Valo u32 num_timeouts; 241bdcd8170SKalle Valo u32 num_hole; 242bdcd8170SKalle Valo u32 num_bar; 243bdcd8170SKalle Valo }; 244bdcd8170SKalle Valo 2457baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 246bdcd8170SKalle Valo u8 aggr_sz; 247bdcd8170SKalle Valo u8 timer_scheduled; 248bdcd8170SKalle Valo struct timer_list timer; 249bdcd8170SKalle Valo struct net_device *dev; 250bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 251bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 2527baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 2537baef812SVasanthakumar Thiagarajan }; 2547baef812SVasanthakumar Thiagarajan 2557baef812SVasanthakumar Thiagarajan struct aggr_info { 2567baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 2577baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 258bdcd8170SKalle Valo }; 259bdcd8170SKalle Valo 260bdcd8170SKalle Valo struct ath6kl_wep_key { 261bdcd8170SKalle Valo u8 key_index; 262bdcd8170SKalle Valo u8 key_len; 263bdcd8170SKalle Valo u8 key[64]; 264bdcd8170SKalle Valo }; 265bdcd8170SKalle Valo 266bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 267bdcd8170SKalle Valo 268bdcd8170SKalle Valo struct ath6kl_key { 269bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 270bdcd8170SKalle Valo u8 key_len; 271bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 272bdcd8170SKalle Valo u8 seq_len; 273bdcd8170SKalle Valo u32 cipher; 274bdcd8170SKalle Valo }; 275bdcd8170SKalle Valo 276bdcd8170SKalle Valo struct ath6kl_node_mapping { 277bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 278bdcd8170SKalle Valo u8 ep_id; 279bdcd8170SKalle Valo u8 tx_pend; 280bdcd8170SKalle Valo }; 281bdcd8170SKalle Valo 282bdcd8170SKalle Valo struct ath6kl_cookie { 283bdcd8170SKalle Valo struct sk_buff *skb; 284bdcd8170SKalle Valo u32 map_no; 285bdcd8170SKalle Valo struct htc_packet htc_pkt; 286bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 287bdcd8170SKalle Valo }; 288bdcd8170SKalle Valo 289d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff { 290d0ff7383SNaveen Gangadharan struct list_head list; 291d0ff7383SNaveen Gangadharan u32 freq; 292d0ff7383SNaveen Gangadharan u32 wait; 293d0ff7383SNaveen Gangadharan u32 id; 294d0ff7383SNaveen Gangadharan bool no_cck; 295d0ff7383SNaveen Gangadharan size_t len; 296d0ff7383SNaveen Gangadharan u8 buf[0]; 297d0ff7383SNaveen Gangadharan }; 298d0ff7383SNaveen Gangadharan 299bdcd8170SKalle Valo struct ath6kl_sta { 300bdcd8170SKalle Valo u16 sta_flags; 301bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 302bdcd8170SKalle Valo u8 aid; 303bdcd8170SKalle Valo u8 keymgmt; 304bdcd8170SKalle Valo u8 ucipher; 305bdcd8170SKalle Valo u8 auth; 306bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 307bdcd8170SKalle Valo struct sk_buff_head psq; 308bdcd8170SKalle Valo spinlock_t psq_lock; 309d0ff7383SNaveen Gangadharan struct list_head mgmt_psq; 310d0ff7383SNaveen Gangadharan size_t mgmt_psq_len; 311c1762a3fSThirumalai Pachamuthu u8 apsd_info; 312c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 3131d2a4456SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 314bdcd8170SKalle Valo }; 315bdcd8170SKalle Valo 316bdcd8170SKalle Valo struct ath6kl_version { 317bdcd8170SKalle Valo u32 target_ver; 318bdcd8170SKalle Valo u32 wlan_ver; 319bdcd8170SKalle Valo u32 abi_ver; 320bdcd8170SKalle Valo }; 321bdcd8170SKalle Valo 322bdcd8170SKalle Valo struct ath6kl_bmi { 323bdcd8170SKalle Valo u32 cmd_credits; 324bdcd8170SKalle Valo bool done_sent; 325bdcd8170SKalle Valo u8 *cmd_buf; 3261f4c894dSKalle Valo u32 max_data_size; 3271f4c894dSKalle Valo u32 max_cmd_size; 328bdcd8170SKalle Valo }; 329bdcd8170SKalle Valo 330bdcd8170SKalle Valo struct target_stats { 331bdcd8170SKalle Valo u64 tx_pkt; 332bdcd8170SKalle Valo u64 tx_byte; 333bdcd8170SKalle Valo u64 tx_ucast_pkt; 334bdcd8170SKalle Valo u64 tx_ucast_byte; 335bdcd8170SKalle Valo u64 tx_mcast_pkt; 336bdcd8170SKalle Valo u64 tx_mcast_byte; 337bdcd8170SKalle Valo u64 tx_bcast_pkt; 338bdcd8170SKalle Valo u64 tx_bcast_byte; 339bdcd8170SKalle Valo u64 tx_rts_success_cnt; 340bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 341bdcd8170SKalle Valo 342bdcd8170SKalle Valo u64 tx_err; 343bdcd8170SKalle Valo u64 tx_fail_cnt; 344bdcd8170SKalle Valo u64 tx_retry_cnt; 345bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 346bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 347bdcd8170SKalle Valo 348bdcd8170SKalle Valo u64 rx_pkt; 349bdcd8170SKalle Valo u64 rx_byte; 350bdcd8170SKalle Valo u64 rx_ucast_pkt; 351bdcd8170SKalle Valo u64 rx_ucast_byte; 352bdcd8170SKalle Valo u64 rx_mcast_pkt; 353bdcd8170SKalle Valo u64 rx_mcast_byte; 354bdcd8170SKalle Valo u64 rx_bcast_pkt; 355bdcd8170SKalle Valo u64 rx_bcast_byte; 356bdcd8170SKalle Valo u64 rx_frgment_pkt; 357bdcd8170SKalle Valo 358bdcd8170SKalle Valo u64 rx_err; 359bdcd8170SKalle Valo u64 rx_crc_err; 360bdcd8170SKalle Valo u64 rx_key_cache_miss; 361bdcd8170SKalle Valo u64 rx_decrypt_err; 362bdcd8170SKalle Valo u64 rx_dupl_frame; 363bdcd8170SKalle Valo 364bdcd8170SKalle Valo u64 tkip_local_mic_fail; 365bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 366bdcd8170SKalle Valo u64 tkip_replays; 367bdcd8170SKalle Valo u64 tkip_fmt_err; 368bdcd8170SKalle Valo u64 ccmp_fmt_err; 369bdcd8170SKalle Valo u64 ccmp_replays; 370bdcd8170SKalle Valo 371bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 372bdcd8170SKalle Valo 373bdcd8170SKalle Valo u64 cs_bmiss_cnt; 374bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 375bdcd8170SKalle Valo u64 cs_connect_cnt; 376bdcd8170SKalle Valo u64 cs_discon_cnt; 377bdcd8170SKalle Valo 378bdcd8170SKalle Valo s32 tx_ucast_rate; 379bdcd8170SKalle Valo s32 rx_ucast_rate; 380bdcd8170SKalle Valo 381bdcd8170SKalle Valo u32 lq_val; 382bdcd8170SKalle Valo 383bdcd8170SKalle Valo u32 wow_pkt_dropped; 384bdcd8170SKalle Valo u16 wow_evt_discarded; 385bdcd8170SKalle Valo 386bdcd8170SKalle Valo s16 noise_floor_calib; 387bdcd8170SKalle Valo s16 cs_rssi; 388bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 389bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 390bdcd8170SKalle Valo u8 cs_last_roam_msec; 391bdcd8170SKalle Valo u8 cs_snr; 392bdcd8170SKalle Valo 393bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 394bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 395bdcd8170SKalle Valo 396bdcd8170SKalle Valo u32 arp_received; 397bdcd8170SKalle Valo u32 arp_matched; 398bdcd8170SKalle Valo u32 arp_replied; 399bdcd8170SKalle Valo }; 400bdcd8170SKalle Valo 401bdcd8170SKalle Valo struct ath6kl_mbox_info { 402bdcd8170SKalle Valo u32 htc_addr; 403bdcd8170SKalle Valo u32 htc_ext_addr; 404bdcd8170SKalle Valo u32 htc_ext_sz; 405bdcd8170SKalle Valo 406bdcd8170SKalle Valo u32 block_size; 407bdcd8170SKalle Valo 408bdcd8170SKalle Valo u32 gmbox_addr; 409bdcd8170SKalle Valo 410bdcd8170SKalle Valo u32 gmbox_sz; 411bdcd8170SKalle Valo }; 412bdcd8170SKalle Valo 413bdcd8170SKalle Valo /* 414bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 415bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 416bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 417bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 418bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 419bdcd8170SKalle Valo */ 420bdcd8170SKalle Valo 421bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 422bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 423bdcd8170SKalle Valo 424bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 425bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 426bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 427bdcd8170SKalle Valo 4289a5b1318SJouni Malinen /* Initial group key for AP mode */ 429bdcd8170SKalle Valo struct ath6kl_req_key { 4309a5b1318SJouni Malinen bool valid; 4319a5b1318SJouni Malinen u8 key_index; 4329a5b1318SJouni Malinen int key_type; 4339a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 4349a5b1318SJouni Malinen u8 key_len; 435bdcd8170SKalle Valo }; 436bdcd8170SKalle Valo 43777eab1e9SKalle Valo enum ath6kl_hif_type { 43877eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 43977eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 44077eab1e9SKalle Valo }; 44177eab1e9SKalle Valo 44280abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 44380abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 44480abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 44580abaf9bSVasanthakumar Thiagarajan struct list_head list; 44680abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 44780abaf9bSVasanthakumar Thiagarajan }; 44880abaf9bSVasanthakumar Thiagarajan 44971f96ee6SKalle Valo /* 45071f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 45171f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 45271f96ee6SKalle Valo */ 453b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 454334234b5SVasanthakumar Thiagarajan 45559c98449SVasanthakumar Thiagarajan /* vif flags info */ 45659c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 45759c98449SVasanthakumar Thiagarajan CONNECTED, 45859c98449SVasanthakumar Thiagarajan CONNECT_PEND, 45959c98449SVasanthakumar Thiagarajan WMM_ENABLED, 46059c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 46159c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 46259c98449SVasanthakumar Thiagarajan NETDEV_REGISTERED, 46359c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 46459c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 46559c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 466b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 467081c7a84SRaja Mani HOST_SLEEP_MODE_CMD_PROCESSED, 46859c98449SVasanthakumar Thiagarajan }; 46959c98449SVasanthakumar Thiagarajan 470108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 471990bd915SVasanthakumar Thiagarajan struct list_head list; 472108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 473108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 474108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 475478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 476478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 477334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 47859c98449SVasanthakumar Thiagarajan unsigned long flags; 4793450334fSVasanthakumar Thiagarajan int ssid_len; 4803450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 4813450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 4823450334fSVasanthakumar Thiagarajan u8 auth_mode; 4833450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 4843450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 4853450334fSVasanthakumar Thiagarajan u8 grp_crypto; 4863450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 4873450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 488f5938f24SVasanthakumar Thiagarajan u8 next_mode; 489f5938f24SVasanthakumar Thiagarajan u8 nw_type; 4908c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 4918c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 492f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 493f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 4946f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 4956f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 4962132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 49710509f90SKalle Valo 498de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 49910509f90SKalle Valo struct timer_list sched_scan_timer; 50010509f90SKalle Valo 50114ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 50214ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 503cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 5041052261eSJouni Malinen u32 last_roc_id; 5051052261eSJouni Malinen u32 last_cancel_roc_id; 506cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 507cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 508cf5333d7SVasanthakumar Thiagarajan u16 next_chan; 509cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 510cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 511b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 512b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 51380abaf9bSVasanthakumar Thiagarajan 51480abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 515108438bcSVasanthakumar Thiagarajan }; 516108438bcSVasanthakumar Thiagarajan 5176cb3c714SRaja Mani #define WOW_LIST_ID 0 5186cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 5196cb3c714SRaja Mani 52010509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 52110509f90SKalle Valo 522bdcd8170SKalle Valo /* Flag info */ 52359c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 52459c98449SVasanthakumar Thiagarajan WMI_ENABLED, 52559c98449SVasanthakumar Thiagarajan WMI_READY, 52659c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 52759c98449SVasanthakumar Thiagarajan TESTMODE, 52859c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 52959c98449SVasanthakumar Thiagarajan SKIP_SCAN, 53059c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 5315fe4dffbSKalle Valo FIRST_BOOT, 53259c98449SVasanthakumar Thiagarajan }; 533bdcd8170SKalle Valo 53476a9fbe2SKalle Valo enum ath6kl_state { 53576a9fbe2SKalle Valo ATH6KL_STATE_OFF, 53676a9fbe2SKalle Valo ATH6KL_STATE_ON, 53776a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 538b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 539dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 54010509f90SKalle Valo ATH6KL_STATE_SCHED_SCAN, 54176a9fbe2SKalle Valo }; 54276a9fbe2SKalle Valo 543bdcd8170SKalle Valo struct ath6kl { 544bdcd8170SKalle Valo struct device *dev; 545be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 54676a9fbe2SKalle Valo 54776a9fbe2SKalle Valo enum ath6kl_state state; 5485f1127ffSKalle Valo unsigned int testmode; 54976a9fbe2SKalle Valo 550bdcd8170SKalle Valo struct ath6kl_bmi bmi; 551bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 552bdcd8170SKalle Valo struct wmi *wmi; 553bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 554bdcd8170SKalle Valo int total_tx_data_pend; 555bdcd8170SKalle Valo struct htc_target *htc_target; 55677eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 557bdcd8170SKalle Valo void *hif_priv; 558990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 559990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 560990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 56155055976SVasanthakumar Thiagarajan u8 num_vif; 562368b1b0fSKalle Valo unsigned int vif_max; 5633226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 56455055976SVasanthakumar Thiagarajan u8 avail_idx_map; 565bdcd8170SKalle Valo spinlock_t lock; 566bdcd8170SKalle Valo struct semaphore sem; 567bdcd8170SKalle Valo u16 listen_intvl_b; 568e5090444SVivek Natarajan u8 lrssi_roam_threshold; 569bdcd8170SKalle Valo struct ath6kl_version version; 570bdcd8170SKalle Valo u32 target_type; 571bdcd8170SKalle Valo u8 tx_pwr; 572bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 573bdcd8170SKalle Valo u8 ibss_ps_enable; 57455055976SVasanthakumar Thiagarajan bool ibss_if_active; 575bdcd8170SKalle Valo u8 node_num; 576bdcd8170SKalle Valo u8 next_ep_id; 577bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 578bdcd8170SKalle Valo u32 cookie_count; 579bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 580bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 581bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 582bdcd8170SKalle Valo u8 hiac_stream_active_pri; 583bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 584bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 5853c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 586bdcd8170SKalle Valo u32 connect_ctrl_flags; 587bdcd8170SKalle Valo u32 user_key_ctrl; 588bdcd8170SKalle Valo u8 usr_bss_filter; 589bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 590bdcd8170SKalle Valo u8 sta_list_index; 591bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 592bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 593bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 594bdcd8170SKalle Valo u8 intra_bss; 595bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 596bdcd8170SKalle Valo u8 ap_country_code[3]; 597bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 598bdcd8170SKalle Valo u8 rx_meta_ver; 599bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 600d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 601bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 602003353b0SKalle Valo struct { 603003353b0SKalle Valo void *rx_report; 604003353b0SKalle Valo size_t rx_report_len; 605003353b0SKalle Valo } tm; 606003353b0SKalle Valo 607856f4b31SKalle Valo struct ath6kl_hw { 608856f4b31SKalle Valo u32 id; 609293badf4SKalle Valo const char *name; 610a01ac414SKalle Valo u32 dataset_patch_addr; 611a01ac414SKalle Valo u32 app_load_addr; 612a01ac414SKalle Valo u32 app_start_override_addr; 613991b27eaSKalle Valo u32 board_ext_data_addr; 614991b27eaSKalle Valo u32 reserved_ram_size; 6150d4d72bfSKalle Valo u32 board_addr; 61639586bf2SRyan Hsu u32 refclk_hz; 61739586bf2SRyan Hsu u32 uarttx_pin; 618cd23c1c9SAlex Yang u32 testscript_addr; 619d1a9421dSKalle Valo 620c0038972SKalle Valo struct ath6kl_hw_fw { 621c0038972SKalle Valo const char *dir; 622c0038972SKalle Valo const char *otp; 623d1a9421dSKalle Valo const char *fw; 624c0038972SKalle Valo const char *tcmd; 625c0038972SKalle Valo const char *patch; 626cd23c1c9SAlex Yang const char *utf; 627cd23c1c9SAlex Yang const char *testscript; 628c0038972SKalle Valo } fw; 629c0038972SKalle Valo 630d1a9421dSKalle Valo const char *fw_board; 631d1a9421dSKalle Valo const char *fw_default_board; 632a01ac414SKalle Valo } hw; 633a01ac414SKalle Valo 634bdcd8170SKalle Valo u16 conf_flags; 635e390af77SRaja Mani u16 suspend_mode; 636bdcd8170SKalle Valo wait_queue_head_t event_wq; 637bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 638bdcd8170SKalle Valo 639bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 640bdcd8170SKalle Valo unsigned long flag; 641bdcd8170SKalle Valo 642bdcd8170SKalle Valo u8 *fw_board; 643bdcd8170SKalle Valo size_t fw_board_len; 644bdcd8170SKalle Valo 645bdcd8170SKalle Valo u8 *fw_otp; 646bdcd8170SKalle Valo size_t fw_otp_len; 647bdcd8170SKalle Valo 648bdcd8170SKalle Valo u8 *fw; 649bdcd8170SKalle Valo size_t fw_len; 650bdcd8170SKalle Valo 651bdcd8170SKalle Valo u8 *fw_patch; 652bdcd8170SKalle Valo size_t fw_patch_len; 653bdcd8170SKalle Valo 654cd23c1c9SAlex Yang u8 *fw_testscript; 655cd23c1c9SAlex Yang size_t fw_testscript_len; 656cd23c1c9SAlex Yang 65765a8b4ccSKalle Valo unsigned int fw_api; 65897e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 65997e0496dSKalle Valo 660bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 6617c3075e9SVasanthakumar Thiagarajan 662d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 6636a7c9badSJouni Malinen 6646bbc7c35SJouni Malinen bool p2p; 6656bbc7c35SJouni Malinen 666bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 667bdf5396bSKalle Valo struct { 6689b9a4f2aSKalle Valo struct sk_buff_head fwlog_queue; 669c807b30dSKalle Valo struct completion fwlog_completion; 670c807b30dSKalle Valo bool fwlog_open; 671c807b30dSKalle Valo 672939f1cceSKalle Valo u32 fwlog_mask; 6739b9a4f2aSKalle Valo 67491d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 675252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 676252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 6779a730834SKalle Valo 6789a730834SKalle Valo struct { 6799a730834SKalle Valo unsigned int invalid_rate; 6809a730834SKalle Valo } war_stats; 6814b28a80dSJouni Malinen 6824b28a80dSJouni Malinen u8 *roam_tbl; 6834b28a80dSJouni Malinen unsigned int roam_tbl_len; 684ff0b0075SJouni Malinen 685ff0b0075SJouni Malinen u8 keepalive; 686ff0b0075SJouni Malinen u8 disc_timeout; 687bdf5396bSKalle Valo } debug; 688bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 689bdcd8170SKalle Valo }; 690bdcd8170SKalle Valo 691d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 692bdcd8170SKalle Valo { 693108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 694bdcd8170SKalle Valo } 695bdcd8170SKalle Valo 696bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 697bc07ddb2SKalle Valo u32 item_offset) 698bc07ddb2SKalle Valo { 699bc07ddb2SKalle Valo u32 addr = 0; 700bc07ddb2SKalle Valo 701bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 702bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 703bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 704bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 705bc07ddb2SKalle Valo 706bc07ddb2SKalle Valo return addr; 707bc07ddb2SKalle Valo } 708bc07ddb2SKalle Valo 709bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 710bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 711bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 712bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 713bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 714bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 715bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 716bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue); 717bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 718bdcd8170SKalle Valo struct htc_packet *packet); 719bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 720bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 721f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 722addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 723addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 724addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 725bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 726e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 727bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 728bdcd8170SKalle Valo 729bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 730bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 731bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 732bdcd8170SKalle Valo 7337baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 734c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info, 735c8651541SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn); 736bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 737bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 738bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 739bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 740bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 741bdcd8170SKalle Valo int len); 742bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 7431d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn); 744bdcd8170SKalle Valo 7456765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 * node_addr); 746bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 747bdcd8170SKalle Valo 748bdcd8170SKalle Valo void ath6kl_ready_event(void *devt, u8 * datap, u32 sw_ver, u32 abi_ver); 749bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 750bdcd8170SKalle Valo enum htc_endpoint_id eid); 751240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 752bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 753bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 754bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 755bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 756240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 757240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 758572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 759c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 760240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 761bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 762bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 763240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 764bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 765240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 766240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 767bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 768bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 769bdcd8170SKalle Valo 770240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 771bdcd8170SKalle Valo 772240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 773240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 774240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 775240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 776bdcd8170SKalle Valo u8 win_sz); 777bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 778bdcd8170SKalle Valo 7796db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type, 7806db8fa53SVasanthakumar Thiagarajan bool wait_fot_compltn, bool cold_reset); 781e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 782990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 78355055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready); 7845fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 7855fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 78645eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 78745eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 78845eaa78fSKalle Valo 789a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 7905fe4dffbSKalle Valo 79145eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 79245eaa78fSKalle Valo int ath6kl_core_init(struct ath6kl *ar); 79345eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 79445eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 79545eaa78fSKalle Valo 796bdcd8170SKalle Valo #endif /* CORE_H */ 797