1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
100d97c121bSVasanthakumar Thiagarajan 	/* Firmware has support to override rsn cap of rsn ie */
101d97c121bSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102d97c121bSVasanthakumar Thiagarajan 
1036821d4f0SNaveen Gangadharan 	/*
1046821d4f0SNaveen Gangadharan 	 * Multicast support in WOW and host awake mode.
1056821d4f0SNaveen Gangadharan 	 * Allow all multicast in host awake mode.
1066821d4f0SNaveen Gangadharan 	 * Apply multicast filter in WOW mode.
1076821d4f0SNaveen Gangadharan 	 */
1086821d4f0SNaveen Gangadharan 	ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
1096821d4f0SNaveen Gangadharan 
110c422d52dSThomas Pedersen 	/* Firmware supports enhanced bmiss detection */
111c422d52dSThomas Pedersen 	ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
112c422d52dSThomas Pedersen 
113dd45b759SNaveen Singh 	/*
114dd45b759SNaveen Singh 	 * FW supports matching of ssid in schedule scan
115dd45b759SNaveen Singh 	 */
116dd45b759SNaveen Singh 	ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
117dd45b759SNaveen Singh 
11885b20fc2SThomas Pedersen 	/* Firmware supports filtering BSS results by RSSI */
11985b20fc2SThomas Pedersen 	ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
12085b20fc2SThomas Pedersen 
121c95dcb59SAarthi Thiruvengadam 	/* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */
122c95dcb59SAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
123c95dcb59SAarthi Thiruvengadam 
12497e0496dSKalle Valo 	/* this needs to be last */
12597e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
12697e0496dSKalle Valo };
12797e0496dSKalle Valo 
12897e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
12997e0496dSKalle Valo 
13050d41234SKalle Valo struct ath6kl_fw_ie {
13150d41234SKalle Valo 	__le32 id;
13250d41234SKalle Valo 	__le32 len;
13350d41234SKalle Valo 	u8 data[0];
13450d41234SKalle Valo };
13550d41234SKalle Valo 
13606e360acSBala Shanmugam enum ath6kl_hw_flags {
13706e360acSBala Shanmugam 	ATH6KL_HW_FLAG_64BIT_RATES	= BIT(0),
13806e360acSBala Shanmugam };
13906e360acSBala Shanmugam 
140c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
14165a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
142c0038972SKalle Valo 
143bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1440d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
145bdcd8170SKalle Valo 
146bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1470d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1480d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
149c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
150c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
151c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
152c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
153c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1542023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
1550d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1562023dbb8STim Gardner 			AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
157bdcd8170SKalle Valo 
158bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1590d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
160c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
161c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
162c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
163c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
164cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
165cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
166c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1672023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
1680d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
1692023dbb8STim Gardner 			AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
170bdcd8170SKalle Valo 
17131024d99SKevin Fang /* AR6004 1.0 definitions */
1720d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
173c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
174c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1752023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE         AR6004_HW_1_0_FW_DIR "/bdata.bin"
1760d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
1772023dbb8STim Gardner 	AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
178d5720e59SKalle Valo 
179d5720e59SKalle Valo /* AR6004 1.1 definitions */
1800d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
181c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
182c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1832023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE         AR6004_HW_1_1_FW_DIR "/bdata.bin"
1840d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
1852023dbb8STim Gardner 	AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
18631024d99SKevin Fang 
1876146ca69SRay Chen /* AR6004 1.2 definitions */
1886146ca69SRay Chen #define AR6004_HW_1_2_VERSION                 0x300007e8
1896146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR			"ath6k/AR6004/hw1.2"
1906146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE           "fw.ram.bin"
1912023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE         AR6004_HW_1_2_FW_DIR "/bdata.bin"
1926146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
1932023dbb8STim Gardner 	AR6004_HW_1_2_FW_DIR "/bdata.bin"
1946146ca69SRay Chen 
195bdcd8170SKalle Valo /* Per STA data, used in AP mode */
196bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
197bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
198bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
199c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
200c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
201bdcd8170SKalle Valo 
202bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
203bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
204bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
205bdcd8170SKalle Valo 
206bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
207bdcd8170SKalle Valo 
208bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
209bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
210bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
211bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
212bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
213bdcd8170SKalle Valo 
214bdcd8170SKalle Valo #define NUM_OF_TIDS         8
215bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
216bdcd8170SKalle Valo 
217bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
218bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
219bdcd8170SKalle Valo 
220bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
221bdcd8170SKalle Valo 
222bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
223bdcd8170SKalle Valo 
2247940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT     100	/* in ms */
225bdcd8170SKalle Valo 
226bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
227bdcd8170SKalle Valo 
228bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
229bdcd8170SKalle Valo 
2308f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
231ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
232ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
233ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
2348f46fccdSRaja Mani 
235bdcd8170SKalle Valo /* configuration lags */
236bdcd8170SKalle Valo /*
237bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
238bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
239bdcd8170SKalle Valo  * sending (Re)Assoc req.
240bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
241bdcd8170SKalle Valo  * module state transition failure events which happen during
242bdcd8170SKalle Valo  * scan, to the host.
243bdcd8170SKalle Valo  */
244bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
245bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
246bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
247bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
248e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
249bdcd8170SKalle Valo 
250c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
251c86e4f44SAarthi Thiruvengadam 
252bdcd8170SKalle Valo enum wlan_low_pwr_state {
253bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
254bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
255bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
256bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
257bdcd8170SKalle Valo };
258bdcd8170SKalle Valo 
259bdcd8170SKalle Valo enum sme_state {
260bdcd8170SKalle Valo 	SME_DISCONNECTED,
261bdcd8170SKalle Valo 	SME_CONNECTING,
262bdcd8170SKalle Valo 	SME_CONNECTED
263bdcd8170SKalle Valo };
264bdcd8170SKalle Valo 
265bdcd8170SKalle Valo struct skb_hold_q {
266bdcd8170SKalle Valo 	struct sk_buff *skb;
267bdcd8170SKalle Valo 	bool is_amsdu;
268bdcd8170SKalle Valo 	u16 seq_no;
269bdcd8170SKalle Valo };
270bdcd8170SKalle Valo 
271bdcd8170SKalle Valo struct rxtid {
272bdcd8170SKalle Valo 	bool aggr;
273bdcd8170SKalle Valo 	bool timer_mon;
274bdcd8170SKalle Valo 	u16 win_sz;
275bdcd8170SKalle Valo 	u16 seq_next;
276bdcd8170SKalle Valo 	u32 hold_q_sz;
277bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
278bdcd8170SKalle Valo 	struct sk_buff_head q;
27912eb9444SKalle Valo 
28012eb9444SKalle Valo 	/*
2810faf7458SVasanthakumar Thiagarajan 	 * lock mainly protects seq_next and hold_q. Movement of seq_next
2820faf7458SVasanthakumar Thiagarajan 	 * needs to be protected between aggr_timeout() and
2830faf7458SVasanthakumar Thiagarajan 	 * aggr_process_recv_frm(). hold_q will be holding the pending
2840faf7458SVasanthakumar Thiagarajan 	 * reorder frames and it's access should also be protected.
2850faf7458SVasanthakumar Thiagarajan 	 * Some of the other fields like hold_q_sz, win_sz and aggr are
2860faf7458SVasanthakumar Thiagarajan 	 * initialized/reset when receiving addba/delba req, also while
2870faf7458SVasanthakumar Thiagarajan 	 * deleting aggr state all the pending buffers are flushed before
2880faf7458SVasanthakumar Thiagarajan 	 * resetting these fields, so there should not be any race in accessing
2890faf7458SVasanthakumar Thiagarajan 	 * these fields.
29012eb9444SKalle Valo 	 */
291bdcd8170SKalle Valo 	spinlock_t lock;
292bdcd8170SKalle Valo };
293bdcd8170SKalle Valo 
294bdcd8170SKalle Valo struct rxtid_stats {
295bdcd8170SKalle Valo 	u32 num_into_aggr;
296bdcd8170SKalle Valo 	u32 num_dups;
297bdcd8170SKalle Valo 	u32 num_oow;
298bdcd8170SKalle Valo 	u32 num_mpdu;
299bdcd8170SKalle Valo 	u32 num_amsdu;
300bdcd8170SKalle Valo 	u32 num_delivered;
301bdcd8170SKalle Valo 	u32 num_timeouts;
302bdcd8170SKalle Valo 	u32 num_hole;
303bdcd8170SKalle Valo 	u32 num_bar;
304bdcd8170SKalle Valo };
305bdcd8170SKalle Valo 
3067baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
307bdcd8170SKalle Valo 	u8 aggr_sz;
308bdcd8170SKalle Valo 	u8 timer_scheduled;
309bdcd8170SKalle Valo 	struct timer_list timer;
310bdcd8170SKalle Valo 	struct net_device *dev;
311bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
312bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
3137baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
3147baef812SVasanthakumar Thiagarajan };
3157baef812SVasanthakumar Thiagarajan 
3167baef812SVasanthakumar Thiagarajan struct aggr_info {
3177baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
3187baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
319bdcd8170SKalle Valo };
320bdcd8170SKalle Valo 
321bdcd8170SKalle Valo struct ath6kl_wep_key {
322bdcd8170SKalle Valo 	u8 key_index;
323bdcd8170SKalle Valo 	u8 key_len;
324bdcd8170SKalle Valo 	u8 key[64];
325bdcd8170SKalle Valo };
326bdcd8170SKalle Valo 
327bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
328bdcd8170SKalle Valo 
329bdcd8170SKalle Valo struct ath6kl_key {
330bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
331bdcd8170SKalle Valo 	u8 key_len;
332bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
333bdcd8170SKalle Valo 	u8 seq_len;
334bdcd8170SKalle Valo 	u32 cipher;
335bdcd8170SKalle Valo };
336bdcd8170SKalle Valo 
337bdcd8170SKalle Valo struct ath6kl_node_mapping {
338bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
339bdcd8170SKalle Valo 	u8 ep_id;
340bdcd8170SKalle Valo 	u8 tx_pend;
341bdcd8170SKalle Valo };
342bdcd8170SKalle Valo 
343bdcd8170SKalle Valo struct ath6kl_cookie {
344bdcd8170SKalle Valo 	struct sk_buff *skb;
345bdcd8170SKalle Valo 	u32 map_no;
346bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
347bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
348bdcd8170SKalle Valo };
349bdcd8170SKalle Valo 
350d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
351d0ff7383SNaveen Gangadharan 	struct list_head list;
352d0ff7383SNaveen Gangadharan 	u32 freq;
353d0ff7383SNaveen Gangadharan 	u32 wait;
354d0ff7383SNaveen Gangadharan 	u32 id;
355d0ff7383SNaveen Gangadharan 	bool no_cck;
356d0ff7383SNaveen Gangadharan 	size_t len;
357d0ff7383SNaveen Gangadharan 	u8 buf[0];
358d0ff7383SNaveen Gangadharan };
359d0ff7383SNaveen Gangadharan 
360bdcd8170SKalle Valo struct ath6kl_sta {
361bdcd8170SKalle Valo 	u16 sta_flags;
362bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
363bdcd8170SKalle Valo 	u8 aid;
364bdcd8170SKalle Valo 	u8 keymgmt;
365bdcd8170SKalle Valo 	u8 ucipher;
366bdcd8170SKalle Valo 	u8 auth;
367bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
368bdcd8170SKalle Valo 	struct sk_buff_head psq;
36912eb9444SKalle Valo 
37012eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
371bdcd8170SKalle Valo 	spinlock_t psq_lock;
37212eb9444SKalle Valo 
373d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
374d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
375c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
376c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3771d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
378bdcd8170SKalle Valo };
379bdcd8170SKalle Valo 
380bdcd8170SKalle Valo struct ath6kl_version {
381bdcd8170SKalle Valo 	u32 target_ver;
382bdcd8170SKalle Valo 	u32 wlan_ver;
383bdcd8170SKalle Valo 	u32 abi_ver;
384bdcd8170SKalle Valo };
385bdcd8170SKalle Valo 
386bdcd8170SKalle Valo struct ath6kl_bmi {
387bdcd8170SKalle Valo 	u32 cmd_credits;
388bdcd8170SKalle Valo 	bool done_sent;
389bdcd8170SKalle Valo 	u8 *cmd_buf;
3901f4c894dSKalle Valo 	u32 max_data_size;
3911f4c894dSKalle Valo 	u32 max_cmd_size;
392bdcd8170SKalle Valo };
393bdcd8170SKalle Valo 
394bdcd8170SKalle Valo struct target_stats {
395bdcd8170SKalle Valo 	u64 tx_pkt;
396bdcd8170SKalle Valo 	u64 tx_byte;
397bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
398bdcd8170SKalle Valo 	u64 tx_ucast_byte;
399bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
400bdcd8170SKalle Valo 	u64 tx_mcast_byte;
401bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
402bdcd8170SKalle Valo 	u64 tx_bcast_byte;
403bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
404bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
405bdcd8170SKalle Valo 
406bdcd8170SKalle Valo 	u64 tx_err;
407bdcd8170SKalle Valo 	u64 tx_fail_cnt;
408bdcd8170SKalle Valo 	u64 tx_retry_cnt;
409bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
410bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
411bdcd8170SKalle Valo 
412bdcd8170SKalle Valo 	u64 rx_pkt;
413bdcd8170SKalle Valo 	u64 rx_byte;
414bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
415bdcd8170SKalle Valo 	u64 rx_ucast_byte;
416bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
417bdcd8170SKalle Valo 	u64 rx_mcast_byte;
418bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
419bdcd8170SKalle Valo 	u64 rx_bcast_byte;
420bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
421bdcd8170SKalle Valo 
422bdcd8170SKalle Valo 	u64 rx_err;
423bdcd8170SKalle Valo 	u64 rx_crc_err;
424bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
425bdcd8170SKalle Valo 	u64 rx_decrypt_err;
426bdcd8170SKalle Valo 	u64 rx_dupl_frame;
427bdcd8170SKalle Valo 
428bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
429bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
430bdcd8170SKalle Valo 	u64 tkip_replays;
431bdcd8170SKalle Valo 	u64 tkip_fmt_err;
432bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
433bdcd8170SKalle Valo 	u64 ccmp_replays;
434bdcd8170SKalle Valo 
435bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
436bdcd8170SKalle Valo 
437bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
438bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
439bdcd8170SKalle Valo 	u64 cs_connect_cnt;
440bdcd8170SKalle Valo 	u64 cs_discon_cnt;
441bdcd8170SKalle Valo 
442bdcd8170SKalle Valo 	s32 tx_ucast_rate;
443bdcd8170SKalle Valo 	s32 rx_ucast_rate;
444bdcd8170SKalle Valo 
445bdcd8170SKalle Valo 	u32 lq_val;
446bdcd8170SKalle Valo 
447bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
448bdcd8170SKalle Valo 	u16 wow_evt_discarded;
449bdcd8170SKalle Valo 
450bdcd8170SKalle Valo 	s16 noise_floor_calib;
451bdcd8170SKalle Valo 	s16 cs_rssi;
452bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
453bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
454bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
455bdcd8170SKalle Valo 	u8 cs_snr;
456bdcd8170SKalle Valo 
457bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
458bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
459bdcd8170SKalle Valo 
460bdcd8170SKalle Valo 	u32 arp_received;
461bdcd8170SKalle Valo 	u32 arp_matched;
462bdcd8170SKalle Valo 	u32 arp_replied;
463bdcd8170SKalle Valo };
464bdcd8170SKalle Valo 
465bdcd8170SKalle Valo struct ath6kl_mbox_info {
466bdcd8170SKalle Valo 	u32 htc_addr;
467bdcd8170SKalle Valo 	u32 htc_ext_addr;
468bdcd8170SKalle Valo 	u32 htc_ext_sz;
469bdcd8170SKalle Valo 
470bdcd8170SKalle Valo 	u32 block_size;
471bdcd8170SKalle Valo 
472bdcd8170SKalle Valo 	u32 gmbox_addr;
473bdcd8170SKalle Valo 
474bdcd8170SKalle Valo 	u32 gmbox_sz;
475bdcd8170SKalle Valo };
476bdcd8170SKalle Valo 
477bdcd8170SKalle Valo /*
478bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
479bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
480bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
481bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
482bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
483bdcd8170SKalle Valo  */
484bdcd8170SKalle Valo 
485bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
486bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
487bdcd8170SKalle Valo 
488bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
489bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
490bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
491bdcd8170SKalle Valo 
4929a5b1318SJouni Malinen /* Initial group key for AP mode */
493bdcd8170SKalle Valo struct ath6kl_req_key {
4949a5b1318SJouni Malinen 	bool valid;
4959a5b1318SJouni Malinen 	u8 key_index;
4969a5b1318SJouni Malinen 	int key_type;
4979a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
4989a5b1318SJouni Malinen 	u8 key_len;
499bdcd8170SKalle Valo };
500bdcd8170SKalle Valo 
50177eab1e9SKalle Valo enum ath6kl_hif_type {
50277eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
50377eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
50477eab1e9SKalle Valo };
50577eab1e9SKalle Valo 
506e76ac2bfSKalle Valo enum ath6kl_htc_type {
507e76ac2bfSKalle Valo 	ATH6KL_HTC_TYPE_MBOX,
508636f8288SKalle Valo 	ATH6KL_HTC_TYPE_PIPE,
509e76ac2bfSKalle Valo };
510e76ac2bfSKalle Valo 
51180abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
51280abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
51380abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
51480abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
51580abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
51680abaf9bSVasanthakumar Thiagarajan };
51780abaf9bSVasanthakumar Thiagarajan 
518df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap {
519df90b369SVasanthakumar Thiagarajan 	bool ht_enable;
520df90b369SVasanthakumar Thiagarajan 	u8 ampdu_factor;
521df90b369SVasanthakumar Thiagarajan 	unsigned short cap_info;
522df90b369SVasanthakumar Thiagarajan };
523df90b369SVasanthakumar Thiagarajan 
52471f96ee6SKalle Valo /*
52571f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
52671f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
52771f96ee6SKalle Valo  */
528b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
529334234b5SVasanthakumar Thiagarajan 
53059c98449SVasanthakumar Thiagarajan /* vif flags info */
53159c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
53259c98449SVasanthakumar Thiagarajan 	CONNECTED,
53359c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
53459c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
53559c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
53659c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
53759c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
53859c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
53959c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
54059c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
541b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
542081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
5436251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_ON,
5446251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_OFF,
54559c98449SVasanthakumar Thiagarajan };
54659c98449SVasanthakumar Thiagarajan 
547108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
548990bd915SVasanthakumar Thiagarajan 	struct list_head list;
549108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
550108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
551108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
552478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
553478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
554334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
55559c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5563450334fSVasanthakumar Thiagarajan 	int ssid_len;
5573450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5583450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5593450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5603450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5613450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5623450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5633450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5643450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
565f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
566f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5678c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5688c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
569f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
570f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5716f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5726f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5732132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
57467b3f129SKiran Reddy 	struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
57510509f90SKalle Valo 
576de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
57710509f90SKalle Valo 	struct timer_list sched_scan_timer;
57810509f90SKalle Valo 
57914ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
58014ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
581cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
5821052261eSJouni Malinen 	u32 last_roc_id;
5831052261eSJouni Malinen 	u32 last_cancel_roc_id;
584cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
585cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
586cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
5878f46fccdSRaja Mani 	u16 listen_intvl_t;
588ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
589eb38987eSRaja Mani 	u16 bg_scan_period;
590cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
591b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
592b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
593c4f7863eSThomas Pedersen 	struct wmi_connect_cmd profile;
59480abaf9bSVasanthakumar Thiagarajan 
59580abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
596108438bcSVasanthakumar Thiagarajan };
597108438bcSVasanthakumar Thiagarajan 
59871bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
59971bbc994SJohannes Berg {
60071bbc994SJohannes Berg 	return container_of(wdev, struct ath6kl_vif, wdev);
60171bbc994SJohannes Berg }
60271bbc994SJohannes Berg 
6036cb3c714SRaja Mani #define WOW_LIST_ID		0
6046cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
6056cb3c714SRaja Mani 
60610509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
60710509f90SKalle Valo 
608bdcd8170SKalle Valo /* Flag info */
60959c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
61059c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
61159c98449SVasanthakumar Thiagarajan 	WMI_READY,
61259c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
61359c98449SVasanthakumar Thiagarajan 	TESTMODE,
61459c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
61559c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
61659c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
6175fe4dffbSKalle Valo 	FIRST_BOOT,
61859c98449SVasanthakumar Thiagarajan };
619bdcd8170SKalle Valo 
62076a9fbe2SKalle Valo enum ath6kl_state {
62176a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
62276a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
623390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
624390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
62576a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
626b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
627dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
62810509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
62976a9fbe2SKalle Valo };
63076a9fbe2SKalle Valo 
631bdcd8170SKalle Valo struct ath6kl {
632bdcd8170SKalle Valo 	struct device *dev;
633be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
63476a9fbe2SKalle Valo 
63576a9fbe2SKalle Valo 	enum ath6kl_state state;
6365f1127ffSKalle Valo 	unsigned int testmode;
63776a9fbe2SKalle Valo 
638bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
639bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
640e76ac2bfSKalle Valo 	const struct ath6kl_htc_ops *htc_ops;
641bdcd8170SKalle Valo 	struct wmi *wmi;
642bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
643bdcd8170SKalle Valo 	int total_tx_data_pend;
644bdcd8170SKalle Valo 	struct htc_target *htc_target;
64577eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
646bdcd8170SKalle Valo 	void *hif_priv;
647990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
648990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
649990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
65055055976SVasanthakumar Thiagarajan 	u8 num_vif;
651368b1b0fSKalle Valo 	unsigned int vif_max;
6523226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
65355055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
65412eb9444SKalle Valo 
65512eb9444SKalle Valo 	/*
65612eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
65712eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
65812eb9444SKalle Valo 	 */
659bdcd8170SKalle Valo 	spinlock_t lock;
66012eb9444SKalle Valo 
661bdcd8170SKalle Valo 	struct semaphore sem;
662e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
663bdcd8170SKalle Valo 	struct ath6kl_version version;
664bdcd8170SKalle Valo 	u32 target_type;
665bdcd8170SKalle Valo 	u8 tx_pwr;
666bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
667bdcd8170SKalle Valo 	u8 ibss_ps_enable;
66855055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
669bdcd8170SKalle Valo 	u8 node_num;
670bdcd8170SKalle Valo 	u8 next_ep_id;
671bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
672bdcd8170SKalle Valo 	u32 cookie_count;
673bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
674bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
675bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
676bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
677bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
678bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
6793c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
680bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
681bdcd8170SKalle Valo 	u32 user_key_ctrl;
682bdcd8170SKalle Valo 	u8 usr_bss_filter;
683bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
684bdcd8170SKalle Valo 	u8 sta_list_index;
685bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
686bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
687c4f7863eSThomas Pedersen 	u32 want_ch_switch;
68812eb9444SKalle Valo 
68912eb9444SKalle Valo 	/*
69012eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
69112eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
69212eb9444SKalle Valo 	 */
693bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
69412eb9444SKalle Valo 
695bdcd8170SKalle Valo 	u8 intra_bss;
696bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
697bdcd8170SKalle Valo 	u8 ap_country_code[3];
698bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
699bdcd8170SKalle Valo 	u8 rx_meta_ver;
700bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
701d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
702bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
703003353b0SKalle Valo 	struct {
704003353b0SKalle Valo 		void *rx_report;
705003353b0SKalle Valo 		size_t rx_report_len;
706003353b0SKalle Valo 	} tm;
707003353b0SKalle Valo 
708856f4b31SKalle Valo 	struct ath6kl_hw {
709856f4b31SKalle Valo 		u32 id;
710293badf4SKalle Valo 		const char *name;
711a01ac414SKalle Valo 		u32 dataset_patch_addr;
712a01ac414SKalle Valo 		u32 app_load_addr;
713a01ac414SKalle Valo 		u32 app_start_override_addr;
714991b27eaSKalle Valo 		u32 board_ext_data_addr;
715991b27eaSKalle Valo 		u32 reserved_ram_size;
7160d4d72bfSKalle Valo 		u32 board_addr;
71739586bf2SRyan Hsu 		u32 refclk_hz;
71839586bf2SRyan Hsu 		u32 uarttx_pin;
719cd23c1c9SAlex Yang 		u32 testscript_addr;
720d92917e4SThomas Pedersen 		enum wmi_phy_cap cap;
721d1a9421dSKalle Valo 
72206e360acSBala Shanmugam 		u32 flags;
72306e360acSBala Shanmugam 
724c0038972SKalle Valo 		struct ath6kl_hw_fw {
725c0038972SKalle Valo 			const char *dir;
726c0038972SKalle Valo 			const char *otp;
727d1a9421dSKalle Valo 			const char *fw;
728c0038972SKalle Valo 			const char *tcmd;
729c0038972SKalle Valo 			const char *patch;
730cd23c1c9SAlex Yang 			const char *utf;
731cd23c1c9SAlex Yang 			const char *testscript;
732c0038972SKalle Valo 		} fw;
733c0038972SKalle Valo 
734d1a9421dSKalle Valo 		const char *fw_board;
735d1a9421dSKalle Valo 		const char *fw_default_board;
736a01ac414SKalle Valo 	} hw;
737a01ac414SKalle Valo 
738bdcd8170SKalle Valo 	u16 conf_flags;
739e390af77SRaja Mani 	u16 suspend_mode;
7401e9a905dSRaja Mani 	u16 wow_suspend_mode;
741bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
742bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
743bdcd8170SKalle Valo 
744bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
745bdcd8170SKalle Valo 	unsigned long flag;
746bdcd8170SKalle Valo 
747bdcd8170SKalle Valo 	u8 *fw_board;
748bdcd8170SKalle Valo 	size_t fw_board_len;
749bdcd8170SKalle Valo 
750bdcd8170SKalle Valo 	u8 *fw_otp;
751bdcd8170SKalle Valo 	size_t fw_otp_len;
752bdcd8170SKalle Valo 
753bdcd8170SKalle Valo 	u8 *fw;
754bdcd8170SKalle Valo 	size_t fw_len;
755bdcd8170SKalle Valo 
756bdcd8170SKalle Valo 	u8 *fw_patch;
757bdcd8170SKalle Valo 	size_t fw_patch_len;
758bdcd8170SKalle Valo 
759cd23c1c9SAlex Yang 	u8 *fw_testscript;
760cd23c1c9SAlex Yang 	size_t fw_testscript_len;
761cd23c1c9SAlex Yang 
76265a8b4ccSKalle Valo 	unsigned int fw_api;
76397e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
76497e0496dSKalle Valo 
765bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7667c3075e9SVasanthakumar Thiagarajan 
767d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7686a7c9badSJouni Malinen 
7696bbc7c35SJouni Malinen 	bool p2p;
7706bbc7c35SJouni Malinen 
771e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
772e5348a1eSVasanthakumar Thiagarajan 
773bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
774bdf5396bSKalle Valo 	struct {
7759b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
776c807b30dSKalle Valo 		struct completion fwlog_completion;
777c807b30dSKalle Valo 		bool fwlog_open;
778c807b30dSKalle Valo 
779939f1cceSKalle Valo 		u32 fwlog_mask;
7809b9a4f2aSKalle Valo 
78191d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
782252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
783252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
7849a730834SKalle Valo 
7859a730834SKalle Valo 		struct {
7869a730834SKalle Valo 			unsigned int invalid_rate;
7879a730834SKalle Valo 		} war_stats;
7884b28a80dSJouni Malinen 
7894b28a80dSJouni Malinen 		u8 *roam_tbl;
7904b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
791ff0b0075SJouni Malinen 
792ff0b0075SJouni Malinen 		u8 keepalive;
793ff0b0075SJouni Malinen 		u8 disc_timeout;
794bdf5396bSKalle Valo 	} debug;
795bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
796bdcd8170SKalle Valo };
797bdcd8170SKalle Valo 
798d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
799bdcd8170SKalle Valo {
800108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
801bdcd8170SKalle Valo }
802bdcd8170SKalle Valo 
803bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
804bc07ddb2SKalle Valo 					  u32 item_offset)
805bc07ddb2SKalle Valo {
806bc07ddb2SKalle Valo 	u32 addr = 0;
807bc07ddb2SKalle Valo 
808bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
809bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
810bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
811bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
812bc07ddb2SKalle Valo 
813bc07ddb2SKalle Valo 	return addr;
814bc07ddb2SKalle Valo }
815bc07ddb2SKalle Valo 
816bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
817bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
818bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
819bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
820bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
821bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
822bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
82363de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
82463de1112SKalle Valo 			struct list_head *packet_queue);
825bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
826bdcd8170SKalle Valo 					       struct htc_packet *packet);
827bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
828bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
829f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
830addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
831addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
832addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
833bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
834e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
835bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
836bdcd8170SKalle Valo 
837bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
838bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
839bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
840bdcd8170SKalle Valo 
8417baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
842c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
843c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
844bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
845bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
846bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
847bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
848bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
849bdcd8170SKalle Valo 					    int len);
850bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
8511d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
852bdcd8170SKalle Valo 
8536765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
854bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
855bdcd8170SKalle Valo 
856d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
857d92917e4SThomas Pedersen 			enum wmi_phy_cap cap);
858bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
859bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
860240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
861bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
862bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
863bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
864bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
865240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
866240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
867572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
868c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
869240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
870bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
871bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
872240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
873bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
874240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
875240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
876bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
877bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
878bdcd8170SKalle Valo 
879240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
880bdcd8170SKalle Valo 
881240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
882240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
883240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
884240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
885bdcd8170SKalle Valo 			     u8 win_sz);
886bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
887bdcd8170SKalle Valo 
8886db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
8896db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
890e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
891990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
89255055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
8935fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
8945fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
89545eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
89645eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
89745eaa78fSKalle Valo 
898a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
8995fe4dffbSKalle Valo 
900636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
901636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
902636f8288SKalle Valo 
90345eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
904e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
90545eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
90645eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
90745eaa78fSKalle Valo 
908bdcd8170SKalle Valo #endif /* CORE_H */
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