1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef CORE_H 19bdcd8170SKalle Valo #define CORE_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #include <linux/etherdevice.h> 22bdcd8170SKalle Valo #include <linux/rtnetlink.h> 23bdcd8170SKalle Valo #include <linux/firmware.h> 24bdcd8170SKalle Valo #include <linux/sched.h> 25bdf5396bSKalle Valo #include <linux/circ_buf.h> 26bdcd8170SKalle Valo #include <net/cfg80211.h> 27bdcd8170SKalle Valo #include "htc.h" 28bdcd8170SKalle Valo #include "wmi.h" 29bdcd8170SKalle Valo #include "bmi.h" 30bc07ddb2SKalle Valo #include "target.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define MAX_ATH6KL 1 33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 46bdcd8170SKalle Valo #define MAX_NODE_NUM 15 47bdcd8170SKalle Valo 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 51c1762a3fSThirumalai Pachamuthu 521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 541df94a85SVasanthakumar Thiagarajan 55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 58bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 59bdcd8170SKalle Valo 60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 63bdcd8170SKalle Valo 6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */ 6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */ 6613423c31SVasanthakumar Thiagarajan 6750d41234SKalle Valo /* includes also the null byte */ 6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6950d41234SKalle Valo 7050d41234SKalle Valo enum ath6kl_fw_ie_type { 7150d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7250d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7350d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7450d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7550d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 768a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7797e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 781b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7903ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 80368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 8150d41234SKalle Valo }; 8250d41234SKalle Valo 8397e0496dSKalle Valo enum ath6kl_fw_capability { 8497e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8510509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8697e0496dSKalle Valo 873ca9d1fcSAarthi Thiruvengadam /* 883ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 893ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 903ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 913ca9d1fcSAarthi Thiruvengadam */ 923ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 933ca9d1fcSAarthi Thiruvengadam 9497e0496dSKalle Valo /* this needs to be last */ 9597e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 9697e0496dSKalle Valo }; 9797e0496dSKalle Valo 9897e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 9997e0496dSKalle Valo 10050d41234SKalle Valo struct ath6kl_fw_ie { 10150d41234SKalle Valo __le32 id; 10250d41234SKalle Valo __le32 len; 10350d41234SKalle Valo u8 data[0]; 10450d41234SKalle Valo }; 10550d41234SKalle Valo 106c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 10765a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 108c0038972SKalle Valo 109bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1100d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 111bdcd8170SKalle Valo 112bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1130d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1140d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 115c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 116c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 117c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 118c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 119c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1200d0192baSKalle Valo #define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin" 1210d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1220d0192baSKalle Valo "ath6k/AR6003/hw2.0/bdata.SD31.bin" 123bdcd8170SKalle Valo 124bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1250d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 126c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 127c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 128c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 129c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 130cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 131cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 132c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1330d0192baSKalle Valo #define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin" 1340d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 135bdcd8170SKalle Valo "ath6k/AR6003/hw2.1.1/bdata.SD31.bin" 136bdcd8170SKalle Valo 13731024d99SKevin Fang /* AR6004 1.0 definitions */ 1380d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 139c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 140c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 1410d0192baSKalle Valo #define AR6004_HW_1_0_BOARD_DATA_FILE "ath6k/AR6004/hw1.0/bdata.bin" 1420d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 143d5720e59SKalle Valo "ath6k/AR6004/hw1.0/bdata.DB132.bin" 144d5720e59SKalle Valo 145d5720e59SKalle Valo /* AR6004 1.1 definitions */ 1460d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 147c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 148c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 1490d0192baSKalle Valo #define AR6004_HW_1_1_BOARD_DATA_FILE "ath6k/AR6004/hw1.1/bdata.bin" 1500d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 151d5720e59SKalle Valo "ath6k/AR6004/hw1.1/bdata.DB132.bin" 15231024d99SKevin Fang 153bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 154bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 155bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 156bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 157c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 158c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 159bdcd8170SKalle Valo 160bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 161bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 162bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 163bdcd8170SKalle Valo 164bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 165bdcd8170SKalle Valo 166bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 167bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 168bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 169bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 170bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 171bdcd8170SKalle Valo 172bdcd8170SKalle Valo #define NUM_OF_TIDS 8 173bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 174bdcd8170SKalle Valo 175bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 176bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 177bdcd8170SKalle Valo 178bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 179bdcd8170SKalle Valo 180bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 181bdcd8170SKalle Valo 182bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT 400 /* in ms */ 183bdcd8170SKalle Valo 184bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 187bdcd8170SKalle Valo 1888f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */ 189ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME 1500 190ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */ 191ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME 5000 1928f46fccdSRaja Mani 193bdcd8170SKalle Valo /* configuration lags */ 194bdcd8170SKalle Valo /* 195bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 196bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 197bdcd8170SKalle Valo * sending (Re)Assoc req. 198bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 199bdcd8170SKalle Valo * module state transition failure events which happen during 200bdcd8170SKalle Valo * scan, to the host. 201bdcd8170SKalle Valo */ 202bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 203bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 204bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 205bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 206e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG BIT(4) 207bdcd8170SKalle Valo 208c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */ 209c86e4f44SAarthi Thiruvengadam 210bdcd8170SKalle Valo enum wlan_low_pwr_state { 211bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 212bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 213bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 214bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 215bdcd8170SKalle Valo }; 216bdcd8170SKalle Valo 217bdcd8170SKalle Valo enum sme_state { 218bdcd8170SKalle Valo SME_DISCONNECTED, 219bdcd8170SKalle Valo SME_CONNECTING, 220bdcd8170SKalle Valo SME_CONNECTED 221bdcd8170SKalle Valo }; 222bdcd8170SKalle Valo 223bdcd8170SKalle Valo struct skb_hold_q { 224bdcd8170SKalle Valo struct sk_buff *skb; 225bdcd8170SKalle Valo bool is_amsdu; 226bdcd8170SKalle Valo u16 seq_no; 227bdcd8170SKalle Valo }; 228bdcd8170SKalle Valo 229bdcd8170SKalle Valo struct rxtid { 230bdcd8170SKalle Valo bool aggr; 231bdcd8170SKalle Valo bool progress; 232bdcd8170SKalle Valo bool timer_mon; 233bdcd8170SKalle Valo u16 win_sz; 234bdcd8170SKalle Valo u16 seq_next; 235bdcd8170SKalle Valo u32 hold_q_sz; 236bdcd8170SKalle Valo struct skb_hold_q *hold_q; 237bdcd8170SKalle Valo struct sk_buff_head q; 23812eb9444SKalle Valo 23912eb9444SKalle Valo /* 24012eb9444SKalle Valo * FIXME: No clue what this should protect. Apparently it should 24112eb9444SKalle Valo * protect some of the fields above but they are also accessed 24212eb9444SKalle Valo * without taking the lock. 24312eb9444SKalle Valo */ 244bdcd8170SKalle Valo spinlock_t lock; 245bdcd8170SKalle Valo }; 246bdcd8170SKalle Valo 247bdcd8170SKalle Valo struct rxtid_stats { 248bdcd8170SKalle Valo u32 num_into_aggr; 249bdcd8170SKalle Valo u32 num_dups; 250bdcd8170SKalle Valo u32 num_oow; 251bdcd8170SKalle Valo u32 num_mpdu; 252bdcd8170SKalle Valo u32 num_amsdu; 253bdcd8170SKalle Valo u32 num_delivered; 254bdcd8170SKalle Valo u32 num_timeouts; 255bdcd8170SKalle Valo u32 num_hole; 256bdcd8170SKalle Valo u32 num_bar; 257bdcd8170SKalle Valo }; 258bdcd8170SKalle Valo 2597baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 260bdcd8170SKalle Valo u8 aggr_sz; 261bdcd8170SKalle Valo u8 timer_scheduled; 262bdcd8170SKalle Valo struct timer_list timer; 263bdcd8170SKalle Valo struct net_device *dev; 264bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 265bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 2667baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 2677baef812SVasanthakumar Thiagarajan }; 2687baef812SVasanthakumar Thiagarajan 2697baef812SVasanthakumar Thiagarajan struct aggr_info { 2707baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 2717baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 272bdcd8170SKalle Valo }; 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo struct ath6kl_wep_key { 275bdcd8170SKalle Valo u8 key_index; 276bdcd8170SKalle Valo u8 key_len; 277bdcd8170SKalle Valo u8 key[64]; 278bdcd8170SKalle Valo }; 279bdcd8170SKalle Valo 280bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 281bdcd8170SKalle Valo 282bdcd8170SKalle Valo struct ath6kl_key { 283bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 284bdcd8170SKalle Valo u8 key_len; 285bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 286bdcd8170SKalle Valo u8 seq_len; 287bdcd8170SKalle Valo u32 cipher; 288bdcd8170SKalle Valo }; 289bdcd8170SKalle Valo 290bdcd8170SKalle Valo struct ath6kl_node_mapping { 291bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 292bdcd8170SKalle Valo u8 ep_id; 293bdcd8170SKalle Valo u8 tx_pend; 294bdcd8170SKalle Valo }; 295bdcd8170SKalle Valo 296bdcd8170SKalle Valo struct ath6kl_cookie { 297bdcd8170SKalle Valo struct sk_buff *skb; 298bdcd8170SKalle Valo u32 map_no; 299bdcd8170SKalle Valo struct htc_packet htc_pkt; 300bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 301bdcd8170SKalle Valo }; 302bdcd8170SKalle Valo 303d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff { 304d0ff7383SNaveen Gangadharan struct list_head list; 305d0ff7383SNaveen Gangadharan u32 freq; 306d0ff7383SNaveen Gangadharan u32 wait; 307d0ff7383SNaveen Gangadharan u32 id; 308d0ff7383SNaveen Gangadharan bool no_cck; 309d0ff7383SNaveen Gangadharan size_t len; 310d0ff7383SNaveen Gangadharan u8 buf[0]; 311d0ff7383SNaveen Gangadharan }; 312d0ff7383SNaveen Gangadharan 313bdcd8170SKalle Valo struct ath6kl_sta { 314bdcd8170SKalle Valo u16 sta_flags; 315bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 316bdcd8170SKalle Valo u8 aid; 317bdcd8170SKalle Valo u8 keymgmt; 318bdcd8170SKalle Valo u8 ucipher; 319bdcd8170SKalle Valo u8 auth; 320bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 321bdcd8170SKalle Valo struct sk_buff_head psq; 32212eb9444SKalle Valo 32312eb9444SKalle Valo /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */ 324bdcd8170SKalle Valo spinlock_t psq_lock; 32512eb9444SKalle Valo 326d0ff7383SNaveen Gangadharan struct list_head mgmt_psq; 327d0ff7383SNaveen Gangadharan size_t mgmt_psq_len; 328c1762a3fSThirumalai Pachamuthu u8 apsd_info; 329c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 3301d2a4456SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 331bdcd8170SKalle Valo }; 332bdcd8170SKalle Valo 333bdcd8170SKalle Valo struct ath6kl_version { 334bdcd8170SKalle Valo u32 target_ver; 335bdcd8170SKalle Valo u32 wlan_ver; 336bdcd8170SKalle Valo u32 abi_ver; 337bdcd8170SKalle Valo }; 338bdcd8170SKalle Valo 339bdcd8170SKalle Valo struct ath6kl_bmi { 340bdcd8170SKalle Valo u32 cmd_credits; 341bdcd8170SKalle Valo bool done_sent; 342bdcd8170SKalle Valo u8 *cmd_buf; 3431f4c894dSKalle Valo u32 max_data_size; 3441f4c894dSKalle Valo u32 max_cmd_size; 345bdcd8170SKalle Valo }; 346bdcd8170SKalle Valo 347bdcd8170SKalle Valo struct target_stats { 348bdcd8170SKalle Valo u64 tx_pkt; 349bdcd8170SKalle Valo u64 tx_byte; 350bdcd8170SKalle Valo u64 tx_ucast_pkt; 351bdcd8170SKalle Valo u64 tx_ucast_byte; 352bdcd8170SKalle Valo u64 tx_mcast_pkt; 353bdcd8170SKalle Valo u64 tx_mcast_byte; 354bdcd8170SKalle Valo u64 tx_bcast_pkt; 355bdcd8170SKalle Valo u64 tx_bcast_byte; 356bdcd8170SKalle Valo u64 tx_rts_success_cnt; 357bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 358bdcd8170SKalle Valo 359bdcd8170SKalle Valo u64 tx_err; 360bdcd8170SKalle Valo u64 tx_fail_cnt; 361bdcd8170SKalle Valo u64 tx_retry_cnt; 362bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 363bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 364bdcd8170SKalle Valo 365bdcd8170SKalle Valo u64 rx_pkt; 366bdcd8170SKalle Valo u64 rx_byte; 367bdcd8170SKalle Valo u64 rx_ucast_pkt; 368bdcd8170SKalle Valo u64 rx_ucast_byte; 369bdcd8170SKalle Valo u64 rx_mcast_pkt; 370bdcd8170SKalle Valo u64 rx_mcast_byte; 371bdcd8170SKalle Valo u64 rx_bcast_pkt; 372bdcd8170SKalle Valo u64 rx_bcast_byte; 373bdcd8170SKalle Valo u64 rx_frgment_pkt; 374bdcd8170SKalle Valo 375bdcd8170SKalle Valo u64 rx_err; 376bdcd8170SKalle Valo u64 rx_crc_err; 377bdcd8170SKalle Valo u64 rx_key_cache_miss; 378bdcd8170SKalle Valo u64 rx_decrypt_err; 379bdcd8170SKalle Valo u64 rx_dupl_frame; 380bdcd8170SKalle Valo 381bdcd8170SKalle Valo u64 tkip_local_mic_fail; 382bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 383bdcd8170SKalle Valo u64 tkip_replays; 384bdcd8170SKalle Valo u64 tkip_fmt_err; 385bdcd8170SKalle Valo u64 ccmp_fmt_err; 386bdcd8170SKalle Valo u64 ccmp_replays; 387bdcd8170SKalle Valo 388bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 389bdcd8170SKalle Valo 390bdcd8170SKalle Valo u64 cs_bmiss_cnt; 391bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 392bdcd8170SKalle Valo u64 cs_connect_cnt; 393bdcd8170SKalle Valo u64 cs_discon_cnt; 394bdcd8170SKalle Valo 395bdcd8170SKalle Valo s32 tx_ucast_rate; 396bdcd8170SKalle Valo s32 rx_ucast_rate; 397bdcd8170SKalle Valo 398bdcd8170SKalle Valo u32 lq_val; 399bdcd8170SKalle Valo 400bdcd8170SKalle Valo u32 wow_pkt_dropped; 401bdcd8170SKalle Valo u16 wow_evt_discarded; 402bdcd8170SKalle Valo 403bdcd8170SKalle Valo s16 noise_floor_calib; 404bdcd8170SKalle Valo s16 cs_rssi; 405bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 406bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 407bdcd8170SKalle Valo u8 cs_last_roam_msec; 408bdcd8170SKalle Valo u8 cs_snr; 409bdcd8170SKalle Valo 410bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 411bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 412bdcd8170SKalle Valo 413bdcd8170SKalle Valo u32 arp_received; 414bdcd8170SKalle Valo u32 arp_matched; 415bdcd8170SKalle Valo u32 arp_replied; 416bdcd8170SKalle Valo }; 417bdcd8170SKalle Valo 418bdcd8170SKalle Valo struct ath6kl_mbox_info { 419bdcd8170SKalle Valo u32 htc_addr; 420bdcd8170SKalle Valo u32 htc_ext_addr; 421bdcd8170SKalle Valo u32 htc_ext_sz; 422bdcd8170SKalle Valo 423bdcd8170SKalle Valo u32 block_size; 424bdcd8170SKalle Valo 425bdcd8170SKalle Valo u32 gmbox_addr; 426bdcd8170SKalle Valo 427bdcd8170SKalle Valo u32 gmbox_sz; 428bdcd8170SKalle Valo }; 429bdcd8170SKalle Valo 430bdcd8170SKalle Valo /* 431bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 432bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 433bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 434bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 435bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 436bdcd8170SKalle Valo */ 437bdcd8170SKalle Valo 438bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 439bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 440bdcd8170SKalle Valo 441bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 442bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 443bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 444bdcd8170SKalle Valo 4459a5b1318SJouni Malinen /* Initial group key for AP mode */ 446bdcd8170SKalle Valo struct ath6kl_req_key { 4479a5b1318SJouni Malinen bool valid; 4489a5b1318SJouni Malinen u8 key_index; 4499a5b1318SJouni Malinen int key_type; 4509a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 4519a5b1318SJouni Malinen u8 key_len; 452bdcd8170SKalle Valo }; 453bdcd8170SKalle Valo 45477eab1e9SKalle Valo enum ath6kl_hif_type { 45577eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 45677eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 45777eab1e9SKalle Valo }; 45877eab1e9SKalle Valo 45980abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 46080abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 46180abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 46280abaf9bSVasanthakumar Thiagarajan struct list_head list; 46380abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 46480abaf9bSVasanthakumar Thiagarajan }; 46580abaf9bSVasanthakumar Thiagarajan 46671f96ee6SKalle Valo /* 46771f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 46871f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 46971f96ee6SKalle Valo */ 470b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 471334234b5SVasanthakumar Thiagarajan 47259c98449SVasanthakumar Thiagarajan /* vif flags info */ 47359c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 47459c98449SVasanthakumar Thiagarajan CONNECTED, 47559c98449SVasanthakumar Thiagarajan CONNECT_PEND, 47659c98449SVasanthakumar Thiagarajan WMM_ENABLED, 47759c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 47859c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 47959c98449SVasanthakumar Thiagarajan NETDEV_REGISTERED, 48059c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 48159c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 48259c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 483b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 484081c7a84SRaja Mani HOST_SLEEP_MODE_CMD_PROCESSED, 48559c98449SVasanthakumar Thiagarajan }; 48659c98449SVasanthakumar Thiagarajan 487108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 488990bd915SVasanthakumar Thiagarajan struct list_head list; 489108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 490108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 491108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 492478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 493478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 494334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 49559c98449SVasanthakumar Thiagarajan unsigned long flags; 4963450334fSVasanthakumar Thiagarajan int ssid_len; 4973450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 4983450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 4993450334fSVasanthakumar Thiagarajan u8 auth_mode; 5003450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 5013450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 5023450334fSVasanthakumar Thiagarajan u8 grp_crypto; 5033450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 5043450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 505f5938f24SVasanthakumar Thiagarajan u8 next_mode; 506f5938f24SVasanthakumar Thiagarajan u8 nw_type; 5078c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 5088c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 509f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 510f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 5116f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 5126f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 5132132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 51410509f90SKalle Valo 515de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 51610509f90SKalle Valo struct timer_list sched_scan_timer; 51710509f90SKalle Valo 51814ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 51914ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 520cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 5211052261eSJouni Malinen u32 last_roc_id; 5221052261eSJouni Malinen u32 last_cancel_roc_id; 523cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 524cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 525cf5333d7SVasanthakumar Thiagarajan u16 next_chan; 526cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 5278f46fccdSRaja Mani u16 listen_intvl_t; 528ce0dc0cfSRaja Mani u16 bmiss_time_t; 529cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 530b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 531b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 53280abaf9bSVasanthakumar Thiagarajan 53380abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 534108438bcSVasanthakumar Thiagarajan }; 535108438bcSVasanthakumar Thiagarajan 5366cb3c714SRaja Mani #define WOW_LIST_ID 0 5376cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 5386cb3c714SRaja Mani 53910509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 54010509f90SKalle Valo 541bdcd8170SKalle Valo /* Flag info */ 54259c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 54359c98449SVasanthakumar Thiagarajan WMI_ENABLED, 54459c98449SVasanthakumar Thiagarajan WMI_READY, 54559c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 54659c98449SVasanthakumar Thiagarajan TESTMODE, 54759c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 54859c98449SVasanthakumar Thiagarajan SKIP_SCAN, 54959c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 5505fe4dffbSKalle Valo FIRST_BOOT, 55159c98449SVasanthakumar Thiagarajan }; 552bdcd8170SKalle Valo 55376a9fbe2SKalle Valo enum ath6kl_state { 55476a9fbe2SKalle Valo ATH6KL_STATE_OFF, 55576a9fbe2SKalle Valo ATH6KL_STATE_ON, 556390a8c8fSRaja Mani ATH6KL_STATE_SUSPENDING, 557390a8c8fSRaja Mani ATH6KL_STATE_RESUMING, 55876a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 559b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 560dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 56110509f90SKalle Valo ATH6KL_STATE_SCHED_SCAN, 56276a9fbe2SKalle Valo }; 56376a9fbe2SKalle Valo 564bdcd8170SKalle Valo struct ath6kl { 565bdcd8170SKalle Valo struct device *dev; 566be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 56776a9fbe2SKalle Valo 56876a9fbe2SKalle Valo enum ath6kl_state state; 5695f1127ffSKalle Valo unsigned int testmode; 57076a9fbe2SKalle Valo 571bdcd8170SKalle Valo struct ath6kl_bmi bmi; 572bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 573bdcd8170SKalle Valo struct wmi *wmi; 574bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 575bdcd8170SKalle Valo int total_tx_data_pend; 576bdcd8170SKalle Valo struct htc_target *htc_target; 57777eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 578bdcd8170SKalle Valo void *hif_priv; 579990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 580990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 581990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 58255055976SVasanthakumar Thiagarajan u8 num_vif; 583368b1b0fSKalle Valo unsigned int vif_max; 5843226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 58555055976SVasanthakumar Thiagarajan u8 avail_idx_map; 58612eb9444SKalle Valo 58712eb9444SKalle Valo /* 58812eb9444SKalle Valo * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie() 58912eb9444SKalle Valo * calls, tx_pending and total_tx_data_pend. 59012eb9444SKalle Valo */ 591bdcd8170SKalle Valo spinlock_t lock; 59212eb9444SKalle Valo 593bdcd8170SKalle Valo struct semaphore sem; 594e5090444SVivek Natarajan u8 lrssi_roam_threshold; 595bdcd8170SKalle Valo struct ath6kl_version version; 596bdcd8170SKalle Valo u32 target_type; 597bdcd8170SKalle Valo u8 tx_pwr; 598bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 599bdcd8170SKalle Valo u8 ibss_ps_enable; 60055055976SVasanthakumar Thiagarajan bool ibss_if_active; 601bdcd8170SKalle Valo u8 node_num; 602bdcd8170SKalle Valo u8 next_ep_id; 603bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 604bdcd8170SKalle Valo u32 cookie_count; 605bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 606bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 607bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 608bdcd8170SKalle Valo u8 hiac_stream_active_pri; 609bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 610bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 6113c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 612bdcd8170SKalle Valo u32 connect_ctrl_flags; 613bdcd8170SKalle Valo u32 user_key_ctrl; 614bdcd8170SKalle Valo u8 usr_bss_filter; 615bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 616bdcd8170SKalle Valo u8 sta_list_index; 617bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 618bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 61912eb9444SKalle Valo 62012eb9444SKalle Valo /* 62112eb9444SKalle Valo * FIXME: protects access to mcastpsq but is actually useless as 62212eb9444SKalle Valo * all skbe_queue_*() functions provide serialisation themselves 62312eb9444SKalle Valo */ 624bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 62512eb9444SKalle Valo 626bdcd8170SKalle Valo u8 intra_bss; 627bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 628bdcd8170SKalle Valo u8 ap_country_code[3]; 629bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 630bdcd8170SKalle Valo u8 rx_meta_ver; 631bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 632d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 633bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 634003353b0SKalle Valo struct { 635003353b0SKalle Valo void *rx_report; 636003353b0SKalle Valo size_t rx_report_len; 637003353b0SKalle Valo } tm; 638003353b0SKalle Valo 639856f4b31SKalle Valo struct ath6kl_hw { 640856f4b31SKalle Valo u32 id; 641293badf4SKalle Valo const char *name; 642a01ac414SKalle Valo u32 dataset_patch_addr; 643a01ac414SKalle Valo u32 app_load_addr; 644a01ac414SKalle Valo u32 app_start_override_addr; 645991b27eaSKalle Valo u32 board_ext_data_addr; 646991b27eaSKalle Valo u32 reserved_ram_size; 6470d4d72bfSKalle Valo u32 board_addr; 64839586bf2SRyan Hsu u32 refclk_hz; 64939586bf2SRyan Hsu u32 uarttx_pin; 650cd23c1c9SAlex Yang u32 testscript_addr; 651d1a9421dSKalle Valo 652c0038972SKalle Valo struct ath6kl_hw_fw { 653c0038972SKalle Valo const char *dir; 654c0038972SKalle Valo const char *otp; 655d1a9421dSKalle Valo const char *fw; 656c0038972SKalle Valo const char *tcmd; 657c0038972SKalle Valo const char *patch; 658cd23c1c9SAlex Yang const char *utf; 659cd23c1c9SAlex Yang const char *testscript; 660c0038972SKalle Valo } fw; 661c0038972SKalle Valo 662d1a9421dSKalle Valo const char *fw_board; 663d1a9421dSKalle Valo const char *fw_default_board; 664a01ac414SKalle Valo } hw; 665a01ac414SKalle Valo 666bdcd8170SKalle Valo u16 conf_flags; 667e390af77SRaja Mani u16 suspend_mode; 6681e9a905dSRaja Mani u16 wow_suspend_mode; 669bdcd8170SKalle Valo wait_queue_head_t event_wq; 670bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 671bdcd8170SKalle Valo 672bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 673bdcd8170SKalle Valo unsigned long flag; 674bdcd8170SKalle Valo 675bdcd8170SKalle Valo u8 *fw_board; 676bdcd8170SKalle Valo size_t fw_board_len; 677bdcd8170SKalle Valo 678bdcd8170SKalle Valo u8 *fw_otp; 679bdcd8170SKalle Valo size_t fw_otp_len; 680bdcd8170SKalle Valo 681bdcd8170SKalle Valo u8 *fw; 682bdcd8170SKalle Valo size_t fw_len; 683bdcd8170SKalle Valo 684bdcd8170SKalle Valo u8 *fw_patch; 685bdcd8170SKalle Valo size_t fw_patch_len; 686bdcd8170SKalle Valo 687cd23c1c9SAlex Yang u8 *fw_testscript; 688cd23c1c9SAlex Yang size_t fw_testscript_len; 689cd23c1c9SAlex Yang 69065a8b4ccSKalle Valo unsigned int fw_api; 69197e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 69297e0496dSKalle Valo 693bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 6947c3075e9SVasanthakumar Thiagarajan 695d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 6966a7c9badSJouni Malinen 6976bbc7c35SJouni Malinen bool p2p; 6986bbc7c35SJouni Malinen 699e5348a1eSVasanthakumar Thiagarajan bool wiphy_registered; 700e5348a1eSVasanthakumar Thiagarajan 701bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 702bdf5396bSKalle Valo struct { 7039b9a4f2aSKalle Valo struct sk_buff_head fwlog_queue; 704c807b30dSKalle Valo struct completion fwlog_completion; 705c807b30dSKalle Valo bool fwlog_open; 706c807b30dSKalle Valo 707939f1cceSKalle Valo u32 fwlog_mask; 7089b9a4f2aSKalle Valo 70991d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 710252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 711252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 7129a730834SKalle Valo 7139a730834SKalle Valo struct { 7149a730834SKalle Valo unsigned int invalid_rate; 7159a730834SKalle Valo } war_stats; 7164b28a80dSJouni Malinen 7174b28a80dSJouni Malinen u8 *roam_tbl; 7184b28a80dSJouni Malinen unsigned int roam_tbl_len; 719ff0b0075SJouni Malinen 720ff0b0075SJouni Malinen u8 keepalive; 721ff0b0075SJouni Malinen u8 disc_timeout; 722bdf5396bSKalle Valo } debug; 723bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 724bdcd8170SKalle Valo }; 725bdcd8170SKalle Valo 726d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 727bdcd8170SKalle Valo { 728108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 729bdcd8170SKalle Valo } 730bdcd8170SKalle Valo 731bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 732bc07ddb2SKalle Valo u32 item_offset) 733bc07ddb2SKalle Valo { 734bc07ddb2SKalle Valo u32 addr = 0; 735bc07ddb2SKalle Valo 736bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 737bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 738bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 739bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 740bc07ddb2SKalle Valo 741bc07ddb2SKalle Valo return addr; 742bc07ddb2SKalle Valo } 743bc07ddb2SKalle Valo 744bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 745bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 746bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 747bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 748bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 749bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 750bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 751bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue); 752bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 753bdcd8170SKalle Valo struct htc_packet *packet); 754bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 755bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 756f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 757addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 758addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 759addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 760bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 761e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 762bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 763bdcd8170SKalle Valo 764bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 765bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 766bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 767bdcd8170SKalle Valo 7687baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 769c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info, 770c8651541SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn); 771bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 772bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 773bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 774bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 775bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 776bdcd8170SKalle Valo int len); 777bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 7781d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn); 779bdcd8170SKalle Valo 7806765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr); 781bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 782bdcd8170SKalle Valo 783bdcd8170SKalle Valo void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver); 784bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 785bdcd8170SKalle Valo enum htc_endpoint_id eid); 786240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 787bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 788bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 789bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 790bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 791240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 792240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 793572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 794c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 795240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 796bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 797bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 798240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 799bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 800240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 801240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 802bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 803bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 804bdcd8170SKalle Valo 805240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 806bdcd8170SKalle Valo 807240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 808240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 809240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 810240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 811bdcd8170SKalle Valo u8 win_sz); 812bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 813bdcd8170SKalle Valo 8146db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type, 8156db8fa53SVasanthakumar Thiagarajan bool wait_fot_compltn, bool cold_reset); 816e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 817990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 81855055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready); 8195fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 8205fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 82145eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 82245eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 82345eaa78fSKalle Valo 824a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 8255fe4dffbSKalle Valo 82645eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 82745eaa78fSKalle Valo int ath6kl_core_init(struct ath6kl *ar); 82845eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 82945eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 83045eaa78fSKalle Valo 831bdcd8170SKalle Valo #endif /* CORE_H */ 832