1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef CORE_H 19bdcd8170SKalle Valo #define CORE_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #include <linux/etherdevice.h> 22bdcd8170SKalle Valo #include <linux/rtnetlink.h> 23bdcd8170SKalle Valo #include <linux/firmware.h> 24bdcd8170SKalle Valo #include <linux/sched.h> 25bdf5396bSKalle Valo #include <linux/circ_buf.h> 26bdcd8170SKalle Valo #include <net/cfg80211.h> 27bdcd8170SKalle Valo #include "htc.h" 28bdcd8170SKalle Valo #include "wmi.h" 29bdcd8170SKalle Valo #include "bmi.h" 30bc07ddb2SKalle Valo #include "target.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define MAX_ATH6KL 1 33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 46bdcd8170SKalle Valo #define MAX_NODE_NUM 15 47bdcd8170SKalle Valo 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 51c1762a3fSThirumalai Pachamuthu 521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 541df94a85SVasanthakumar Thiagarajan 55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 58bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 59bdcd8170SKalle Valo 60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 63bdcd8170SKalle Valo 6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */ 6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */ 6613423c31SVasanthakumar Thiagarajan 6750d41234SKalle Valo /* includes also the null byte */ 6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6950d41234SKalle Valo 7050d41234SKalle Valo enum ath6kl_fw_ie_type { 7150d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7250d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7350d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7450d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7550d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 768a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7797e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 781b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7903ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 80368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 8150d41234SKalle Valo }; 8250d41234SKalle Valo 8397e0496dSKalle Valo enum ath6kl_fw_capability { 8497e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8510509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8697e0496dSKalle Valo 873ca9d1fcSAarthi Thiruvengadam /* 883ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 893ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 903ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 913ca9d1fcSAarthi Thiruvengadam */ 923ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 933ca9d1fcSAarthi Thiruvengadam 9403bdeb0dSVasanthakumar Thiagarajan /* 9503bdeb0dSVasanthakumar Thiagarajan * Firmware has support to cleanup inactive stations 9603bdeb0dSVasanthakumar Thiagarajan * in AP mode. 9703bdeb0dSVasanthakumar Thiagarajan */ 9803bdeb0dSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT, 9903bdeb0dSVasanthakumar Thiagarajan 100d97c121bSVasanthakumar Thiagarajan /* Firmware has support to override rsn cap of rsn ie */ 101d97c121bSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, 102d97c121bSVasanthakumar Thiagarajan 1036821d4f0SNaveen Gangadharan /* 1046821d4f0SNaveen Gangadharan * Multicast support in WOW and host awake mode. 1056821d4f0SNaveen Gangadharan * Allow all multicast in host awake mode. 1066821d4f0SNaveen Gangadharan * Apply multicast filter in WOW mode. 1076821d4f0SNaveen Gangadharan */ 1086821d4f0SNaveen Gangadharan ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER, 1096821d4f0SNaveen Gangadharan 110c422d52dSThomas Pedersen /* Firmware supports enhanced bmiss detection */ 111c422d52dSThomas Pedersen ATH6KL_FW_CAPABILITY_BMISS_ENHANCE, 112c422d52dSThomas Pedersen 113dd45b759SNaveen Singh /* 114dd45b759SNaveen Singh * FW supports matching of ssid in schedule scan 115dd45b759SNaveen Singh */ 116dd45b759SNaveen Singh ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST, 117dd45b759SNaveen Singh 11885b20fc2SThomas Pedersen /* Firmware supports filtering BSS results by RSSI */ 11985b20fc2SThomas Pedersen ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD, 12085b20fc2SThomas Pedersen 121c95dcb59SAarthi Thiruvengadam /* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */ 122c95dcb59SAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR, 123c95dcb59SAarthi Thiruvengadam 124279b2862SThomas Pedersen /* Firmware supports TX error rate notification */ 125279b2862SThomas Pedersen ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY, 126279b2862SThomas Pedersen 12784841ba2SKalle Valo /* supports WMI_SET_REGDOMAIN_CMDID command */ 12884841ba2SKalle Valo ATH6KL_FW_CAPABILITY_REGDOMAIN, 12984841ba2SKalle Valo 130b1f47e3aSThomas Pedersen /* Firmware supports sched scan decoupled from host sleep */ 131b1f47e3aSThomas Pedersen ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2, 132b1f47e3aSThomas Pedersen 13392332993SVasanthakumar Thiagarajan /* 13492332993SVasanthakumar Thiagarajan * Firmware capability for hang detection through heart beat 13592332993SVasanthakumar Thiagarajan * challenge messages. 13692332993SVasanthakumar Thiagarajan */ 13792332993SVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL, 13892332993SVasanthakumar Thiagarajan 139eba95bceSKalle Valo /* WMI_SET_TX_SELECT_RATES_CMDID uses 64 bit size rate table */ 140eba95bceSKalle Valo ATH6KL_FW_CAPABILITY_64BIT_RATES, 141eba95bceSKalle Valo 142eba95bceSKalle Valo /* WMI_AP_CONN_INACT_CMDID uses minutes as units */ 143eba95bceSKalle Valo ATH6KL_FW_CAPABILITY_AP_INACTIVITY_MINS, 144eba95bceSKalle Valo 145eba95bceSKalle Valo /* use low priority endpoint for all data */ 146eba95bceSKalle Valo ATH6KL_FW_CAPABILITY_MAP_LP_ENDPOINT, 147eba95bceSKalle Valo 148c1d32d30SJessica Wu /* ratetable is the 2 stream version (max MCS15) */ 149c1d32d30SJessica Wu ATH6KL_FW_CAPABILITY_RATETABLE_MCS15, 150c1d32d30SJessica Wu 15197e0496dSKalle Valo /* this needs to be last */ 15297e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 15397e0496dSKalle Valo }; 15497e0496dSKalle Valo 15597e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 15697e0496dSKalle Valo 15750d41234SKalle Valo struct ath6kl_fw_ie { 15850d41234SKalle Valo __le32 id; 15950d41234SKalle Valo __le32 len; 16050d41234SKalle Valo u8 data[0]; 16150d41234SKalle Valo }; 16250d41234SKalle Valo 16306e360acSBala Shanmugam enum ath6kl_hw_flags { 164a2e1be33SMohammed Shafi Shajakhan ATH6KL_HW_SDIO_CRC_ERROR_WAR = BIT(3), 16506e360acSBala Shanmugam }; 16606e360acSBala Shanmugam 167c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 16865a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 169b1f47e3aSThomas Pedersen #define ATH6KL_FW_API4_FILE "fw-4.bin" 170c0038972SKalle Valo 171bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1720d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 173bdcd8170SKalle Valo 174bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1750d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1760d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 177c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 178c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 179c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 180c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 181c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1822023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin" 1830d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1842023dbb8STim Gardner AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin" 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1870d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 188c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 189c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 190c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 191c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 192cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 193cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 194c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1952023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin" 1960d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 1972023dbb8STim Gardner AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin" 198bdcd8170SKalle Valo 19931024d99SKevin Fang /* AR6004 1.0 definitions */ 2000d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 201c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 202c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 2032023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin" 2040d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 2052023dbb8STim Gardner AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin" 206d5720e59SKalle Valo 207d5720e59SKalle Valo /* AR6004 1.1 definitions */ 2080d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 209c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 210c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 2112023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin" 2120d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 2132023dbb8STim Gardner AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin" 21431024d99SKevin Fang 2156146ca69SRay Chen /* AR6004 1.2 definitions */ 2166146ca69SRay Chen #define AR6004_HW_1_2_VERSION 0x300007e8 2176146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2" 2186146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin" 2192023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin" 2206146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \ 2212023dbb8STim Gardner AR6004_HW_1_2_FW_DIR "/bdata.bin" 2226146ca69SRay Chen 223bf744f11SBala Shanmugam /* AR6004 1.3 definitions */ 224bf744f11SBala Shanmugam #define AR6004_HW_1_3_VERSION 0x31c8088a 225bf744f11SBala Shanmugam #define AR6004_HW_1_3_FW_DIR "ath6k/AR6004/hw1.3" 226bf744f11SBala Shanmugam #define AR6004_HW_1_3_FIRMWARE_FILE "fw.ram.bin" 227bf744f11SBala Shanmugam #define AR6004_HW_1_3_BOARD_DATA_FILE "ath6k/AR6004/hw1.3/bdata.bin" 228bf744f11SBala Shanmugam #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE "ath6k/AR6004/hw1.3/bdata.bin" 229bf744f11SBala Shanmugam 230bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 231bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 232bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 233bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 234c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 235c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 236bdcd8170SKalle Valo 237bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 238bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 239bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 240bdcd8170SKalle Valo 241bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 242bdcd8170SKalle Valo 243bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 244bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 245bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 246bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 247bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 248bdcd8170SKalle Valo 249bdcd8170SKalle Valo #define NUM_OF_TIDS 8 250bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 251bdcd8170SKalle Valo 252bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 253bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 254bdcd8170SKalle Valo 255bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 256bdcd8170SKalle Valo 257bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 258bdcd8170SKalle Valo 2597940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT 100 /* in ms */ 260bdcd8170SKalle Valo 261bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 264bdcd8170SKalle Valo 2658f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */ 266ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME 1500 267ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */ 268ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME 5000 2698f46fccdSRaja Mani 270bdcd8170SKalle Valo /* configuration lags */ 271bdcd8170SKalle Valo /* 272bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 273bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 274bdcd8170SKalle Valo * sending (Re)Assoc req. 275bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 276bdcd8170SKalle Valo * module state transition failure events which happen during 277bdcd8170SKalle Valo * scan, to the host. 278bdcd8170SKalle Valo */ 279bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 280bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 281bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 282bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 283e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG BIT(4) 284bdcd8170SKalle Valo 285c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */ 286c86e4f44SAarthi Thiruvengadam 287bdcd8170SKalle Valo enum wlan_low_pwr_state { 288bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 289bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 290bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 291bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 292bdcd8170SKalle Valo }; 293bdcd8170SKalle Valo 294bdcd8170SKalle Valo enum sme_state { 295bdcd8170SKalle Valo SME_DISCONNECTED, 296bdcd8170SKalle Valo SME_CONNECTING, 297bdcd8170SKalle Valo SME_CONNECTED 298bdcd8170SKalle Valo }; 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo struct skb_hold_q { 301bdcd8170SKalle Valo struct sk_buff *skb; 302bdcd8170SKalle Valo bool is_amsdu; 303bdcd8170SKalle Valo u16 seq_no; 304bdcd8170SKalle Valo }; 305bdcd8170SKalle Valo 306bdcd8170SKalle Valo struct rxtid { 307bdcd8170SKalle Valo bool aggr; 308bdcd8170SKalle Valo bool timer_mon; 309bdcd8170SKalle Valo u16 win_sz; 310bdcd8170SKalle Valo u16 seq_next; 311bdcd8170SKalle Valo u32 hold_q_sz; 312bdcd8170SKalle Valo struct skb_hold_q *hold_q; 313bdcd8170SKalle Valo struct sk_buff_head q; 31412eb9444SKalle Valo 31512eb9444SKalle Valo /* 3160faf7458SVasanthakumar Thiagarajan * lock mainly protects seq_next and hold_q. Movement of seq_next 3170faf7458SVasanthakumar Thiagarajan * needs to be protected between aggr_timeout() and 3180faf7458SVasanthakumar Thiagarajan * aggr_process_recv_frm(). hold_q will be holding the pending 3190faf7458SVasanthakumar Thiagarajan * reorder frames and it's access should also be protected. 3200faf7458SVasanthakumar Thiagarajan * Some of the other fields like hold_q_sz, win_sz and aggr are 3210faf7458SVasanthakumar Thiagarajan * initialized/reset when receiving addba/delba req, also while 3220faf7458SVasanthakumar Thiagarajan * deleting aggr state all the pending buffers are flushed before 3230faf7458SVasanthakumar Thiagarajan * resetting these fields, so there should not be any race in accessing 3240faf7458SVasanthakumar Thiagarajan * these fields. 32512eb9444SKalle Valo */ 326bdcd8170SKalle Valo spinlock_t lock; 327bdcd8170SKalle Valo }; 328bdcd8170SKalle Valo 329bdcd8170SKalle Valo struct rxtid_stats { 330bdcd8170SKalle Valo u32 num_into_aggr; 331bdcd8170SKalle Valo u32 num_dups; 332bdcd8170SKalle Valo u32 num_oow; 333bdcd8170SKalle Valo u32 num_mpdu; 334bdcd8170SKalle Valo u32 num_amsdu; 335bdcd8170SKalle Valo u32 num_delivered; 336bdcd8170SKalle Valo u32 num_timeouts; 337bdcd8170SKalle Valo u32 num_hole; 338bdcd8170SKalle Valo u32 num_bar; 339bdcd8170SKalle Valo }; 340bdcd8170SKalle Valo 3417baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 342bdcd8170SKalle Valo u8 aggr_sz; 343bdcd8170SKalle Valo u8 timer_scheduled; 344bdcd8170SKalle Valo struct timer_list timer; 345bdcd8170SKalle Valo struct net_device *dev; 346bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 347bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 3487baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 3497baef812SVasanthakumar Thiagarajan }; 3507baef812SVasanthakumar Thiagarajan 3517baef812SVasanthakumar Thiagarajan struct aggr_info { 3527baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 3537baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 354bdcd8170SKalle Valo }; 355bdcd8170SKalle Valo 356bdcd8170SKalle Valo struct ath6kl_wep_key { 357bdcd8170SKalle Valo u8 key_index; 358bdcd8170SKalle Valo u8 key_len; 359bdcd8170SKalle Valo u8 key[64]; 360bdcd8170SKalle Valo }; 361bdcd8170SKalle Valo 362bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 363bdcd8170SKalle Valo 364bdcd8170SKalle Valo struct ath6kl_key { 365bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 366bdcd8170SKalle Valo u8 key_len; 367bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 368bdcd8170SKalle Valo u8 seq_len; 369bdcd8170SKalle Valo u32 cipher; 370bdcd8170SKalle Valo }; 371bdcd8170SKalle Valo 372bdcd8170SKalle Valo struct ath6kl_node_mapping { 373bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 374bdcd8170SKalle Valo u8 ep_id; 375bdcd8170SKalle Valo u8 tx_pend; 376bdcd8170SKalle Valo }; 377bdcd8170SKalle Valo 378bdcd8170SKalle Valo struct ath6kl_cookie { 379bdcd8170SKalle Valo struct sk_buff *skb; 380bdcd8170SKalle Valo u32 map_no; 381bdcd8170SKalle Valo struct htc_packet htc_pkt; 382bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 383bdcd8170SKalle Valo }; 384bdcd8170SKalle Valo 385d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff { 386d0ff7383SNaveen Gangadharan struct list_head list; 387d0ff7383SNaveen Gangadharan u32 freq; 388d0ff7383SNaveen Gangadharan u32 wait; 389d0ff7383SNaveen Gangadharan u32 id; 390d0ff7383SNaveen Gangadharan bool no_cck; 391d0ff7383SNaveen Gangadharan size_t len; 392d0ff7383SNaveen Gangadharan u8 buf[0]; 393d0ff7383SNaveen Gangadharan }; 394d0ff7383SNaveen Gangadharan 395bdcd8170SKalle Valo struct ath6kl_sta { 396bdcd8170SKalle Valo u16 sta_flags; 397bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 398bdcd8170SKalle Valo u8 aid; 399bdcd8170SKalle Valo u8 keymgmt; 400bdcd8170SKalle Valo u8 ucipher; 401bdcd8170SKalle Valo u8 auth; 402bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 403bdcd8170SKalle Valo struct sk_buff_head psq; 40412eb9444SKalle Valo 40512eb9444SKalle Valo /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */ 406bdcd8170SKalle Valo spinlock_t psq_lock; 40712eb9444SKalle Valo 408d0ff7383SNaveen Gangadharan struct list_head mgmt_psq; 409d0ff7383SNaveen Gangadharan size_t mgmt_psq_len; 410c1762a3fSThirumalai Pachamuthu u8 apsd_info; 411c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 4121d2a4456SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 413bdcd8170SKalle Valo }; 414bdcd8170SKalle Valo 415bdcd8170SKalle Valo struct ath6kl_version { 416bdcd8170SKalle Valo u32 target_ver; 417bdcd8170SKalle Valo u32 wlan_ver; 418bdcd8170SKalle Valo u32 abi_ver; 419bdcd8170SKalle Valo }; 420bdcd8170SKalle Valo 421bdcd8170SKalle Valo struct ath6kl_bmi { 422bdcd8170SKalle Valo u32 cmd_credits; 423bdcd8170SKalle Valo bool done_sent; 424bdcd8170SKalle Valo u8 *cmd_buf; 4251f4c894dSKalle Valo u32 max_data_size; 4261f4c894dSKalle Valo u32 max_cmd_size; 427bdcd8170SKalle Valo }; 428bdcd8170SKalle Valo 429bdcd8170SKalle Valo struct target_stats { 430bdcd8170SKalle Valo u64 tx_pkt; 431bdcd8170SKalle Valo u64 tx_byte; 432bdcd8170SKalle Valo u64 tx_ucast_pkt; 433bdcd8170SKalle Valo u64 tx_ucast_byte; 434bdcd8170SKalle Valo u64 tx_mcast_pkt; 435bdcd8170SKalle Valo u64 tx_mcast_byte; 436bdcd8170SKalle Valo u64 tx_bcast_pkt; 437bdcd8170SKalle Valo u64 tx_bcast_byte; 438bdcd8170SKalle Valo u64 tx_rts_success_cnt; 439bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 440bdcd8170SKalle Valo 441bdcd8170SKalle Valo u64 tx_err; 442bdcd8170SKalle Valo u64 tx_fail_cnt; 443bdcd8170SKalle Valo u64 tx_retry_cnt; 444bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 445bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 446bdcd8170SKalle Valo 447bdcd8170SKalle Valo u64 rx_pkt; 448bdcd8170SKalle Valo u64 rx_byte; 449bdcd8170SKalle Valo u64 rx_ucast_pkt; 450bdcd8170SKalle Valo u64 rx_ucast_byte; 451bdcd8170SKalle Valo u64 rx_mcast_pkt; 452bdcd8170SKalle Valo u64 rx_mcast_byte; 453bdcd8170SKalle Valo u64 rx_bcast_pkt; 454bdcd8170SKalle Valo u64 rx_bcast_byte; 455bdcd8170SKalle Valo u64 rx_frgment_pkt; 456bdcd8170SKalle Valo 457bdcd8170SKalle Valo u64 rx_err; 458bdcd8170SKalle Valo u64 rx_crc_err; 459bdcd8170SKalle Valo u64 rx_key_cache_miss; 460bdcd8170SKalle Valo u64 rx_decrypt_err; 461bdcd8170SKalle Valo u64 rx_dupl_frame; 462bdcd8170SKalle Valo 463bdcd8170SKalle Valo u64 tkip_local_mic_fail; 464bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 465bdcd8170SKalle Valo u64 tkip_replays; 466bdcd8170SKalle Valo u64 tkip_fmt_err; 467bdcd8170SKalle Valo u64 ccmp_fmt_err; 468bdcd8170SKalle Valo u64 ccmp_replays; 469bdcd8170SKalle Valo 470bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 471bdcd8170SKalle Valo 472bdcd8170SKalle Valo u64 cs_bmiss_cnt; 473bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 474bdcd8170SKalle Valo u64 cs_connect_cnt; 475bdcd8170SKalle Valo u64 cs_discon_cnt; 476bdcd8170SKalle Valo 477bdcd8170SKalle Valo s32 tx_ucast_rate; 478bdcd8170SKalle Valo s32 rx_ucast_rate; 479bdcd8170SKalle Valo 480bdcd8170SKalle Valo u32 lq_val; 481bdcd8170SKalle Valo 482bdcd8170SKalle Valo u32 wow_pkt_dropped; 483bdcd8170SKalle Valo u16 wow_evt_discarded; 484bdcd8170SKalle Valo 485bdcd8170SKalle Valo s16 noise_floor_calib; 486bdcd8170SKalle Valo s16 cs_rssi; 487bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 488bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 489bdcd8170SKalle Valo u8 cs_last_roam_msec; 490bdcd8170SKalle Valo u8 cs_snr; 491bdcd8170SKalle Valo 492bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 493bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 494bdcd8170SKalle Valo 495bdcd8170SKalle Valo u32 arp_received; 496bdcd8170SKalle Valo u32 arp_matched; 497bdcd8170SKalle Valo u32 arp_replied; 498bdcd8170SKalle Valo }; 499bdcd8170SKalle Valo 500bdcd8170SKalle Valo struct ath6kl_mbox_info { 501bdcd8170SKalle Valo u32 htc_addr; 502bdcd8170SKalle Valo u32 htc_ext_addr; 503bdcd8170SKalle Valo u32 htc_ext_sz; 504bdcd8170SKalle Valo 505bdcd8170SKalle Valo u32 block_size; 506bdcd8170SKalle Valo 507bdcd8170SKalle Valo u32 gmbox_addr; 508bdcd8170SKalle Valo 509bdcd8170SKalle Valo u32 gmbox_sz; 510bdcd8170SKalle Valo }; 511bdcd8170SKalle Valo 512bdcd8170SKalle Valo /* 513bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 514bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 515bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 516bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 517bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 518bdcd8170SKalle Valo */ 519bdcd8170SKalle Valo 520bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 521bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 522bdcd8170SKalle Valo 523bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 524bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 525bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 526bdcd8170SKalle Valo 5279a5b1318SJouni Malinen /* Initial group key for AP mode */ 528bdcd8170SKalle Valo struct ath6kl_req_key { 5299a5b1318SJouni Malinen bool valid; 5309a5b1318SJouni Malinen u8 key_index; 5319a5b1318SJouni Malinen int key_type; 5329a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 5339a5b1318SJouni Malinen u8 key_len; 534bdcd8170SKalle Valo }; 535bdcd8170SKalle Valo 53677eab1e9SKalle Valo enum ath6kl_hif_type { 53777eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 53877eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 53977eab1e9SKalle Valo }; 54077eab1e9SKalle Valo 541e76ac2bfSKalle Valo enum ath6kl_htc_type { 542e76ac2bfSKalle Valo ATH6KL_HTC_TYPE_MBOX, 543636f8288SKalle Valo ATH6KL_HTC_TYPE_PIPE, 544e76ac2bfSKalle Valo }; 545e76ac2bfSKalle Valo 54680abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 54780abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 54880abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 54980abaf9bSVasanthakumar Thiagarajan struct list_head list; 55080abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 55180abaf9bSVasanthakumar Thiagarajan }; 55280abaf9bSVasanthakumar Thiagarajan 553df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap { 554df90b369SVasanthakumar Thiagarajan bool ht_enable; 555df90b369SVasanthakumar Thiagarajan u8 ampdu_factor; 556df90b369SVasanthakumar Thiagarajan unsigned short cap_info; 557df90b369SVasanthakumar Thiagarajan }; 558df90b369SVasanthakumar Thiagarajan 55971f96ee6SKalle Valo /* 56071f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 56171f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 56271f96ee6SKalle Valo */ 563b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 564334234b5SVasanthakumar Thiagarajan 56559c98449SVasanthakumar Thiagarajan /* vif flags info */ 56659c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 56759c98449SVasanthakumar Thiagarajan CONNECTED, 56859c98449SVasanthakumar Thiagarajan CONNECT_PEND, 56959c98449SVasanthakumar Thiagarajan WMM_ENABLED, 57059c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 57159c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 57259c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 57359c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 57459c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 575b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 576081c7a84SRaja Mani HOST_SLEEP_MODE_CMD_PROCESSED, 5776251d801SNaveen Gangadharan NETDEV_MCAST_ALL_ON, 5786251d801SNaveen Gangadharan NETDEV_MCAST_ALL_OFF, 579b1f47e3aSThomas Pedersen SCHED_SCANNING, 58059c98449SVasanthakumar Thiagarajan }; 58159c98449SVasanthakumar Thiagarajan 582108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 583990bd915SVasanthakumar Thiagarajan struct list_head list; 584108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 585108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 586108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 587478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 588478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 589334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 59059c98449SVasanthakumar Thiagarajan unsigned long flags; 5913450334fSVasanthakumar Thiagarajan int ssid_len; 5923450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 5933450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 5943450334fSVasanthakumar Thiagarajan u8 auth_mode; 5953450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 5963450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 5973450334fSVasanthakumar Thiagarajan u8 grp_crypto; 5983450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 5993450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 600f5938f24SVasanthakumar Thiagarajan u8 next_mode; 601f5938f24SVasanthakumar Thiagarajan u8 nw_type; 6028c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 6038c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 604f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 605f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 6066f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 6076f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 6082132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 60967b3f129SKiran Reddy struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS]; 61010509f90SKalle Valo 611de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 61210509f90SKalle Valo struct timer_list sched_scan_timer; 61310509f90SKalle Valo 61414ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 61514ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 616cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 6171052261eSJouni Malinen u32 last_roc_id; 6181052261eSJouni Malinen u32 last_cancel_roc_id; 619cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 620cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 621cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 6228f46fccdSRaja Mani u16 listen_intvl_t; 623ce0dc0cfSRaja Mani u16 bmiss_time_t; 624279b2862SThomas Pedersen u32 txe_intvl; 625eb38987eSRaja Mani u16 bg_scan_period; 626cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 627b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 628b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 629c4f7863eSThomas Pedersen struct wmi_connect_cmd profile; 630f21243a8SThomas Pedersen u16 rsn_capab; 63180abaf9bSVasanthakumar Thiagarajan 63280abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 633108438bcSVasanthakumar Thiagarajan }; 634108438bcSVasanthakumar Thiagarajan 63571bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev) 63671bbc994SJohannes Berg { 63771bbc994SJohannes Berg return container_of(wdev, struct ath6kl_vif, wdev); 63871bbc994SJohannes Berg } 63971bbc994SJohannes Berg 6406cb3c714SRaja Mani #define WOW_LIST_ID 0 6416cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 6426cb3c714SRaja Mani 64310509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 64410509f90SKalle Valo 645bdcd8170SKalle Valo /* Flag info */ 64659c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 64759c98449SVasanthakumar Thiagarajan WMI_ENABLED, 64859c98449SVasanthakumar Thiagarajan WMI_READY, 64959c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 65059c98449SVasanthakumar Thiagarajan TESTMODE, 65159c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 65259c98449SVasanthakumar Thiagarajan SKIP_SCAN, 65359c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 6545fe4dffbSKalle Valo FIRST_BOOT, 655a3561706SVasanthakumar Thiagarajan RECOVERY_CLEANUP, 65659c98449SVasanthakumar Thiagarajan }; 657bdcd8170SKalle Valo 65876a9fbe2SKalle Valo enum ath6kl_state { 65976a9fbe2SKalle Valo ATH6KL_STATE_OFF, 66076a9fbe2SKalle Valo ATH6KL_STATE_ON, 661390a8c8fSRaja Mani ATH6KL_STATE_SUSPENDING, 662390a8c8fSRaja Mani ATH6KL_STATE_RESUMING, 66376a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 664b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 665dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 66684caf800SVasanthakumar Thiagarajan ATH6KL_STATE_RECOVERY, 66784caf800SVasanthakumar Thiagarajan }; 66884caf800SVasanthakumar Thiagarajan 66984caf800SVasanthakumar Thiagarajan /* Fw error recovery */ 67092332993SVasanthakumar Thiagarajan #define ATH6KL_HB_RESP_MISS_THRES 5 67192332993SVasanthakumar Thiagarajan 67284caf800SVasanthakumar Thiagarajan enum ath6kl_fw_err { 67384caf800SVasanthakumar Thiagarajan ATH6KL_FW_ASSERT, 67492332993SVasanthakumar Thiagarajan ATH6KL_FW_HB_RESP_FAILURE, 67577565794SVasanthakumar Thiagarajan ATH6KL_FW_EP_FULL, 67676a9fbe2SKalle Valo }; 67776a9fbe2SKalle Valo 678bdcd8170SKalle Valo struct ath6kl { 679bdcd8170SKalle Valo struct device *dev; 680be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 68176a9fbe2SKalle Valo 68276a9fbe2SKalle Valo enum ath6kl_state state; 6835f1127ffSKalle Valo unsigned int testmode; 68476a9fbe2SKalle Valo 685bdcd8170SKalle Valo struct ath6kl_bmi bmi; 686bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 687e76ac2bfSKalle Valo const struct ath6kl_htc_ops *htc_ops; 688bdcd8170SKalle Valo struct wmi *wmi; 689bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 690bdcd8170SKalle Valo int total_tx_data_pend; 691bdcd8170SKalle Valo struct htc_target *htc_target; 69277eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 693bdcd8170SKalle Valo void *hif_priv; 694990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 695990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 696990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 69755055976SVasanthakumar Thiagarajan u8 num_vif; 698368b1b0fSKalle Valo unsigned int vif_max; 6993226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 70055055976SVasanthakumar Thiagarajan u8 avail_idx_map; 70112eb9444SKalle Valo 70212eb9444SKalle Valo /* 70312eb9444SKalle Valo * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie() 70412eb9444SKalle Valo * calls, tx_pending and total_tx_data_pend. 70512eb9444SKalle Valo */ 706bdcd8170SKalle Valo spinlock_t lock; 70712eb9444SKalle Valo 708bdcd8170SKalle Valo struct semaphore sem; 709e5090444SVivek Natarajan u8 lrssi_roam_threshold; 710bdcd8170SKalle Valo struct ath6kl_version version; 711bdcd8170SKalle Valo u32 target_type; 712bdcd8170SKalle Valo u8 tx_pwr; 713bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 714bdcd8170SKalle Valo u8 ibss_ps_enable; 71555055976SVasanthakumar Thiagarajan bool ibss_if_active; 716bdcd8170SKalle Valo u8 node_num; 717bdcd8170SKalle Valo u8 next_ep_id; 718bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 719bdcd8170SKalle Valo u32 cookie_count; 720bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 721bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 722bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 723bdcd8170SKalle Valo u8 hiac_stream_active_pri; 724bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 725bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 7263c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 727bdcd8170SKalle Valo u32 connect_ctrl_flags; 728bdcd8170SKalle Valo u32 user_key_ctrl; 729bdcd8170SKalle Valo u8 usr_bss_filter; 730bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 731bdcd8170SKalle Valo u8 sta_list_index; 732bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 733bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 734c4f7863eSThomas Pedersen u32 want_ch_switch; 735b5495e66SThomas Pedersen u16 last_ch; 73612eb9444SKalle Valo 73712eb9444SKalle Valo /* 73812eb9444SKalle Valo * FIXME: protects access to mcastpsq but is actually useless as 73912eb9444SKalle Valo * all skbe_queue_*() functions provide serialisation themselves 74012eb9444SKalle Valo */ 741bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 74212eb9444SKalle Valo 743bdcd8170SKalle Valo u8 intra_bss; 744bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 745bdcd8170SKalle Valo u8 ap_country_code[3]; 746bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 747bdcd8170SKalle Valo u8 rx_meta_ver; 748bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 749d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 750bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 751003353b0SKalle Valo struct { 752003353b0SKalle Valo void *rx_report; 753003353b0SKalle Valo size_t rx_report_len; 754003353b0SKalle Valo } tm; 755003353b0SKalle Valo 756856f4b31SKalle Valo struct ath6kl_hw { 757856f4b31SKalle Valo u32 id; 758293badf4SKalle Valo const char *name; 759a01ac414SKalle Valo u32 dataset_patch_addr; 760a01ac414SKalle Valo u32 app_load_addr; 761a01ac414SKalle Valo u32 app_start_override_addr; 762991b27eaSKalle Valo u32 board_ext_data_addr; 763991b27eaSKalle Valo u32 reserved_ram_size; 7640d4d72bfSKalle Valo u32 board_addr; 76539586bf2SRyan Hsu u32 refclk_hz; 76639586bf2SRyan Hsu u32 uarttx_pin; 767cd23c1c9SAlex Yang u32 testscript_addr; 768d92917e4SThomas Pedersen enum wmi_phy_cap cap; 769d1a9421dSKalle Valo 77006e360acSBala Shanmugam u32 flags; 77106e360acSBala Shanmugam 772c0038972SKalle Valo struct ath6kl_hw_fw { 773c0038972SKalle Valo const char *dir; 774c0038972SKalle Valo const char *otp; 775d1a9421dSKalle Valo const char *fw; 776c0038972SKalle Valo const char *tcmd; 777c0038972SKalle Valo const char *patch; 778cd23c1c9SAlex Yang const char *utf; 779cd23c1c9SAlex Yang const char *testscript; 780c0038972SKalle Valo } fw; 781c0038972SKalle Valo 782d1a9421dSKalle Valo const char *fw_board; 783d1a9421dSKalle Valo const char *fw_default_board; 784a01ac414SKalle Valo } hw; 785a01ac414SKalle Valo 786bdcd8170SKalle Valo u16 conf_flags; 787e390af77SRaja Mani u16 suspend_mode; 7881e9a905dSRaja Mani u16 wow_suspend_mode; 789bdcd8170SKalle Valo wait_queue_head_t event_wq; 790bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 791bdcd8170SKalle Valo 792bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 793bdcd8170SKalle Valo unsigned long flag; 794bdcd8170SKalle Valo 795bdcd8170SKalle Valo u8 *fw_board; 796bdcd8170SKalle Valo size_t fw_board_len; 797bdcd8170SKalle Valo 798bdcd8170SKalle Valo u8 *fw_otp; 799bdcd8170SKalle Valo size_t fw_otp_len; 800bdcd8170SKalle Valo 801bdcd8170SKalle Valo u8 *fw; 802bdcd8170SKalle Valo size_t fw_len; 803bdcd8170SKalle Valo 804bdcd8170SKalle Valo u8 *fw_patch; 805bdcd8170SKalle Valo size_t fw_patch_len; 806bdcd8170SKalle Valo 807cd23c1c9SAlex Yang u8 *fw_testscript; 808cd23c1c9SAlex Yang size_t fw_testscript_len; 809cd23c1c9SAlex Yang 81065a8b4ccSKalle Valo unsigned int fw_api; 81197e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 81297e0496dSKalle Valo 813bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 8147c3075e9SVasanthakumar Thiagarajan 815d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 8166a7c9badSJouni Malinen 8176bbc7c35SJouni Malinen bool p2p; 8186bbc7c35SJouni Malinen 819e5348a1eSVasanthakumar Thiagarajan bool wiphy_registered; 820e5348a1eSVasanthakumar Thiagarajan 82184caf800SVasanthakumar Thiagarajan struct ath6kl_fw_recovery { 82284caf800SVasanthakumar Thiagarajan struct work_struct recovery_work; 82384caf800SVasanthakumar Thiagarajan unsigned long err_reason; 82492332993SVasanthakumar Thiagarajan unsigned long hb_poll; 82592332993SVasanthakumar Thiagarajan struct timer_list hb_timer; 82692332993SVasanthakumar Thiagarajan u32 seq_num; 82792332993SVasanthakumar Thiagarajan bool hb_pending; 82892332993SVasanthakumar Thiagarajan u8 hb_misscnt; 82966ddcc39SVasanthakumar Thiagarajan bool enable; 83084caf800SVasanthakumar Thiagarajan } fw_recovery; 83184caf800SVasanthakumar Thiagarajan 832bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 833bdf5396bSKalle Valo struct { 8349b9a4f2aSKalle Valo struct sk_buff_head fwlog_queue; 835c807b30dSKalle Valo struct completion fwlog_completion; 836c807b30dSKalle Valo bool fwlog_open; 837c807b30dSKalle Valo 838939f1cceSKalle Valo u32 fwlog_mask; 8399b9a4f2aSKalle Valo 84091d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 841252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 842252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 8439a730834SKalle Valo 8449a730834SKalle Valo struct { 8459a730834SKalle Valo unsigned int invalid_rate; 8469a730834SKalle Valo } war_stats; 8474b28a80dSJouni Malinen 8484b28a80dSJouni Malinen u8 *roam_tbl; 8494b28a80dSJouni Malinen unsigned int roam_tbl_len; 850ff0b0075SJouni Malinen 851ff0b0075SJouni Malinen u8 keepalive; 852ff0b0075SJouni Malinen u8 disc_timeout; 853bdf5396bSKalle Valo } debug; 854bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 855bdcd8170SKalle Valo }; 856bdcd8170SKalle Valo 857d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 858bdcd8170SKalle Valo { 859108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 860bdcd8170SKalle Valo } 861bdcd8170SKalle Valo 862bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 863bc07ddb2SKalle Valo u32 item_offset) 864bc07ddb2SKalle Valo { 865bc07ddb2SKalle Valo u32 addr = 0; 866bc07ddb2SKalle Valo 867bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 868bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 869bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 870bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 871bc07ddb2SKalle Valo 872bc07ddb2SKalle Valo return addr; 873bc07ddb2SKalle Valo } 874bc07ddb2SKalle Valo 875bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 876bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 877bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 878bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 879bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 880bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 881bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 88263de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context, 88363de1112SKalle Valo struct list_head *packet_queue); 884bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 885bdcd8170SKalle Valo struct htc_packet *packet); 886bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 887bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 888f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 889addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 890addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 891addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 892bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 893e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 894bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 895bdcd8170SKalle Valo 896bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 897bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 898bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 899bdcd8170SKalle Valo 9007baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 901c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info, 902c8651541SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn); 903bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 904bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 905bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 906bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 907bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 908bdcd8170SKalle Valo int len); 909bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 9101d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn); 911bdcd8170SKalle Valo 9126765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr); 913bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 914bdcd8170SKalle Valo 915d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver, 916d92917e4SThomas Pedersen enum wmi_phy_cap cap); 917bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 918bdcd8170SKalle Valo enum htc_endpoint_id eid); 919240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 920bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 921bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 922bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 923bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 924240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 925240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 926572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 927c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 928240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 929bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 930bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 931240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 932bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 933240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 934240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 935bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 936bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 937bdcd8170SKalle Valo 938240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 939bdcd8170SKalle Valo 940240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 941240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 942240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 943240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 944bdcd8170SKalle Valo u8 win_sz); 945bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 946bdcd8170SKalle Valo 947e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 948990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 949355b3a98SMohammed Shafi Shajakhan void ath6kl_cfg80211_vif_stop(struct ath6kl_vif *vif, bool wmi_ready); 9505fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 9515fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 95245eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 95345eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 95445eaa78fSKalle Valo 955a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 9565fe4dffbSKalle Valo 957636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb); 958636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe); 959636f8288SKalle Valo 96045eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 961e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type); 96245eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 96345eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 96445eaa78fSKalle Valo 96584caf800SVasanthakumar Thiagarajan /* Fw error recovery */ 96684caf800SVasanthakumar Thiagarajan void ath6kl_init_hw_restart(struct ath6kl *ar); 96784caf800SVasanthakumar Thiagarajan void ath6kl_recovery_err_notify(struct ath6kl *ar, enum ath6kl_fw_err reason); 96892332993SVasanthakumar Thiagarajan void ath6kl_recovery_hb_event(struct ath6kl *ar, u32 cookie); 96984caf800SVasanthakumar Thiagarajan void ath6kl_recovery_init(struct ath6kl *ar); 97084caf800SVasanthakumar Thiagarajan void ath6kl_recovery_cleanup(struct ath6kl *ar); 97184caf800SVasanthakumar Thiagarajan void ath6kl_recovery_suspend(struct ath6kl *ar); 97292332993SVasanthakumar Thiagarajan void ath6kl_recovery_resume(struct ath6kl *ar); 973bdcd8170SKalle Valo #endif /* CORE_H */ 974