1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
100d97c121bSVasanthakumar Thiagarajan 	/* Firmware has support to override rsn cap of rsn ie */
101d97c121bSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102d97c121bSVasanthakumar Thiagarajan 
1036821d4f0SNaveen Gangadharan 	/*
1046821d4f0SNaveen Gangadharan 	 * Multicast support in WOW and host awake mode.
1056821d4f0SNaveen Gangadharan 	 * Allow all multicast in host awake mode.
1066821d4f0SNaveen Gangadharan 	 * Apply multicast filter in WOW mode.
1076821d4f0SNaveen Gangadharan 	 */
1086821d4f0SNaveen Gangadharan 	ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
1096821d4f0SNaveen Gangadharan 
110c422d52dSThomas Pedersen 	/* Firmware supports enhanced bmiss detection */
111c422d52dSThomas Pedersen 	ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
112c422d52dSThomas Pedersen 
113dd45b759SNaveen Singh 	/*
114dd45b759SNaveen Singh 	 * FW supports matching of ssid in schedule scan
115dd45b759SNaveen Singh 	 */
116dd45b759SNaveen Singh 	ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
117dd45b759SNaveen Singh 
11885b20fc2SThomas Pedersen 	/* Firmware supports filtering BSS results by RSSI */
11985b20fc2SThomas Pedersen 	ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
12085b20fc2SThomas Pedersen 
121c95dcb59SAarthi Thiruvengadam 	/* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */
122c95dcb59SAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
123c95dcb59SAarthi Thiruvengadam 
124279b2862SThomas Pedersen 	/* Firmware supports TX error rate notification */
125279b2862SThomas Pedersen 	ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY,
126279b2862SThomas Pedersen 
12784841ba2SKalle Valo 	/* supports WMI_SET_REGDOMAIN_CMDID command */
12884841ba2SKalle Valo 	ATH6KL_FW_CAPABILITY_REGDOMAIN,
12984841ba2SKalle Valo 
130b1f47e3aSThomas Pedersen 	/* Firmware supports sched scan decoupled from host sleep */
131b1f47e3aSThomas Pedersen 	ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2,
132b1f47e3aSThomas Pedersen 
13397e0496dSKalle Valo 	/* this needs to be last */
13497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
13597e0496dSKalle Valo };
13697e0496dSKalle Valo 
13797e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
13897e0496dSKalle Valo 
13950d41234SKalle Valo struct ath6kl_fw_ie {
14050d41234SKalle Valo 	__le32 id;
14150d41234SKalle Valo 	__le32 len;
14250d41234SKalle Valo 	u8 data[0];
14350d41234SKalle Valo };
14450d41234SKalle Valo 
14506e360acSBala Shanmugam enum ath6kl_hw_flags {
14606e360acSBala Shanmugam 	ATH6KL_HW_FLAG_64BIT_RATES	= BIT(0),
14706e360acSBala Shanmugam };
14806e360acSBala Shanmugam 
149c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
15065a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
151b1f47e3aSThomas Pedersen #define ATH6KL_FW_API4_FILE "fw-4.bin"
152c0038972SKalle Valo 
153bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1540d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
155bdcd8170SKalle Valo 
156bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1570d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1580d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
159c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
160c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
161c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
162c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
163c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1642023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
1650d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1662023dbb8STim Gardner 			AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
167bdcd8170SKalle Valo 
168bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1690d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
170c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
171c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
172c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
173c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
174cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
175cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
176c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1772023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
1780d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
1792023dbb8STim Gardner 			AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
180bdcd8170SKalle Valo 
18131024d99SKevin Fang /* AR6004 1.0 definitions */
1820d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
183c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
184c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1852023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE         AR6004_HW_1_0_FW_DIR "/bdata.bin"
1860d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
1872023dbb8STim Gardner 	AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
188d5720e59SKalle Valo 
189d5720e59SKalle Valo /* AR6004 1.1 definitions */
1900d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
191c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
192c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1932023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE         AR6004_HW_1_1_FW_DIR "/bdata.bin"
1940d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
1952023dbb8STim Gardner 	AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
19631024d99SKevin Fang 
1976146ca69SRay Chen /* AR6004 1.2 definitions */
1986146ca69SRay Chen #define AR6004_HW_1_2_VERSION                 0x300007e8
1996146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR			"ath6k/AR6004/hw1.2"
2006146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE           "fw.ram.bin"
2012023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE         AR6004_HW_1_2_FW_DIR "/bdata.bin"
2026146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
2032023dbb8STim Gardner 	AR6004_HW_1_2_FW_DIR "/bdata.bin"
2046146ca69SRay Chen 
205bf744f11SBala Shanmugam /* AR6004 1.3 definitions */
206bf744f11SBala Shanmugam #define AR6004_HW_1_3_VERSION			0x31c8088a
207bf744f11SBala Shanmugam #define AR6004_HW_1_3_FW_DIR			"ath6k/AR6004/hw1.3"
208bf744f11SBala Shanmugam #define AR6004_HW_1_3_FIRMWARE_FILE		"fw.ram.bin"
209bf744f11SBala Shanmugam #define AR6004_HW_1_3_BOARD_DATA_FILE		"ath6k/AR6004/hw1.3/bdata.bin"
210bf744f11SBala Shanmugam #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE	"ath6k/AR6004/hw1.3/bdata.bin"
211bf744f11SBala Shanmugam 
212bdcd8170SKalle Valo /* Per STA data, used in AP mode */
213bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
214bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
215bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
216c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
217c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
218bdcd8170SKalle Valo 
219bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
220bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
221bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
222bdcd8170SKalle Valo 
223bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
224bdcd8170SKalle Valo 
225bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
226bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
227bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
228bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
229bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
230bdcd8170SKalle Valo 
231bdcd8170SKalle Valo #define NUM_OF_TIDS         8
232bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
233bdcd8170SKalle Valo 
234bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
235bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
236bdcd8170SKalle Valo 
237bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
238bdcd8170SKalle Valo 
239bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
240bdcd8170SKalle Valo 
2417940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT     100	/* in ms */
242bdcd8170SKalle Valo 
243bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
244bdcd8170SKalle Valo 
245bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
246bdcd8170SKalle Valo 
2478f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
248ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
249ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
250ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
2518f46fccdSRaja Mani 
252bdcd8170SKalle Valo /* configuration lags */
253bdcd8170SKalle Valo /*
254bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
255bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
256bdcd8170SKalle Valo  * sending (Re)Assoc req.
257bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
258bdcd8170SKalle Valo  * module state transition failure events which happen during
259bdcd8170SKalle Valo  * scan, to the host.
260bdcd8170SKalle Valo  */
261bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
262bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
263bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
264bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
265e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
266bdcd8170SKalle Valo 
267c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
268c86e4f44SAarthi Thiruvengadam 
269bdcd8170SKalle Valo enum wlan_low_pwr_state {
270bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
271bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
272bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
273bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
274bdcd8170SKalle Valo };
275bdcd8170SKalle Valo 
276bdcd8170SKalle Valo enum sme_state {
277bdcd8170SKalle Valo 	SME_DISCONNECTED,
278bdcd8170SKalle Valo 	SME_CONNECTING,
279bdcd8170SKalle Valo 	SME_CONNECTED
280bdcd8170SKalle Valo };
281bdcd8170SKalle Valo 
282bdcd8170SKalle Valo struct skb_hold_q {
283bdcd8170SKalle Valo 	struct sk_buff *skb;
284bdcd8170SKalle Valo 	bool is_amsdu;
285bdcd8170SKalle Valo 	u16 seq_no;
286bdcd8170SKalle Valo };
287bdcd8170SKalle Valo 
288bdcd8170SKalle Valo struct rxtid {
289bdcd8170SKalle Valo 	bool aggr;
290bdcd8170SKalle Valo 	bool timer_mon;
291bdcd8170SKalle Valo 	u16 win_sz;
292bdcd8170SKalle Valo 	u16 seq_next;
293bdcd8170SKalle Valo 	u32 hold_q_sz;
294bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
295bdcd8170SKalle Valo 	struct sk_buff_head q;
29612eb9444SKalle Valo 
29712eb9444SKalle Valo 	/*
2980faf7458SVasanthakumar Thiagarajan 	 * lock mainly protects seq_next and hold_q. Movement of seq_next
2990faf7458SVasanthakumar Thiagarajan 	 * needs to be protected between aggr_timeout() and
3000faf7458SVasanthakumar Thiagarajan 	 * aggr_process_recv_frm(). hold_q will be holding the pending
3010faf7458SVasanthakumar Thiagarajan 	 * reorder frames and it's access should also be protected.
3020faf7458SVasanthakumar Thiagarajan 	 * Some of the other fields like hold_q_sz, win_sz and aggr are
3030faf7458SVasanthakumar Thiagarajan 	 * initialized/reset when receiving addba/delba req, also while
3040faf7458SVasanthakumar Thiagarajan 	 * deleting aggr state all the pending buffers are flushed before
3050faf7458SVasanthakumar Thiagarajan 	 * resetting these fields, so there should not be any race in accessing
3060faf7458SVasanthakumar Thiagarajan 	 * these fields.
30712eb9444SKalle Valo 	 */
308bdcd8170SKalle Valo 	spinlock_t lock;
309bdcd8170SKalle Valo };
310bdcd8170SKalle Valo 
311bdcd8170SKalle Valo struct rxtid_stats {
312bdcd8170SKalle Valo 	u32 num_into_aggr;
313bdcd8170SKalle Valo 	u32 num_dups;
314bdcd8170SKalle Valo 	u32 num_oow;
315bdcd8170SKalle Valo 	u32 num_mpdu;
316bdcd8170SKalle Valo 	u32 num_amsdu;
317bdcd8170SKalle Valo 	u32 num_delivered;
318bdcd8170SKalle Valo 	u32 num_timeouts;
319bdcd8170SKalle Valo 	u32 num_hole;
320bdcd8170SKalle Valo 	u32 num_bar;
321bdcd8170SKalle Valo };
322bdcd8170SKalle Valo 
3237baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
324bdcd8170SKalle Valo 	u8 aggr_sz;
325bdcd8170SKalle Valo 	u8 timer_scheduled;
326bdcd8170SKalle Valo 	struct timer_list timer;
327bdcd8170SKalle Valo 	struct net_device *dev;
328bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
329bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
3307baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
3317baef812SVasanthakumar Thiagarajan };
3327baef812SVasanthakumar Thiagarajan 
3337baef812SVasanthakumar Thiagarajan struct aggr_info {
3347baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
3357baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
336bdcd8170SKalle Valo };
337bdcd8170SKalle Valo 
338bdcd8170SKalle Valo struct ath6kl_wep_key {
339bdcd8170SKalle Valo 	u8 key_index;
340bdcd8170SKalle Valo 	u8 key_len;
341bdcd8170SKalle Valo 	u8 key[64];
342bdcd8170SKalle Valo };
343bdcd8170SKalle Valo 
344bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
345bdcd8170SKalle Valo 
346bdcd8170SKalle Valo struct ath6kl_key {
347bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
348bdcd8170SKalle Valo 	u8 key_len;
349bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
350bdcd8170SKalle Valo 	u8 seq_len;
351bdcd8170SKalle Valo 	u32 cipher;
352bdcd8170SKalle Valo };
353bdcd8170SKalle Valo 
354bdcd8170SKalle Valo struct ath6kl_node_mapping {
355bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
356bdcd8170SKalle Valo 	u8 ep_id;
357bdcd8170SKalle Valo 	u8 tx_pend;
358bdcd8170SKalle Valo };
359bdcd8170SKalle Valo 
360bdcd8170SKalle Valo struct ath6kl_cookie {
361bdcd8170SKalle Valo 	struct sk_buff *skb;
362bdcd8170SKalle Valo 	u32 map_no;
363bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
364bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
365bdcd8170SKalle Valo };
366bdcd8170SKalle Valo 
367d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
368d0ff7383SNaveen Gangadharan 	struct list_head list;
369d0ff7383SNaveen Gangadharan 	u32 freq;
370d0ff7383SNaveen Gangadharan 	u32 wait;
371d0ff7383SNaveen Gangadharan 	u32 id;
372d0ff7383SNaveen Gangadharan 	bool no_cck;
373d0ff7383SNaveen Gangadharan 	size_t len;
374d0ff7383SNaveen Gangadharan 	u8 buf[0];
375d0ff7383SNaveen Gangadharan };
376d0ff7383SNaveen Gangadharan 
377bdcd8170SKalle Valo struct ath6kl_sta {
378bdcd8170SKalle Valo 	u16 sta_flags;
379bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
380bdcd8170SKalle Valo 	u8 aid;
381bdcd8170SKalle Valo 	u8 keymgmt;
382bdcd8170SKalle Valo 	u8 ucipher;
383bdcd8170SKalle Valo 	u8 auth;
384bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
385bdcd8170SKalle Valo 	struct sk_buff_head psq;
38612eb9444SKalle Valo 
38712eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
388bdcd8170SKalle Valo 	spinlock_t psq_lock;
38912eb9444SKalle Valo 
390d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
391d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
392c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
393c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3941d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
395bdcd8170SKalle Valo };
396bdcd8170SKalle Valo 
397bdcd8170SKalle Valo struct ath6kl_version {
398bdcd8170SKalle Valo 	u32 target_ver;
399bdcd8170SKalle Valo 	u32 wlan_ver;
400bdcd8170SKalle Valo 	u32 abi_ver;
401bdcd8170SKalle Valo };
402bdcd8170SKalle Valo 
403bdcd8170SKalle Valo struct ath6kl_bmi {
404bdcd8170SKalle Valo 	u32 cmd_credits;
405bdcd8170SKalle Valo 	bool done_sent;
406bdcd8170SKalle Valo 	u8 *cmd_buf;
4071f4c894dSKalle Valo 	u32 max_data_size;
4081f4c894dSKalle Valo 	u32 max_cmd_size;
409bdcd8170SKalle Valo };
410bdcd8170SKalle Valo 
411bdcd8170SKalle Valo struct target_stats {
412bdcd8170SKalle Valo 	u64 tx_pkt;
413bdcd8170SKalle Valo 	u64 tx_byte;
414bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
415bdcd8170SKalle Valo 	u64 tx_ucast_byte;
416bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
417bdcd8170SKalle Valo 	u64 tx_mcast_byte;
418bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
419bdcd8170SKalle Valo 	u64 tx_bcast_byte;
420bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
421bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
422bdcd8170SKalle Valo 
423bdcd8170SKalle Valo 	u64 tx_err;
424bdcd8170SKalle Valo 	u64 tx_fail_cnt;
425bdcd8170SKalle Valo 	u64 tx_retry_cnt;
426bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
427bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
428bdcd8170SKalle Valo 
429bdcd8170SKalle Valo 	u64 rx_pkt;
430bdcd8170SKalle Valo 	u64 rx_byte;
431bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
432bdcd8170SKalle Valo 	u64 rx_ucast_byte;
433bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
434bdcd8170SKalle Valo 	u64 rx_mcast_byte;
435bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
436bdcd8170SKalle Valo 	u64 rx_bcast_byte;
437bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
438bdcd8170SKalle Valo 
439bdcd8170SKalle Valo 	u64 rx_err;
440bdcd8170SKalle Valo 	u64 rx_crc_err;
441bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
442bdcd8170SKalle Valo 	u64 rx_decrypt_err;
443bdcd8170SKalle Valo 	u64 rx_dupl_frame;
444bdcd8170SKalle Valo 
445bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
446bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
447bdcd8170SKalle Valo 	u64 tkip_replays;
448bdcd8170SKalle Valo 	u64 tkip_fmt_err;
449bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
450bdcd8170SKalle Valo 	u64 ccmp_replays;
451bdcd8170SKalle Valo 
452bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
453bdcd8170SKalle Valo 
454bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
455bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
456bdcd8170SKalle Valo 	u64 cs_connect_cnt;
457bdcd8170SKalle Valo 	u64 cs_discon_cnt;
458bdcd8170SKalle Valo 
459bdcd8170SKalle Valo 	s32 tx_ucast_rate;
460bdcd8170SKalle Valo 	s32 rx_ucast_rate;
461bdcd8170SKalle Valo 
462bdcd8170SKalle Valo 	u32 lq_val;
463bdcd8170SKalle Valo 
464bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
465bdcd8170SKalle Valo 	u16 wow_evt_discarded;
466bdcd8170SKalle Valo 
467bdcd8170SKalle Valo 	s16 noise_floor_calib;
468bdcd8170SKalle Valo 	s16 cs_rssi;
469bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
470bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
471bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
472bdcd8170SKalle Valo 	u8 cs_snr;
473bdcd8170SKalle Valo 
474bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
475bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
476bdcd8170SKalle Valo 
477bdcd8170SKalle Valo 	u32 arp_received;
478bdcd8170SKalle Valo 	u32 arp_matched;
479bdcd8170SKalle Valo 	u32 arp_replied;
480bdcd8170SKalle Valo };
481bdcd8170SKalle Valo 
482bdcd8170SKalle Valo struct ath6kl_mbox_info {
483bdcd8170SKalle Valo 	u32 htc_addr;
484bdcd8170SKalle Valo 	u32 htc_ext_addr;
485bdcd8170SKalle Valo 	u32 htc_ext_sz;
486bdcd8170SKalle Valo 
487bdcd8170SKalle Valo 	u32 block_size;
488bdcd8170SKalle Valo 
489bdcd8170SKalle Valo 	u32 gmbox_addr;
490bdcd8170SKalle Valo 
491bdcd8170SKalle Valo 	u32 gmbox_sz;
492bdcd8170SKalle Valo };
493bdcd8170SKalle Valo 
494bdcd8170SKalle Valo /*
495bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
496bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
497bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
498bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
499bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
500bdcd8170SKalle Valo  */
501bdcd8170SKalle Valo 
502bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
503bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
504bdcd8170SKalle Valo 
505bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
506bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
507bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
508bdcd8170SKalle Valo 
5099a5b1318SJouni Malinen /* Initial group key for AP mode */
510bdcd8170SKalle Valo struct ath6kl_req_key {
5119a5b1318SJouni Malinen 	bool valid;
5129a5b1318SJouni Malinen 	u8 key_index;
5139a5b1318SJouni Malinen 	int key_type;
5149a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
5159a5b1318SJouni Malinen 	u8 key_len;
516bdcd8170SKalle Valo };
517bdcd8170SKalle Valo 
51877eab1e9SKalle Valo enum ath6kl_hif_type {
51977eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
52077eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
52177eab1e9SKalle Valo };
52277eab1e9SKalle Valo 
523e76ac2bfSKalle Valo enum ath6kl_htc_type {
524e76ac2bfSKalle Valo 	ATH6KL_HTC_TYPE_MBOX,
525636f8288SKalle Valo 	ATH6KL_HTC_TYPE_PIPE,
526e76ac2bfSKalle Valo };
527e76ac2bfSKalle Valo 
52880abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
52980abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
53080abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
53180abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
53280abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
53380abaf9bSVasanthakumar Thiagarajan };
53480abaf9bSVasanthakumar Thiagarajan 
535df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap {
536df90b369SVasanthakumar Thiagarajan 	bool ht_enable;
537df90b369SVasanthakumar Thiagarajan 	u8 ampdu_factor;
538df90b369SVasanthakumar Thiagarajan 	unsigned short cap_info;
539df90b369SVasanthakumar Thiagarajan };
540df90b369SVasanthakumar Thiagarajan 
54171f96ee6SKalle Valo /*
54271f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
54371f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
54471f96ee6SKalle Valo  */
545b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
546334234b5SVasanthakumar Thiagarajan 
54759c98449SVasanthakumar Thiagarajan /* vif flags info */
54859c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
54959c98449SVasanthakumar Thiagarajan 	CONNECTED,
55059c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
55159c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
55259c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
55359c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
55459c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
55559c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
55659c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
55759c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
558b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
559081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
5606251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_ON,
5616251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_OFF,
562b1f47e3aSThomas Pedersen 	SCHED_SCANNING,
56359c98449SVasanthakumar Thiagarajan };
56459c98449SVasanthakumar Thiagarajan 
565108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
566990bd915SVasanthakumar Thiagarajan 	struct list_head list;
567108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
568108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
569108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
570478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
571478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
572334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
57359c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5743450334fSVasanthakumar Thiagarajan 	int ssid_len;
5753450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5763450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5773450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5783450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5793450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5803450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5813450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5823450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
583f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
584f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5858c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5868c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
587f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
588f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5896f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5906f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5912132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
59267b3f129SKiran Reddy 	struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
59310509f90SKalle Valo 
594de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
59510509f90SKalle Valo 	struct timer_list sched_scan_timer;
59610509f90SKalle Valo 
59714ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
59814ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
599cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
6001052261eSJouni Malinen 	u32 last_roc_id;
6011052261eSJouni Malinen 	u32 last_cancel_roc_id;
602cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
603cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
604cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
6058f46fccdSRaja Mani 	u16 listen_intvl_t;
606ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
607279b2862SThomas Pedersen 	u32 txe_intvl;
608eb38987eSRaja Mani 	u16 bg_scan_period;
609cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
610b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
611b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
612c4f7863eSThomas Pedersen 	struct wmi_connect_cmd profile;
613f21243a8SThomas Pedersen 	u16 rsn_capab;
61480abaf9bSVasanthakumar Thiagarajan 
61580abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
616108438bcSVasanthakumar Thiagarajan };
617108438bcSVasanthakumar Thiagarajan 
61871bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
61971bbc994SJohannes Berg {
62071bbc994SJohannes Berg 	return container_of(wdev, struct ath6kl_vif, wdev);
62171bbc994SJohannes Berg }
62271bbc994SJohannes Berg 
6236cb3c714SRaja Mani #define WOW_LIST_ID		0
6246cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
6256cb3c714SRaja Mani 
62610509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
62710509f90SKalle Valo 
628bdcd8170SKalle Valo /* Flag info */
62959c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
63059c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
63159c98449SVasanthakumar Thiagarajan 	WMI_READY,
63259c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
63359c98449SVasanthakumar Thiagarajan 	TESTMODE,
63459c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
63559c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
63659c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
6375fe4dffbSKalle Valo 	FIRST_BOOT,
63859c98449SVasanthakumar Thiagarajan };
639bdcd8170SKalle Valo 
64076a9fbe2SKalle Valo enum ath6kl_state {
64176a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
64276a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
643390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
644390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
64576a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
646b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
647dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
64884caf800SVasanthakumar Thiagarajan 	ATH6KL_STATE_RECOVERY,
64984caf800SVasanthakumar Thiagarajan };
65084caf800SVasanthakumar Thiagarajan 
65184caf800SVasanthakumar Thiagarajan /* Fw error recovery */
65284caf800SVasanthakumar Thiagarajan enum ath6kl_fw_err {
65384caf800SVasanthakumar Thiagarajan 	ATH6KL_FW_ASSERT,
65476a9fbe2SKalle Valo };
65576a9fbe2SKalle Valo 
656bdcd8170SKalle Valo struct ath6kl {
657bdcd8170SKalle Valo 	struct device *dev;
658be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
65976a9fbe2SKalle Valo 
66076a9fbe2SKalle Valo 	enum ath6kl_state state;
6615f1127ffSKalle Valo 	unsigned int testmode;
66276a9fbe2SKalle Valo 
663bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
664bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
665e76ac2bfSKalle Valo 	const struct ath6kl_htc_ops *htc_ops;
666bdcd8170SKalle Valo 	struct wmi *wmi;
667bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
668bdcd8170SKalle Valo 	int total_tx_data_pend;
669bdcd8170SKalle Valo 	struct htc_target *htc_target;
67077eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
671bdcd8170SKalle Valo 	void *hif_priv;
672990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
673990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
674990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
67555055976SVasanthakumar Thiagarajan 	u8 num_vif;
676368b1b0fSKalle Valo 	unsigned int vif_max;
6773226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
67855055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
67912eb9444SKalle Valo 
68012eb9444SKalle Valo 	/*
68112eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
68212eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
68312eb9444SKalle Valo 	 */
684bdcd8170SKalle Valo 	spinlock_t lock;
68512eb9444SKalle Valo 
686bdcd8170SKalle Valo 	struct semaphore sem;
687e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
688bdcd8170SKalle Valo 	struct ath6kl_version version;
689bdcd8170SKalle Valo 	u32 target_type;
690bdcd8170SKalle Valo 	u8 tx_pwr;
691bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
692bdcd8170SKalle Valo 	u8 ibss_ps_enable;
69355055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
694bdcd8170SKalle Valo 	u8 node_num;
695bdcd8170SKalle Valo 	u8 next_ep_id;
696bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
697bdcd8170SKalle Valo 	u32 cookie_count;
698bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
699bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
700bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
701bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
702bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
703bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
7043c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
705bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
706bdcd8170SKalle Valo 	u32 user_key_ctrl;
707bdcd8170SKalle Valo 	u8 usr_bss_filter;
708bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
709bdcd8170SKalle Valo 	u8 sta_list_index;
710bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
711bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
712c4f7863eSThomas Pedersen 	u32 want_ch_switch;
713b5495e66SThomas Pedersen 	u16 last_ch;
71412eb9444SKalle Valo 
71512eb9444SKalle Valo 	/*
71612eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
71712eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
71812eb9444SKalle Valo 	 */
719bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
72012eb9444SKalle Valo 
721bdcd8170SKalle Valo 	u8 intra_bss;
722bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
723bdcd8170SKalle Valo 	u8 ap_country_code[3];
724bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
725bdcd8170SKalle Valo 	u8 rx_meta_ver;
726bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
727d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
728bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
729003353b0SKalle Valo 	struct {
730003353b0SKalle Valo 		void *rx_report;
731003353b0SKalle Valo 		size_t rx_report_len;
732003353b0SKalle Valo 	} tm;
733003353b0SKalle Valo 
734856f4b31SKalle Valo 	struct ath6kl_hw {
735856f4b31SKalle Valo 		u32 id;
736293badf4SKalle Valo 		const char *name;
737a01ac414SKalle Valo 		u32 dataset_patch_addr;
738a01ac414SKalle Valo 		u32 app_load_addr;
739a01ac414SKalle Valo 		u32 app_start_override_addr;
740991b27eaSKalle Valo 		u32 board_ext_data_addr;
741991b27eaSKalle Valo 		u32 reserved_ram_size;
7420d4d72bfSKalle Valo 		u32 board_addr;
74339586bf2SRyan Hsu 		u32 refclk_hz;
74439586bf2SRyan Hsu 		u32 uarttx_pin;
745cd23c1c9SAlex Yang 		u32 testscript_addr;
746d92917e4SThomas Pedersen 		enum wmi_phy_cap cap;
747d1a9421dSKalle Valo 
74806e360acSBala Shanmugam 		u32 flags;
74906e360acSBala Shanmugam 
750c0038972SKalle Valo 		struct ath6kl_hw_fw {
751c0038972SKalle Valo 			const char *dir;
752c0038972SKalle Valo 			const char *otp;
753d1a9421dSKalle Valo 			const char *fw;
754c0038972SKalle Valo 			const char *tcmd;
755c0038972SKalle Valo 			const char *patch;
756cd23c1c9SAlex Yang 			const char *utf;
757cd23c1c9SAlex Yang 			const char *testscript;
758c0038972SKalle Valo 		} fw;
759c0038972SKalle Valo 
760d1a9421dSKalle Valo 		const char *fw_board;
761d1a9421dSKalle Valo 		const char *fw_default_board;
762a01ac414SKalle Valo 	} hw;
763a01ac414SKalle Valo 
764bdcd8170SKalle Valo 	u16 conf_flags;
765e390af77SRaja Mani 	u16 suspend_mode;
7661e9a905dSRaja Mani 	u16 wow_suspend_mode;
767bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
768bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
769bdcd8170SKalle Valo 
770bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
771bdcd8170SKalle Valo 	unsigned long flag;
772bdcd8170SKalle Valo 
773bdcd8170SKalle Valo 	u8 *fw_board;
774bdcd8170SKalle Valo 	size_t fw_board_len;
775bdcd8170SKalle Valo 
776bdcd8170SKalle Valo 	u8 *fw_otp;
777bdcd8170SKalle Valo 	size_t fw_otp_len;
778bdcd8170SKalle Valo 
779bdcd8170SKalle Valo 	u8 *fw;
780bdcd8170SKalle Valo 	size_t fw_len;
781bdcd8170SKalle Valo 
782bdcd8170SKalle Valo 	u8 *fw_patch;
783bdcd8170SKalle Valo 	size_t fw_patch_len;
784bdcd8170SKalle Valo 
785cd23c1c9SAlex Yang 	u8 *fw_testscript;
786cd23c1c9SAlex Yang 	size_t fw_testscript_len;
787cd23c1c9SAlex Yang 
78865a8b4ccSKalle Valo 	unsigned int fw_api;
78997e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
79097e0496dSKalle Valo 
791bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7927c3075e9SVasanthakumar Thiagarajan 
793d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7946a7c9badSJouni Malinen 
7956bbc7c35SJouni Malinen 	bool p2p;
7966bbc7c35SJouni Malinen 
797e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
798e5348a1eSVasanthakumar Thiagarajan 
79984caf800SVasanthakumar Thiagarajan 	struct ath6kl_fw_recovery {
80084caf800SVasanthakumar Thiagarajan 		bool enable;
80184caf800SVasanthakumar Thiagarajan 		struct work_struct recovery_work;
80284caf800SVasanthakumar Thiagarajan 		unsigned long err_reason;
80384caf800SVasanthakumar Thiagarajan 	} fw_recovery;
80484caf800SVasanthakumar Thiagarajan 
805bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
806bdf5396bSKalle Valo 	struct {
8079b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
808c807b30dSKalle Valo 		struct completion fwlog_completion;
809c807b30dSKalle Valo 		bool fwlog_open;
810c807b30dSKalle Valo 
811939f1cceSKalle Valo 		u32 fwlog_mask;
8129b9a4f2aSKalle Valo 
81391d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
814252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
815252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
8169a730834SKalle Valo 
8179a730834SKalle Valo 		struct {
8189a730834SKalle Valo 			unsigned int invalid_rate;
8199a730834SKalle Valo 		} war_stats;
8204b28a80dSJouni Malinen 
8214b28a80dSJouni Malinen 		u8 *roam_tbl;
8224b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
823ff0b0075SJouni Malinen 
824ff0b0075SJouni Malinen 		u8 keepalive;
825ff0b0075SJouni Malinen 		u8 disc_timeout;
826bdf5396bSKalle Valo 	} debug;
827bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
828bdcd8170SKalle Valo };
829bdcd8170SKalle Valo 
830d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
831bdcd8170SKalle Valo {
832108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
833bdcd8170SKalle Valo }
834bdcd8170SKalle Valo 
835bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
836bc07ddb2SKalle Valo 					  u32 item_offset)
837bc07ddb2SKalle Valo {
838bc07ddb2SKalle Valo 	u32 addr = 0;
839bc07ddb2SKalle Valo 
840bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
841bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
842bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
843bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
844bc07ddb2SKalle Valo 
845bc07ddb2SKalle Valo 	return addr;
846bc07ddb2SKalle Valo }
847bc07ddb2SKalle Valo 
848bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
849bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
850bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
851bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
852bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
853bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
854bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
85563de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
85663de1112SKalle Valo 			struct list_head *packet_queue);
857bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
858bdcd8170SKalle Valo 					       struct htc_packet *packet);
859bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
860bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
861f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
862addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
863addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
864addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
865bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
866e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
867bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
868bdcd8170SKalle Valo 
869bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
870bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
871bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
872bdcd8170SKalle Valo 
8737baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
874c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
875c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
876bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
877bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
878bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
879bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
880bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
881bdcd8170SKalle Valo 					    int len);
882bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
8831d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
884bdcd8170SKalle Valo 
8856765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
886bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
887bdcd8170SKalle Valo 
888d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
889d92917e4SThomas Pedersen 			enum wmi_phy_cap cap);
890bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
891bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
892240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
893bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
894bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
895bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
896bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
897240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
898240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
899572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
900c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
901240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
902bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
903bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
904240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
905bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
906240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
907240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
908bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
909bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
910bdcd8170SKalle Valo 
911240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
912bdcd8170SKalle Valo 
913240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
914240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
915240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
916240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
917bdcd8170SKalle Valo 			     u8 win_sz);
918bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
919bdcd8170SKalle Valo 
9206db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
9216db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
922e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
923990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
92455055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
9255fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
9265fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
92745eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
92845eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
92945eaa78fSKalle Valo 
930a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
9315fe4dffbSKalle Valo 
932636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
933636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
934636f8288SKalle Valo 
93545eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
936e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
93745eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
93845eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
93945eaa78fSKalle Valo 
94084caf800SVasanthakumar Thiagarajan /* Fw error recovery */
94184caf800SVasanthakumar Thiagarajan void ath6kl_init_hw_restart(struct ath6kl *ar);
94284caf800SVasanthakumar Thiagarajan void ath6kl_recovery_err_notify(struct ath6kl *ar, enum ath6kl_fw_err reason);
94384caf800SVasanthakumar Thiagarajan void ath6kl_recovery_init(struct ath6kl *ar);
94484caf800SVasanthakumar Thiagarajan void ath6kl_recovery_cleanup(struct ath6kl *ar);
94584caf800SVasanthakumar Thiagarajan void ath6kl_recovery_suspend(struct ath6kl *ar);
946bdcd8170SKalle Valo #endif /* CORE_H */
947