1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
100d97c121bSVasanthakumar Thiagarajan 	/* Firmware has support to override rsn cap of rsn ie */
101d97c121bSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102d97c121bSVasanthakumar Thiagarajan 
1036821d4f0SNaveen Gangadharan 	/*
1046821d4f0SNaveen Gangadharan 	 * Multicast support in WOW and host awake mode.
1056821d4f0SNaveen Gangadharan 	 * Allow all multicast in host awake mode.
1066821d4f0SNaveen Gangadharan 	 * Apply multicast filter in WOW mode.
1076821d4f0SNaveen Gangadharan 	 */
1086821d4f0SNaveen Gangadharan 	ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
1096821d4f0SNaveen Gangadharan 
110c422d52dSThomas Pedersen 	/* Firmware supports enhanced bmiss detection */
111c422d52dSThomas Pedersen 	ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
112c422d52dSThomas Pedersen 
113dd45b759SNaveen Singh 	/*
114dd45b759SNaveen Singh 	 * FW supports matching of ssid in schedule scan
115dd45b759SNaveen Singh 	 */
116dd45b759SNaveen Singh 	ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
117dd45b759SNaveen Singh 
11885b20fc2SThomas Pedersen 	/* Firmware supports filtering BSS results by RSSI */
11985b20fc2SThomas Pedersen 	ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
12085b20fc2SThomas Pedersen 
121c95dcb59SAarthi Thiruvengadam 	/* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */
122c95dcb59SAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
123c95dcb59SAarthi Thiruvengadam 
124279b2862SThomas Pedersen 	/* Firmware supports TX error rate notification */
125279b2862SThomas Pedersen 	ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY,
126279b2862SThomas Pedersen 
12784841ba2SKalle Valo 	/* supports WMI_SET_REGDOMAIN_CMDID command */
12884841ba2SKalle Valo 	ATH6KL_FW_CAPABILITY_REGDOMAIN,
12984841ba2SKalle Valo 
13097e0496dSKalle Valo 	/* this needs to be last */
13197e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
13297e0496dSKalle Valo };
13397e0496dSKalle Valo 
13497e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
13597e0496dSKalle Valo 
13650d41234SKalle Valo struct ath6kl_fw_ie {
13750d41234SKalle Valo 	__le32 id;
13850d41234SKalle Valo 	__le32 len;
13950d41234SKalle Valo 	u8 data[0];
14050d41234SKalle Valo };
14150d41234SKalle Valo 
14206e360acSBala Shanmugam enum ath6kl_hw_flags {
14306e360acSBala Shanmugam 	ATH6KL_HW_FLAG_64BIT_RATES	= BIT(0),
14406e360acSBala Shanmugam };
14506e360acSBala Shanmugam 
146c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
14765a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
148c0038972SKalle Valo 
149bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1500d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
151bdcd8170SKalle Valo 
152bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1530d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1540d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
155c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
156c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
157c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
158c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
159c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1602023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
1610d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1622023dbb8STim Gardner 			AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
163bdcd8170SKalle Valo 
164bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1650d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
166c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
167c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
168c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
169c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
170cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
171cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
172c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1732023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
1740d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
1752023dbb8STim Gardner 			AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
176bdcd8170SKalle Valo 
17731024d99SKevin Fang /* AR6004 1.0 definitions */
1780d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
179c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
180c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1812023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE         AR6004_HW_1_0_FW_DIR "/bdata.bin"
1820d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
1832023dbb8STim Gardner 	AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
184d5720e59SKalle Valo 
185d5720e59SKalle Valo /* AR6004 1.1 definitions */
1860d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
187c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
188c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1892023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE         AR6004_HW_1_1_FW_DIR "/bdata.bin"
1900d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
1912023dbb8STim Gardner 	AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
19231024d99SKevin Fang 
1936146ca69SRay Chen /* AR6004 1.2 definitions */
1946146ca69SRay Chen #define AR6004_HW_1_2_VERSION                 0x300007e8
1956146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR			"ath6k/AR6004/hw1.2"
1966146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE           "fw.ram.bin"
1972023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE         AR6004_HW_1_2_FW_DIR "/bdata.bin"
1986146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
1992023dbb8STim Gardner 	AR6004_HW_1_2_FW_DIR "/bdata.bin"
2006146ca69SRay Chen 
201bf744f11SBala Shanmugam /* AR6004 1.3 definitions */
202bf744f11SBala Shanmugam #define AR6004_HW_1_3_VERSION			0x31c8088a
203bf744f11SBala Shanmugam #define AR6004_HW_1_3_FW_DIR			"ath6k/AR6004/hw1.3"
204bf744f11SBala Shanmugam #define AR6004_HW_1_3_FIRMWARE_FILE		"fw.ram.bin"
205bf744f11SBala Shanmugam #define AR6004_HW_1_3_BOARD_DATA_FILE		"ath6k/AR6004/hw1.3/bdata.bin"
206bf744f11SBala Shanmugam #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE	"ath6k/AR6004/hw1.3/bdata.bin"
207bf744f11SBala Shanmugam 
208bdcd8170SKalle Valo /* Per STA data, used in AP mode */
209bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
210bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
211bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
212c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
213c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
214bdcd8170SKalle Valo 
215bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
216bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
217bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
218bdcd8170SKalle Valo 
219bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
220bdcd8170SKalle Valo 
221bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
222bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
223bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
224bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
225bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
226bdcd8170SKalle Valo 
227bdcd8170SKalle Valo #define NUM_OF_TIDS         8
228bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
229bdcd8170SKalle Valo 
230bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
231bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
232bdcd8170SKalle Valo 
233bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
234bdcd8170SKalle Valo 
235bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
236bdcd8170SKalle Valo 
2377940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT     100	/* in ms */
238bdcd8170SKalle Valo 
239bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
240bdcd8170SKalle Valo 
241bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
242bdcd8170SKalle Valo 
2438f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
244ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
245ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
246ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
2478f46fccdSRaja Mani 
248bdcd8170SKalle Valo /* configuration lags */
249bdcd8170SKalle Valo /*
250bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
251bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
252bdcd8170SKalle Valo  * sending (Re)Assoc req.
253bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
254bdcd8170SKalle Valo  * module state transition failure events which happen during
255bdcd8170SKalle Valo  * scan, to the host.
256bdcd8170SKalle Valo  */
257bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
258bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
259bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
260bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
261e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
262bdcd8170SKalle Valo 
263c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
264c86e4f44SAarthi Thiruvengadam 
265bdcd8170SKalle Valo enum wlan_low_pwr_state {
266bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
267bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
268bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
269bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
270bdcd8170SKalle Valo };
271bdcd8170SKalle Valo 
272bdcd8170SKalle Valo enum sme_state {
273bdcd8170SKalle Valo 	SME_DISCONNECTED,
274bdcd8170SKalle Valo 	SME_CONNECTING,
275bdcd8170SKalle Valo 	SME_CONNECTED
276bdcd8170SKalle Valo };
277bdcd8170SKalle Valo 
278bdcd8170SKalle Valo struct skb_hold_q {
279bdcd8170SKalle Valo 	struct sk_buff *skb;
280bdcd8170SKalle Valo 	bool is_amsdu;
281bdcd8170SKalle Valo 	u16 seq_no;
282bdcd8170SKalle Valo };
283bdcd8170SKalle Valo 
284bdcd8170SKalle Valo struct rxtid {
285bdcd8170SKalle Valo 	bool aggr;
286bdcd8170SKalle Valo 	bool timer_mon;
287bdcd8170SKalle Valo 	u16 win_sz;
288bdcd8170SKalle Valo 	u16 seq_next;
289bdcd8170SKalle Valo 	u32 hold_q_sz;
290bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
291bdcd8170SKalle Valo 	struct sk_buff_head q;
29212eb9444SKalle Valo 
29312eb9444SKalle Valo 	/*
2940faf7458SVasanthakumar Thiagarajan 	 * lock mainly protects seq_next and hold_q. Movement of seq_next
2950faf7458SVasanthakumar Thiagarajan 	 * needs to be protected between aggr_timeout() and
2960faf7458SVasanthakumar Thiagarajan 	 * aggr_process_recv_frm(). hold_q will be holding the pending
2970faf7458SVasanthakumar Thiagarajan 	 * reorder frames and it's access should also be protected.
2980faf7458SVasanthakumar Thiagarajan 	 * Some of the other fields like hold_q_sz, win_sz and aggr are
2990faf7458SVasanthakumar Thiagarajan 	 * initialized/reset when receiving addba/delba req, also while
3000faf7458SVasanthakumar Thiagarajan 	 * deleting aggr state all the pending buffers are flushed before
3010faf7458SVasanthakumar Thiagarajan 	 * resetting these fields, so there should not be any race in accessing
3020faf7458SVasanthakumar Thiagarajan 	 * these fields.
30312eb9444SKalle Valo 	 */
304bdcd8170SKalle Valo 	spinlock_t lock;
305bdcd8170SKalle Valo };
306bdcd8170SKalle Valo 
307bdcd8170SKalle Valo struct rxtid_stats {
308bdcd8170SKalle Valo 	u32 num_into_aggr;
309bdcd8170SKalle Valo 	u32 num_dups;
310bdcd8170SKalle Valo 	u32 num_oow;
311bdcd8170SKalle Valo 	u32 num_mpdu;
312bdcd8170SKalle Valo 	u32 num_amsdu;
313bdcd8170SKalle Valo 	u32 num_delivered;
314bdcd8170SKalle Valo 	u32 num_timeouts;
315bdcd8170SKalle Valo 	u32 num_hole;
316bdcd8170SKalle Valo 	u32 num_bar;
317bdcd8170SKalle Valo };
318bdcd8170SKalle Valo 
3197baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
320bdcd8170SKalle Valo 	u8 aggr_sz;
321bdcd8170SKalle Valo 	u8 timer_scheduled;
322bdcd8170SKalle Valo 	struct timer_list timer;
323bdcd8170SKalle Valo 	struct net_device *dev;
324bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
325bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
3267baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
3277baef812SVasanthakumar Thiagarajan };
3287baef812SVasanthakumar Thiagarajan 
3297baef812SVasanthakumar Thiagarajan struct aggr_info {
3307baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
3317baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
332bdcd8170SKalle Valo };
333bdcd8170SKalle Valo 
334bdcd8170SKalle Valo struct ath6kl_wep_key {
335bdcd8170SKalle Valo 	u8 key_index;
336bdcd8170SKalle Valo 	u8 key_len;
337bdcd8170SKalle Valo 	u8 key[64];
338bdcd8170SKalle Valo };
339bdcd8170SKalle Valo 
340bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
341bdcd8170SKalle Valo 
342bdcd8170SKalle Valo struct ath6kl_key {
343bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
344bdcd8170SKalle Valo 	u8 key_len;
345bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
346bdcd8170SKalle Valo 	u8 seq_len;
347bdcd8170SKalle Valo 	u32 cipher;
348bdcd8170SKalle Valo };
349bdcd8170SKalle Valo 
350bdcd8170SKalle Valo struct ath6kl_node_mapping {
351bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
352bdcd8170SKalle Valo 	u8 ep_id;
353bdcd8170SKalle Valo 	u8 tx_pend;
354bdcd8170SKalle Valo };
355bdcd8170SKalle Valo 
356bdcd8170SKalle Valo struct ath6kl_cookie {
357bdcd8170SKalle Valo 	struct sk_buff *skb;
358bdcd8170SKalle Valo 	u32 map_no;
359bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
360bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
361bdcd8170SKalle Valo };
362bdcd8170SKalle Valo 
363d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
364d0ff7383SNaveen Gangadharan 	struct list_head list;
365d0ff7383SNaveen Gangadharan 	u32 freq;
366d0ff7383SNaveen Gangadharan 	u32 wait;
367d0ff7383SNaveen Gangadharan 	u32 id;
368d0ff7383SNaveen Gangadharan 	bool no_cck;
369d0ff7383SNaveen Gangadharan 	size_t len;
370d0ff7383SNaveen Gangadharan 	u8 buf[0];
371d0ff7383SNaveen Gangadharan };
372d0ff7383SNaveen Gangadharan 
373bdcd8170SKalle Valo struct ath6kl_sta {
374bdcd8170SKalle Valo 	u16 sta_flags;
375bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
376bdcd8170SKalle Valo 	u8 aid;
377bdcd8170SKalle Valo 	u8 keymgmt;
378bdcd8170SKalle Valo 	u8 ucipher;
379bdcd8170SKalle Valo 	u8 auth;
380bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
381bdcd8170SKalle Valo 	struct sk_buff_head psq;
38212eb9444SKalle Valo 
38312eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
384bdcd8170SKalle Valo 	spinlock_t psq_lock;
38512eb9444SKalle Valo 
386d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
387d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
388c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
389c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3901d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
391bdcd8170SKalle Valo };
392bdcd8170SKalle Valo 
393bdcd8170SKalle Valo struct ath6kl_version {
394bdcd8170SKalle Valo 	u32 target_ver;
395bdcd8170SKalle Valo 	u32 wlan_ver;
396bdcd8170SKalle Valo 	u32 abi_ver;
397bdcd8170SKalle Valo };
398bdcd8170SKalle Valo 
399bdcd8170SKalle Valo struct ath6kl_bmi {
400bdcd8170SKalle Valo 	u32 cmd_credits;
401bdcd8170SKalle Valo 	bool done_sent;
402bdcd8170SKalle Valo 	u8 *cmd_buf;
4031f4c894dSKalle Valo 	u32 max_data_size;
4041f4c894dSKalle Valo 	u32 max_cmd_size;
405bdcd8170SKalle Valo };
406bdcd8170SKalle Valo 
407bdcd8170SKalle Valo struct target_stats {
408bdcd8170SKalle Valo 	u64 tx_pkt;
409bdcd8170SKalle Valo 	u64 tx_byte;
410bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
411bdcd8170SKalle Valo 	u64 tx_ucast_byte;
412bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
413bdcd8170SKalle Valo 	u64 tx_mcast_byte;
414bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
415bdcd8170SKalle Valo 	u64 tx_bcast_byte;
416bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
417bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
418bdcd8170SKalle Valo 
419bdcd8170SKalle Valo 	u64 tx_err;
420bdcd8170SKalle Valo 	u64 tx_fail_cnt;
421bdcd8170SKalle Valo 	u64 tx_retry_cnt;
422bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
423bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
424bdcd8170SKalle Valo 
425bdcd8170SKalle Valo 	u64 rx_pkt;
426bdcd8170SKalle Valo 	u64 rx_byte;
427bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
428bdcd8170SKalle Valo 	u64 rx_ucast_byte;
429bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
430bdcd8170SKalle Valo 	u64 rx_mcast_byte;
431bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
432bdcd8170SKalle Valo 	u64 rx_bcast_byte;
433bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
434bdcd8170SKalle Valo 
435bdcd8170SKalle Valo 	u64 rx_err;
436bdcd8170SKalle Valo 	u64 rx_crc_err;
437bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
438bdcd8170SKalle Valo 	u64 rx_decrypt_err;
439bdcd8170SKalle Valo 	u64 rx_dupl_frame;
440bdcd8170SKalle Valo 
441bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
442bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
443bdcd8170SKalle Valo 	u64 tkip_replays;
444bdcd8170SKalle Valo 	u64 tkip_fmt_err;
445bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
446bdcd8170SKalle Valo 	u64 ccmp_replays;
447bdcd8170SKalle Valo 
448bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
449bdcd8170SKalle Valo 
450bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
451bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
452bdcd8170SKalle Valo 	u64 cs_connect_cnt;
453bdcd8170SKalle Valo 	u64 cs_discon_cnt;
454bdcd8170SKalle Valo 
455bdcd8170SKalle Valo 	s32 tx_ucast_rate;
456bdcd8170SKalle Valo 	s32 rx_ucast_rate;
457bdcd8170SKalle Valo 
458bdcd8170SKalle Valo 	u32 lq_val;
459bdcd8170SKalle Valo 
460bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
461bdcd8170SKalle Valo 	u16 wow_evt_discarded;
462bdcd8170SKalle Valo 
463bdcd8170SKalle Valo 	s16 noise_floor_calib;
464bdcd8170SKalle Valo 	s16 cs_rssi;
465bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
466bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
467bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
468bdcd8170SKalle Valo 	u8 cs_snr;
469bdcd8170SKalle Valo 
470bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
471bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
472bdcd8170SKalle Valo 
473bdcd8170SKalle Valo 	u32 arp_received;
474bdcd8170SKalle Valo 	u32 arp_matched;
475bdcd8170SKalle Valo 	u32 arp_replied;
476bdcd8170SKalle Valo };
477bdcd8170SKalle Valo 
478bdcd8170SKalle Valo struct ath6kl_mbox_info {
479bdcd8170SKalle Valo 	u32 htc_addr;
480bdcd8170SKalle Valo 	u32 htc_ext_addr;
481bdcd8170SKalle Valo 	u32 htc_ext_sz;
482bdcd8170SKalle Valo 
483bdcd8170SKalle Valo 	u32 block_size;
484bdcd8170SKalle Valo 
485bdcd8170SKalle Valo 	u32 gmbox_addr;
486bdcd8170SKalle Valo 
487bdcd8170SKalle Valo 	u32 gmbox_sz;
488bdcd8170SKalle Valo };
489bdcd8170SKalle Valo 
490bdcd8170SKalle Valo /*
491bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
492bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
493bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
494bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
495bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
496bdcd8170SKalle Valo  */
497bdcd8170SKalle Valo 
498bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
499bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
500bdcd8170SKalle Valo 
501bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
502bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
503bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
504bdcd8170SKalle Valo 
5059a5b1318SJouni Malinen /* Initial group key for AP mode */
506bdcd8170SKalle Valo struct ath6kl_req_key {
5079a5b1318SJouni Malinen 	bool valid;
5089a5b1318SJouni Malinen 	u8 key_index;
5099a5b1318SJouni Malinen 	int key_type;
5109a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
5119a5b1318SJouni Malinen 	u8 key_len;
512bdcd8170SKalle Valo };
513bdcd8170SKalle Valo 
51477eab1e9SKalle Valo enum ath6kl_hif_type {
51577eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
51677eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
51777eab1e9SKalle Valo };
51877eab1e9SKalle Valo 
519e76ac2bfSKalle Valo enum ath6kl_htc_type {
520e76ac2bfSKalle Valo 	ATH6KL_HTC_TYPE_MBOX,
521636f8288SKalle Valo 	ATH6KL_HTC_TYPE_PIPE,
522e76ac2bfSKalle Valo };
523e76ac2bfSKalle Valo 
52480abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
52580abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
52680abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
52780abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
52880abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
52980abaf9bSVasanthakumar Thiagarajan };
53080abaf9bSVasanthakumar Thiagarajan 
531df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap {
532df90b369SVasanthakumar Thiagarajan 	bool ht_enable;
533df90b369SVasanthakumar Thiagarajan 	u8 ampdu_factor;
534df90b369SVasanthakumar Thiagarajan 	unsigned short cap_info;
535df90b369SVasanthakumar Thiagarajan };
536df90b369SVasanthakumar Thiagarajan 
53771f96ee6SKalle Valo /*
53871f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
53971f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
54071f96ee6SKalle Valo  */
541b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
542334234b5SVasanthakumar Thiagarajan 
54359c98449SVasanthakumar Thiagarajan /* vif flags info */
54459c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
54559c98449SVasanthakumar Thiagarajan 	CONNECTED,
54659c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
54759c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
54859c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
54959c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
55059c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
55159c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
55259c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
55359c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
554b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
555081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
5566251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_ON,
5576251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_OFF,
55859c98449SVasanthakumar Thiagarajan };
55959c98449SVasanthakumar Thiagarajan 
560108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
561990bd915SVasanthakumar Thiagarajan 	struct list_head list;
562108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
563108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
564108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
565478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
566478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
567334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
56859c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5693450334fSVasanthakumar Thiagarajan 	int ssid_len;
5703450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5713450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5723450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5733450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5743450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5753450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5763450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5773450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
578f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
579f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5808c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5818c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
582f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
583f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5846f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5856f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5862132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
58767b3f129SKiran Reddy 	struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
58810509f90SKalle Valo 
589de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
59010509f90SKalle Valo 	struct timer_list sched_scan_timer;
59110509f90SKalle Valo 
59214ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
59314ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
594cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
5951052261eSJouni Malinen 	u32 last_roc_id;
5961052261eSJouni Malinen 	u32 last_cancel_roc_id;
597cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
598cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
599cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
6008f46fccdSRaja Mani 	u16 listen_intvl_t;
601ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
602279b2862SThomas Pedersen 	u32 txe_intvl;
603eb38987eSRaja Mani 	u16 bg_scan_period;
604cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
605b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
606b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
607c4f7863eSThomas Pedersen 	struct wmi_connect_cmd profile;
60880abaf9bSVasanthakumar Thiagarajan 
60980abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
610108438bcSVasanthakumar Thiagarajan };
611108438bcSVasanthakumar Thiagarajan 
61271bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
61371bbc994SJohannes Berg {
61471bbc994SJohannes Berg 	return container_of(wdev, struct ath6kl_vif, wdev);
61571bbc994SJohannes Berg }
61671bbc994SJohannes Berg 
6176cb3c714SRaja Mani #define WOW_LIST_ID		0
6186cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
6196cb3c714SRaja Mani 
62010509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
62110509f90SKalle Valo 
622bdcd8170SKalle Valo /* Flag info */
62359c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
62459c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
62559c98449SVasanthakumar Thiagarajan 	WMI_READY,
62659c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
62759c98449SVasanthakumar Thiagarajan 	TESTMODE,
62859c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
62959c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
63059c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
6315fe4dffbSKalle Valo 	FIRST_BOOT,
63259c98449SVasanthakumar Thiagarajan };
633bdcd8170SKalle Valo 
63476a9fbe2SKalle Valo enum ath6kl_state {
63576a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
63676a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
637390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
638390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
63976a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
640b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
641dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
64210509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
64376a9fbe2SKalle Valo };
64476a9fbe2SKalle Valo 
645bdcd8170SKalle Valo struct ath6kl {
646bdcd8170SKalle Valo 	struct device *dev;
647be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
64876a9fbe2SKalle Valo 
64976a9fbe2SKalle Valo 	enum ath6kl_state state;
6505f1127ffSKalle Valo 	unsigned int testmode;
65176a9fbe2SKalle Valo 
652bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
653bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
654e76ac2bfSKalle Valo 	const struct ath6kl_htc_ops *htc_ops;
655bdcd8170SKalle Valo 	struct wmi *wmi;
656bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
657bdcd8170SKalle Valo 	int total_tx_data_pend;
658bdcd8170SKalle Valo 	struct htc_target *htc_target;
65977eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
660bdcd8170SKalle Valo 	void *hif_priv;
661990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
662990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
663990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
66455055976SVasanthakumar Thiagarajan 	u8 num_vif;
665368b1b0fSKalle Valo 	unsigned int vif_max;
6663226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
66755055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
66812eb9444SKalle Valo 
66912eb9444SKalle Valo 	/*
67012eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
67112eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
67212eb9444SKalle Valo 	 */
673bdcd8170SKalle Valo 	spinlock_t lock;
67412eb9444SKalle Valo 
675bdcd8170SKalle Valo 	struct semaphore sem;
676e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
677bdcd8170SKalle Valo 	struct ath6kl_version version;
678bdcd8170SKalle Valo 	u32 target_type;
679bdcd8170SKalle Valo 	u8 tx_pwr;
680bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
681bdcd8170SKalle Valo 	u8 ibss_ps_enable;
68255055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
683bdcd8170SKalle Valo 	u8 node_num;
684bdcd8170SKalle Valo 	u8 next_ep_id;
685bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
686bdcd8170SKalle Valo 	u32 cookie_count;
687bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
688bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
689bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
690bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
691bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
692bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
6933c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
694bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
695bdcd8170SKalle Valo 	u32 user_key_ctrl;
696bdcd8170SKalle Valo 	u8 usr_bss_filter;
697bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
698bdcd8170SKalle Valo 	u8 sta_list_index;
699bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
700bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
701c4f7863eSThomas Pedersen 	u32 want_ch_switch;
70212eb9444SKalle Valo 
70312eb9444SKalle Valo 	/*
70412eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
70512eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
70612eb9444SKalle Valo 	 */
707bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
70812eb9444SKalle Valo 
709bdcd8170SKalle Valo 	u8 intra_bss;
710bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
711bdcd8170SKalle Valo 	u8 ap_country_code[3];
712bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
713bdcd8170SKalle Valo 	u8 rx_meta_ver;
714bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
715d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
716bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
717003353b0SKalle Valo 	struct {
718003353b0SKalle Valo 		void *rx_report;
719003353b0SKalle Valo 		size_t rx_report_len;
720003353b0SKalle Valo 	} tm;
721003353b0SKalle Valo 
722856f4b31SKalle Valo 	struct ath6kl_hw {
723856f4b31SKalle Valo 		u32 id;
724293badf4SKalle Valo 		const char *name;
725a01ac414SKalle Valo 		u32 dataset_patch_addr;
726a01ac414SKalle Valo 		u32 app_load_addr;
727a01ac414SKalle Valo 		u32 app_start_override_addr;
728991b27eaSKalle Valo 		u32 board_ext_data_addr;
729991b27eaSKalle Valo 		u32 reserved_ram_size;
7300d4d72bfSKalle Valo 		u32 board_addr;
73139586bf2SRyan Hsu 		u32 refclk_hz;
73239586bf2SRyan Hsu 		u32 uarttx_pin;
733cd23c1c9SAlex Yang 		u32 testscript_addr;
734d92917e4SThomas Pedersen 		enum wmi_phy_cap cap;
735d1a9421dSKalle Valo 
73606e360acSBala Shanmugam 		u32 flags;
73706e360acSBala Shanmugam 
738c0038972SKalle Valo 		struct ath6kl_hw_fw {
739c0038972SKalle Valo 			const char *dir;
740c0038972SKalle Valo 			const char *otp;
741d1a9421dSKalle Valo 			const char *fw;
742c0038972SKalle Valo 			const char *tcmd;
743c0038972SKalle Valo 			const char *patch;
744cd23c1c9SAlex Yang 			const char *utf;
745cd23c1c9SAlex Yang 			const char *testscript;
746c0038972SKalle Valo 		} fw;
747c0038972SKalle Valo 
748d1a9421dSKalle Valo 		const char *fw_board;
749d1a9421dSKalle Valo 		const char *fw_default_board;
750a01ac414SKalle Valo 	} hw;
751a01ac414SKalle Valo 
752bdcd8170SKalle Valo 	u16 conf_flags;
753e390af77SRaja Mani 	u16 suspend_mode;
7541e9a905dSRaja Mani 	u16 wow_suspend_mode;
755bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
756bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
757bdcd8170SKalle Valo 
758bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
759bdcd8170SKalle Valo 	unsigned long flag;
760bdcd8170SKalle Valo 
761bdcd8170SKalle Valo 	u8 *fw_board;
762bdcd8170SKalle Valo 	size_t fw_board_len;
763bdcd8170SKalle Valo 
764bdcd8170SKalle Valo 	u8 *fw_otp;
765bdcd8170SKalle Valo 	size_t fw_otp_len;
766bdcd8170SKalle Valo 
767bdcd8170SKalle Valo 	u8 *fw;
768bdcd8170SKalle Valo 	size_t fw_len;
769bdcd8170SKalle Valo 
770bdcd8170SKalle Valo 	u8 *fw_patch;
771bdcd8170SKalle Valo 	size_t fw_patch_len;
772bdcd8170SKalle Valo 
773cd23c1c9SAlex Yang 	u8 *fw_testscript;
774cd23c1c9SAlex Yang 	size_t fw_testscript_len;
775cd23c1c9SAlex Yang 
77665a8b4ccSKalle Valo 	unsigned int fw_api;
77797e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
77897e0496dSKalle Valo 
779bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7807c3075e9SVasanthakumar Thiagarajan 
781d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7826a7c9badSJouni Malinen 
7836bbc7c35SJouni Malinen 	bool p2p;
7846bbc7c35SJouni Malinen 
785e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
786e5348a1eSVasanthakumar Thiagarajan 
787bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
788bdf5396bSKalle Valo 	struct {
7899b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
790c807b30dSKalle Valo 		struct completion fwlog_completion;
791c807b30dSKalle Valo 		bool fwlog_open;
792c807b30dSKalle Valo 
793939f1cceSKalle Valo 		u32 fwlog_mask;
7949b9a4f2aSKalle Valo 
79591d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
796252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
797252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
7989a730834SKalle Valo 
7999a730834SKalle Valo 		struct {
8009a730834SKalle Valo 			unsigned int invalid_rate;
8019a730834SKalle Valo 		} war_stats;
8024b28a80dSJouni Malinen 
8034b28a80dSJouni Malinen 		u8 *roam_tbl;
8044b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
805ff0b0075SJouni Malinen 
806ff0b0075SJouni Malinen 		u8 keepalive;
807ff0b0075SJouni Malinen 		u8 disc_timeout;
808bdf5396bSKalle Valo 	} debug;
809bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
810bdcd8170SKalle Valo };
811bdcd8170SKalle Valo 
812d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
813bdcd8170SKalle Valo {
814108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
815bdcd8170SKalle Valo }
816bdcd8170SKalle Valo 
817bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
818bc07ddb2SKalle Valo 					  u32 item_offset)
819bc07ddb2SKalle Valo {
820bc07ddb2SKalle Valo 	u32 addr = 0;
821bc07ddb2SKalle Valo 
822bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
823bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
824bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
825bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
826bc07ddb2SKalle Valo 
827bc07ddb2SKalle Valo 	return addr;
828bc07ddb2SKalle Valo }
829bc07ddb2SKalle Valo 
830bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
831bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
832bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
833bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
834bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
835bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
836bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
83763de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
83863de1112SKalle Valo 			struct list_head *packet_queue);
839bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
840bdcd8170SKalle Valo 					       struct htc_packet *packet);
841bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
842bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
843f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
844addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
845addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
846addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
847bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
848e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
849bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
850bdcd8170SKalle Valo 
851bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
852bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
853bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
854bdcd8170SKalle Valo 
8557baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
856c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
857c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
858bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
859bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
860bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
861bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
862bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
863bdcd8170SKalle Valo 					    int len);
864bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
8651d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
866bdcd8170SKalle Valo 
8676765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
868bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
869bdcd8170SKalle Valo 
870d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
871d92917e4SThomas Pedersen 			enum wmi_phy_cap cap);
872bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
873bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
874240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
875bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
876bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
877bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
878bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
879240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
880240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
881572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
882c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
883240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
884bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
885bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
886240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
887bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
888240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
889240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
890bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
891bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
892bdcd8170SKalle Valo 
893240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
894bdcd8170SKalle Valo 
895240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
896240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
897240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
898240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
899bdcd8170SKalle Valo 			     u8 win_sz);
900bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
901bdcd8170SKalle Valo 
9026db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
9036db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
904e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
905990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
90655055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
9075fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
9085fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
90945eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
91045eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
91145eaa78fSKalle Valo 
912a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
9135fe4dffbSKalle Valo 
914636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
915636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
916636f8288SKalle Valo 
91745eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
918e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
91945eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
92045eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
92145eaa78fSKalle Valo 
922bdcd8170SKalle Valo #endif /* CORE_H */
923