1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #ifndef CORE_H 18bdcd8170SKalle Valo #define CORE_H 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo #include <linux/etherdevice.h> 21bdcd8170SKalle Valo #include <linux/rtnetlink.h> 22bdcd8170SKalle Valo #include <linux/firmware.h> 23bdcd8170SKalle Valo #include <linux/sched.h> 24bdf5396bSKalle Valo #include <linux/circ_buf.h> 25bdcd8170SKalle Valo #include <net/cfg80211.h> 26bdcd8170SKalle Valo #include "htc.h" 27bdcd8170SKalle Valo #include "wmi.h" 28bdcd8170SKalle Valo #include "bmi.h" 29bc07ddb2SKalle Valo #include "target.h" 30bdcd8170SKalle Valo 31bdcd8170SKalle Valo #define MAX_ATH6KL 1 32bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 33bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 34bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 35bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 37bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 38bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 39bdcd8170SKalle Valo 40bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 42bdcd8170SKalle Valo 43bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 44bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 45bdcd8170SKalle Valo #define MAX_NODE_NUM 15 46bdcd8170SKalle Valo 47c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 50c1762a3fSThirumalai Pachamuthu 511df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 521df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 531df94a85SVasanthakumar Thiagarajan 54bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 55bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 56bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 57bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 58bdcd8170SKalle Valo 59bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 60bdcd8170SKalle Valo 61bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 628232736dSSujith Manoharan #define A_DEFAULT_LISTEN_INTERVAL 1 /* beacon intervals */ 63bdcd8170SKalle Valo #define A_MAX_WOW_LISTEN_INTERVAL 1000 64bdcd8170SKalle Valo 6550d41234SKalle Valo /* includes also the null byte */ 6650d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6750d41234SKalle Valo 6850d41234SKalle Valo enum ath6kl_fw_ie_type { 6950d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7050d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7150d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7250d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7350d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 748a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7597e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 761b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7703ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 78368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 7950d41234SKalle Valo }; 8050d41234SKalle Valo 8197e0496dSKalle Valo enum ath6kl_fw_capability { 8297e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8310509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8497e0496dSKalle Valo 853ca9d1fcSAarthi Thiruvengadam /* 863ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 873ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 883ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 893ca9d1fcSAarthi Thiruvengadam */ 903ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 913ca9d1fcSAarthi Thiruvengadam 9297e0496dSKalle Valo /* this needs to be last */ 9397e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 9497e0496dSKalle Valo }; 9597e0496dSKalle Valo 9697e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 9797e0496dSKalle Valo 9850d41234SKalle Valo struct ath6kl_fw_ie { 9950d41234SKalle Valo __le32 id; 10050d41234SKalle Valo __le32 len; 10150d41234SKalle Valo u8 data[0]; 10250d41234SKalle Valo }; 10350d41234SKalle Valo 104c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 10565a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 106c0038972SKalle Valo 107bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1080d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 109bdcd8170SKalle Valo 110bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1110d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1120d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 113c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 114c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 115c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 116c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 117c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1180d0192baSKalle Valo #define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin" 1190d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1200d0192baSKalle Valo "ath6k/AR6003/hw2.0/bdata.SD31.bin" 121bdcd8170SKalle Valo 122bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1230d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 124c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 125c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 126c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 127c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 128cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 129cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 130c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1310d0192baSKalle Valo #define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin" 1320d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 133bdcd8170SKalle Valo "ath6k/AR6003/hw2.1.1/bdata.SD31.bin" 134bdcd8170SKalle Valo 13531024d99SKevin Fang /* AR6004 1.0 definitions */ 1360d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 137c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 138c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 1390d0192baSKalle Valo #define AR6004_HW_1_0_BOARD_DATA_FILE "ath6k/AR6004/hw1.0/bdata.bin" 1400d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 141d5720e59SKalle Valo "ath6k/AR6004/hw1.0/bdata.DB132.bin" 142d5720e59SKalle Valo 143d5720e59SKalle Valo /* AR6004 1.1 definitions */ 1440d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 145c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 146c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 1470d0192baSKalle Valo #define AR6004_HW_1_1_BOARD_DATA_FILE "ath6k/AR6004/hw1.1/bdata.bin" 1480d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 149d5720e59SKalle Valo "ath6k/AR6004/hw1.1/bdata.DB132.bin" 15031024d99SKevin Fang 151bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 152bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 153bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 154bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 155c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 156c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 157bdcd8170SKalle Valo 158bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 159bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 160bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 161bdcd8170SKalle Valo 162bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 163bdcd8170SKalle Valo 164bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 165bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 166bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 167bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 168bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 169bdcd8170SKalle Valo 170bdcd8170SKalle Valo #define NUM_OF_TIDS 8 171bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 172bdcd8170SKalle Valo 173bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 174bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 175bdcd8170SKalle Valo 176bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 177bdcd8170SKalle Valo 178bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 179bdcd8170SKalle Valo 180bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT 400 /* in ms */ 181bdcd8170SKalle Valo 182bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 183bdcd8170SKalle Valo 184bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo /* configuration lags */ 187bdcd8170SKalle Valo /* 188bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 189bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 190bdcd8170SKalle Valo * sending (Re)Assoc req. 191bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 192bdcd8170SKalle Valo * module state transition failure events which happen during 193bdcd8170SKalle Valo * scan, to the host. 194bdcd8170SKalle Valo */ 195bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 196bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 197bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 198bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 1998277de15SKalle Valo #define ATH6KL_CONF_SUSPEND_CUTPOWER BIT(4) 200f29af978SKalle Valo #define ATH6KL_CONF_UART_DEBUG BIT(5) 201bdcd8170SKalle Valo 202bdcd8170SKalle Valo enum wlan_low_pwr_state { 203bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 204bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 205bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 206bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 207bdcd8170SKalle Valo }; 208bdcd8170SKalle Valo 209bdcd8170SKalle Valo enum sme_state { 210bdcd8170SKalle Valo SME_DISCONNECTED, 211bdcd8170SKalle Valo SME_CONNECTING, 212bdcd8170SKalle Valo SME_CONNECTED 213bdcd8170SKalle Valo }; 214bdcd8170SKalle Valo 215bdcd8170SKalle Valo struct skb_hold_q { 216bdcd8170SKalle Valo struct sk_buff *skb; 217bdcd8170SKalle Valo bool is_amsdu; 218bdcd8170SKalle Valo u16 seq_no; 219bdcd8170SKalle Valo }; 220bdcd8170SKalle Valo 221bdcd8170SKalle Valo struct rxtid { 222bdcd8170SKalle Valo bool aggr; 223bdcd8170SKalle Valo bool progress; 224bdcd8170SKalle Valo bool timer_mon; 225bdcd8170SKalle Valo u16 win_sz; 226bdcd8170SKalle Valo u16 seq_next; 227bdcd8170SKalle Valo u32 hold_q_sz; 228bdcd8170SKalle Valo struct skb_hold_q *hold_q; 229bdcd8170SKalle Valo struct sk_buff_head q; 230bdcd8170SKalle Valo spinlock_t lock; 231bdcd8170SKalle Valo }; 232bdcd8170SKalle Valo 233bdcd8170SKalle Valo struct rxtid_stats { 234bdcd8170SKalle Valo u32 num_into_aggr; 235bdcd8170SKalle Valo u32 num_dups; 236bdcd8170SKalle Valo u32 num_oow; 237bdcd8170SKalle Valo u32 num_mpdu; 238bdcd8170SKalle Valo u32 num_amsdu; 239bdcd8170SKalle Valo u32 num_delivered; 240bdcd8170SKalle Valo u32 num_timeouts; 241bdcd8170SKalle Valo u32 num_hole; 242bdcd8170SKalle Valo u32 num_bar; 243bdcd8170SKalle Valo }; 244bdcd8170SKalle Valo 2457baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 246bdcd8170SKalle Valo u8 aggr_sz; 247bdcd8170SKalle Valo u8 timer_scheduled; 248bdcd8170SKalle Valo struct timer_list timer; 249bdcd8170SKalle Valo struct net_device *dev; 250bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 251bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 2527baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 2537baef812SVasanthakumar Thiagarajan }; 2547baef812SVasanthakumar Thiagarajan 2557baef812SVasanthakumar Thiagarajan struct aggr_info { 2567baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 2577baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 258bdcd8170SKalle Valo }; 259bdcd8170SKalle Valo 260bdcd8170SKalle Valo struct ath6kl_wep_key { 261bdcd8170SKalle Valo u8 key_index; 262bdcd8170SKalle Valo u8 key_len; 263bdcd8170SKalle Valo u8 key[64]; 264bdcd8170SKalle Valo }; 265bdcd8170SKalle Valo 266bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 267bdcd8170SKalle Valo 268bdcd8170SKalle Valo struct ath6kl_key { 269bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 270bdcd8170SKalle Valo u8 key_len; 271bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 272bdcd8170SKalle Valo u8 seq_len; 273bdcd8170SKalle Valo u32 cipher; 274bdcd8170SKalle Valo }; 275bdcd8170SKalle Valo 276bdcd8170SKalle Valo struct ath6kl_node_mapping { 277bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 278bdcd8170SKalle Valo u8 ep_id; 279bdcd8170SKalle Valo u8 tx_pend; 280bdcd8170SKalle Valo }; 281bdcd8170SKalle Valo 282bdcd8170SKalle Valo struct ath6kl_cookie { 283bdcd8170SKalle Valo struct sk_buff *skb; 284bdcd8170SKalle Valo u32 map_no; 285bdcd8170SKalle Valo struct htc_packet htc_pkt; 286bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 287bdcd8170SKalle Valo }; 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo struct ath6kl_sta { 290bdcd8170SKalle Valo u16 sta_flags; 291bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 292bdcd8170SKalle Valo u8 aid; 293bdcd8170SKalle Valo u8 keymgmt; 294bdcd8170SKalle Valo u8 ucipher; 295bdcd8170SKalle Valo u8 auth; 296bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 297bdcd8170SKalle Valo struct sk_buff_head psq; 298bdcd8170SKalle Valo spinlock_t psq_lock; 299c1762a3fSThirumalai Pachamuthu u8 apsd_info; 300c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 301bdcd8170SKalle Valo }; 302bdcd8170SKalle Valo 303bdcd8170SKalle Valo struct ath6kl_version { 304bdcd8170SKalle Valo u32 target_ver; 305bdcd8170SKalle Valo u32 wlan_ver; 306bdcd8170SKalle Valo u32 abi_ver; 307bdcd8170SKalle Valo }; 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo struct ath6kl_bmi { 310bdcd8170SKalle Valo u32 cmd_credits; 311bdcd8170SKalle Valo bool done_sent; 312bdcd8170SKalle Valo u8 *cmd_buf; 3131f4c894dSKalle Valo u32 max_data_size; 3141f4c894dSKalle Valo u32 max_cmd_size; 315bdcd8170SKalle Valo }; 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo struct target_stats { 318bdcd8170SKalle Valo u64 tx_pkt; 319bdcd8170SKalle Valo u64 tx_byte; 320bdcd8170SKalle Valo u64 tx_ucast_pkt; 321bdcd8170SKalle Valo u64 tx_ucast_byte; 322bdcd8170SKalle Valo u64 tx_mcast_pkt; 323bdcd8170SKalle Valo u64 tx_mcast_byte; 324bdcd8170SKalle Valo u64 tx_bcast_pkt; 325bdcd8170SKalle Valo u64 tx_bcast_byte; 326bdcd8170SKalle Valo u64 tx_rts_success_cnt; 327bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 328bdcd8170SKalle Valo 329bdcd8170SKalle Valo u64 tx_err; 330bdcd8170SKalle Valo u64 tx_fail_cnt; 331bdcd8170SKalle Valo u64 tx_retry_cnt; 332bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 333bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 334bdcd8170SKalle Valo 335bdcd8170SKalle Valo u64 rx_pkt; 336bdcd8170SKalle Valo u64 rx_byte; 337bdcd8170SKalle Valo u64 rx_ucast_pkt; 338bdcd8170SKalle Valo u64 rx_ucast_byte; 339bdcd8170SKalle Valo u64 rx_mcast_pkt; 340bdcd8170SKalle Valo u64 rx_mcast_byte; 341bdcd8170SKalle Valo u64 rx_bcast_pkt; 342bdcd8170SKalle Valo u64 rx_bcast_byte; 343bdcd8170SKalle Valo u64 rx_frgment_pkt; 344bdcd8170SKalle Valo 345bdcd8170SKalle Valo u64 rx_err; 346bdcd8170SKalle Valo u64 rx_crc_err; 347bdcd8170SKalle Valo u64 rx_key_cache_miss; 348bdcd8170SKalle Valo u64 rx_decrypt_err; 349bdcd8170SKalle Valo u64 rx_dupl_frame; 350bdcd8170SKalle Valo 351bdcd8170SKalle Valo u64 tkip_local_mic_fail; 352bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 353bdcd8170SKalle Valo u64 tkip_replays; 354bdcd8170SKalle Valo u64 tkip_fmt_err; 355bdcd8170SKalle Valo u64 ccmp_fmt_err; 356bdcd8170SKalle Valo u64 ccmp_replays; 357bdcd8170SKalle Valo 358bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 359bdcd8170SKalle Valo 360bdcd8170SKalle Valo u64 cs_bmiss_cnt; 361bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 362bdcd8170SKalle Valo u64 cs_connect_cnt; 363bdcd8170SKalle Valo u64 cs_discon_cnt; 364bdcd8170SKalle Valo 365bdcd8170SKalle Valo s32 tx_ucast_rate; 366bdcd8170SKalle Valo s32 rx_ucast_rate; 367bdcd8170SKalle Valo 368bdcd8170SKalle Valo u32 lq_val; 369bdcd8170SKalle Valo 370bdcd8170SKalle Valo u32 wow_pkt_dropped; 371bdcd8170SKalle Valo u16 wow_evt_discarded; 372bdcd8170SKalle Valo 373bdcd8170SKalle Valo s16 noise_floor_calib; 374bdcd8170SKalle Valo s16 cs_rssi; 375bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 376bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 377bdcd8170SKalle Valo u8 cs_last_roam_msec; 378bdcd8170SKalle Valo u8 cs_snr; 379bdcd8170SKalle Valo 380bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 381bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 382bdcd8170SKalle Valo 383bdcd8170SKalle Valo u32 arp_received; 384bdcd8170SKalle Valo u32 arp_matched; 385bdcd8170SKalle Valo u32 arp_replied; 386bdcd8170SKalle Valo }; 387bdcd8170SKalle Valo 388bdcd8170SKalle Valo struct ath6kl_mbox_info { 389bdcd8170SKalle Valo u32 htc_addr; 390bdcd8170SKalle Valo u32 htc_ext_addr; 391bdcd8170SKalle Valo u32 htc_ext_sz; 392bdcd8170SKalle Valo 393bdcd8170SKalle Valo u32 block_size; 394bdcd8170SKalle Valo 395bdcd8170SKalle Valo u32 gmbox_addr; 396bdcd8170SKalle Valo 397bdcd8170SKalle Valo u32 gmbox_sz; 398bdcd8170SKalle Valo }; 399bdcd8170SKalle Valo 400bdcd8170SKalle Valo /* 401bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 402bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 403bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 404bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 405bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 406bdcd8170SKalle Valo */ 407bdcd8170SKalle Valo 408bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 409bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 410bdcd8170SKalle Valo 411bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 412bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 413bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 414bdcd8170SKalle Valo 4159a5b1318SJouni Malinen /* Initial group key for AP mode */ 416bdcd8170SKalle Valo struct ath6kl_req_key { 4179a5b1318SJouni Malinen bool valid; 4189a5b1318SJouni Malinen u8 key_index; 4199a5b1318SJouni Malinen int key_type; 4209a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 4219a5b1318SJouni Malinen u8 key_len; 422bdcd8170SKalle Valo }; 423bdcd8170SKalle Valo 42477eab1e9SKalle Valo enum ath6kl_hif_type { 42577eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 42677eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 42777eab1e9SKalle Valo }; 42877eab1e9SKalle Valo 42980abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 43080abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 43180abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 43280abaf9bSVasanthakumar Thiagarajan struct list_head list; 43380abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 43480abaf9bSVasanthakumar Thiagarajan }; 43580abaf9bSVasanthakumar Thiagarajan 43671f96ee6SKalle Valo /* 43771f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 43871f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 43971f96ee6SKalle Valo */ 440b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 441334234b5SVasanthakumar Thiagarajan 44259c98449SVasanthakumar Thiagarajan /* vif flags info */ 44359c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 44459c98449SVasanthakumar Thiagarajan CONNECTED, 44559c98449SVasanthakumar Thiagarajan CONNECT_PEND, 44659c98449SVasanthakumar Thiagarajan WMM_ENABLED, 44759c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 44859c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 44959c98449SVasanthakumar Thiagarajan NETDEV_REGISTERED, 45059c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 45159c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 45259c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 453b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 45459c98449SVasanthakumar Thiagarajan }; 45559c98449SVasanthakumar Thiagarajan 456108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 457990bd915SVasanthakumar Thiagarajan struct list_head list; 458108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 459108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 460108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 461478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 462478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 463334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 46459c98449SVasanthakumar Thiagarajan unsigned long flags; 4653450334fSVasanthakumar Thiagarajan int ssid_len; 4663450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 4673450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 4683450334fSVasanthakumar Thiagarajan u8 auth_mode; 4693450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 4703450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 4713450334fSVasanthakumar Thiagarajan u8 grp_crypto; 4723450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 4733450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 474f5938f24SVasanthakumar Thiagarajan u8 next_mode; 475f5938f24SVasanthakumar Thiagarajan u8 nw_type; 4768c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 4778c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 478f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 479f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 4806f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 4816f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 4822132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 48310509f90SKalle Valo 484de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 48510509f90SKalle Valo struct timer_list sched_scan_timer; 48610509f90SKalle Valo 48714ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 48814ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 489cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 4901052261eSJouni Malinen u32 last_roc_id; 4911052261eSJouni Malinen u32 last_cancel_roc_id; 492cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 493cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 494cf5333d7SVasanthakumar Thiagarajan u16 next_chan; 495cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 496cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 497b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 498b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 49980abaf9bSVasanthakumar Thiagarajan 50080abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 501108438bcSVasanthakumar Thiagarajan }; 502108438bcSVasanthakumar Thiagarajan 5036cb3c714SRaja Mani #define WOW_LIST_ID 0 5046cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 5056cb3c714SRaja Mani 50610509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 50710509f90SKalle Valo 508bdcd8170SKalle Valo /* Flag info */ 50959c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 51059c98449SVasanthakumar Thiagarajan WMI_ENABLED, 51159c98449SVasanthakumar Thiagarajan WMI_READY, 51259c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 51359c98449SVasanthakumar Thiagarajan TESTMODE, 51459c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 51559c98449SVasanthakumar Thiagarajan SKIP_SCAN, 51659c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 5175fe4dffbSKalle Valo FIRST_BOOT, 51859c98449SVasanthakumar Thiagarajan }; 519bdcd8170SKalle Valo 52076a9fbe2SKalle Valo enum ath6kl_state { 52176a9fbe2SKalle Valo ATH6KL_STATE_OFF, 52276a9fbe2SKalle Valo ATH6KL_STATE_ON, 52376a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 524b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 525dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 52610509f90SKalle Valo ATH6KL_STATE_SCHED_SCAN, 52776a9fbe2SKalle Valo }; 52876a9fbe2SKalle Valo 529bdcd8170SKalle Valo struct ath6kl { 530bdcd8170SKalle Valo struct device *dev; 531be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 53276a9fbe2SKalle Valo 53376a9fbe2SKalle Valo enum ath6kl_state state; 53476a9fbe2SKalle Valo 535bdcd8170SKalle Valo struct ath6kl_bmi bmi; 536bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 537bdcd8170SKalle Valo struct wmi *wmi; 538bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 539bdcd8170SKalle Valo int total_tx_data_pend; 540bdcd8170SKalle Valo struct htc_target *htc_target; 54177eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 542bdcd8170SKalle Valo void *hif_priv; 543990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 544990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 545990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 54655055976SVasanthakumar Thiagarajan u8 num_vif; 547368b1b0fSKalle Valo unsigned int vif_max; 5483226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 54955055976SVasanthakumar Thiagarajan u8 avail_idx_map; 550bdcd8170SKalle Valo spinlock_t lock; 551bdcd8170SKalle Valo struct semaphore sem; 552bdcd8170SKalle Valo u16 listen_intvl_b; 553e5090444SVivek Natarajan u8 lrssi_roam_threshold; 554bdcd8170SKalle Valo struct ath6kl_version version; 555bdcd8170SKalle Valo u32 target_type; 556bdcd8170SKalle Valo u8 tx_pwr; 557bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 558bdcd8170SKalle Valo u8 ibss_ps_enable; 55955055976SVasanthakumar Thiagarajan bool ibss_if_active; 560bdcd8170SKalle Valo u8 node_num; 561bdcd8170SKalle Valo u8 next_ep_id; 562bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 563bdcd8170SKalle Valo u32 cookie_count; 564bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 565bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 566bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 567bdcd8170SKalle Valo u8 hiac_stream_active_pri; 568bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 569bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 5703c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 571bdcd8170SKalle Valo u32 connect_ctrl_flags; 572bdcd8170SKalle Valo u32 user_key_ctrl; 573bdcd8170SKalle Valo u8 usr_bss_filter; 574bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 575bdcd8170SKalle Valo u8 sta_list_index; 576bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 577bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 578bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 579bdcd8170SKalle Valo u8 intra_bss; 580bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 581bdcd8170SKalle Valo u8 ap_country_code[3]; 582bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 583bdcd8170SKalle Valo u8 rx_meta_ver; 584bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 585d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 586bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 587003353b0SKalle Valo struct { 588003353b0SKalle Valo void *rx_report; 589003353b0SKalle Valo size_t rx_report_len; 590003353b0SKalle Valo } tm; 591003353b0SKalle Valo 592856f4b31SKalle Valo struct ath6kl_hw { 593856f4b31SKalle Valo u32 id; 594293badf4SKalle Valo const char *name; 595a01ac414SKalle Valo u32 dataset_patch_addr; 596a01ac414SKalle Valo u32 app_load_addr; 597a01ac414SKalle Valo u32 app_start_override_addr; 598991b27eaSKalle Valo u32 board_ext_data_addr; 599991b27eaSKalle Valo u32 reserved_ram_size; 6000d4d72bfSKalle Valo u32 board_addr; 60139586bf2SRyan Hsu u32 refclk_hz; 60239586bf2SRyan Hsu u32 uarttx_pin; 603cd23c1c9SAlex Yang u32 testscript_addr; 604d1a9421dSKalle Valo 605c0038972SKalle Valo struct ath6kl_hw_fw { 606c0038972SKalle Valo const char *dir; 607c0038972SKalle Valo const char *otp; 608d1a9421dSKalle Valo const char *fw; 609c0038972SKalle Valo const char *tcmd; 610c0038972SKalle Valo const char *patch; 611cd23c1c9SAlex Yang const char *utf; 612cd23c1c9SAlex Yang const char *testscript; 613c0038972SKalle Valo } fw; 614c0038972SKalle Valo 615d1a9421dSKalle Valo const char *fw_board; 616d1a9421dSKalle Valo const char *fw_default_board; 617a01ac414SKalle Valo } hw; 618a01ac414SKalle Valo 619bdcd8170SKalle Valo u16 conf_flags; 620bdcd8170SKalle Valo wait_queue_head_t event_wq; 621bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 622bdcd8170SKalle Valo 623bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 624bdcd8170SKalle Valo unsigned long flag; 625bdcd8170SKalle Valo 626bdcd8170SKalle Valo u8 *fw_board; 627bdcd8170SKalle Valo size_t fw_board_len; 628bdcd8170SKalle Valo 629bdcd8170SKalle Valo u8 *fw_otp; 630bdcd8170SKalle Valo size_t fw_otp_len; 631bdcd8170SKalle Valo 632bdcd8170SKalle Valo u8 *fw; 633bdcd8170SKalle Valo size_t fw_len; 634bdcd8170SKalle Valo 635bdcd8170SKalle Valo u8 *fw_patch; 636bdcd8170SKalle Valo size_t fw_patch_len; 637bdcd8170SKalle Valo 638cd23c1c9SAlex Yang u8 *fw_testscript; 639cd23c1c9SAlex Yang size_t fw_testscript_len; 640cd23c1c9SAlex Yang 64165a8b4ccSKalle Valo unsigned int fw_api; 64297e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 64397e0496dSKalle Valo 644bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 6457c3075e9SVasanthakumar Thiagarajan 646d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 6476a7c9badSJouni Malinen 6486bbc7c35SJouni Malinen bool p2p; 6496bbc7c35SJouni Malinen 650bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 651bdf5396bSKalle Valo struct { 652bdf5396bSKalle Valo struct circ_buf fwlog_buf; 653bdf5396bSKalle Valo spinlock_t fwlog_lock; 654bdf5396bSKalle Valo void *fwlog_tmp; 655939f1cceSKalle Valo u32 fwlog_mask; 65691d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 657252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 658252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 6599a730834SKalle Valo 6609a730834SKalle Valo struct { 6619a730834SKalle Valo unsigned int invalid_rate; 6629a730834SKalle Valo } war_stats; 6634b28a80dSJouni Malinen 6644b28a80dSJouni Malinen u8 *roam_tbl; 6654b28a80dSJouni Malinen unsigned int roam_tbl_len; 666ff0b0075SJouni Malinen 667ff0b0075SJouni Malinen u8 keepalive; 668ff0b0075SJouni Malinen u8 disc_timeout; 669bdf5396bSKalle Valo } debug; 670bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 671bdcd8170SKalle Valo }; 672bdcd8170SKalle Valo 673d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 674bdcd8170SKalle Valo { 675108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 676bdcd8170SKalle Valo } 677bdcd8170SKalle Valo 678bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 679bc07ddb2SKalle Valo u32 item_offset) 680bc07ddb2SKalle Valo { 681bc07ddb2SKalle Valo u32 addr = 0; 682bc07ddb2SKalle Valo 683bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 684bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 685bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 686bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 687bc07ddb2SKalle Valo 688bc07ddb2SKalle Valo return addr; 689bc07ddb2SKalle Valo } 690bc07ddb2SKalle Valo 691bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 692bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 693bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 694bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 695bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 696bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 697bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 698bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue); 699bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 700bdcd8170SKalle Valo struct htc_packet *packet); 701bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 702bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 703f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 704addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 705addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 706addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 707bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 708e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 709bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 710bdcd8170SKalle Valo 711bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 712bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 713bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 714bdcd8170SKalle Valo 7157baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 716bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 717bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 718bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 719bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 720bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 721bdcd8170SKalle Valo int len); 722bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 723bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info); 724bdcd8170SKalle Valo 7256765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 * node_addr); 726bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 727bdcd8170SKalle Valo 728bdcd8170SKalle Valo void ath6kl_ready_event(void *devt, u8 * datap, u32 sw_ver, u32 abi_ver); 729bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 730bdcd8170SKalle Valo enum htc_endpoint_id eid); 731240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 732bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 733bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 734bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 735bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 736240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 737240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 738572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 739c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 740240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 741bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 742bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 743240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 744bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 745240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 746240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 747bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 748bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 749bdcd8170SKalle Valo 750240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 751bdcd8170SKalle Valo 752240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 753240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 754240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 755240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 756bdcd8170SKalle Valo u8 win_sz); 757bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 758bdcd8170SKalle Valo 7596db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type, 7606db8fa53SVasanthakumar Thiagarajan bool wait_fot_compltn, bool cold_reset); 761e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 762990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 76355055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready); 7645fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 7655fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 76645eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 76745eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 76845eaa78fSKalle Valo 769a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 7705fe4dffbSKalle Valo 77145eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 77245eaa78fSKalle Valo int ath6kl_core_init(struct ath6kl *ar); 77345eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 77445eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 77545eaa78fSKalle Valo 776bdcd8170SKalle Valo #endif /* CORE_H */ 777