1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef CORE_H 19bdcd8170SKalle Valo #define CORE_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #include <linux/etherdevice.h> 22bdcd8170SKalle Valo #include <linux/rtnetlink.h> 23bdcd8170SKalle Valo #include <linux/firmware.h> 24bdcd8170SKalle Valo #include <linux/sched.h> 25bdf5396bSKalle Valo #include <linux/circ_buf.h> 26bdcd8170SKalle Valo #include <net/cfg80211.h> 27bdcd8170SKalle Valo #include "htc.h" 28bdcd8170SKalle Valo #include "wmi.h" 29bdcd8170SKalle Valo #include "bmi.h" 30bc07ddb2SKalle Valo #include "target.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define MAX_ATH6KL 1 33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 46bdcd8170SKalle Valo #define MAX_NODE_NUM 15 47bdcd8170SKalle Valo 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 51c1762a3fSThirumalai Pachamuthu 521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 541df94a85SVasanthakumar Thiagarajan 55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 58bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 59bdcd8170SKalle Valo 60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 63bdcd8170SKalle Valo 6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */ 6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */ 6613423c31SVasanthakumar Thiagarajan 6750d41234SKalle Valo /* includes also the null byte */ 6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6950d41234SKalle Valo 7050d41234SKalle Valo enum ath6kl_fw_ie_type { 7150d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7250d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7350d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7450d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7550d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 768a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7797e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 781b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7903ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 80368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 8150d41234SKalle Valo }; 8250d41234SKalle Valo 8397e0496dSKalle Valo enum ath6kl_fw_capability { 8497e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8510509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8697e0496dSKalle Valo 873ca9d1fcSAarthi Thiruvengadam /* 883ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 893ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 903ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 913ca9d1fcSAarthi Thiruvengadam */ 923ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 933ca9d1fcSAarthi Thiruvengadam 9403bdeb0dSVasanthakumar Thiagarajan /* 9503bdeb0dSVasanthakumar Thiagarajan * Firmware has support to cleanup inactive stations 9603bdeb0dSVasanthakumar Thiagarajan * in AP mode. 9703bdeb0dSVasanthakumar Thiagarajan */ 9803bdeb0dSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT, 9903bdeb0dSVasanthakumar Thiagarajan 100d97c121bSVasanthakumar Thiagarajan /* Firmware has support to override rsn cap of rsn ie */ 101d97c121bSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, 102d97c121bSVasanthakumar Thiagarajan 1036821d4f0SNaveen Gangadharan /* 1046821d4f0SNaveen Gangadharan * Multicast support in WOW and host awake mode. 1056821d4f0SNaveen Gangadharan * Allow all multicast in host awake mode. 1066821d4f0SNaveen Gangadharan * Apply multicast filter in WOW mode. 1076821d4f0SNaveen Gangadharan */ 1086821d4f0SNaveen Gangadharan ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER, 1096821d4f0SNaveen Gangadharan 110c422d52dSThomas Pedersen /* Firmware supports enhanced bmiss detection */ 111c422d52dSThomas Pedersen ATH6KL_FW_CAPABILITY_BMISS_ENHANCE, 112c422d52dSThomas Pedersen 113dd45b759SNaveen Singh /* 114dd45b759SNaveen Singh * FW supports matching of ssid in schedule scan 115dd45b759SNaveen Singh */ 116dd45b759SNaveen Singh ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST, 117dd45b759SNaveen Singh 11885b20fc2SThomas Pedersen /* Firmware supports filtering BSS results by RSSI */ 11985b20fc2SThomas Pedersen ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD, 12085b20fc2SThomas Pedersen 121c95dcb59SAarthi Thiruvengadam /* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */ 122c95dcb59SAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR, 123c95dcb59SAarthi Thiruvengadam 124279b2862SThomas Pedersen /* Firmware supports TX error rate notification */ 125279b2862SThomas Pedersen ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY, 126279b2862SThomas Pedersen 12784841ba2SKalle Valo /* supports WMI_SET_REGDOMAIN_CMDID command */ 12884841ba2SKalle Valo ATH6KL_FW_CAPABILITY_REGDOMAIN, 12984841ba2SKalle Valo 130b1f47e3aSThomas Pedersen /* Firmware supports sched scan decoupled from host sleep */ 131b1f47e3aSThomas Pedersen ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2, 132b1f47e3aSThomas Pedersen 13392332993SVasanthakumar Thiagarajan /* 13492332993SVasanthakumar Thiagarajan * Firmware capability for hang detection through heart beat 13592332993SVasanthakumar Thiagarajan * challenge messages. 13692332993SVasanthakumar Thiagarajan */ 13792332993SVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL, 13892332993SVasanthakumar Thiagarajan 13997e0496dSKalle Valo /* this needs to be last */ 14097e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 14197e0496dSKalle Valo }; 14297e0496dSKalle Valo 14397e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 14497e0496dSKalle Valo 14550d41234SKalle Valo struct ath6kl_fw_ie { 14650d41234SKalle Valo __le32 id; 14750d41234SKalle Valo __le32 len; 14850d41234SKalle Valo u8 data[0]; 14950d41234SKalle Valo }; 15050d41234SKalle Valo 15106e360acSBala Shanmugam enum ath6kl_hw_flags { 152c0b34e2bSMohammed Shafi Shajakhan ATH6KL_HW_64BIT_RATES = BIT(0), 1537ac25eacSMohammed Shafi Shajakhan ATH6KL_HW_AP_INACTIVITY_MINS = BIT(1), 15406e360acSBala Shanmugam }; 15506e360acSBala Shanmugam 156c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 15765a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 158b1f47e3aSThomas Pedersen #define ATH6KL_FW_API4_FILE "fw-4.bin" 159c0038972SKalle Valo 160bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1610d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 162bdcd8170SKalle Valo 163bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1640d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1650d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 166c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 167c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 168c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 169c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 170c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1712023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin" 1720d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1732023dbb8STim Gardner AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin" 174bdcd8170SKalle Valo 175bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1760d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 177c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 178c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 179c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 180c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 181cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 182cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 183c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1842023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin" 1850d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 1862023dbb8STim Gardner AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin" 187bdcd8170SKalle Valo 18831024d99SKevin Fang /* AR6004 1.0 definitions */ 1890d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 190c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 191c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 1922023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin" 1930d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 1942023dbb8STim Gardner AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin" 195d5720e59SKalle Valo 196d5720e59SKalle Valo /* AR6004 1.1 definitions */ 1970d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 198c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 199c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 2002023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin" 2010d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 2022023dbb8STim Gardner AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin" 20331024d99SKevin Fang 2046146ca69SRay Chen /* AR6004 1.2 definitions */ 2056146ca69SRay Chen #define AR6004_HW_1_2_VERSION 0x300007e8 2066146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2" 2076146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin" 2082023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin" 2096146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \ 2102023dbb8STim Gardner AR6004_HW_1_2_FW_DIR "/bdata.bin" 2116146ca69SRay Chen 212bf744f11SBala Shanmugam /* AR6004 1.3 definitions */ 213bf744f11SBala Shanmugam #define AR6004_HW_1_3_VERSION 0x31c8088a 214bf744f11SBala Shanmugam #define AR6004_HW_1_3_FW_DIR "ath6k/AR6004/hw1.3" 215bf744f11SBala Shanmugam #define AR6004_HW_1_3_FIRMWARE_FILE "fw.ram.bin" 216bf744f11SBala Shanmugam #define AR6004_HW_1_3_BOARD_DATA_FILE "ath6k/AR6004/hw1.3/bdata.bin" 217bf744f11SBala Shanmugam #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE "ath6k/AR6004/hw1.3/bdata.bin" 218bf744f11SBala Shanmugam 219bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 220bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 221bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 222bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 223c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 224c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 225bdcd8170SKalle Valo 226bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 227bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 228bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 229bdcd8170SKalle Valo 230bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 231bdcd8170SKalle Valo 232bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 233bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 234bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 235bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 236bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 237bdcd8170SKalle Valo 238bdcd8170SKalle Valo #define NUM_OF_TIDS 8 239bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 240bdcd8170SKalle Valo 241bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 242bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 243bdcd8170SKalle Valo 244bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 245bdcd8170SKalle Valo 246bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 247bdcd8170SKalle Valo 2487940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT 100 /* in ms */ 249bdcd8170SKalle Valo 250bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 251bdcd8170SKalle Valo 252bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 253bdcd8170SKalle Valo 2548f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */ 255ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME 1500 256ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */ 257ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME 5000 2588f46fccdSRaja Mani 259bdcd8170SKalle Valo /* configuration lags */ 260bdcd8170SKalle Valo /* 261bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 262bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 263bdcd8170SKalle Valo * sending (Re)Assoc req. 264bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 265bdcd8170SKalle Valo * module state transition failure events which happen during 266bdcd8170SKalle Valo * scan, to the host. 267bdcd8170SKalle Valo */ 268bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 269bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 270bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 271bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 272e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG BIT(4) 273bdcd8170SKalle Valo 274c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */ 275c86e4f44SAarthi Thiruvengadam 276bdcd8170SKalle Valo enum wlan_low_pwr_state { 277bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 278bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 279bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 280bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 281bdcd8170SKalle Valo }; 282bdcd8170SKalle Valo 283bdcd8170SKalle Valo enum sme_state { 284bdcd8170SKalle Valo SME_DISCONNECTED, 285bdcd8170SKalle Valo SME_CONNECTING, 286bdcd8170SKalle Valo SME_CONNECTED 287bdcd8170SKalle Valo }; 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo struct skb_hold_q { 290bdcd8170SKalle Valo struct sk_buff *skb; 291bdcd8170SKalle Valo bool is_amsdu; 292bdcd8170SKalle Valo u16 seq_no; 293bdcd8170SKalle Valo }; 294bdcd8170SKalle Valo 295bdcd8170SKalle Valo struct rxtid { 296bdcd8170SKalle Valo bool aggr; 297bdcd8170SKalle Valo bool timer_mon; 298bdcd8170SKalle Valo u16 win_sz; 299bdcd8170SKalle Valo u16 seq_next; 300bdcd8170SKalle Valo u32 hold_q_sz; 301bdcd8170SKalle Valo struct skb_hold_q *hold_q; 302bdcd8170SKalle Valo struct sk_buff_head q; 30312eb9444SKalle Valo 30412eb9444SKalle Valo /* 3050faf7458SVasanthakumar Thiagarajan * lock mainly protects seq_next and hold_q. Movement of seq_next 3060faf7458SVasanthakumar Thiagarajan * needs to be protected between aggr_timeout() and 3070faf7458SVasanthakumar Thiagarajan * aggr_process_recv_frm(). hold_q will be holding the pending 3080faf7458SVasanthakumar Thiagarajan * reorder frames and it's access should also be protected. 3090faf7458SVasanthakumar Thiagarajan * Some of the other fields like hold_q_sz, win_sz and aggr are 3100faf7458SVasanthakumar Thiagarajan * initialized/reset when receiving addba/delba req, also while 3110faf7458SVasanthakumar Thiagarajan * deleting aggr state all the pending buffers are flushed before 3120faf7458SVasanthakumar Thiagarajan * resetting these fields, so there should not be any race in accessing 3130faf7458SVasanthakumar Thiagarajan * these fields. 31412eb9444SKalle Valo */ 315bdcd8170SKalle Valo spinlock_t lock; 316bdcd8170SKalle Valo }; 317bdcd8170SKalle Valo 318bdcd8170SKalle Valo struct rxtid_stats { 319bdcd8170SKalle Valo u32 num_into_aggr; 320bdcd8170SKalle Valo u32 num_dups; 321bdcd8170SKalle Valo u32 num_oow; 322bdcd8170SKalle Valo u32 num_mpdu; 323bdcd8170SKalle Valo u32 num_amsdu; 324bdcd8170SKalle Valo u32 num_delivered; 325bdcd8170SKalle Valo u32 num_timeouts; 326bdcd8170SKalle Valo u32 num_hole; 327bdcd8170SKalle Valo u32 num_bar; 328bdcd8170SKalle Valo }; 329bdcd8170SKalle Valo 3307baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 331bdcd8170SKalle Valo u8 aggr_sz; 332bdcd8170SKalle Valo u8 timer_scheduled; 333bdcd8170SKalle Valo struct timer_list timer; 334bdcd8170SKalle Valo struct net_device *dev; 335bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 336bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 3377baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 3387baef812SVasanthakumar Thiagarajan }; 3397baef812SVasanthakumar Thiagarajan 3407baef812SVasanthakumar Thiagarajan struct aggr_info { 3417baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 3427baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 343bdcd8170SKalle Valo }; 344bdcd8170SKalle Valo 345bdcd8170SKalle Valo struct ath6kl_wep_key { 346bdcd8170SKalle Valo u8 key_index; 347bdcd8170SKalle Valo u8 key_len; 348bdcd8170SKalle Valo u8 key[64]; 349bdcd8170SKalle Valo }; 350bdcd8170SKalle Valo 351bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 352bdcd8170SKalle Valo 353bdcd8170SKalle Valo struct ath6kl_key { 354bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 355bdcd8170SKalle Valo u8 key_len; 356bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 357bdcd8170SKalle Valo u8 seq_len; 358bdcd8170SKalle Valo u32 cipher; 359bdcd8170SKalle Valo }; 360bdcd8170SKalle Valo 361bdcd8170SKalle Valo struct ath6kl_node_mapping { 362bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 363bdcd8170SKalle Valo u8 ep_id; 364bdcd8170SKalle Valo u8 tx_pend; 365bdcd8170SKalle Valo }; 366bdcd8170SKalle Valo 367bdcd8170SKalle Valo struct ath6kl_cookie { 368bdcd8170SKalle Valo struct sk_buff *skb; 369bdcd8170SKalle Valo u32 map_no; 370bdcd8170SKalle Valo struct htc_packet htc_pkt; 371bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 372bdcd8170SKalle Valo }; 373bdcd8170SKalle Valo 374d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff { 375d0ff7383SNaveen Gangadharan struct list_head list; 376d0ff7383SNaveen Gangadharan u32 freq; 377d0ff7383SNaveen Gangadharan u32 wait; 378d0ff7383SNaveen Gangadharan u32 id; 379d0ff7383SNaveen Gangadharan bool no_cck; 380d0ff7383SNaveen Gangadharan size_t len; 381d0ff7383SNaveen Gangadharan u8 buf[0]; 382d0ff7383SNaveen Gangadharan }; 383d0ff7383SNaveen Gangadharan 384bdcd8170SKalle Valo struct ath6kl_sta { 385bdcd8170SKalle Valo u16 sta_flags; 386bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 387bdcd8170SKalle Valo u8 aid; 388bdcd8170SKalle Valo u8 keymgmt; 389bdcd8170SKalle Valo u8 ucipher; 390bdcd8170SKalle Valo u8 auth; 391bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 392bdcd8170SKalle Valo struct sk_buff_head psq; 39312eb9444SKalle Valo 39412eb9444SKalle Valo /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */ 395bdcd8170SKalle Valo spinlock_t psq_lock; 39612eb9444SKalle Valo 397d0ff7383SNaveen Gangadharan struct list_head mgmt_psq; 398d0ff7383SNaveen Gangadharan size_t mgmt_psq_len; 399c1762a3fSThirumalai Pachamuthu u8 apsd_info; 400c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 4011d2a4456SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 402bdcd8170SKalle Valo }; 403bdcd8170SKalle Valo 404bdcd8170SKalle Valo struct ath6kl_version { 405bdcd8170SKalle Valo u32 target_ver; 406bdcd8170SKalle Valo u32 wlan_ver; 407bdcd8170SKalle Valo u32 abi_ver; 408bdcd8170SKalle Valo }; 409bdcd8170SKalle Valo 410bdcd8170SKalle Valo struct ath6kl_bmi { 411bdcd8170SKalle Valo u32 cmd_credits; 412bdcd8170SKalle Valo bool done_sent; 413bdcd8170SKalle Valo u8 *cmd_buf; 4141f4c894dSKalle Valo u32 max_data_size; 4151f4c894dSKalle Valo u32 max_cmd_size; 416bdcd8170SKalle Valo }; 417bdcd8170SKalle Valo 418bdcd8170SKalle Valo struct target_stats { 419bdcd8170SKalle Valo u64 tx_pkt; 420bdcd8170SKalle Valo u64 tx_byte; 421bdcd8170SKalle Valo u64 tx_ucast_pkt; 422bdcd8170SKalle Valo u64 tx_ucast_byte; 423bdcd8170SKalle Valo u64 tx_mcast_pkt; 424bdcd8170SKalle Valo u64 tx_mcast_byte; 425bdcd8170SKalle Valo u64 tx_bcast_pkt; 426bdcd8170SKalle Valo u64 tx_bcast_byte; 427bdcd8170SKalle Valo u64 tx_rts_success_cnt; 428bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 429bdcd8170SKalle Valo 430bdcd8170SKalle Valo u64 tx_err; 431bdcd8170SKalle Valo u64 tx_fail_cnt; 432bdcd8170SKalle Valo u64 tx_retry_cnt; 433bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 434bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 435bdcd8170SKalle Valo 436bdcd8170SKalle Valo u64 rx_pkt; 437bdcd8170SKalle Valo u64 rx_byte; 438bdcd8170SKalle Valo u64 rx_ucast_pkt; 439bdcd8170SKalle Valo u64 rx_ucast_byte; 440bdcd8170SKalle Valo u64 rx_mcast_pkt; 441bdcd8170SKalle Valo u64 rx_mcast_byte; 442bdcd8170SKalle Valo u64 rx_bcast_pkt; 443bdcd8170SKalle Valo u64 rx_bcast_byte; 444bdcd8170SKalle Valo u64 rx_frgment_pkt; 445bdcd8170SKalle Valo 446bdcd8170SKalle Valo u64 rx_err; 447bdcd8170SKalle Valo u64 rx_crc_err; 448bdcd8170SKalle Valo u64 rx_key_cache_miss; 449bdcd8170SKalle Valo u64 rx_decrypt_err; 450bdcd8170SKalle Valo u64 rx_dupl_frame; 451bdcd8170SKalle Valo 452bdcd8170SKalle Valo u64 tkip_local_mic_fail; 453bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 454bdcd8170SKalle Valo u64 tkip_replays; 455bdcd8170SKalle Valo u64 tkip_fmt_err; 456bdcd8170SKalle Valo u64 ccmp_fmt_err; 457bdcd8170SKalle Valo u64 ccmp_replays; 458bdcd8170SKalle Valo 459bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 460bdcd8170SKalle Valo 461bdcd8170SKalle Valo u64 cs_bmiss_cnt; 462bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 463bdcd8170SKalle Valo u64 cs_connect_cnt; 464bdcd8170SKalle Valo u64 cs_discon_cnt; 465bdcd8170SKalle Valo 466bdcd8170SKalle Valo s32 tx_ucast_rate; 467bdcd8170SKalle Valo s32 rx_ucast_rate; 468bdcd8170SKalle Valo 469bdcd8170SKalle Valo u32 lq_val; 470bdcd8170SKalle Valo 471bdcd8170SKalle Valo u32 wow_pkt_dropped; 472bdcd8170SKalle Valo u16 wow_evt_discarded; 473bdcd8170SKalle Valo 474bdcd8170SKalle Valo s16 noise_floor_calib; 475bdcd8170SKalle Valo s16 cs_rssi; 476bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 477bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 478bdcd8170SKalle Valo u8 cs_last_roam_msec; 479bdcd8170SKalle Valo u8 cs_snr; 480bdcd8170SKalle Valo 481bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 482bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 483bdcd8170SKalle Valo 484bdcd8170SKalle Valo u32 arp_received; 485bdcd8170SKalle Valo u32 arp_matched; 486bdcd8170SKalle Valo u32 arp_replied; 487bdcd8170SKalle Valo }; 488bdcd8170SKalle Valo 489bdcd8170SKalle Valo struct ath6kl_mbox_info { 490bdcd8170SKalle Valo u32 htc_addr; 491bdcd8170SKalle Valo u32 htc_ext_addr; 492bdcd8170SKalle Valo u32 htc_ext_sz; 493bdcd8170SKalle Valo 494bdcd8170SKalle Valo u32 block_size; 495bdcd8170SKalle Valo 496bdcd8170SKalle Valo u32 gmbox_addr; 497bdcd8170SKalle Valo 498bdcd8170SKalle Valo u32 gmbox_sz; 499bdcd8170SKalle Valo }; 500bdcd8170SKalle Valo 501bdcd8170SKalle Valo /* 502bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 503bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 504bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 505bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 506bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 507bdcd8170SKalle Valo */ 508bdcd8170SKalle Valo 509bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 510bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 511bdcd8170SKalle Valo 512bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 513bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 514bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 515bdcd8170SKalle Valo 5169a5b1318SJouni Malinen /* Initial group key for AP mode */ 517bdcd8170SKalle Valo struct ath6kl_req_key { 5189a5b1318SJouni Malinen bool valid; 5199a5b1318SJouni Malinen u8 key_index; 5209a5b1318SJouni Malinen int key_type; 5219a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 5229a5b1318SJouni Malinen u8 key_len; 523bdcd8170SKalle Valo }; 524bdcd8170SKalle Valo 52577eab1e9SKalle Valo enum ath6kl_hif_type { 52677eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 52777eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 52877eab1e9SKalle Valo }; 52977eab1e9SKalle Valo 530e76ac2bfSKalle Valo enum ath6kl_htc_type { 531e76ac2bfSKalle Valo ATH6KL_HTC_TYPE_MBOX, 532636f8288SKalle Valo ATH6KL_HTC_TYPE_PIPE, 533e76ac2bfSKalle Valo }; 534e76ac2bfSKalle Valo 53580abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 53680abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 53780abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 53880abaf9bSVasanthakumar Thiagarajan struct list_head list; 53980abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 54080abaf9bSVasanthakumar Thiagarajan }; 54180abaf9bSVasanthakumar Thiagarajan 542df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap { 543df90b369SVasanthakumar Thiagarajan bool ht_enable; 544df90b369SVasanthakumar Thiagarajan u8 ampdu_factor; 545df90b369SVasanthakumar Thiagarajan unsigned short cap_info; 546df90b369SVasanthakumar Thiagarajan }; 547df90b369SVasanthakumar Thiagarajan 54871f96ee6SKalle Valo /* 54971f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 55071f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 55171f96ee6SKalle Valo */ 552b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 553334234b5SVasanthakumar Thiagarajan 55459c98449SVasanthakumar Thiagarajan /* vif flags info */ 55559c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 55659c98449SVasanthakumar Thiagarajan CONNECTED, 55759c98449SVasanthakumar Thiagarajan CONNECT_PEND, 55859c98449SVasanthakumar Thiagarajan WMM_ENABLED, 55959c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 56059c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 56159c98449SVasanthakumar Thiagarajan NETDEV_REGISTERED, 56259c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 56359c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 56459c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 565b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 566081c7a84SRaja Mani HOST_SLEEP_MODE_CMD_PROCESSED, 5676251d801SNaveen Gangadharan NETDEV_MCAST_ALL_ON, 5686251d801SNaveen Gangadharan NETDEV_MCAST_ALL_OFF, 569b1f47e3aSThomas Pedersen SCHED_SCANNING, 57059c98449SVasanthakumar Thiagarajan }; 57159c98449SVasanthakumar Thiagarajan 572108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 573990bd915SVasanthakumar Thiagarajan struct list_head list; 574108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 575108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 576108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 577478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 578478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 579334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 58059c98449SVasanthakumar Thiagarajan unsigned long flags; 5813450334fSVasanthakumar Thiagarajan int ssid_len; 5823450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 5833450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 5843450334fSVasanthakumar Thiagarajan u8 auth_mode; 5853450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 5863450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 5873450334fSVasanthakumar Thiagarajan u8 grp_crypto; 5883450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 5893450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 590f5938f24SVasanthakumar Thiagarajan u8 next_mode; 591f5938f24SVasanthakumar Thiagarajan u8 nw_type; 5928c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 5938c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 594f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 595f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 5966f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 5976f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 5982132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 59967b3f129SKiran Reddy struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS]; 60010509f90SKalle Valo 601de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 60210509f90SKalle Valo struct timer_list sched_scan_timer; 60310509f90SKalle Valo 60414ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 60514ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 606cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 6071052261eSJouni Malinen u32 last_roc_id; 6081052261eSJouni Malinen u32 last_cancel_roc_id; 609cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 610cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 611cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 6128f46fccdSRaja Mani u16 listen_intvl_t; 613ce0dc0cfSRaja Mani u16 bmiss_time_t; 614279b2862SThomas Pedersen u32 txe_intvl; 615eb38987eSRaja Mani u16 bg_scan_period; 616cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 617b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 618b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 619c4f7863eSThomas Pedersen struct wmi_connect_cmd profile; 620f21243a8SThomas Pedersen u16 rsn_capab; 62180abaf9bSVasanthakumar Thiagarajan 62280abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 623108438bcSVasanthakumar Thiagarajan }; 624108438bcSVasanthakumar Thiagarajan 62571bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev) 62671bbc994SJohannes Berg { 62771bbc994SJohannes Berg return container_of(wdev, struct ath6kl_vif, wdev); 62871bbc994SJohannes Berg } 62971bbc994SJohannes Berg 6306cb3c714SRaja Mani #define WOW_LIST_ID 0 6316cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 6326cb3c714SRaja Mani 63310509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 63410509f90SKalle Valo 635bdcd8170SKalle Valo /* Flag info */ 63659c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 63759c98449SVasanthakumar Thiagarajan WMI_ENABLED, 63859c98449SVasanthakumar Thiagarajan WMI_READY, 63959c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 64059c98449SVasanthakumar Thiagarajan TESTMODE, 64159c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 64259c98449SVasanthakumar Thiagarajan SKIP_SCAN, 64359c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 6445fe4dffbSKalle Valo FIRST_BOOT, 645a3561706SVasanthakumar Thiagarajan RECOVERY_CLEANUP, 64659c98449SVasanthakumar Thiagarajan }; 647bdcd8170SKalle Valo 64876a9fbe2SKalle Valo enum ath6kl_state { 64976a9fbe2SKalle Valo ATH6KL_STATE_OFF, 65076a9fbe2SKalle Valo ATH6KL_STATE_ON, 651390a8c8fSRaja Mani ATH6KL_STATE_SUSPENDING, 652390a8c8fSRaja Mani ATH6KL_STATE_RESUMING, 65376a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 654b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 655dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 65684caf800SVasanthakumar Thiagarajan ATH6KL_STATE_RECOVERY, 65784caf800SVasanthakumar Thiagarajan }; 65884caf800SVasanthakumar Thiagarajan 65984caf800SVasanthakumar Thiagarajan /* Fw error recovery */ 66092332993SVasanthakumar Thiagarajan #define ATH6KL_HB_RESP_MISS_THRES 5 66192332993SVasanthakumar Thiagarajan 66284caf800SVasanthakumar Thiagarajan enum ath6kl_fw_err { 66384caf800SVasanthakumar Thiagarajan ATH6KL_FW_ASSERT, 66492332993SVasanthakumar Thiagarajan ATH6KL_FW_HB_RESP_FAILURE, 66577565794SVasanthakumar Thiagarajan ATH6KL_FW_EP_FULL, 66676a9fbe2SKalle Valo }; 66776a9fbe2SKalle Valo 668bdcd8170SKalle Valo struct ath6kl { 669bdcd8170SKalle Valo struct device *dev; 670be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 67176a9fbe2SKalle Valo 67276a9fbe2SKalle Valo enum ath6kl_state state; 6735f1127ffSKalle Valo unsigned int testmode; 67476a9fbe2SKalle Valo 675bdcd8170SKalle Valo struct ath6kl_bmi bmi; 676bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 677e76ac2bfSKalle Valo const struct ath6kl_htc_ops *htc_ops; 678bdcd8170SKalle Valo struct wmi *wmi; 679bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 680bdcd8170SKalle Valo int total_tx_data_pend; 681bdcd8170SKalle Valo struct htc_target *htc_target; 68277eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 683bdcd8170SKalle Valo void *hif_priv; 684990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 685990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 686990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 68755055976SVasanthakumar Thiagarajan u8 num_vif; 688368b1b0fSKalle Valo unsigned int vif_max; 6893226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 69055055976SVasanthakumar Thiagarajan u8 avail_idx_map; 69112eb9444SKalle Valo 69212eb9444SKalle Valo /* 69312eb9444SKalle Valo * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie() 69412eb9444SKalle Valo * calls, tx_pending and total_tx_data_pend. 69512eb9444SKalle Valo */ 696bdcd8170SKalle Valo spinlock_t lock; 69712eb9444SKalle Valo 698bdcd8170SKalle Valo struct semaphore sem; 699e5090444SVivek Natarajan u8 lrssi_roam_threshold; 700bdcd8170SKalle Valo struct ath6kl_version version; 701bdcd8170SKalle Valo u32 target_type; 702bdcd8170SKalle Valo u8 tx_pwr; 703bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 704bdcd8170SKalle Valo u8 ibss_ps_enable; 70555055976SVasanthakumar Thiagarajan bool ibss_if_active; 706bdcd8170SKalle Valo u8 node_num; 707bdcd8170SKalle Valo u8 next_ep_id; 708bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 709bdcd8170SKalle Valo u32 cookie_count; 710bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 711bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 712bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 713bdcd8170SKalle Valo u8 hiac_stream_active_pri; 714bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 715bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 7163c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 717bdcd8170SKalle Valo u32 connect_ctrl_flags; 718bdcd8170SKalle Valo u32 user_key_ctrl; 719bdcd8170SKalle Valo u8 usr_bss_filter; 720bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 721bdcd8170SKalle Valo u8 sta_list_index; 722bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 723bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 724c4f7863eSThomas Pedersen u32 want_ch_switch; 725b5495e66SThomas Pedersen u16 last_ch; 72612eb9444SKalle Valo 72712eb9444SKalle Valo /* 72812eb9444SKalle Valo * FIXME: protects access to mcastpsq but is actually useless as 72912eb9444SKalle Valo * all skbe_queue_*() functions provide serialisation themselves 73012eb9444SKalle Valo */ 731bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 73212eb9444SKalle Valo 733bdcd8170SKalle Valo u8 intra_bss; 734bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 735bdcd8170SKalle Valo u8 ap_country_code[3]; 736bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 737bdcd8170SKalle Valo u8 rx_meta_ver; 738bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 739d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 740bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 741003353b0SKalle Valo struct { 742003353b0SKalle Valo void *rx_report; 743003353b0SKalle Valo size_t rx_report_len; 744003353b0SKalle Valo } tm; 745003353b0SKalle Valo 746856f4b31SKalle Valo struct ath6kl_hw { 747856f4b31SKalle Valo u32 id; 748293badf4SKalle Valo const char *name; 749a01ac414SKalle Valo u32 dataset_patch_addr; 750a01ac414SKalle Valo u32 app_load_addr; 751a01ac414SKalle Valo u32 app_start_override_addr; 752991b27eaSKalle Valo u32 board_ext_data_addr; 753991b27eaSKalle Valo u32 reserved_ram_size; 7540d4d72bfSKalle Valo u32 board_addr; 75539586bf2SRyan Hsu u32 refclk_hz; 75639586bf2SRyan Hsu u32 uarttx_pin; 757cd23c1c9SAlex Yang u32 testscript_addr; 758d92917e4SThomas Pedersen enum wmi_phy_cap cap; 759d1a9421dSKalle Valo 76006e360acSBala Shanmugam u32 flags; 76106e360acSBala Shanmugam 762c0038972SKalle Valo struct ath6kl_hw_fw { 763c0038972SKalle Valo const char *dir; 764c0038972SKalle Valo const char *otp; 765d1a9421dSKalle Valo const char *fw; 766c0038972SKalle Valo const char *tcmd; 767c0038972SKalle Valo const char *patch; 768cd23c1c9SAlex Yang const char *utf; 769cd23c1c9SAlex Yang const char *testscript; 770c0038972SKalle Valo } fw; 771c0038972SKalle Valo 772d1a9421dSKalle Valo const char *fw_board; 773d1a9421dSKalle Valo const char *fw_default_board; 774a01ac414SKalle Valo } hw; 775a01ac414SKalle Valo 776bdcd8170SKalle Valo u16 conf_flags; 777e390af77SRaja Mani u16 suspend_mode; 7781e9a905dSRaja Mani u16 wow_suspend_mode; 779bdcd8170SKalle Valo wait_queue_head_t event_wq; 780bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 781bdcd8170SKalle Valo 782bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 783bdcd8170SKalle Valo unsigned long flag; 784bdcd8170SKalle Valo 785bdcd8170SKalle Valo u8 *fw_board; 786bdcd8170SKalle Valo size_t fw_board_len; 787bdcd8170SKalle Valo 788bdcd8170SKalle Valo u8 *fw_otp; 789bdcd8170SKalle Valo size_t fw_otp_len; 790bdcd8170SKalle Valo 791bdcd8170SKalle Valo u8 *fw; 792bdcd8170SKalle Valo size_t fw_len; 793bdcd8170SKalle Valo 794bdcd8170SKalle Valo u8 *fw_patch; 795bdcd8170SKalle Valo size_t fw_patch_len; 796bdcd8170SKalle Valo 797cd23c1c9SAlex Yang u8 *fw_testscript; 798cd23c1c9SAlex Yang size_t fw_testscript_len; 799cd23c1c9SAlex Yang 80065a8b4ccSKalle Valo unsigned int fw_api; 80197e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 80297e0496dSKalle Valo 803bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 8047c3075e9SVasanthakumar Thiagarajan 805d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 8066a7c9badSJouni Malinen 8076bbc7c35SJouni Malinen bool p2p; 8086bbc7c35SJouni Malinen 809e5348a1eSVasanthakumar Thiagarajan bool wiphy_registered; 810e5348a1eSVasanthakumar Thiagarajan 81184caf800SVasanthakumar Thiagarajan struct ath6kl_fw_recovery { 81284caf800SVasanthakumar Thiagarajan struct work_struct recovery_work; 81384caf800SVasanthakumar Thiagarajan unsigned long err_reason; 81492332993SVasanthakumar Thiagarajan unsigned long hb_poll; 81592332993SVasanthakumar Thiagarajan struct timer_list hb_timer; 81692332993SVasanthakumar Thiagarajan u32 seq_num; 81792332993SVasanthakumar Thiagarajan bool hb_pending; 81892332993SVasanthakumar Thiagarajan u8 hb_misscnt; 81966ddcc39SVasanthakumar Thiagarajan bool enable; 82084caf800SVasanthakumar Thiagarajan } fw_recovery; 82184caf800SVasanthakumar Thiagarajan 822bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 823bdf5396bSKalle Valo struct { 8249b9a4f2aSKalle Valo struct sk_buff_head fwlog_queue; 825c807b30dSKalle Valo struct completion fwlog_completion; 826c807b30dSKalle Valo bool fwlog_open; 827c807b30dSKalle Valo 828939f1cceSKalle Valo u32 fwlog_mask; 8299b9a4f2aSKalle Valo 83091d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 831252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 832252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 8339a730834SKalle Valo 8349a730834SKalle Valo struct { 8359a730834SKalle Valo unsigned int invalid_rate; 8369a730834SKalle Valo } war_stats; 8374b28a80dSJouni Malinen 8384b28a80dSJouni Malinen u8 *roam_tbl; 8394b28a80dSJouni Malinen unsigned int roam_tbl_len; 840ff0b0075SJouni Malinen 841ff0b0075SJouni Malinen u8 keepalive; 842ff0b0075SJouni Malinen u8 disc_timeout; 843bdf5396bSKalle Valo } debug; 844bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 845bdcd8170SKalle Valo }; 846bdcd8170SKalle Valo 847d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 848bdcd8170SKalle Valo { 849108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 850bdcd8170SKalle Valo } 851bdcd8170SKalle Valo 852bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 853bc07ddb2SKalle Valo u32 item_offset) 854bc07ddb2SKalle Valo { 855bc07ddb2SKalle Valo u32 addr = 0; 856bc07ddb2SKalle Valo 857bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 858bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 859bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 860bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 861bc07ddb2SKalle Valo 862bc07ddb2SKalle Valo return addr; 863bc07ddb2SKalle Valo } 864bc07ddb2SKalle Valo 865bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 866bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 867bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 868bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 869bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 870bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 871bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 87263de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context, 87363de1112SKalle Valo struct list_head *packet_queue); 874bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 875bdcd8170SKalle Valo struct htc_packet *packet); 876bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 877bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 878f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 879addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 880addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 881addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 882bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 883e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 884bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 885bdcd8170SKalle Valo 886bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 887bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 888bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 889bdcd8170SKalle Valo 8907baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 891c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info, 892c8651541SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn); 893bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 894bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 895bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 896bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 897bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 898bdcd8170SKalle Valo int len); 899bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 9001d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn); 901bdcd8170SKalle Valo 9026765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr); 903bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 904bdcd8170SKalle Valo 905d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver, 906d92917e4SThomas Pedersen enum wmi_phy_cap cap); 907bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 908bdcd8170SKalle Valo enum htc_endpoint_id eid); 909240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 910bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 911bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 912bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 913bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 914240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 915240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 916572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 917c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 918240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 919bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 920bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 921240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 922bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 923240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 924240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 925bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 926bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 927bdcd8170SKalle Valo 928240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 929bdcd8170SKalle Valo 930240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 931240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 932240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 933240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 934bdcd8170SKalle Valo u8 win_sz); 935bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 936bdcd8170SKalle Valo 9376db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type, 9386db8fa53SVasanthakumar Thiagarajan bool wait_fot_compltn, bool cold_reset); 939e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 940990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 94155055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready); 9425fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 9435fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 94445eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 94545eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 94645eaa78fSKalle Valo 947a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 9485fe4dffbSKalle Valo 949636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb); 950636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe); 951636f8288SKalle Valo 95245eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 953e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type); 95445eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 95545eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 95645eaa78fSKalle Valo 95784caf800SVasanthakumar Thiagarajan /* Fw error recovery */ 95884caf800SVasanthakumar Thiagarajan void ath6kl_init_hw_restart(struct ath6kl *ar); 95984caf800SVasanthakumar Thiagarajan void ath6kl_recovery_err_notify(struct ath6kl *ar, enum ath6kl_fw_err reason); 96092332993SVasanthakumar Thiagarajan void ath6kl_recovery_hb_event(struct ath6kl *ar, u32 cookie); 96184caf800SVasanthakumar Thiagarajan void ath6kl_recovery_init(struct ath6kl *ar); 96284caf800SVasanthakumar Thiagarajan void ath6kl_recovery_cleanup(struct ath6kl *ar); 96384caf800SVasanthakumar Thiagarajan void ath6kl_recovery_suspend(struct ath6kl *ar); 96492332993SVasanthakumar Thiagarajan void ath6kl_recovery_resume(struct ath6kl *ar); 965bdcd8170SKalle Valo #endif /* CORE_H */ 966