1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef CORE_H 19bdcd8170SKalle Valo #define CORE_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #include <linux/etherdevice.h> 22bdcd8170SKalle Valo #include <linux/rtnetlink.h> 23bdcd8170SKalle Valo #include <linux/firmware.h> 24bdcd8170SKalle Valo #include <linux/sched.h> 25bdf5396bSKalle Valo #include <linux/circ_buf.h> 26bdcd8170SKalle Valo #include <net/cfg80211.h> 27bdcd8170SKalle Valo #include "htc.h" 28bdcd8170SKalle Valo #include "wmi.h" 29bdcd8170SKalle Valo #include "bmi.h" 30bc07ddb2SKalle Valo #include "target.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define MAX_ATH6KL 1 33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 46bdcd8170SKalle Valo #define MAX_NODE_NUM 15 47bdcd8170SKalle Valo 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 51c1762a3fSThirumalai Pachamuthu 521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 541df94a85SVasanthakumar Thiagarajan 55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 58bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 59bdcd8170SKalle Valo 60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 63bdcd8170SKalle Valo 6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */ 6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */ 6613423c31SVasanthakumar Thiagarajan 6750d41234SKalle Valo /* includes also the null byte */ 6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6950d41234SKalle Valo 7050d41234SKalle Valo enum ath6kl_fw_ie_type { 7150d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7250d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7350d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7450d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7550d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 768a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7797e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 781b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7903ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 80368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 8150d41234SKalle Valo }; 8250d41234SKalle Valo 8397e0496dSKalle Valo enum ath6kl_fw_capability { 8497e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8510509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8697e0496dSKalle Valo 873ca9d1fcSAarthi Thiruvengadam /* 883ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 893ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 903ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 913ca9d1fcSAarthi Thiruvengadam */ 923ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 933ca9d1fcSAarthi Thiruvengadam 9403bdeb0dSVasanthakumar Thiagarajan /* 9503bdeb0dSVasanthakumar Thiagarajan * Firmware has support to cleanup inactive stations 9603bdeb0dSVasanthakumar Thiagarajan * in AP mode. 9703bdeb0dSVasanthakumar Thiagarajan */ 9803bdeb0dSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT, 9903bdeb0dSVasanthakumar Thiagarajan 100d97c121bSVasanthakumar Thiagarajan /* Firmware has support to override rsn cap of rsn ie */ 101d97c121bSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, 102d97c121bSVasanthakumar Thiagarajan 1036821d4f0SNaveen Gangadharan /* 1046821d4f0SNaveen Gangadharan * Multicast support in WOW and host awake mode. 1056821d4f0SNaveen Gangadharan * Allow all multicast in host awake mode. 1066821d4f0SNaveen Gangadharan * Apply multicast filter in WOW mode. 1076821d4f0SNaveen Gangadharan */ 1086821d4f0SNaveen Gangadharan ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER, 1096821d4f0SNaveen Gangadharan 110c422d52dSThomas Pedersen /* Firmware supports enhanced bmiss detection */ 111c422d52dSThomas Pedersen ATH6KL_FW_CAPABILITY_BMISS_ENHANCE, 112c422d52dSThomas Pedersen 113dd45b759SNaveen Singh /* 114dd45b759SNaveen Singh * FW supports matching of ssid in schedule scan 115dd45b759SNaveen Singh */ 116dd45b759SNaveen Singh ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST, 117dd45b759SNaveen Singh 11885b20fc2SThomas Pedersen /* Firmware supports filtering BSS results by RSSI */ 11985b20fc2SThomas Pedersen ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD, 12085b20fc2SThomas Pedersen 121c95dcb59SAarthi Thiruvengadam /* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */ 122c95dcb59SAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR, 123c95dcb59SAarthi Thiruvengadam 124279b2862SThomas Pedersen /* Firmware supports TX error rate notification */ 125279b2862SThomas Pedersen ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY, 126279b2862SThomas Pedersen 12784841ba2SKalle Valo /* supports WMI_SET_REGDOMAIN_CMDID command */ 12884841ba2SKalle Valo ATH6KL_FW_CAPABILITY_REGDOMAIN, 12984841ba2SKalle Valo 130b1f47e3aSThomas Pedersen /* Firmware supports sched scan decoupled from host sleep */ 131b1f47e3aSThomas Pedersen ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2, 132b1f47e3aSThomas Pedersen 13392332993SVasanthakumar Thiagarajan /* 13492332993SVasanthakumar Thiagarajan * Firmware capability for hang detection through heart beat 13592332993SVasanthakumar Thiagarajan * challenge messages. 13692332993SVasanthakumar Thiagarajan */ 13792332993SVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL, 13892332993SVasanthakumar Thiagarajan 139eba95bceSKalle Valo /* WMI_SET_TX_SELECT_RATES_CMDID uses 64 bit size rate table */ 140eba95bceSKalle Valo ATH6KL_FW_CAPABILITY_64BIT_RATES, 141eba95bceSKalle Valo 142eba95bceSKalle Valo /* WMI_AP_CONN_INACT_CMDID uses minutes as units */ 143eba95bceSKalle Valo ATH6KL_FW_CAPABILITY_AP_INACTIVITY_MINS, 144eba95bceSKalle Valo 145eba95bceSKalle Valo /* use low priority endpoint for all data */ 146eba95bceSKalle Valo ATH6KL_FW_CAPABILITY_MAP_LP_ENDPOINT, 147eba95bceSKalle Valo 148c1d32d30SJessica Wu /* ratetable is the 2 stream version (max MCS15) */ 149c1d32d30SJessica Wu ATH6KL_FW_CAPABILITY_RATETABLE_MCS15, 150c1d32d30SJessica Wu 15178803770SJessica Wu /* firmare doesn't support IP checksumming */ 15278803770SJessica Wu ATH6KL_FW_CAPABILITY_NO_IP_CHECKSUM, 15378803770SJessica Wu 15497e0496dSKalle Valo /* this needs to be last */ 15597e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 15697e0496dSKalle Valo }; 15797e0496dSKalle Valo 15897e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 15997e0496dSKalle Valo 16050d41234SKalle Valo struct ath6kl_fw_ie { 16150d41234SKalle Valo __le32 id; 16250d41234SKalle Valo __le32 len; 16350d41234SKalle Valo u8 data[0]; 16450d41234SKalle Valo }; 16550d41234SKalle Valo 16606e360acSBala Shanmugam enum ath6kl_hw_flags { 167a2e1be33SMohammed Shafi Shajakhan ATH6KL_HW_SDIO_CRC_ERROR_WAR = BIT(3), 16806e360acSBala Shanmugam }; 16906e360acSBala Shanmugam 170c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 17165a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 172b1f47e3aSThomas Pedersen #define ATH6KL_FW_API4_FILE "fw-4.bin" 17378803770SJessica Wu #define ATH6KL_FW_API5_FILE "fw-5.bin" 174c0038972SKalle Valo 175bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1760d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 177bdcd8170SKalle Valo 178bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1790d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1800d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 181c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 182c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 183c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 184c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 185c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1862023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin" 1870d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1882023dbb8STim Gardner AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin" 189bdcd8170SKalle Valo 190bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1910d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 192c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 193c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 194c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 195c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 196cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 197cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 198c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1992023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin" 2000d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 2012023dbb8STim Gardner AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin" 202bdcd8170SKalle Valo 20331024d99SKevin Fang /* AR6004 1.0 definitions */ 2040d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 205c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 206c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 2072023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin" 2080d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 2092023dbb8STim Gardner AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin" 210d5720e59SKalle Valo 211d5720e59SKalle Valo /* AR6004 1.1 definitions */ 2120d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 213c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 214c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 2152023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin" 2160d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 2172023dbb8STim Gardner AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin" 21831024d99SKevin Fang 2196146ca69SRay Chen /* AR6004 1.2 definitions */ 2206146ca69SRay Chen #define AR6004_HW_1_2_VERSION 0x300007e8 2216146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2" 2226146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin" 2232023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin" 2246146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \ 2252023dbb8STim Gardner AR6004_HW_1_2_FW_DIR "/bdata.bin" 2266146ca69SRay Chen 227bf744f11SBala Shanmugam /* AR6004 1.3 definitions */ 228bf744f11SBala Shanmugam #define AR6004_HW_1_3_VERSION 0x31c8088a 229bf744f11SBala Shanmugam #define AR6004_HW_1_3_FW_DIR "ath6k/AR6004/hw1.3" 230bf744f11SBala Shanmugam #define AR6004_HW_1_3_FIRMWARE_FILE "fw.ram.bin" 23178803770SJessica Wu #define AR6004_HW_1_3_TCMD_FIRMWARE_FILE "utf.bin" 23278803770SJessica Wu #define AR6004_HW_1_3_UTF_FIRMWARE_FILE "utf.bin" 23378803770SJessica Wu #define AR6004_HW_1_3_TESTSCRIPT_FILE "nullTestFlow.bin" 23478803770SJessica Wu #define AR6004_HW_1_3_BOARD_DATA_FILE AR6004_HW_1_3_FW_DIR "/bdata.bin" 23578803770SJessica Wu #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE AR6004_HW_1_3_FW_DIR "/bdata.bin" 23678803770SJessica Wu 23778803770SJessica Wu /* AR6004 3.0 definitions */ 23878803770SJessica Wu #define AR6004_HW_3_0_VERSION 0x31C809F8 23978803770SJessica Wu #define AR6004_HW_3_0_FW_DIR "ath6k/AR6004/hw3.0" 24078803770SJessica Wu #define AR6004_HW_3_0_FIRMWARE_FILE "fw.ram.bin" 24178803770SJessica Wu #define AR6004_HW_3_0_TCMD_FIRMWARE_FILE "utf.bin" 24278803770SJessica Wu #define AR6004_HW_3_0_UTF_FIRMWARE_FILE "utf.bin" 24378803770SJessica Wu #define AR6004_HW_3_0_TESTSCRIPT_FILE "nullTestFlow.bin" 24478803770SJessica Wu #define AR6004_HW_3_0_BOARD_DATA_FILE AR6004_HW_3_0_FW_DIR "/bdata.bin" 24578803770SJessica Wu #define AR6004_HW_3_0_DEFAULT_BOARD_DATA_FILE AR6004_HW_3_0_FW_DIR "/bdata.bin" 246bf744f11SBala Shanmugam 247bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 248bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 249bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 250bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 251c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 252c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 253bdcd8170SKalle Valo 254bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 255bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 256bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 257bdcd8170SKalle Valo 258bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 259bdcd8170SKalle Valo 260bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 261bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 262bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 263bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 264bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 265bdcd8170SKalle Valo 266bdcd8170SKalle Valo #define NUM_OF_TIDS 8 267bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 268bdcd8170SKalle Valo 269bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 270bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 271bdcd8170SKalle Valo 272bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 275bdcd8170SKalle Valo 2767940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT 100 /* in ms */ 277bdcd8170SKalle Valo 278bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 279bdcd8170SKalle Valo 280bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 281bdcd8170SKalle Valo 2828f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */ 283ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME 1500 284ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */ 285ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME 5000 2868f46fccdSRaja Mani 287bdcd8170SKalle Valo /* configuration lags */ 288bdcd8170SKalle Valo /* 289bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 290bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 291bdcd8170SKalle Valo * sending (Re)Assoc req. 292bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 293bdcd8170SKalle Valo * module state transition failure events which happen during 294bdcd8170SKalle Valo * scan, to the host. 295bdcd8170SKalle Valo */ 296bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 297bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 298bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 299bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 300e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG BIT(4) 301bdcd8170SKalle Valo 302c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */ 303c86e4f44SAarthi Thiruvengadam 304bdcd8170SKalle Valo enum wlan_low_pwr_state { 305bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 306bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 307bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 308bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 309bdcd8170SKalle Valo }; 310bdcd8170SKalle Valo 311bdcd8170SKalle Valo enum sme_state { 312bdcd8170SKalle Valo SME_DISCONNECTED, 313bdcd8170SKalle Valo SME_CONNECTING, 314bdcd8170SKalle Valo SME_CONNECTED 315bdcd8170SKalle Valo }; 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo struct skb_hold_q { 318bdcd8170SKalle Valo struct sk_buff *skb; 319bdcd8170SKalle Valo bool is_amsdu; 320bdcd8170SKalle Valo u16 seq_no; 321bdcd8170SKalle Valo }; 322bdcd8170SKalle Valo 323bdcd8170SKalle Valo struct rxtid { 324bdcd8170SKalle Valo bool aggr; 325bdcd8170SKalle Valo bool timer_mon; 326bdcd8170SKalle Valo u16 win_sz; 327bdcd8170SKalle Valo u16 seq_next; 328bdcd8170SKalle Valo u32 hold_q_sz; 329bdcd8170SKalle Valo struct skb_hold_q *hold_q; 330bdcd8170SKalle Valo struct sk_buff_head q; 33112eb9444SKalle Valo 33212eb9444SKalle Valo /* 3330faf7458SVasanthakumar Thiagarajan * lock mainly protects seq_next and hold_q. Movement of seq_next 3340faf7458SVasanthakumar Thiagarajan * needs to be protected between aggr_timeout() and 3350faf7458SVasanthakumar Thiagarajan * aggr_process_recv_frm(). hold_q will be holding the pending 3360faf7458SVasanthakumar Thiagarajan * reorder frames and it's access should also be protected. 3370faf7458SVasanthakumar Thiagarajan * Some of the other fields like hold_q_sz, win_sz and aggr are 3380faf7458SVasanthakumar Thiagarajan * initialized/reset when receiving addba/delba req, also while 3390faf7458SVasanthakumar Thiagarajan * deleting aggr state all the pending buffers are flushed before 3400faf7458SVasanthakumar Thiagarajan * resetting these fields, so there should not be any race in accessing 3410faf7458SVasanthakumar Thiagarajan * these fields. 34212eb9444SKalle Valo */ 343bdcd8170SKalle Valo spinlock_t lock; 344bdcd8170SKalle Valo }; 345bdcd8170SKalle Valo 346bdcd8170SKalle Valo struct rxtid_stats { 347bdcd8170SKalle Valo u32 num_into_aggr; 348bdcd8170SKalle Valo u32 num_dups; 349bdcd8170SKalle Valo u32 num_oow; 350bdcd8170SKalle Valo u32 num_mpdu; 351bdcd8170SKalle Valo u32 num_amsdu; 352bdcd8170SKalle Valo u32 num_delivered; 353bdcd8170SKalle Valo u32 num_timeouts; 354bdcd8170SKalle Valo u32 num_hole; 355bdcd8170SKalle Valo u32 num_bar; 356bdcd8170SKalle Valo }; 357bdcd8170SKalle Valo 3587baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 359bdcd8170SKalle Valo u8 aggr_sz; 360bdcd8170SKalle Valo u8 timer_scheduled; 361bdcd8170SKalle Valo struct timer_list timer; 362bdcd8170SKalle Valo struct net_device *dev; 363bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 364bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 3657baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 3667baef812SVasanthakumar Thiagarajan }; 3677baef812SVasanthakumar Thiagarajan 3687baef812SVasanthakumar Thiagarajan struct aggr_info { 3697baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 3707baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 371bdcd8170SKalle Valo }; 372bdcd8170SKalle Valo 373bdcd8170SKalle Valo struct ath6kl_wep_key { 374bdcd8170SKalle Valo u8 key_index; 375bdcd8170SKalle Valo u8 key_len; 376bdcd8170SKalle Valo u8 key[64]; 377bdcd8170SKalle Valo }; 378bdcd8170SKalle Valo 379bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 380bdcd8170SKalle Valo 381bdcd8170SKalle Valo struct ath6kl_key { 382bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 383bdcd8170SKalle Valo u8 key_len; 384bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 385bdcd8170SKalle Valo u8 seq_len; 386bdcd8170SKalle Valo u32 cipher; 387bdcd8170SKalle Valo }; 388bdcd8170SKalle Valo 389bdcd8170SKalle Valo struct ath6kl_node_mapping { 390bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 391bdcd8170SKalle Valo u8 ep_id; 392bdcd8170SKalle Valo u8 tx_pend; 393bdcd8170SKalle Valo }; 394bdcd8170SKalle Valo 395bdcd8170SKalle Valo struct ath6kl_cookie { 396bdcd8170SKalle Valo struct sk_buff *skb; 397bdcd8170SKalle Valo u32 map_no; 398bdcd8170SKalle Valo struct htc_packet htc_pkt; 399bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 400bdcd8170SKalle Valo }; 401bdcd8170SKalle Valo 402d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff { 403d0ff7383SNaveen Gangadharan struct list_head list; 404d0ff7383SNaveen Gangadharan u32 freq; 405d0ff7383SNaveen Gangadharan u32 wait; 406d0ff7383SNaveen Gangadharan u32 id; 407d0ff7383SNaveen Gangadharan bool no_cck; 408d0ff7383SNaveen Gangadharan size_t len; 409d0ff7383SNaveen Gangadharan u8 buf[0]; 410d0ff7383SNaveen Gangadharan }; 411d0ff7383SNaveen Gangadharan 412bdcd8170SKalle Valo struct ath6kl_sta { 413bdcd8170SKalle Valo u16 sta_flags; 414bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 415bdcd8170SKalle Valo u8 aid; 416bdcd8170SKalle Valo u8 keymgmt; 417bdcd8170SKalle Valo u8 ucipher; 418bdcd8170SKalle Valo u8 auth; 419bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 420bdcd8170SKalle Valo struct sk_buff_head psq; 42112eb9444SKalle Valo 42212eb9444SKalle Valo /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */ 423bdcd8170SKalle Valo spinlock_t psq_lock; 42412eb9444SKalle Valo 425d0ff7383SNaveen Gangadharan struct list_head mgmt_psq; 426d0ff7383SNaveen Gangadharan size_t mgmt_psq_len; 427c1762a3fSThirumalai Pachamuthu u8 apsd_info; 428c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 4291d2a4456SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 430bdcd8170SKalle Valo }; 431bdcd8170SKalle Valo 432bdcd8170SKalle Valo struct ath6kl_version { 433bdcd8170SKalle Valo u32 target_ver; 434bdcd8170SKalle Valo u32 wlan_ver; 435bdcd8170SKalle Valo u32 abi_ver; 436bdcd8170SKalle Valo }; 437bdcd8170SKalle Valo 438bdcd8170SKalle Valo struct ath6kl_bmi { 439bdcd8170SKalle Valo u32 cmd_credits; 440bdcd8170SKalle Valo bool done_sent; 441bdcd8170SKalle Valo u8 *cmd_buf; 4421f4c894dSKalle Valo u32 max_data_size; 4431f4c894dSKalle Valo u32 max_cmd_size; 444bdcd8170SKalle Valo }; 445bdcd8170SKalle Valo 446bdcd8170SKalle Valo struct target_stats { 447bdcd8170SKalle Valo u64 tx_pkt; 448bdcd8170SKalle Valo u64 tx_byte; 449bdcd8170SKalle Valo u64 tx_ucast_pkt; 450bdcd8170SKalle Valo u64 tx_ucast_byte; 451bdcd8170SKalle Valo u64 tx_mcast_pkt; 452bdcd8170SKalle Valo u64 tx_mcast_byte; 453bdcd8170SKalle Valo u64 tx_bcast_pkt; 454bdcd8170SKalle Valo u64 tx_bcast_byte; 455bdcd8170SKalle Valo u64 tx_rts_success_cnt; 456bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 457bdcd8170SKalle Valo 458bdcd8170SKalle Valo u64 tx_err; 459bdcd8170SKalle Valo u64 tx_fail_cnt; 460bdcd8170SKalle Valo u64 tx_retry_cnt; 461bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 462bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 463bdcd8170SKalle Valo 464bdcd8170SKalle Valo u64 rx_pkt; 465bdcd8170SKalle Valo u64 rx_byte; 466bdcd8170SKalle Valo u64 rx_ucast_pkt; 467bdcd8170SKalle Valo u64 rx_ucast_byte; 468bdcd8170SKalle Valo u64 rx_mcast_pkt; 469bdcd8170SKalle Valo u64 rx_mcast_byte; 470bdcd8170SKalle Valo u64 rx_bcast_pkt; 471bdcd8170SKalle Valo u64 rx_bcast_byte; 472bdcd8170SKalle Valo u64 rx_frgment_pkt; 473bdcd8170SKalle Valo 474bdcd8170SKalle Valo u64 rx_err; 475bdcd8170SKalle Valo u64 rx_crc_err; 476bdcd8170SKalle Valo u64 rx_key_cache_miss; 477bdcd8170SKalle Valo u64 rx_decrypt_err; 478bdcd8170SKalle Valo u64 rx_dupl_frame; 479bdcd8170SKalle Valo 480bdcd8170SKalle Valo u64 tkip_local_mic_fail; 481bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 482bdcd8170SKalle Valo u64 tkip_replays; 483bdcd8170SKalle Valo u64 tkip_fmt_err; 484bdcd8170SKalle Valo u64 ccmp_fmt_err; 485bdcd8170SKalle Valo u64 ccmp_replays; 486bdcd8170SKalle Valo 487bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 488bdcd8170SKalle Valo 489bdcd8170SKalle Valo u64 cs_bmiss_cnt; 490bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 491bdcd8170SKalle Valo u64 cs_connect_cnt; 492bdcd8170SKalle Valo u64 cs_discon_cnt; 493bdcd8170SKalle Valo 494bdcd8170SKalle Valo s32 tx_ucast_rate; 495bdcd8170SKalle Valo s32 rx_ucast_rate; 496bdcd8170SKalle Valo 497bdcd8170SKalle Valo u32 lq_val; 498bdcd8170SKalle Valo 499bdcd8170SKalle Valo u32 wow_pkt_dropped; 500bdcd8170SKalle Valo u16 wow_evt_discarded; 501bdcd8170SKalle Valo 502bdcd8170SKalle Valo s16 noise_floor_calib; 503bdcd8170SKalle Valo s16 cs_rssi; 504bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 505bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 506bdcd8170SKalle Valo u8 cs_last_roam_msec; 507bdcd8170SKalle Valo u8 cs_snr; 508bdcd8170SKalle Valo 509bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 510bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 511bdcd8170SKalle Valo 512bdcd8170SKalle Valo u32 arp_received; 513bdcd8170SKalle Valo u32 arp_matched; 514bdcd8170SKalle Valo u32 arp_replied; 515bdcd8170SKalle Valo }; 516bdcd8170SKalle Valo 517bdcd8170SKalle Valo struct ath6kl_mbox_info { 518bdcd8170SKalle Valo u32 htc_addr; 519bdcd8170SKalle Valo u32 htc_ext_addr; 520bdcd8170SKalle Valo u32 htc_ext_sz; 521bdcd8170SKalle Valo 522bdcd8170SKalle Valo u32 block_size; 523bdcd8170SKalle Valo 524bdcd8170SKalle Valo u32 gmbox_addr; 525bdcd8170SKalle Valo 526bdcd8170SKalle Valo u32 gmbox_sz; 527bdcd8170SKalle Valo }; 528bdcd8170SKalle Valo 529bdcd8170SKalle Valo /* 530bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 531bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 532bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 533bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 534bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 535bdcd8170SKalle Valo */ 536bdcd8170SKalle Valo 537bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 538bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 539bdcd8170SKalle Valo 540bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 541bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 542bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 543bdcd8170SKalle Valo 5449a5b1318SJouni Malinen /* Initial group key for AP mode */ 545bdcd8170SKalle Valo struct ath6kl_req_key { 5469a5b1318SJouni Malinen bool valid; 5479a5b1318SJouni Malinen u8 key_index; 5489a5b1318SJouni Malinen int key_type; 5499a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 5509a5b1318SJouni Malinen u8 key_len; 551bdcd8170SKalle Valo }; 552bdcd8170SKalle Valo 55377eab1e9SKalle Valo enum ath6kl_hif_type { 55477eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 55577eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 55677eab1e9SKalle Valo }; 55777eab1e9SKalle Valo 558e76ac2bfSKalle Valo enum ath6kl_htc_type { 559e76ac2bfSKalle Valo ATH6KL_HTC_TYPE_MBOX, 560636f8288SKalle Valo ATH6KL_HTC_TYPE_PIPE, 561e76ac2bfSKalle Valo }; 562e76ac2bfSKalle Valo 56380abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 56480abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 56580abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 56680abaf9bSVasanthakumar Thiagarajan struct list_head list; 56780abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 56880abaf9bSVasanthakumar Thiagarajan }; 56980abaf9bSVasanthakumar Thiagarajan 570df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap { 571df90b369SVasanthakumar Thiagarajan bool ht_enable; 572df90b369SVasanthakumar Thiagarajan u8 ampdu_factor; 573df90b369SVasanthakumar Thiagarajan unsigned short cap_info; 574df90b369SVasanthakumar Thiagarajan }; 575df90b369SVasanthakumar Thiagarajan 57671f96ee6SKalle Valo /* 57771f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 57871f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 57971f96ee6SKalle Valo */ 580b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 581334234b5SVasanthakumar Thiagarajan 58259c98449SVasanthakumar Thiagarajan /* vif flags info */ 58359c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 58459c98449SVasanthakumar Thiagarajan CONNECTED, 58559c98449SVasanthakumar Thiagarajan CONNECT_PEND, 58659c98449SVasanthakumar Thiagarajan WMM_ENABLED, 58759c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 58859c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 58959c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 59059c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 59159c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 592b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 593081c7a84SRaja Mani HOST_SLEEP_MODE_CMD_PROCESSED, 5946251d801SNaveen Gangadharan NETDEV_MCAST_ALL_ON, 5956251d801SNaveen Gangadharan NETDEV_MCAST_ALL_OFF, 596b1f47e3aSThomas Pedersen SCHED_SCANNING, 59759c98449SVasanthakumar Thiagarajan }; 59859c98449SVasanthakumar Thiagarajan 599108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 600990bd915SVasanthakumar Thiagarajan struct list_head list; 601108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 602108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 603108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 604478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 605478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 606334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 60759c98449SVasanthakumar Thiagarajan unsigned long flags; 6083450334fSVasanthakumar Thiagarajan int ssid_len; 6093450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 6103450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 6113450334fSVasanthakumar Thiagarajan u8 auth_mode; 6123450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 6133450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 6143450334fSVasanthakumar Thiagarajan u8 grp_crypto; 6153450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 6163450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 617f5938f24SVasanthakumar Thiagarajan u8 next_mode; 618f5938f24SVasanthakumar Thiagarajan u8 nw_type; 6198c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 6208c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 621f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 622f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 6236f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 6246f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 6252132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 62667b3f129SKiran Reddy struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS]; 62710509f90SKalle Valo 628de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 62910509f90SKalle Valo struct timer_list sched_scan_timer; 63010509f90SKalle Valo 63114ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 63214ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 633cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 6341052261eSJouni Malinen u32 last_roc_id; 6351052261eSJouni Malinen u32 last_cancel_roc_id; 636cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 637cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 638cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 6398f46fccdSRaja Mani u16 listen_intvl_t; 640ce0dc0cfSRaja Mani u16 bmiss_time_t; 641279b2862SThomas Pedersen u32 txe_intvl; 642eb38987eSRaja Mani u16 bg_scan_period; 643cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 644b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 645b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 646c4f7863eSThomas Pedersen struct wmi_connect_cmd profile; 647f21243a8SThomas Pedersen u16 rsn_capab; 64880abaf9bSVasanthakumar Thiagarajan 64980abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 650108438bcSVasanthakumar Thiagarajan }; 651108438bcSVasanthakumar Thiagarajan 65271bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev) 65371bbc994SJohannes Berg { 65471bbc994SJohannes Berg return container_of(wdev, struct ath6kl_vif, wdev); 65571bbc994SJohannes Berg } 65671bbc994SJohannes Berg 6576cb3c714SRaja Mani #define WOW_LIST_ID 0 6586cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 6596cb3c714SRaja Mani 66010509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 66110509f90SKalle Valo 662bdcd8170SKalle Valo /* Flag info */ 66359c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 66459c98449SVasanthakumar Thiagarajan WMI_ENABLED, 66559c98449SVasanthakumar Thiagarajan WMI_READY, 66659c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 66759c98449SVasanthakumar Thiagarajan TESTMODE, 66859c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 66959c98449SVasanthakumar Thiagarajan SKIP_SCAN, 67059c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 6715fe4dffbSKalle Valo FIRST_BOOT, 672a3561706SVasanthakumar Thiagarajan RECOVERY_CLEANUP, 67359c98449SVasanthakumar Thiagarajan }; 674bdcd8170SKalle Valo 67576a9fbe2SKalle Valo enum ath6kl_state { 67676a9fbe2SKalle Valo ATH6KL_STATE_OFF, 67776a9fbe2SKalle Valo ATH6KL_STATE_ON, 678390a8c8fSRaja Mani ATH6KL_STATE_SUSPENDING, 679390a8c8fSRaja Mani ATH6KL_STATE_RESUMING, 68076a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 681b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 682dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 68384caf800SVasanthakumar Thiagarajan ATH6KL_STATE_RECOVERY, 68484caf800SVasanthakumar Thiagarajan }; 68584caf800SVasanthakumar Thiagarajan 68684caf800SVasanthakumar Thiagarajan /* Fw error recovery */ 68792332993SVasanthakumar Thiagarajan #define ATH6KL_HB_RESP_MISS_THRES 5 68892332993SVasanthakumar Thiagarajan 68984caf800SVasanthakumar Thiagarajan enum ath6kl_fw_err { 69084caf800SVasanthakumar Thiagarajan ATH6KL_FW_ASSERT, 69192332993SVasanthakumar Thiagarajan ATH6KL_FW_HB_RESP_FAILURE, 69277565794SVasanthakumar Thiagarajan ATH6KL_FW_EP_FULL, 69376a9fbe2SKalle Valo }; 69476a9fbe2SKalle Valo 695bdcd8170SKalle Valo struct ath6kl { 696bdcd8170SKalle Valo struct device *dev; 697be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 69876a9fbe2SKalle Valo 69976a9fbe2SKalle Valo enum ath6kl_state state; 7005f1127ffSKalle Valo unsigned int testmode; 70176a9fbe2SKalle Valo 702bdcd8170SKalle Valo struct ath6kl_bmi bmi; 703bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 704e76ac2bfSKalle Valo const struct ath6kl_htc_ops *htc_ops; 705bdcd8170SKalle Valo struct wmi *wmi; 706bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 707bdcd8170SKalle Valo int total_tx_data_pend; 708bdcd8170SKalle Valo struct htc_target *htc_target; 70977eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 710bdcd8170SKalle Valo void *hif_priv; 711990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 712990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 713990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 71455055976SVasanthakumar Thiagarajan u8 num_vif; 715368b1b0fSKalle Valo unsigned int vif_max; 7163226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 71755055976SVasanthakumar Thiagarajan u8 avail_idx_map; 71812eb9444SKalle Valo 71912eb9444SKalle Valo /* 72012eb9444SKalle Valo * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie() 72112eb9444SKalle Valo * calls, tx_pending and total_tx_data_pend. 72212eb9444SKalle Valo */ 723bdcd8170SKalle Valo spinlock_t lock; 72412eb9444SKalle Valo 725bdcd8170SKalle Valo struct semaphore sem; 726e5090444SVivek Natarajan u8 lrssi_roam_threshold; 727bdcd8170SKalle Valo struct ath6kl_version version; 728bdcd8170SKalle Valo u32 target_type; 729bdcd8170SKalle Valo u8 tx_pwr; 730bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 731bdcd8170SKalle Valo u8 ibss_ps_enable; 73255055976SVasanthakumar Thiagarajan bool ibss_if_active; 733bdcd8170SKalle Valo u8 node_num; 734bdcd8170SKalle Valo u8 next_ep_id; 735bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 736bdcd8170SKalle Valo u32 cookie_count; 737bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 738bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 739bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 740bdcd8170SKalle Valo u8 hiac_stream_active_pri; 741bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 742bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 7433c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 744bdcd8170SKalle Valo u32 connect_ctrl_flags; 745bdcd8170SKalle Valo u32 user_key_ctrl; 746bdcd8170SKalle Valo u8 usr_bss_filter; 747bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 748bdcd8170SKalle Valo u8 sta_list_index; 749bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 750bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 751c4f7863eSThomas Pedersen u32 want_ch_switch; 752b5495e66SThomas Pedersen u16 last_ch; 75312eb9444SKalle Valo 75412eb9444SKalle Valo /* 75512eb9444SKalle Valo * FIXME: protects access to mcastpsq but is actually useless as 75612eb9444SKalle Valo * all skbe_queue_*() functions provide serialisation themselves 75712eb9444SKalle Valo */ 758bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 75912eb9444SKalle Valo 760bdcd8170SKalle Valo u8 intra_bss; 761bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 762bdcd8170SKalle Valo u8 ap_country_code[3]; 763bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 764bdcd8170SKalle Valo u8 rx_meta_ver; 765bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 766d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 767bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 768003353b0SKalle Valo struct { 769003353b0SKalle Valo void *rx_report; 770003353b0SKalle Valo size_t rx_report_len; 771003353b0SKalle Valo } tm; 772003353b0SKalle Valo 773856f4b31SKalle Valo struct ath6kl_hw { 774856f4b31SKalle Valo u32 id; 775293badf4SKalle Valo const char *name; 776a01ac414SKalle Valo u32 dataset_patch_addr; 777a01ac414SKalle Valo u32 app_load_addr; 778a01ac414SKalle Valo u32 app_start_override_addr; 779991b27eaSKalle Valo u32 board_ext_data_addr; 780991b27eaSKalle Valo u32 reserved_ram_size; 7810d4d72bfSKalle Valo u32 board_addr; 78239586bf2SRyan Hsu u32 refclk_hz; 78339586bf2SRyan Hsu u32 uarttx_pin; 784cd23c1c9SAlex Yang u32 testscript_addr; 785d92917e4SThomas Pedersen enum wmi_phy_cap cap; 786d1a9421dSKalle Valo 78706e360acSBala Shanmugam u32 flags; 78806e360acSBala Shanmugam 789c0038972SKalle Valo struct ath6kl_hw_fw { 790c0038972SKalle Valo const char *dir; 791c0038972SKalle Valo const char *otp; 792d1a9421dSKalle Valo const char *fw; 793c0038972SKalle Valo const char *tcmd; 794c0038972SKalle Valo const char *patch; 795cd23c1c9SAlex Yang const char *utf; 796cd23c1c9SAlex Yang const char *testscript; 797c0038972SKalle Valo } fw; 798c0038972SKalle Valo 799d1a9421dSKalle Valo const char *fw_board; 800d1a9421dSKalle Valo const char *fw_default_board; 801a01ac414SKalle Valo } hw; 802a01ac414SKalle Valo 803bdcd8170SKalle Valo u16 conf_flags; 804e390af77SRaja Mani u16 suspend_mode; 8051e9a905dSRaja Mani u16 wow_suspend_mode; 806bdcd8170SKalle Valo wait_queue_head_t event_wq; 807bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 808bdcd8170SKalle Valo 809bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 810bdcd8170SKalle Valo unsigned long flag; 811bdcd8170SKalle Valo 812bdcd8170SKalle Valo u8 *fw_board; 813bdcd8170SKalle Valo size_t fw_board_len; 814bdcd8170SKalle Valo 815bdcd8170SKalle Valo u8 *fw_otp; 816bdcd8170SKalle Valo size_t fw_otp_len; 817bdcd8170SKalle Valo 818bdcd8170SKalle Valo u8 *fw; 819bdcd8170SKalle Valo size_t fw_len; 820bdcd8170SKalle Valo 821bdcd8170SKalle Valo u8 *fw_patch; 822bdcd8170SKalle Valo size_t fw_patch_len; 823bdcd8170SKalle Valo 824cd23c1c9SAlex Yang u8 *fw_testscript; 825cd23c1c9SAlex Yang size_t fw_testscript_len; 826cd23c1c9SAlex Yang 82765a8b4ccSKalle Valo unsigned int fw_api; 82897e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 82997e0496dSKalle Valo 830bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 8317c3075e9SVasanthakumar Thiagarajan 832d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 8336a7c9badSJouni Malinen 8346bbc7c35SJouni Malinen bool p2p; 8356bbc7c35SJouni Malinen 836e5348a1eSVasanthakumar Thiagarajan bool wiphy_registered; 837e5348a1eSVasanthakumar Thiagarajan 83884caf800SVasanthakumar Thiagarajan struct ath6kl_fw_recovery { 83984caf800SVasanthakumar Thiagarajan struct work_struct recovery_work; 84084caf800SVasanthakumar Thiagarajan unsigned long err_reason; 84192332993SVasanthakumar Thiagarajan unsigned long hb_poll; 84292332993SVasanthakumar Thiagarajan struct timer_list hb_timer; 84392332993SVasanthakumar Thiagarajan u32 seq_num; 84492332993SVasanthakumar Thiagarajan bool hb_pending; 84592332993SVasanthakumar Thiagarajan u8 hb_misscnt; 84666ddcc39SVasanthakumar Thiagarajan bool enable; 84784caf800SVasanthakumar Thiagarajan } fw_recovery; 84884caf800SVasanthakumar Thiagarajan 849bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 850bdf5396bSKalle Valo struct { 8519b9a4f2aSKalle Valo struct sk_buff_head fwlog_queue; 852c807b30dSKalle Valo struct completion fwlog_completion; 853c807b30dSKalle Valo bool fwlog_open; 854c807b30dSKalle Valo 855939f1cceSKalle Valo u32 fwlog_mask; 8569b9a4f2aSKalle Valo 85791d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 858252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 859252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 8609a730834SKalle Valo 8619a730834SKalle Valo struct { 8629a730834SKalle Valo unsigned int invalid_rate; 8639a730834SKalle Valo } war_stats; 8644b28a80dSJouni Malinen 8654b28a80dSJouni Malinen u8 *roam_tbl; 8664b28a80dSJouni Malinen unsigned int roam_tbl_len; 867ff0b0075SJouni Malinen 868ff0b0075SJouni Malinen u8 keepalive; 869ff0b0075SJouni Malinen u8 disc_timeout; 870bdf5396bSKalle Valo } debug; 871bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 872bdcd8170SKalle Valo }; 873bdcd8170SKalle Valo 874d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 875bdcd8170SKalle Valo { 876108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 877bdcd8170SKalle Valo } 878bdcd8170SKalle Valo 879bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 880bc07ddb2SKalle Valo u32 item_offset) 881bc07ddb2SKalle Valo { 882bc07ddb2SKalle Valo u32 addr = 0; 883bc07ddb2SKalle Valo 884bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 885bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 886bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 887bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 888bc07ddb2SKalle Valo 889bc07ddb2SKalle Valo return addr; 890bc07ddb2SKalle Valo } 891bc07ddb2SKalle Valo 892bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 893bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 894bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 895bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 896bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 897bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 898bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 89963de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context, 90063de1112SKalle Valo struct list_head *packet_queue); 901bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 902bdcd8170SKalle Valo struct htc_packet *packet); 903bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 904bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 905f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 906addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 907addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 908addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 909bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 910e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 911bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 912bdcd8170SKalle Valo 913bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 914bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 915bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 916bdcd8170SKalle Valo 9177baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 918c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info, 919c8651541SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn); 920bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 921bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 922bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 923bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 924bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 925bdcd8170SKalle Valo int len); 926bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 9271d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn); 928bdcd8170SKalle Valo 9296765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr); 930bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 931bdcd8170SKalle Valo 932d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver, 933d92917e4SThomas Pedersen enum wmi_phy_cap cap); 934bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 935bdcd8170SKalle Valo enum htc_endpoint_id eid); 936240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 937bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 938bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 939bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 940bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 941240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 942240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 943572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 944c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 945240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 946bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 947bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 948240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 949bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 950240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 951240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 952bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 953bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 954bdcd8170SKalle Valo 955240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 956bdcd8170SKalle Valo 957240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 958240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 959240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 960240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 961bdcd8170SKalle Valo u8 win_sz); 962bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 963bdcd8170SKalle Valo 964e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 965990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 966355b3a98SMohammed Shafi Shajakhan void ath6kl_cfg80211_vif_stop(struct ath6kl_vif *vif, bool wmi_ready); 9675fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 9685fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 96945eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 97045eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 97145eaa78fSKalle Valo 972a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 9735fe4dffbSKalle Valo 974636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb); 975636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe); 976636f8288SKalle Valo 97745eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 978e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type); 97945eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 98045eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 98145eaa78fSKalle Valo 98284caf800SVasanthakumar Thiagarajan /* Fw error recovery */ 98384caf800SVasanthakumar Thiagarajan void ath6kl_init_hw_restart(struct ath6kl *ar); 98484caf800SVasanthakumar Thiagarajan void ath6kl_recovery_err_notify(struct ath6kl *ar, enum ath6kl_fw_err reason); 98592332993SVasanthakumar Thiagarajan void ath6kl_recovery_hb_event(struct ath6kl *ar, u32 cookie); 98684caf800SVasanthakumar Thiagarajan void ath6kl_recovery_init(struct ath6kl *ar); 98784caf800SVasanthakumar Thiagarajan void ath6kl_recovery_cleanup(struct ath6kl *ar); 98884caf800SVasanthakumar Thiagarajan void ath6kl_recovery_suspend(struct ath6kl *ar); 98992332993SVasanthakumar Thiagarajan void ath6kl_recovery_resume(struct ath6kl *ar); 990bdcd8170SKalle Valo #endif /* CORE_H */ 991