1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #ifndef CORE_H 18bdcd8170SKalle Valo #define CORE_H 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo #include <linux/etherdevice.h> 21bdcd8170SKalle Valo #include <linux/rtnetlink.h> 22bdcd8170SKalle Valo #include <linux/firmware.h> 23bdcd8170SKalle Valo #include <linux/sched.h> 24bdf5396bSKalle Valo #include <linux/circ_buf.h> 25bdcd8170SKalle Valo #include <net/cfg80211.h> 26bdcd8170SKalle Valo #include "htc.h" 27bdcd8170SKalle Valo #include "wmi.h" 28bdcd8170SKalle Valo #include "bmi.h" 29bc07ddb2SKalle Valo #include "target.h" 30bdcd8170SKalle Valo 31bdcd8170SKalle Valo #define MAX_ATH6KL 1 32bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 33bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 34bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 35bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 37bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 38bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 39bdcd8170SKalle Valo 40bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 42bdcd8170SKalle Valo 43bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 44bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 45bdcd8170SKalle Valo #define MAX_NODE_NUM 15 46bdcd8170SKalle Valo 471df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 481df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 491df94a85SVasanthakumar Thiagarajan 50bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 51bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 52bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 53bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 54bdcd8170SKalle Valo 55bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 56bdcd8170SKalle Valo 57bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 58bdcd8170SKalle Valo #define A_DEFAULT_LISTEN_INTERVAL 100 59bdcd8170SKalle Valo #define A_MAX_WOW_LISTEN_INTERVAL 1000 60bdcd8170SKalle Valo 6150d41234SKalle Valo /* includes also the null byte */ 6250d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6350d41234SKalle Valo 6450d41234SKalle Valo enum ath6kl_fw_ie_type { 6550d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 6650d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 6750d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 6850d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 6950d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 708a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7197e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 721b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7303ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 7450d41234SKalle Valo }; 7550d41234SKalle Valo 7697e0496dSKalle Valo enum ath6kl_fw_capability { 7797e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 7897e0496dSKalle Valo 7997e0496dSKalle Valo /* this needs to be last */ 8097e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 8197e0496dSKalle Valo }; 8297e0496dSKalle Valo 8397e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 8497e0496dSKalle Valo 8550d41234SKalle Valo struct ath6kl_fw_ie { 8650d41234SKalle Valo __le32 id; 8750d41234SKalle Valo __le32 len; 8850d41234SKalle Valo u8 data[0]; 8950d41234SKalle Valo }; 9050d41234SKalle Valo 91bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 920d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 93bdcd8170SKalle Valo 94bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 950d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 960d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 970d0192baSKalle Valo #define AR6003_HW_2_0_OTP_FILE "ath6k/AR6003/hw2.0/otp.bin.z77" 980d0192baSKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athwlan.bin.z77" 990d0192baSKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athtcmd_ram.bin" 1000d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_FILE "ath6k/AR6003/hw2.0/data.patch.bin" 1010d0192baSKalle Valo #define AR6003_HW_2_0_FIRMWARE_2_FILE "ath6k/AR6003/hw2.0/fw-2.bin" 1020d0192baSKalle Valo #define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin" 1030d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1040d0192baSKalle Valo "ath6k/AR6003/hw2.0/bdata.SD31.bin" 105bdcd8170SKalle Valo 106bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1070d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 1080d0192baSKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "ath6k/AR6003/hw2.1.1/otp.bin" 1090d0192baSKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/athwlan.bin" 1100d0192baSKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE \ 1110d0192baSKalle Valo "ath6k/AR6003/hw2.1.1/athtcmd_ram.bin" 1120d0192baSKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "ath6k/AR6003/hw2.1.1/data.patch.bin" 1130d0192baSKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_2_FILE "ath6k/AR6003/hw2.1.1/fw-2.bin" 1140d0192baSKalle Valo #define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin" 1150d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 116bdcd8170SKalle Valo "ath6k/AR6003/hw2.1.1/bdata.SD31.bin" 117bdcd8170SKalle Valo 11831024d99SKevin Fang /* AR6004 1.0 definitions */ 1190d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 1200d0192baSKalle Valo #define AR6004_HW_1_0_FIRMWARE_2_FILE "ath6k/AR6004/hw1.0/fw-2.bin" 1210d0192baSKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "ath6k/AR6004/hw1.0/fw.ram.bin" 1220d0192baSKalle Valo #define AR6004_HW_1_0_BOARD_DATA_FILE "ath6k/AR6004/hw1.0/bdata.bin" 1230d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 124d5720e59SKalle Valo "ath6k/AR6004/hw1.0/bdata.DB132.bin" 125d5720e59SKalle Valo 126d5720e59SKalle Valo /* AR6004 1.1 definitions */ 1270d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 1280d0192baSKalle Valo #define AR6004_HW_1_1_FIRMWARE_2_FILE "ath6k/AR6004/hw1.1/fw-2.bin" 1290d0192baSKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "ath6k/AR6004/hw1.1/fw.ram.bin" 1300d0192baSKalle Valo #define AR6004_HW_1_1_BOARD_DATA_FILE "ath6k/AR6004/hw1.1/bdata.bin" 1310d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 132d5720e59SKalle Valo "ath6k/AR6004/hw1.1/bdata.DB132.bin" 13331024d99SKevin Fang 134bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 135bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 136bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 137bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 138bdcd8170SKalle Valo 139bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 140bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 141bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 142bdcd8170SKalle Valo 143bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 144bdcd8170SKalle Valo 145bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 146bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 147bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 148bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 149bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 150bdcd8170SKalle Valo 151bdcd8170SKalle Valo #define NUM_OF_TIDS 8 152bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 153bdcd8170SKalle Valo 154bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 155bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 156bdcd8170SKalle Valo 157bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 158bdcd8170SKalle Valo 159bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 160bdcd8170SKalle Valo 161bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT 400 /* in ms */ 162bdcd8170SKalle Valo 163bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 164bdcd8170SKalle Valo 165bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 166bdcd8170SKalle Valo 167bdcd8170SKalle Valo /* configuration lags */ 168bdcd8170SKalle Valo /* 169bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 170bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 171bdcd8170SKalle Valo * sending (Re)Assoc req. 172bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 173bdcd8170SKalle Valo * module state transition failure events which happen during 174bdcd8170SKalle Valo * scan, to the host. 175bdcd8170SKalle Valo */ 176bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 177bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 178bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 179bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 1808277de15SKalle Valo #define ATH6KL_CONF_SUSPEND_CUTPOWER BIT(4) 181bdcd8170SKalle Valo 182bdcd8170SKalle Valo enum wlan_low_pwr_state { 183bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 184bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 185bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 186bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 187bdcd8170SKalle Valo }; 188bdcd8170SKalle Valo 189bdcd8170SKalle Valo enum sme_state { 190bdcd8170SKalle Valo SME_DISCONNECTED, 191bdcd8170SKalle Valo SME_CONNECTING, 192bdcd8170SKalle Valo SME_CONNECTED 193bdcd8170SKalle Valo }; 194bdcd8170SKalle Valo 195bdcd8170SKalle Valo struct skb_hold_q { 196bdcd8170SKalle Valo struct sk_buff *skb; 197bdcd8170SKalle Valo bool is_amsdu; 198bdcd8170SKalle Valo u16 seq_no; 199bdcd8170SKalle Valo }; 200bdcd8170SKalle Valo 201bdcd8170SKalle Valo struct rxtid { 202bdcd8170SKalle Valo bool aggr; 203bdcd8170SKalle Valo bool progress; 204bdcd8170SKalle Valo bool timer_mon; 205bdcd8170SKalle Valo u16 win_sz; 206bdcd8170SKalle Valo u16 seq_next; 207bdcd8170SKalle Valo u32 hold_q_sz; 208bdcd8170SKalle Valo struct skb_hold_q *hold_q; 209bdcd8170SKalle Valo struct sk_buff_head q; 210bdcd8170SKalle Valo spinlock_t lock; 211bdcd8170SKalle Valo }; 212bdcd8170SKalle Valo 213bdcd8170SKalle Valo struct rxtid_stats { 214bdcd8170SKalle Valo u32 num_into_aggr; 215bdcd8170SKalle Valo u32 num_dups; 216bdcd8170SKalle Valo u32 num_oow; 217bdcd8170SKalle Valo u32 num_mpdu; 218bdcd8170SKalle Valo u32 num_amsdu; 219bdcd8170SKalle Valo u32 num_delivered; 220bdcd8170SKalle Valo u32 num_timeouts; 221bdcd8170SKalle Valo u32 num_hole; 222bdcd8170SKalle Valo u32 num_bar; 223bdcd8170SKalle Valo }; 224bdcd8170SKalle Valo 225bdcd8170SKalle Valo struct aggr_info { 226bdcd8170SKalle Valo u8 aggr_sz; 227bdcd8170SKalle Valo u8 timer_scheduled; 228bdcd8170SKalle Valo struct timer_list timer; 229bdcd8170SKalle Valo struct net_device *dev; 230bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 231bdcd8170SKalle Valo struct sk_buff_head free_q; 232bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 233bdcd8170SKalle Valo }; 234bdcd8170SKalle Valo 235bdcd8170SKalle Valo struct ath6kl_wep_key { 236bdcd8170SKalle Valo u8 key_index; 237bdcd8170SKalle Valo u8 key_len; 238bdcd8170SKalle Valo u8 key[64]; 239bdcd8170SKalle Valo }; 240bdcd8170SKalle Valo 241bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 242bdcd8170SKalle Valo 243bdcd8170SKalle Valo struct ath6kl_key { 244bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 245bdcd8170SKalle Valo u8 key_len; 246bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 247bdcd8170SKalle Valo u8 seq_len; 248bdcd8170SKalle Valo u32 cipher; 249bdcd8170SKalle Valo }; 250bdcd8170SKalle Valo 251bdcd8170SKalle Valo struct ath6kl_node_mapping { 252bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 253bdcd8170SKalle Valo u8 ep_id; 254bdcd8170SKalle Valo u8 tx_pend; 255bdcd8170SKalle Valo }; 256bdcd8170SKalle Valo 257bdcd8170SKalle Valo struct ath6kl_cookie { 258bdcd8170SKalle Valo struct sk_buff *skb; 259bdcd8170SKalle Valo u32 map_no; 260bdcd8170SKalle Valo struct htc_packet htc_pkt; 261bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 262bdcd8170SKalle Valo }; 263bdcd8170SKalle Valo 264bdcd8170SKalle Valo struct ath6kl_sta { 265bdcd8170SKalle Valo u16 sta_flags; 266bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 267bdcd8170SKalle Valo u8 aid; 268bdcd8170SKalle Valo u8 keymgmt; 269bdcd8170SKalle Valo u8 ucipher; 270bdcd8170SKalle Valo u8 auth; 271bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 272bdcd8170SKalle Valo struct sk_buff_head psq; 273bdcd8170SKalle Valo spinlock_t psq_lock; 274bdcd8170SKalle Valo }; 275bdcd8170SKalle Valo 276bdcd8170SKalle Valo struct ath6kl_version { 277bdcd8170SKalle Valo u32 target_ver; 278bdcd8170SKalle Valo u32 wlan_ver; 279bdcd8170SKalle Valo u32 abi_ver; 280bdcd8170SKalle Valo }; 281bdcd8170SKalle Valo 282bdcd8170SKalle Valo struct ath6kl_bmi { 283bdcd8170SKalle Valo u32 cmd_credits; 284bdcd8170SKalle Valo bool done_sent; 285bdcd8170SKalle Valo u8 *cmd_buf; 2861f4c894dSKalle Valo u32 max_data_size; 2871f4c894dSKalle Valo u32 max_cmd_size; 288bdcd8170SKalle Valo }; 289bdcd8170SKalle Valo 290bdcd8170SKalle Valo struct target_stats { 291bdcd8170SKalle Valo u64 tx_pkt; 292bdcd8170SKalle Valo u64 tx_byte; 293bdcd8170SKalle Valo u64 tx_ucast_pkt; 294bdcd8170SKalle Valo u64 tx_ucast_byte; 295bdcd8170SKalle Valo u64 tx_mcast_pkt; 296bdcd8170SKalle Valo u64 tx_mcast_byte; 297bdcd8170SKalle Valo u64 tx_bcast_pkt; 298bdcd8170SKalle Valo u64 tx_bcast_byte; 299bdcd8170SKalle Valo u64 tx_rts_success_cnt; 300bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 301bdcd8170SKalle Valo 302bdcd8170SKalle Valo u64 tx_err; 303bdcd8170SKalle Valo u64 tx_fail_cnt; 304bdcd8170SKalle Valo u64 tx_retry_cnt; 305bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 306bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 307bdcd8170SKalle Valo 308bdcd8170SKalle Valo u64 rx_pkt; 309bdcd8170SKalle Valo u64 rx_byte; 310bdcd8170SKalle Valo u64 rx_ucast_pkt; 311bdcd8170SKalle Valo u64 rx_ucast_byte; 312bdcd8170SKalle Valo u64 rx_mcast_pkt; 313bdcd8170SKalle Valo u64 rx_mcast_byte; 314bdcd8170SKalle Valo u64 rx_bcast_pkt; 315bdcd8170SKalle Valo u64 rx_bcast_byte; 316bdcd8170SKalle Valo u64 rx_frgment_pkt; 317bdcd8170SKalle Valo 318bdcd8170SKalle Valo u64 rx_err; 319bdcd8170SKalle Valo u64 rx_crc_err; 320bdcd8170SKalle Valo u64 rx_key_cache_miss; 321bdcd8170SKalle Valo u64 rx_decrypt_err; 322bdcd8170SKalle Valo u64 rx_dupl_frame; 323bdcd8170SKalle Valo 324bdcd8170SKalle Valo u64 tkip_local_mic_fail; 325bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 326bdcd8170SKalle Valo u64 tkip_replays; 327bdcd8170SKalle Valo u64 tkip_fmt_err; 328bdcd8170SKalle Valo u64 ccmp_fmt_err; 329bdcd8170SKalle Valo u64 ccmp_replays; 330bdcd8170SKalle Valo 331bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 332bdcd8170SKalle Valo 333bdcd8170SKalle Valo u64 cs_bmiss_cnt; 334bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 335bdcd8170SKalle Valo u64 cs_connect_cnt; 336bdcd8170SKalle Valo u64 cs_discon_cnt; 337bdcd8170SKalle Valo 338bdcd8170SKalle Valo s32 tx_ucast_rate; 339bdcd8170SKalle Valo s32 rx_ucast_rate; 340bdcd8170SKalle Valo 341bdcd8170SKalle Valo u32 lq_val; 342bdcd8170SKalle Valo 343bdcd8170SKalle Valo u32 wow_pkt_dropped; 344bdcd8170SKalle Valo u16 wow_evt_discarded; 345bdcd8170SKalle Valo 346bdcd8170SKalle Valo s16 noise_floor_calib; 347bdcd8170SKalle Valo s16 cs_rssi; 348bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 349bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 350bdcd8170SKalle Valo u8 cs_last_roam_msec; 351bdcd8170SKalle Valo u8 cs_snr; 352bdcd8170SKalle Valo 353bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 354bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 355bdcd8170SKalle Valo 356bdcd8170SKalle Valo u32 arp_received; 357bdcd8170SKalle Valo u32 arp_matched; 358bdcd8170SKalle Valo u32 arp_replied; 359bdcd8170SKalle Valo }; 360bdcd8170SKalle Valo 361bdcd8170SKalle Valo struct ath6kl_mbox_info { 362bdcd8170SKalle Valo u32 htc_addr; 363bdcd8170SKalle Valo u32 htc_ext_addr; 364bdcd8170SKalle Valo u32 htc_ext_sz; 365bdcd8170SKalle Valo 366bdcd8170SKalle Valo u32 block_size; 367bdcd8170SKalle Valo 368bdcd8170SKalle Valo u32 gmbox_addr; 369bdcd8170SKalle Valo 370bdcd8170SKalle Valo u32 gmbox_sz; 371bdcd8170SKalle Valo }; 372bdcd8170SKalle Valo 373bdcd8170SKalle Valo /* 374bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 375bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 376bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 377bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 378bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 379bdcd8170SKalle Valo */ 380bdcd8170SKalle Valo 381bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 382bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 383bdcd8170SKalle Valo 384bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 385bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 386bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 387bdcd8170SKalle Valo 3889a5b1318SJouni Malinen /* Initial group key for AP mode */ 389bdcd8170SKalle Valo struct ath6kl_req_key { 3909a5b1318SJouni Malinen bool valid; 3919a5b1318SJouni Malinen u8 key_index; 3929a5b1318SJouni Malinen int key_type; 3939a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 3949a5b1318SJouni Malinen u8 key_len; 395bdcd8170SKalle Valo }; 396bdcd8170SKalle Valo 39777eab1e9SKalle Valo enum ath6kl_hif_type { 39877eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 39977eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 40077eab1e9SKalle Valo }; 40177eab1e9SKalle Valo 40271f96ee6SKalle Valo /* 40371f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 40471f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 40571f96ee6SKalle Valo */ 40671f96ee6SKalle Valo #define ATH6KL_VIF_MAX 1 407334234b5SVasanthakumar Thiagarajan 40859c98449SVasanthakumar Thiagarajan /* vif flags info */ 40959c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 41059c98449SVasanthakumar Thiagarajan CONNECTED, 41159c98449SVasanthakumar Thiagarajan CONNECT_PEND, 41259c98449SVasanthakumar Thiagarajan WMM_ENABLED, 41359c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 41459c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 41559c98449SVasanthakumar Thiagarajan NETDEV_REGISTERED, 41659c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 41759c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 41859c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 419b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 42059c98449SVasanthakumar Thiagarajan }; 42159c98449SVasanthakumar Thiagarajan 422108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 423990bd915SVasanthakumar Thiagarajan struct list_head list; 424108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 425108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 426108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 427478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 428478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 429334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 43059c98449SVasanthakumar Thiagarajan unsigned long flags; 4313450334fSVasanthakumar Thiagarajan int ssid_len; 4323450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 4333450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 4343450334fSVasanthakumar Thiagarajan u8 auth_mode; 4353450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 4363450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 4373450334fSVasanthakumar Thiagarajan u8 grp_crypto; 4383450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 4393450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 440f5938f24SVasanthakumar Thiagarajan u8 next_mode; 441f5938f24SVasanthakumar Thiagarajan u8 nw_type; 4428c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 4438c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 444f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 445f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 4466f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 4476f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 4482132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 449de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 45014ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 45114ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 452cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 4531052261eSJouni Malinen u32 last_roc_id; 4541052261eSJouni Malinen u32 last_cancel_roc_id; 455cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 456cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 457cf5333d7SVasanthakumar Thiagarajan u16 next_chan; 458cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 459cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 460b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 461b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 462108438bcSVasanthakumar Thiagarajan }; 463108438bcSVasanthakumar Thiagarajan 4646cb3c714SRaja Mani #define WOW_LIST_ID 0 4656cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 4666cb3c714SRaja Mani 467bdcd8170SKalle Valo /* Flag info */ 46859c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 46959c98449SVasanthakumar Thiagarajan WMI_ENABLED, 47059c98449SVasanthakumar Thiagarajan WMI_READY, 47159c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 47259c98449SVasanthakumar Thiagarajan TESTMODE, 47359c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 47459c98449SVasanthakumar Thiagarajan SKIP_SCAN, 47559c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 4765fe4dffbSKalle Valo FIRST_BOOT, 47759c98449SVasanthakumar Thiagarajan }; 478bdcd8170SKalle Valo 47976a9fbe2SKalle Valo enum ath6kl_state { 48076a9fbe2SKalle Valo ATH6KL_STATE_OFF, 48176a9fbe2SKalle Valo ATH6KL_STATE_ON, 48276a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 483b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 484dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 48576a9fbe2SKalle Valo }; 48676a9fbe2SKalle Valo 487bdcd8170SKalle Valo struct ath6kl { 488bdcd8170SKalle Valo struct device *dev; 489be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 49076a9fbe2SKalle Valo 49176a9fbe2SKalle Valo enum ath6kl_state state; 49276a9fbe2SKalle Valo 493bdcd8170SKalle Valo struct ath6kl_bmi bmi; 494bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 495bdcd8170SKalle Valo struct wmi *wmi; 496bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 497bdcd8170SKalle Valo int total_tx_data_pend; 498bdcd8170SKalle Valo struct htc_target *htc_target; 49977eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 500bdcd8170SKalle Valo void *hif_priv; 501990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 502990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 503990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 50455055976SVasanthakumar Thiagarajan u8 num_vif; 50571f96ee6SKalle Valo int vif_max; 5063226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 50755055976SVasanthakumar Thiagarajan u8 avail_idx_map; 508bdcd8170SKalle Valo spinlock_t lock; 509bdcd8170SKalle Valo struct semaphore sem; 510bdcd8170SKalle Valo u16 listen_intvl_b; 511bdcd8170SKalle Valo u16 listen_intvl_t; 512e5090444SVivek Natarajan u8 lrssi_roam_threshold; 513bdcd8170SKalle Valo struct ath6kl_version version; 514bdcd8170SKalle Valo u32 target_type; 515bdcd8170SKalle Valo u8 tx_pwr; 516bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 517bdcd8170SKalle Valo u8 ibss_ps_enable; 51855055976SVasanthakumar Thiagarajan bool ibss_if_active; 519bdcd8170SKalle Valo u8 node_num; 520bdcd8170SKalle Valo u8 next_ep_id; 521bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 522bdcd8170SKalle Valo u32 cookie_count; 523bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 524bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 525bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 526bdcd8170SKalle Valo u8 hiac_stream_active_pri; 527bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 528bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 5293c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 530bdcd8170SKalle Valo u32 connect_ctrl_flags; 531bdcd8170SKalle Valo u32 user_key_ctrl; 532bdcd8170SKalle Valo u8 usr_bss_filter; 533bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 534bdcd8170SKalle Valo u8 sta_list_index; 535bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 536bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 537bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 538bdcd8170SKalle Valo u8 intra_bss; 539bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 540bdcd8170SKalle Valo u8 ap_country_code[3]; 541bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 542bdcd8170SKalle Valo u8 rx_meta_ver; 543bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 544bdcd8170SKalle Valo struct wmi_scan_params_cmd sc_params; 545d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 546bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 547003353b0SKalle Valo struct { 548003353b0SKalle Valo void *rx_report; 549003353b0SKalle Valo size_t rx_report_len; 550003353b0SKalle Valo } tm; 551003353b0SKalle Valo 552856f4b31SKalle Valo struct ath6kl_hw { 553856f4b31SKalle Valo u32 id; 554293badf4SKalle Valo const char *name; 555a01ac414SKalle Valo u32 dataset_patch_addr; 556a01ac414SKalle Valo u32 app_load_addr; 557a01ac414SKalle Valo u32 app_start_override_addr; 558991b27eaSKalle Valo u32 board_ext_data_addr; 559991b27eaSKalle Valo u32 reserved_ram_size; 5600d4d72bfSKalle Valo u32 board_addr; 561d1a9421dSKalle Valo 562d1a9421dSKalle Valo const char *fw_otp; 563d1a9421dSKalle Valo const char *fw; 564d1a9421dSKalle Valo const char *fw_tcmd; 565d1a9421dSKalle Valo const char *fw_patch; 566d1a9421dSKalle Valo const char *fw_api2; 567d1a9421dSKalle Valo const char *fw_board; 568d1a9421dSKalle Valo const char *fw_default_board; 569a01ac414SKalle Valo } hw; 570a01ac414SKalle Valo 571bdcd8170SKalle Valo u16 conf_flags; 572bdcd8170SKalle Valo wait_queue_head_t event_wq; 573bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 574bdcd8170SKalle Valo 575bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 576bdcd8170SKalle Valo unsigned long flag; 577bdcd8170SKalle Valo 578bdcd8170SKalle Valo u8 *fw_board; 579bdcd8170SKalle Valo size_t fw_board_len; 580bdcd8170SKalle Valo 581bdcd8170SKalle Valo u8 *fw_otp; 582bdcd8170SKalle Valo size_t fw_otp_len; 583bdcd8170SKalle Valo 584bdcd8170SKalle Valo u8 *fw; 585bdcd8170SKalle Valo size_t fw_len; 586bdcd8170SKalle Valo 587bdcd8170SKalle Valo u8 *fw_patch; 588bdcd8170SKalle Valo size_t fw_patch_len; 589bdcd8170SKalle Valo 59097e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 59197e0496dSKalle Valo 592bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 5937c3075e9SVasanthakumar Thiagarajan 594d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 5956a7c9badSJouni Malinen 5966bbc7c35SJouni Malinen bool p2p; 5976bbc7c35SJouni Malinen 598bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 599bdf5396bSKalle Valo struct { 600bdf5396bSKalle Valo struct circ_buf fwlog_buf; 601bdf5396bSKalle Valo spinlock_t fwlog_lock; 602bdf5396bSKalle Valo void *fwlog_tmp; 603939f1cceSKalle Valo u32 fwlog_mask; 60491d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 605252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 606252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 6079a730834SKalle Valo 6089a730834SKalle Valo struct { 6099a730834SKalle Valo unsigned int invalid_rate; 6109a730834SKalle Valo } war_stats; 6114b28a80dSJouni Malinen 6124b28a80dSJouni Malinen u8 *roam_tbl; 6134b28a80dSJouni Malinen unsigned int roam_tbl_len; 614ff0b0075SJouni Malinen 615ff0b0075SJouni Malinen u8 keepalive; 616ff0b0075SJouni Malinen u8 disc_timeout; 617bdf5396bSKalle Valo } debug; 618bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 619bdcd8170SKalle Valo }; 620bdcd8170SKalle Valo 621bdcd8170SKalle Valo static inline void *ath6kl_priv(struct net_device *dev) 622bdcd8170SKalle Valo { 623108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 624bdcd8170SKalle Valo } 625bdcd8170SKalle Valo 626bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 627bc07ddb2SKalle Valo u32 item_offset) 628bc07ddb2SKalle Valo { 629bc07ddb2SKalle Valo u32 addr = 0; 630bc07ddb2SKalle Valo 631bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 632bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 633bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 634bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 635bc07ddb2SKalle Valo 636bc07ddb2SKalle Valo return addr; 637bc07ddb2SKalle Valo } 638bc07ddb2SKalle Valo 639bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 640bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 641bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 642bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 643bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 644bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 645bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 646bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue); 647bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 648bdcd8170SKalle Valo struct htc_packet *packet); 649bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 650bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 651f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 652addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 653addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 654addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 655bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 656e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 657bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 658bdcd8170SKalle Valo 659bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 660bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 661bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 662bdcd8170SKalle Valo 663bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev); 664bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 665bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 666bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 667bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 668bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 669bdcd8170SKalle Valo int len); 670bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 671bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info); 672bdcd8170SKalle Valo 6736765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 * node_addr); 674bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 675bdcd8170SKalle Valo 676bdcd8170SKalle Valo void ath6kl_ready_event(void *devt, u8 * datap, u32 sw_ver, u32 abi_ver); 677bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 678bdcd8170SKalle Valo enum htc_endpoint_id eid); 679240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 680bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 681bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 682bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 683bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 684240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 685240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 686572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 687572e27c0SJouni Malinen u8 assoc_req_len, u8 *assoc_info); 688240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 689bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 690bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 691240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 692bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 693240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 694240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 695bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 696bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 697bdcd8170SKalle Valo 698240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 699bdcd8170SKalle Valo 700240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 701240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 702240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 703240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 704bdcd8170SKalle Valo u8 win_sz); 705bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 706bdcd8170SKalle Valo 7076db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type, 7086db8fa53SVasanthakumar Thiagarajan bool wait_fot_compltn, bool cold_reset); 709e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 710108438bcSVasanthakumar Thiagarajan void ath6kl_deinit_if_data(struct ath6kl_vif *vif); 7118dafb70eSVasanthakumar Thiagarajan void ath6kl_core_free(struct ath6kl *ar); 712990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 71355055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready); 7145fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 7155fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 716a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 7175fe4dffbSKalle Valo 718bdcd8170SKalle Valo #endif /* CORE_H */ 719