1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
100d97c121bSVasanthakumar Thiagarajan 	/* Firmware has support to override rsn cap of rsn ie */
101d97c121bSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102d97c121bSVasanthakumar Thiagarajan 
1036821d4f0SNaveen Gangadharan 	/*
1046821d4f0SNaveen Gangadharan 	 * Multicast support in WOW and host awake mode.
1056821d4f0SNaveen Gangadharan 	 * Allow all multicast in host awake mode.
1066821d4f0SNaveen Gangadharan 	 * Apply multicast filter in WOW mode.
1076821d4f0SNaveen Gangadharan 	 */
1086821d4f0SNaveen Gangadharan 	ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
1096821d4f0SNaveen Gangadharan 
11097e0496dSKalle Valo 	/* this needs to be last */
11197e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
11297e0496dSKalle Valo };
11397e0496dSKalle Valo 
11497e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
11597e0496dSKalle Valo 
11650d41234SKalle Valo struct ath6kl_fw_ie {
11750d41234SKalle Valo 	__le32 id;
11850d41234SKalle Valo 	__le32 len;
11950d41234SKalle Valo 	u8 data[0];
12050d41234SKalle Valo };
12150d41234SKalle Valo 
122c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
12365a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
124c0038972SKalle Valo 
125bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1260d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
127bdcd8170SKalle Valo 
128bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1290d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1300d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
131c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
132c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
133c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
134c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
135c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1362023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
1370d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1382023dbb8STim Gardner 			AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
139bdcd8170SKalle Valo 
140bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1410d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
142c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
143c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
144c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
145c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
146cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
147cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
148c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1492023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
1500d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
1512023dbb8STim Gardner 			AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
152bdcd8170SKalle Valo 
15331024d99SKevin Fang /* AR6004 1.0 definitions */
1540d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
155c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
156c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1572023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE         AR6004_HW_1_0_FW_DIR "/bdata.bin"
1580d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
1592023dbb8STim Gardner 	AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
160d5720e59SKalle Valo 
161d5720e59SKalle Valo /* AR6004 1.1 definitions */
1620d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
163c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
164c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1652023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE         AR6004_HW_1_1_FW_DIR "/bdata.bin"
1660d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
1672023dbb8STim Gardner 	AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
16831024d99SKevin Fang 
1696146ca69SRay Chen /* AR6004 1.2 definitions */
1706146ca69SRay Chen #define AR6004_HW_1_2_VERSION                 0x300007e8
1716146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR			"ath6k/AR6004/hw1.2"
1726146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE           "fw.ram.bin"
1732023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE         AR6004_HW_1_2_FW_DIR "/bdata.bin"
1746146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
1752023dbb8STim Gardner 	AR6004_HW_1_2_FW_DIR "/bdata.bin"
1766146ca69SRay Chen 
177bdcd8170SKalle Valo /* Per STA data, used in AP mode */
178bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
179bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
180bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
181c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
182c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
183bdcd8170SKalle Valo 
184bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
185bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
186bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
187bdcd8170SKalle Valo 
188bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
189bdcd8170SKalle Valo 
190bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
191bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
192bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
193bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
194bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
195bdcd8170SKalle Valo 
196bdcd8170SKalle Valo #define NUM_OF_TIDS         8
197bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
198bdcd8170SKalle Valo 
199bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
200bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
201bdcd8170SKalle Valo 
202bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
203bdcd8170SKalle Valo 
204bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
205bdcd8170SKalle Valo 
206bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT     400	/* in ms */
207bdcd8170SKalle Valo 
208bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
209bdcd8170SKalle Valo 
210bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
211bdcd8170SKalle Valo 
2128f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
213ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
214ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
215ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
2168f46fccdSRaja Mani 
217bdcd8170SKalle Valo /* configuration lags */
218bdcd8170SKalle Valo /*
219bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
220bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
221bdcd8170SKalle Valo  * sending (Re)Assoc req.
222bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
223bdcd8170SKalle Valo  * module state transition failure events which happen during
224bdcd8170SKalle Valo  * scan, to the host.
225bdcd8170SKalle Valo  */
226bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
227bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
228bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
229bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
230e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
231bdcd8170SKalle Valo 
232c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
233c86e4f44SAarthi Thiruvengadam 
234bdcd8170SKalle Valo enum wlan_low_pwr_state {
235bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
236bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
237bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
238bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
239bdcd8170SKalle Valo };
240bdcd8170SKalle Valo 
241bdcd8170SKalle Valo enum sme_state {
242bdcd8170SKalle Valo 	SME_DISCONNECTED,
243bdcd8170SKalle Valo 	SME_CONNECTING,
244bdcd8170SKalle Valo 	SME_CONNECTED
245bdcd8170SKalle Valo };
246bdcd8170SKalle Valo 
247bdcd8170SKalle Valo struct skb_hold_q {
248bdcd8170SKalle Valo 	struct sk_buff *skb;
249bdcd8170SKalle Valo 	bool is_amsdu;
250bdcd8170SKalle Valo 	u16 seq_no;
251bdcd8170SKalle Valo };
252bdcd8170SKalle Valo 
253bdcd8170SKalle Valo struct rxtid {
254bdcd8170SKalle Valo 	bool aggr;
255bdcd8170SKalle Valo 	bool progress;
256bdcd8170SKalle Valo 	bool timer_mon;
257bdcd8170SKalle Valo 	u16 win_sz;
258bdcd8170SKalle Valo 	u16 seq_next;
259bdcd8170SKalle Valo 	u32 hold_q_sz;
260bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
261bdcd8170SKalle Valo 	struct sk_buff_head q;
26212eb9444SKalle Valo 
26312eb9444SKalle Valo 	/*
26412eb9444SKalle Valo 	 * FIXME: No clue what this should protect. Apparently it should
26512eb9444SKalle Valo 	 * protect some of the fields above but they are also accessed
26612eb9444SKalle Valo 	 * without taking the lock.
26712eb9444SKalle Valo 	 */
268bdcd8170SKalle Valo 	spinlock_t lock;
269bdcd8170SKalle Valo };
270bdcd8170SKalle Valo 
271bdcd8170SKalle Valo struct rxtid_stats {
272bdcd8170SKalle Valo 	u32 num_into_aggr;
273bdcd8170SKalle Valo 	u32 num_dups;
274bdcd8170SKalle Valo 	u32 num_oow;
275bdcd8170SKalle Valo 	u32 num_mpdu;
276bdcd8170SKalle Valo 	u32 num_amsdu;
277bdcd8170SKalle Valo 	u32 num_delivered;
278bdcd8170SKalle Valo 	u32 num_timeouts;
279bdcd8170SKalle Valo 	u32 num_hole;
280bdcd8170SKalle Valo 	u32 num_bar;
281bdcd8170SKalle Valo };
282bdcd8170SKalle Valo 
2837baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
284bdcd8170SKalle Valo 	u8 aggr_sz;
285bdcd8170SKalle Valo 	u8 timer_scheduled;
286bdcd8170SKalle Valo 	struct timer_list timer;
287bdcd8170SKalle Valo 	struct net_device *dev;
288bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
289bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
2907baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
2917baef812SVasanthakumar Thiagarajan };
2927baef812SVasanthakumar Thiagarajan 
2937baef812SVasanthakumar Thiagarajan struct aggr_info {
2947baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
2957baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
296bdcd8170SKalle Valo };
297bdcd8170SKalle Valo 
298bdcd8170SKalle Valo struct ath6kl_wep_key {
299bdcd8170SKalle Valo 	u8 key_index;
300bdcd8170SKalle Valo 	u8 key_len;
301bdcd8170SKalle Valo 	u8 key[64];
302bdcd8170SKalle Valo };
303bdcd8170SKalle Valo 
304bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
305bdcd8170SKalle Valo 
306bdcd8170SKalle Valo struct ath6kl_key {
307bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
308bdcd8170SKalle Valo 	u8 key_len;
309bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
310bdcd8170SKalle Valo 	u8 seq_len;
311bdcd8170SKalle Valo 	u32 cipher;
312bdcd8170SKalle Valo };
313bdcd8170SKalle Valo 
314bdcd8170SKalle Valo struct ath6kl_node_mapping {
315bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
316bdcd8170SKalle Valo 	u8 ep_id;
317bdcd8170SKalle Valo 	u8 tx_pend;
318bdcd8170SKalle Valo };
319bdcd8170SKalle Valo 
320bdcd8170SKalle Valo struct ath6kl_cookie {
321bdcd8170SKalle Valo 	struct sk_buff *skb;
322bdcd8170SKalle Valo 	u32 map_no;
323bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
324bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
325bdcd8170SKalle Valo };
326bdcd8170SKalle Valo 
327d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
328d0ff7383SNaveen Gangadharan 	struct list_head list;
329d0ff7383SNaveen Gangadharan 	u32 freq;
330d0ff7383SNaveen Gangadharan 	u32 wait;
331d0ff7383SNaveen Gangadharan 	u32 id;
332d0ff7383SNaveen Gangadharan 	bool no_cck;
333d0ff7383SNaveen Gangadharan 	size_t len;
334d0ff7383SNaveen Gangadharan 	u8 buf[0];
335d0ff7383SNaveen Gangadharan };
336d0ff7383SNaveen Gangadharan 
337bdcd8170SKalle Valo struct ath6kl_sta {
338bdcd8170SKalle Valo 	u16 sta_flags;
339bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
340bdcd8170SKalle Valo 	u8 aid;
341bdcd8170SKalle Valo 	u8 keymgmt;
342bdcd8170SKalle Valo 	u8 ucipher;
343bdcd8170SKalle Valo 	u8 auth;
344bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
345bdcd8170SKalle Valo 	struct sk_buff_head psq;
34612eb9444SKalle Valo 
34712eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
348bdcd8170SKalle Valo 	spinlock_t psq_lock;
34912eb9444SKalle Valo 
350d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
351d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
352c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
353c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3541d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
355bdcd8170SKalle Valo };
356bdcd8170SKalle Valo 
357bdcd8170SKalle Valo struct ath6kl_version {
358bdcd8170SKalle Valo 	u32 target_ver;
359bdcd8170SKalle Valo 	u32 wlan_ver;
360bdcd8170SKalle Valo 	u32 abi_ver;
361bdcd8170SKalle Valo };
362bdcd8170SKalle Valo 
363bdcd8170SKalle Valo struct ath6kl_bmi {
364bdcd8170SKalle Valo 	u32 cmd_credits;
365bdcd8170SKalle Valo 	bool done_sent;
366bdcd8170SKalle Valo 	u8 *cmd_buf;
3671f4c894dSKalle Valo 	u32 max_data_size;
3681f4c894dSKalle Valo 	u32 max_cmd_size;
369bdcd8170SKalle Valo };
370bdcd8170SKalle Valo 
371bdcd8170SKalle Valo struct target_stats {
372bdcd8170SKalle Valo 	u64 tx_pkt;
373bdcd8170SKalle Valo 	u64 tx_byte;
374bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
375bdcd8170SKalle Valo 	u64 tx_ucast_byte;
376bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
377bdcd8170SKalle Valo 	u64 tx_mcast_byte;
378bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
379bdcd8170SKalle Valo 	u64 tx_bcast_byte;
380bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
381bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
382bdcd8170SKalle Valo 
383bdcd8170SKalle Valo 	u64 tx_err;
384bdcd8170SKalle Valo 	u64 tx_fail_cnt;
385bdcd8170SKalle Valo 	u64 tx_retry_cnt;
386bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
387bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
388bdcd8170SKalle Valo 
389bdcd8170SKalle Valo 	u64 rx_pkt;
390bdcd8170SKalle Valo 	u64 rx_byte;
391bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
392bdcd8170SKalle Valo 	u64 rx_ucast_byte;
393bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
394bdcd8170SKalle Valo 	u64 rx_mcast_byte;
395bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
396bdcd8170SKalle Valo 	u64 rx_bcast_byte;
397bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
398bdcd8170SKalle Valo 
399bdcd8170SKalle Valo 	u64 rx_err;
400bdcd8170SKalle Valo 	u64 rx_crc_err;
401bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
402bdcd8170SKalle Valo 	u64 rx_decrypt_err;
403bdcd8170SKalle Valo 	u64 rx_dupl_frame;
404bdcd8170SKalle Valo 
405bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
406bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
407bdcd8170SKalle Valo 	u64 tkip_replays;
408bdcd8170SKalle Valo 	u64 tkip_fmt_err;
409bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
410bdcd8170SKalle Valo 	u64 ccmp_replays;
411bdcd8170SKalle Valo 
412bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
413bdcd8170SKalle Valo 
414bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
415bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
416bdcd8170SKalle Valo 	u64 cs_connect_cnt;
417bdcd8170SKalle Valo 	u64 cs_discon_cnt;
418bdcd8170SKalle Valo 
419bdcd8170SKalle Valo 	s32 tx_ucast_rate;
420bdcd8170SKalle Valo 	s32 rx_ucast_rate;
421bdcd8170SKalle Valo 
422bdcd8170SKalle Valo 	u32 lq_val;
423bdcd8170SKalle Valo 
424bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
425bdcd8170SKalle Valo 	u16 wow_evt_discarded;
426bdcd8170SKalle Valo 
427bdcd8170SKalle Valo 	s16 noise_floor_calib;
428bdcd8170SKalle Valo 	s16 cs_rssi;
429bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
430bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
431bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
432bdcd8170SKalle Valo 	u8 cs_snr;
433bdcd8170SKalle Valo 
434bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
435bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
436bdcd8170SKalle Valo 
437bdcd8170SKalle Valo 	u32 arp_received;
438bdcd8170SKalle Valo 	u32 arp_matched;
439bdcd8170SKalle Valo 	u32 arp_replied;
440bdcd8170SKalle Valo };
441bdcd8170SKalle Valo 
442bdcd8170SKalle Valo struct ath6kl_mbox_info {
443bdcd8170SKalle Valo 	u32 htc_addr;
444bdcd8170SKalle Valo 	u32 htc_ext_addr;
445bdcd8170SKalle Valo 	u32 htc_ext_sz;
446bdcd8170SKalle Valo 
447bdcd8170SKalle Valo 	u32 block_size;
448bdcd8170SKalle Valo 
449bdcd8170SKalle Valo 	u32 gmbox_addr;
450bdcd8170SKalle Valo 
451bdcd8170SKalle Valo 	u32 gmbox_sz;
452bdcd8170SKalle Valo };
453bdcd8170SKalle Valo 
454bdcd8170SKalle Valo /*
455bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
456bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
457bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
458bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
459bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
460bdcd8170SKalle Valo  */
461bdcd8170SKalle Valo 
462bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
463bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
464bdcd8170SKalle Valo 
465bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
466bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
467bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
468bdcd8170SKalle Valo 
4699a5b1318SJouni Malinen /* Initial group key for AP mode */
470bdcd8170SKalle Valo struct ath6kl_req_key {
4719a5b1318SJouni Malinen 	bool valid;
4729a5b1318SJouni Malinen 	u8 key_index;
4739a5b1318SJouni Malinen 	int key_type;
4749a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
4759a5b1318SJouni Malinen 	u8 key_len;
476bdcd8170SKalle Valo };
477bdcd8170SKalle Valo 
47877eab1e9SKalle Valo enum ath6kl_hif_type {
47977eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
48077eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
48177eab1e9SKalle Valo };
48277eab1e9SKalle Valo 
483e76ac2bfSKalle Valo enum ath6kl_htc_type {
484e76ac2bfSKalle Valo 	ATH6KL_HTC_TYPE_MBOX,
485636f8288SKalle Valo 	ATH6KL_HTC_TYPE_PIPE,
486e76ac2bfSKalle Valo };
487e76ac2bfSKalle Valo 
48880abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
48980abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
49080abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
49180abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
49280abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
49380abaf9bSVasanthakumar Thiagarajan };
49480abaf9bSVasanthakumar Thiagarajan 
495df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap {
496df90b369SVasanthakumar Thiagarajan 	bool ht_enable;
497df90b369SVasanthakumar Thiagarajan 	u8 ampdu_factor;
498df90b369SVasanthakumar Thiagarajan 	unsigned short cap_info;
499df90b369SVasanthakumar Thiagarajan };
500df90b369SVasanthakumar Thiagarajan 
50171f96ee6SKalle Valo /*
50271f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
50371f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
50471f96ee6SKalle Valo  */
505b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
506334234b5SVasanthakumar Thiagarajan 
50759c98449SVasanthakumar Thiagarajan /* vif flags info */
50859c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
50959c98449SVasanthakumar Thiagarajan 	CONNECTED,
51059c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
51159c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
51259c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
51359c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
51459c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
51559c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
51659c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
51759c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
518b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
519081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
5206251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_ON,
5216251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_OFF,
52259c98449SVasanthakumar Thiagarajan };
52359c98449SVasanthakumar Thiagarajan 
524108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
525990bd915SVasanthakumar Thiagarajan 	struct list_head list;
526108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
527108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
528108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
529478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
530478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
531334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
53259c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5333450334fSVasanthakumar Thiagarajan 	int ssid_len;
5343450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5353450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5363450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5373450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5383450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5393450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5403450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5413450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
542f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
543f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5448c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5458c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
546f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
547f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5486f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5496f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5502132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
551df90b369SVasanthakumar Thiagarajan 	struct ath6kl_htcap htcap;
55210509f90SKalle Valo 
553de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
55410509f90SKalle Valo 	struct timer_list sched_scan_timer;
55510509f90SKalle Valo 
55614ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
55714ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
558cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
5591052261eSJouni Malinen 	u32 last_roc_id;
5601052261eSJouni Malinen 	u32 last_cancel_roc_id;
561cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
562cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
563cf5333d7SVasanthakumar Thiagarajan 	u16 next_chan;
564df90b369SVasanthakumar Thiagarajan 	enum nl80211_channel_type next_ch_type;
565df90b369SVasanthakumar Thiagarajan 	enum ieee80211_band next_ch_band;
566cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
5678f46fccdSRaja Mani 	u16 listen_intvl_t;
568ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
569eb38987eSRaja Mani 	u16 bg_scan_period;
570cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
571b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
572b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
573c4f7863eSThomas Pedersen 	struct wmi_connect_cmd profile;
57480abaf9bSVasanthakumar Thiagarajan 
57580abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
576108438bcSVasanthakumar Thiagarajan };
577108438bcSVasanthakumar Thiagarajan 
5786cb3c714SRaja Mani #define WOW_LIST_ID		0
5796cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
5806cb3c714SRaja Mani 
58110509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
58210509f90SKalle Valo 
583bdcd8170SKalle Valo /* Flag info */
58459c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
58559c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
58659c98449SVasanthakumar Thiagarajan 	WMI_READY,
58759c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
58859c98449SVasanthakumar Thiagarajan 	TESTMODE,
58959c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
59059c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
59159c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
5925fe4dffbSKalle Valo 	FIRST_BOOT,
59359c98449SVasanthakumar Thiagarajan };
594bdcd8170SKalle Valo 
59576a9fbe2SKalle Valo enum ath6kl_state {
59676a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
59776a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
598390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
599390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
60076a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
601b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
602dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
60310509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
60476a9fbe2SKalle Valo };
60576a9fbe2SKalle Valo 
606bdcd8170SKalle Valo struct ath6kl {
607bdcd8170SKalle Valo 	struct device *dev;
608be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
60976a9fbe2SKalle Valo 
61076a9fbe2SKalle Valo 	enum ath6kl_state state;
6115f1127ffSKalle Valo 	unsigned int testmode;
61276a9fbe2SKalle Valo 
613bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
614bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
615e76ac2bfSKalle Valo 	const struct ath6kl_htc_ops *htc_ops;
616bdcd8170SKalle Valo 	struct wmi *wmi;
617bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
618bdcd8170SKalle Valo 	int total_tx_data_pend;
619bdcd8170SKalle Valo 	struct htc_target *htc_target;
62077eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
621bdcd8170SKalle Valo 	void *hif_priv;
622990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
623990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
624990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
62555055976SVasanthakumar Thiagarajan 	u8 num_vif;
626368b1b0fSKalle Valo 	unsigned int vif_max;
6273226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
62855055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
62912eb9444SKalle Valo 
63012eb9444SKalle Valo 	/*
63112eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
63212eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
63312eb9444SKalle Valo 	 */
634bdcd8170SKalle Valo 	spinlock_t lock;
63512eb9444SKalle Valo 
636bdcd8170SKalle Valo 	struct semaphore sem;
637e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
638bdcd8170SKalle Valo 	struct ath6kl_version version;
639bdcd8170SKalle Valo 	u32 target_type;
640bdcd8170SKalle Valo 	u8 tx_pwr;
641bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
642bdcd8170SKalle Valo 	u8 ibss_ps_enable;
64355055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
644bdcd8170SKalle Valo 	u8 node_num;
645bdcd8170SKalle Valo 	u8 next_ep_id;
646bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
647bdcd8170SKalle Valo 	u32 cookie_count;
648bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
649bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
650bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
651bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
652bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
653bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
6543c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
655bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
656bdcd8170SKalle Valo 	u32 user_key_ctrl;
657bdcd8170SKalle Valo 	u8 usr_bss_filter;
658bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
659bdcd8170SKalle Valo 	u8 sta_list_index;
660bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
661bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
662c4f7863eSThomas Pedersen 	u32 want_ch_switch;
66312eb9444SKalle Valo 
66412eb9444SKalle Valo 	/*
66512eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
66612eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
66712eb9444SKalle Valo 	 */
668bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
66912eb9444SKalle Valo 
670bdcd8170SKalle Valo 	u8 intra_bss;
671bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
672bdcd8170SKalle Valo 	u8 ap_country_code[3];
673bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
674bdcd8170SKalle Valo 	u8 rx_meta_ver;
675bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
676d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
677bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
678003353b0SKalle Valo 	struct {
679003353b0SKalle Valo 		void *rx_report;
680003353b0SKalle Valo 		size_t rx_report_len;
681003353b0SKalle Valo 	} tm;
682003353b0SKalle Valo 
683856f4b31SKalle Valo 	struct ath6kl_hw {
684856f4b31SKalle Valo 		u32 id;
685293badf4SKalle Valo 		const char *name;
686a01ac414SKalle Valo 		u32 dataset_patch_addr;
687a01ac414SKalle Valo 		u32 app_load_addr;
688a01ac414SKalle Valo 		u32 app_start_override_addr;
689991b27eaSKalle Valo 		u32 board_ext_data_addr;
690991b27eaSKalle Valo 		u32 reserved_ram_size;
6910d4d72bfSKalle Valo 		u32 board_addr;
69239586bf2SRyan Hsu 		u32 refclk_hz;
69339586bf2SRyan Hsu 		u32 uarttx_pin;
694cd23c1c9SAlex Yang 		u32 testscript_addr;
695d92917e4SThomas Pedersen 		enum wmi_phy_cap cap;
696d1a9421dSKalle Valo 
697c0038972SKalle Valo 		struct ath6kl_hw_fw {
698c0038972SKalle Valo 			const char *dir;
699c0038972SKalle Valo 			const char *otp;
700d1a9421dSKalle Valo 			const char *fw;
701c0038972SKalle Valo 			const char *tcmd;
702c0038972SKalle Valo 			const char *patch;
703cd23c1c9SAlex Yang 			const char *utf;
704cd23c1c9SAlex Yang 			const char *testscript;
705c0038972SKalle Valo 		} fw;
706c0038972SKalle Valo 
707d1a9421dSKalle Valo 		const char *fw_board;
708d1a9421dSKalle Valo 		const char *fw_default_board;
709a01ac414SKalle Valo 	} hw;
710a01ac414SKalle Valo 
711bdcd8170SKalle Valo 	u16 conf_flags;
712e390af77SRaja Mani 	u16 suspend_mode;
7131e9a905dSRaja Mani 	u16 wow_suspend_mode;
714bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
715bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
716bdcd8170SKalle Valo 
717bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
718bdcd8170SKalle Valo 	unsigned long flag;
719bdcd8170SKalle Valo 
720bdcd8170SKalle Valo 	u8 *fw_board;
721bdcd8170SKalle Valo 	size_t fw_board_len;
722bdcd8170SKalle Valo 
723bdcd8170SKalle Valo 	u8 *fw_otp;
724bdcd8170SKalle Valo 	size_t fw_otp_len;
725bdcd8170SKalle Valo 
726bdcd8170SKalle Valo 	u8 *fw;
727bdcd8170SKalle Valo 	size_t fw_len;
728bdcd8170SKalle Valo 
729bdcd8170SKalle Valo 	u8 *fw_patch;
730bdcd8170SKalle Valo 	size_t fw_patch_len;
731bdcd8170SKalle Valo 
732cd23c1c9SAlex Yang 	u8 *fw_testscript;
733cd23c1c9SAlex Yang 	size_t fw_testscript_len;
734cd23c1c9SAlex Yang 
73565a8b4ccSKalle Valo 	unsigned int fw_api;
73697e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
73797e0496dSKalle Valo 
738bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7397c3075e9SVasanthakumar Thiagarajan 
740d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7416a7c9badSJouni Malinen 
7426bbc7c35SJouni Malinen 	bool p2p;
7436bbc7c35SJouni Malinen 
744e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
745e5348a1eSVasanthakumar Thiagarajan 
746bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
747bdf5396bSKalle Valo 	struct {
7489b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
749c807b30dSKalle Valo 		struct completion fwlog_completion;
750c807b30dSKalle Valo 		bool fwlog_open;
751c807b30dSKalle Valo 
752939f1cceSKalle Valo 		u32 fwlog_mask;
7539b9a4f2aSKalle Valo 
75491d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
755252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
756252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
7579a730834SKalle Valo 
7589a730834SKalle Valo 		struct {
7599a730834SKalle Valo 			unsigned int invalid_rate;
7609a730834SKalle Valo 		} war_stats;
7614b28a80dSJouni Malinen 
7624b28a80dSJouni Malinen 		u8 *roam_tbl;
7634b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
764ff0b0075SJouni Malinen 
765ff0b0075SJouni Malinen 		u8 keepalive;
766ff0b0075SJouni Malinen 		u8 disc_timeout;
767bdf5396bSKalle Valo 	} debug;
768bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
769bdcd8170SKalle Valo };
770bdcd8170SKalle Valo 
771d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
772bdcd8170SKalle Valo {
773108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
774bdcd8170SKalle Valo }
775bdcd8170SKalle Valo 
776bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
777bc07ddb2SKalle Valo 					  u32 item_offset)
778bc07ddb2SKalle Valo {
779bc07ddb2SKalle Valo 	u32 addr = 0;
780bc07ddb2SKalle Valo 
781bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
782bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
783bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
784bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
785bc07ddb2SKalle Valo 
786bc07ddb2SKalle Valo 	return addr;
787bc07ddb2SKalle Valo }
788bc07ddb2SKalle Valo 
789bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
790bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
791bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
792bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
793bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
794bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
795bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
79663de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
79763de1112SKalle Valo 			struct list_head *packet_queue);
798bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
799bdcd8170SKalle Valo 					       struct htc_packet *packet);
800bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
801bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
802f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
803addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
804addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
805addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
806bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
807e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
808bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
809bdcd8170SKalle Valo 
810bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
811bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
812bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
813bdcd8170SKalle Valo 
8147baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
815c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
816c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
817bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
818bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
819bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
820bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
821bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
822bdcd8170SKalle Valo 					    int len);
823bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
8241d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
825bdcd8170SKalle Valo 
8266765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
827bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
828bdcd8170SKalle Valo 
829d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
830d92917e4SThomas Pedersen 			enum wmi_phy_cap cap);
831bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
832bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
833240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
834bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
835bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
836bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
837bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
838240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
839240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
840572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
841c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
842240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
843bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
844bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
845240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
846bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
847240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
848240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
849bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
850bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
851bdcd8170SKalle Valo 
852240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
853bdcd8170SKalle Valo 
854240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
855240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
856240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
857240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
858bdcd8170SKalle Valo 			     u8 win_sz);
859bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
860bdcd8170SKalle Valo 
8616db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
8626db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
863e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
864990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
86555055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
8665fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
8675fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
86845eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
86945eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
87045eaa78fSKalle Valo 
871a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
8725fe4dffbSKalle Valo 
873636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
874636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
875636f8288SKalle Valo 
87645eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
877e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
87845eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
87945eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
88045eaa78fSKalle Valo 
881bdcd8170SKalle Valo #endif /* CORE_H */
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