1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
10097e0496dSKalle Valo 	/* this needs to be last */
10197e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
10297e0496dSKalle Valo };
10397e0496dSKalle Valo 
10497e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
10597e0496dSKalle Valo 
10650d41234SKalle Valo struct ath6kl_fw_ie {
10750d41234SKalle Valo 	__le32 id;
10850d41234SKalle Valo 	__le32 len;
10950d41234SKalle Valo 	u8 data[0];
11050d41234SKalle Valo };
11150d41234SKalle Valo 
112c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
11365a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
114c0038972SKalle Valo 
115bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1160d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
117bdcd8170SKalle Valo 
118bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1190d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1200d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
121c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
122c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
123c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
124c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
125c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1260d0192baSKalle Valo #define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin"
1270d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1280d0192baSKalle Valo 			"ath6k/AR6003/hw2.0/bdata.SD31.bin"
129bdcd8170SKalle Valo 
130bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1310d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
132c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
133c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
134c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
135c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
136cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
137cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
138c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1390d0192baSKalle Valo #define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin"
1400d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
141bdcd8170SKalle Valo 			"ath6k/AR6003/hw2.1.1/bdata.SD31.bin"
142bdcd8170SKalle Valo 
14331024d99SKevin Fang /* AR6004 1.0 definitions */
1440d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
145c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
146c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1470d0192baSKalle Valo #define AR6004_HW_1_0_BOARD_DATA_FILE         "ath6k/AR6004/hw1.0/bdata.bin"
1480d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
149d5720e59SKalle Valo 	"ath6k/AR6004/hw1.0/bdata.DB132.bin"
150d5720e59SKalle Valo 
151d5720e59SKalle Valo /* AR6004 1.1 definitions */
1520d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
153c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
154c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1550d0192baSKalle Valo #define AR6004_HW_1_1_BOARD_DATA_FILE         "ath6k/AR6004/hw1.1/bdata.bin"
1560d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
157d5720e59SKalle Valo 	"ath6k/AR6004/hw1.1/bdata.DB132.bin"
15831024d99SKevin Fang 
159bdcd8170SKalle Valo /* Per STA data, used in AP mode */
160bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
161bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
162bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
163c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
164c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
165bdcd8170SKalle Valo 
166bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
167bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
168bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
169bdcd8170SKalle Valo 
170bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
171bdcd8170SKalle Valo 
172bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
173bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
174bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
175bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
176bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
177bdcd8170SKalle Valo 
178bdcd8170SKalle Valo #define NUM_OF_TIDS         8
179bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
180bdcd8170SKalle Valo 
181bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
182bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
183bdcd8170SKalle Valo 
184bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
185bdcd8170SKalle Valo 
186bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
187bdcd8170SKalle Valo 
188bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT     400	/* in ms */
189bdcd8170SKalle Valo 
190bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
191bdcd8170SKalle Valo 
192bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
193bdcd8170SKalle Valo 
1948f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
195ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
196ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
197ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
1988f46fccdSRaja Mani 
199bdcd8170SKalle Valo /* configuration lags */
200bdcd8170SKalle Valo /*
201bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
202bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
203bdcd8170SKalle Valo  * sending (Re)Assoc req.
204bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
205bdcd8170SKalle Valo  * module state transition failure events which happen during
206bdcd8170SKalle Valo  * scan, to the host.
207bdcd8170SKalle Valo  */
208bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
209bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
210bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
211bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
212e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
213bdcd8170SKalle Valo 
214c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
215c86e4f44SAarthi Thiruvengadam 
216bdcd8170SKalle Valo enum wlan_low_pwr_state {
217bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
218bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
219bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
220bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
221bdcd8170SKalle Valo };
222bdcd8170SKalle Valo 
223bdcd8170SKalle Valo enum sme_state {
224bdcd8170SKalle Valo 	SME_DISCONNECTED,
225bdcd8170SKalle Valo 	SME_CONNECTING,
226bdcd8170SKalle Valo 	SME_CONNECTED
227bdcd8170SKalle Valo };
228bdcd8170SKalle Valo 
229bdcd8170SKalle Valo struct skb_hold_q {
230bdcd8170SKalle Valo 	struct sk_buff *skb;
231bdcd8170SKalle Valo 	bool is_amsdu;
232bdcd8170SKalle Valo 	u16 seq_no;
233bdcd8170SKalle Valo };
234bdcd8170SKalle Valo 
235bdcd8170SKalle Valo struct rxtid {
236bdcd8170SKalle Valo 	bool aggr;
237bdcd8170SKalle Valo 	bool progress;
238bdcd8170SKalle Valo 	bool timer_mon;
239bdcd8170SKalle Valo 	u16 win_sz;
240bdcd8170SKalle Valo 	u16 seq_next;
241bdcd8170SKalle Valo 	u32 hold_q_sz;
242bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
243bdcd8170SKalle Valo 	struct sk_buff_head q;
24412eb9444SKalle Valo 
24512eb9444SKalle Valo 	/*
24612eb9444SKalle Valo 	 * FIXME: No clue what this should protect. Apparently it should
24712eb9444SKalle Valo 	 * protect some of the fields above but they are also accessed
24812eb9444SKalle Valo 	 * without taking the lock.
24912eb9444SKalle Valo 	 */
250bdcd8170SKalle Valo 	spinlock_t lock;
251bdcd8170SKalle Valo };
252bdcd8170SKalle Valo 
253bdcd8170SKalle Valo struct rxtid_stats {
254bdcd8170SKalle Valo 	u32 num_into_aggr;
255bdcd8170SKalle Valo 	u32 num_dups;
256bdcd8170SKalle Valo 	u32 num_oow;
257bdcd8170SKalle Valo 	u32 num_mpdu;
258bdcd8170SKalle Valo 	u32 num_amsdu;
259bdcd8170SKalle Valo 	u32 num_delivered;
260bdcd8170SKalle Valo 	u32 num_timeouts;
261bdcd8170SKalle Valo 	u32 num_hole;
262bdcd8170SKalle Valo 	u32 num_bar;
263bdcd8170SKalle Valo };
264bdcd8170SKalle Valo 
2657baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
266bdcd8170SKalle Valo 	u8 aggr_sz;
267bdcd8170SKalle Valo 	u8 timer_scheduled;
268bdcd8170SKalle Valo 	struct timer_list timer;
269bdcd8170SKalle Valo 	struct net_device *dev;
270bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
271bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
2727baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
2737baef812SVasanthakumar Thiagarajan };
2747baef812SVasanthakumar Thiagarajan 
2757baef812SVasanthakumar Thiagarajan struct aggr_info {
2767baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
2777baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
278bdcd8170SKalle Valo };
279bdcd8170SKalle Valo 
280bdcd8170SKalle Valo struct ath6kl_wep_key {
281bdcd8170SKalle Valo 	u8 key_index;
282bdcd8170SKalle Valo 	u8 key_len;
283bdcd8170SKalle Valo 	u8 key[64];
284bdcd8170SKalle Valo };
285bdcd8170SKalle Valo 
286bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
287bdcd8170SKalle Valo 
288bdcd8170SKalle Valo struct ath6kl_key {
289bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
290bdcd8170SKalle Valo 	u8 key_len;
291bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
292bdcd8170SKalle Valo 	u8 seq_len;
293bdcd8170SKalle Valo 	u32 cipher;
294bdcd8170SKalle Valo };
295bdcd8170SKalle Valo 
296bdcd8170SKalle Valo struct ath6kl_node_mapping {
297bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
298bdcd8170SKalle Valo 	u8 ep_id;
299bdcd8170SKalle Valo 	u8 tx_pend;
300bdcd8170SKalle Valo };
301bdcd8170SKalle Valo 
302bdcd8170SKalle Valo struct ath6kl_cookie {
303bdcd8170SKalle Valo 	struct sk_buff *skb;
304bdcd8170SKalle Valo 	u32 map_no;
305bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
306bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
307bdcd8170SKalle Valo };
308bdcd8170SKalle Valo 
309d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
310d0ff7383SNaveen Gangadharan 	struct list_head list;
311d0ff7383SNaveen Gangadharan 	u32 freq;
312d0ff7383SNaveen Gangadharan 	u32 wait;
313d0ff7383SNaveen Gangadharan 	u32 id;
314d0ff7383SNaveen Gangadharan 	bool no_cck;
315d0ff7383SNaveen Gangadharan 	size_t len;
316d0ff7383SNaveen Gangadharan 	u8 buf[0];
317d0ff7383SNaveen Gangadharan };
318d0ff7383SNaveen Gangadharan 
319bdcd8170SKalle Valo struct ath6kl_sta {
320bdcd8170SKalle Valo 	u16 sta_flags;
321bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
322bdcd8170SKalle Valo 	u8 aid;
323bdcd8170SKalle Valo 	u8 keymgmt;
324bdcd8170SKalle Valo 	u8 ucipher;
325bdcd8170SKalle Valo 	u8 auth;
326bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
327bdcd8170SKalle Valo 	struct sk_buff_head psq;
32812eb9444SKalle Valo 
32912eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
330bdcd8170SKalle Valo 	spinlock_t psq_lock;
33112eb9444SKalle Valo 
332d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
333d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
334c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
335c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3361d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
337bdcd8170SKalle Valo };
338bdcd8170SKalle Valo 
339bdcd8170SKalle Valo struct ath6kl_version {
340bdcd8170SKalle Valo 	u32 target_ver;
341bdcd8170SKalle Valo 	u32 wlan_ver;
342bdcd8170SKalle Valo 	u32 abi_ver;
343bdcd8170SKalle Valo };
344bdcd8170SKalle Valo 
345bdcd8170SKalle Valo struct ath6kl_bmi {
346bdcd8170SKalle Valo 	u32 cmd_credits;
347bdcd8170SKalle Valo 	bool done_sent;
348bdcd8170SKalle Valo 	u8 *cmd_buf;
3491f4c894dSKalle Valo 	u32 max_data_size;
3501f4c894dSKalle Valo 	u32 max_cmd_size;
351bdcd8170SKalle Valo };
352bdcd8170SKalle Valo 
353bdcd8170SKalle Valo struct target_stats {
354bdcd8170SKalle Valo 	u64 tx_pkt;
355bdcd8170SKalle Valo 	u64 tx_byte;
356bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
357bdcd8170SKalle Valo 	u64 tx_ucast_byte;
358bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
359bdcd8170SKalle Valo 	u64 tx_mcast_byte;
360bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
361bdcd8170SKalle Valo 	u64 tx_bcast_byte;
362bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
363bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
364bdcd8170SKalle Valo 
365bdcd8170SKalle Valo 	u64 tx_err;
366bdcd8170SKalle Valo 	u64 tx_fail_cnt;
367bdcd8170SKalle Valo 	u64 tx_retry_cnt;
368bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
369bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
370bdcd8170SKalle Valo 
371bdcd8170SKalle Valo 	u64 rx_pkt;
372bdcd8170SKalle Valo 	u64 rx_byte;
373bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
374bdcd8170SKalle Valo 	u64 rx_ucast_byte;
375bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
376bdcd8170SKalle Valo 	u64 rx_mcast_byte;
377bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
378bdcd8170SKalle Valo 	u64 rx_bcast_byte;
379bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
380bdcd8170SKalle Valo 
381bdcd8170SKalle Valo 	u64 rx_err;
382bdcd8170SKalle Valo 	u64 rx_crc_err;
383bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
384bdcd8170SKalle Valo 	u64 rx_decrypt_err;
385bdcd8170SKalle Valo 	u64 rx_dupl_frame;
386bdcd8170SKalle Valo 
387bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
388bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
389bdcd8170SKalle Valo 	u64 tkip_replays;
390bdcd8170SKalle Valo 	u64 tkip_fmt_err;
391bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
392bdcd8170SKalle Valo 	u64 ccmp_replays;
393bdcd8170SKalle Valo 
394bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
395bdcd8170SKalle Valo 
396bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
397bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
398bdcd8170SKalle Valo 	u64 cs_connect_cnt;
399bdcd8170SKalle Valo 	u64 cs_discon_cnt;
400bdcd8170SKalle Valo 
401bdcd8170SKalle Valo 	s32 tx_ucast_rate;
402bdcd8170SKalle Valo 	s32 rx_ucast_rate;
403bdcd8170SKalle Valo 
404bdcd8170SKalle Valo 	u32 lq_val;
405bdcd8170SKalle Valo 
406bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
407bdcd8170SKalle Valo 	u16 wow_evt_discarded;
408bdcd8170SKalle Valo 
409bdcd8170SKalle Valo 	s16 noise_floor_calib;
410bdcd8170SKalle Valo 	s16 cs_rssi;
411bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
412bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
413bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
414bdcd8170SKalle Valo 	u8 cs_snr;
415bdcd8170SKalle Valo 
416bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
417bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
418bdcd8170SKalle Valo 
419bdcd8170SKalle Valo 	u32 arp_received;
420bdcd8170SKalle Valo 	u32 arp_matched;
421bdcd8170SKalle Valo 	u32 arp_replied;
422bdcd8170SKalle Valo };
423bdcd8170SKalle Valo 
424bdcd8170SKalle Valo struct ath6kl_mbox_info {
425bdcd8170SKalle Valo 	u32 htc_addr;
426bdcd8170SKalle Valo 	u32 htc_ext_addr;
427bdcd8170SKalle Valo 	u32 htc_ext_sz;
428bdcd8170SKalle Valo 
429bdcd8170SKalle Valo 	u32 block_size;
430bdcd8170SKalle Valo 
431bdcd8170SKalle Valo 	u32 gmbox_addr;
432bdcd8170SKalle Valo 
433bdcd8170SKalle Valo 	u32 gmbox_sz;
434bdcd8170SKalle Valo };
435bdcd8170SKalle Valo 
436bdcd8170SKalle Valo /*
437bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
438bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
439bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
440bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
441bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
442bdcd8170SKalle Valo  */
443bdcd8170SKalle Valo 
444bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
445bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
446bdcd8170SKalle Valo 
447bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
448bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
449bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
450bdcd8170SKalle Valo 
4519a5b1318SJouni Malinen /* Initial group key for AP mode */
452bdcd8170SKalle Valo struct ath6kl_req_key {
4539a5b1318SJouni Malinen 	bool valid;
4549a5b1318SJouni Malinen 	u8 key_index;
4559a5b1318SJouni Malinen 	int key_type;
4569a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
4579a5b1318SJouni Malinen 	u8 key_len;
458bdcd8170SKalle Valo };
459bdcd8170SKalle Valo 
46077eab1e9SKalle Valo enum ath6kl_hif_type {
46177eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
46277eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
46377eab1e9SKalle Valo };
46477eab1e9SKalle Valo 
46580abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
46680abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
46780abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
46880abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
46980abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
47080abaf9bSVasanthakumar Thiagarajan };
47180abaf9bSVasanthakumar Thiagarajan 
47271f96ee6SKalle Valo /*
47371f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
47471f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
47571f96ee6SKalle Valo  */
476b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
477334234b5SVasanthakumar Thiagarajan 
47859c98449SVasanthakumar Thiagarajan /* vif flags info */
47959c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
48059c98449SVasanthakumar Thiagarajan 	CONNECTED,
48159c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
48259c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
48359c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
48459c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
48559c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
48659c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
48759c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
48859c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
489b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
490081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
49159c98449SVasanthakumar Thiagarajan };
49259c98449SVasanthakumar Thiagarajan 
493108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
494990bd915SVasanthakumar Thiagarajan 	struct list_head list;
495108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
496108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
497108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
498478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
499478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
500334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
50159c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5023450334fSVasanthakumar Thiagarajan 	int ssid_len;
5033450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5043450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5053450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5063450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5073450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5083450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5093450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5103450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
511f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
512f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5138c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5148c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
515f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
516f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5176f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5186f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5192132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
52010509f90SKalle Valo 
521de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
52210509f90SKalle Valo 	struct timer_list sched_scan_timer;
52310509f90SKalle Valo 
52414ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
52514ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
526cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
5271052261eSJouni Malinen 	u32 last_roc_id;
5281052261eSJouni Malinen 	u32 last_cancel_roc_id;
529cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
530cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
531cf5333d7SVasanthakumar Thiagarajan 	u16 next_chan;
532cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
5338f46fccdSRaja Mani 	u16 listen_intvl_t;
534ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
535cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
536b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
537b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
53880abaf9bSVasanthakumar Thiagarajan 
53980abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
540108438bcSVasanthakumar Thiagarajan };
541108438bcSVasanthakumar Thiagarajan 
5426cb3c714SRaja Mani #define WOW_LIST_ID		0
5436cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
5446cb3c714SRaja Mani 
54510509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
54610509f90SKalle Valo 
547bdcd8170SKalle Valo /* Flag info */
54859c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
54959c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
55059c98449SVasanthakumar Thiagarajan 	WMI_READY,
55159c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
55259c98449SVasanthakumar Thiagarajan 	TESTMODE,
55359c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
55459c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
55559c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
5565fe4dffbSKalle Valo 	FIRST_BOOT,
55759c98449SVasanthakumar Thiagarajan };
558bdcd8170SKalle Valo 
55976a9fbe2SKalle Valo enum ath6kl_state {
56076a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
56176a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
562390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
563390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
56476a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
565b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
566dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
56710509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
56876a9fbe2SKalle Valo };
56976a9fbe2SKalle Valo 
570bdcd8170SKalle Valo struct ath6kl {
571bdcd8170SKalle Valo 	struct device *dev;
572be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
57376a9fbe2SKalle Valo 
57476a9fbe2SKalle Valo 	enum ath6kl_state state;
5755f1127ffSKalle Valo 	unsigned int testmode;
57676a9fbe2SKalle Valo 
577bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
578bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
579bdcd8170SKalle Valo 	struct wmi *wmi;
580bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
581bdcd8170SKalle Valo 	int total_tx_data_pend;
582bdcd8170SKalle Valo 	struct htc_target *htc_target;
58377eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
584bdcd8170SKalle Valo 	void *hif_priv;
585990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
586990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
587990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
58855055976SVasanthakumar Thiagarajan 	u8 num_vif;
589368b1b0fSKalle Valo 	unsigned int vif_max;
5903226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
59155055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
59212eb9444SKalle Valo 
59312eb9444SKalle Valo 	/*
59412eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
59512eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
59612eb9444SKalle Valo 	 */
597bdcd8170SKalle Valo 	spinlock_t lock;
59812eb9444SKalle Valo 
599bdcd8170SKalle Valo 	struct semaphore sem;
600e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
601bdcd8170SKalle Valo 	struct ath6kl_version version;
602bdcd8170SKalle Valo 	u32 target_type;
603bdcd8170SKalle Valo 	u8 tx_pwr;
604bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
605bdcd8170SKalle Valo 	u8 ibss_ps_enable;
60655055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
607bdcd8170SKalle Valo 	u8 node_num;
608bdcd8170SKalle Valo 	u8 next_ep_id;
609bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
610bdcd8170SKalle Valo 	u32 cookie_count;
611bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
612bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
613bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
614bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
615bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
616bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
6173c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
618bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
619bdcd8170SKalle Valo 	u32 user_key_ctrl;
620bdcd8170SKalle Valo 	u8 usr_bss_filter;
621bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
622bdcd8170SKalle Valo 	u8 sta_list_index;
623bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
624bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
62512eb9444SKalle Valo 
62612eb9444SKalle Valo 	/*
62712eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
62812eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
62912eb9444SKalle Valo 	 */
630bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
63112eb9444SKalle Valo 
632bdcd8170SKalle Valo 	u8 intra_bss;
633bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
634bdcd8170SKalle Valo 	u8 ap_country_code[3];
635bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
636bdcd8170SKalle Valo 	u8 rx_meta_ver;
637bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
638d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
639bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
640003353b0SKalle Valo 	struct {
641003353b0SKalle Valo 		void *rx_report;
642003353b0SKalle Valo 		size_t rx_report_len;
643003353b0SKalle Valo 	} tm;
644003353b0SKalle Valo 
645856f4b31SKalle Valo 	struct ath6kl_hw {
646856f4b31SKalle Valo 		u32 id;
647293badf4SKalle Valo 		const char *name;
648a01ac414SKalle Valo 		u32 dataset_patch_addr;
649a01ac414SKalle Valo 		u32 app_load_addr;
650a01ac414SKalle Valo 		u32 app_start_override_addr;
651991b27eaSKalle Valo 		u32 board_ext_data_addr;
652991b27eaSKalle Valo 		u32 reserved_ram_size;
6530d4d72bfSKalle Valo 		u32 board_addr;
65439586bf2SRyan Hsu 		u32 refclk_hz;
65539586bf2SRyan Hsu 		u32 uarttx_pin;
656cd23c1c9SAlex Yang 		u32 testscript_addr;
657d1a9421dSKalle Valo 
658c0038972SKalle Valo 		struct ath6kl_hw_fw {
659c0038972SKalle Valo 			const char *dir;
660c0038972SKalle Valo 			const char *otp;
661d1a9421dSKalle Valo 			const char *fw;
662c0038972SKalle Valo 			const char *tcmd;
663c0038972SKalle Valo 			const char *patch;
664cd23c1c9SAlex Yang 			const char *utf;
665cd23c1c9SAlex Yang 			const char *testscript;
666c0038972SKalle Valo 		} fw;
667c0038972SKalle Valo 
668d1a9421dSKalle Valo 		const char *fw_board;
669d1a9421dSKalle Valo 		const char *fw_default_board;
670a01ac414SKalle Valo 	} hw;
671a01ac414SKalle Valo 
672bdcd8170SKalle Valo 	u16 conf_flags;
673e390af77SRaja Mani 	u16 suspend_mode;
6741e9a905dSRaja Mani 	u16 wow_suspend_mode;
675bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
676bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
677bdcd8170SKalle Valo 
678bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
679bdcd8170SKalle Valo 	unsigned long flag;
680bdcd8170SKalle Valo 
681bdcd8170SKalle Valo 	u8 *fw_board;
682bdcd8170SKalle Valo 	size_t fw_board_len;
683bdcd8170SKalle Valo 
684bdcd8170SKalle Valo 	u8 *fw_otp;
685bdcd8170SKalle Valo 	size_t fw_otp_len;
686bdcd8170SKalle Valo 
687bdcd8170SKalle Valo 	u8 *fw;
688bdcd8170SKalle Valo 	size_t fw_len;
689bdcd8170SKalle Valo 
690bdcd8170SKalle Valo 	u8 *fw_patch;
691bdcd8170SKalle Valo 	size_t fw_patch_len;
692bdcd8170SKalle Valo 
693cd23c1c9SAlex Yang 	u8 *fw_testscript;
694cd23c1c9SAlex Yang 	size_t fw_testscript_len;
695cd23c1c9SAlex Yang 
69665a8b4ccSKalle Valo 	unsigned int fw_api;
69797e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
69897e0496dSKalle Valo 
699bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7007c3075e9SVasanthakumar Thiagarajan 
701d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7026a7c9badSJouni Malinen 
7036bbc7c35SJouni Malinen 	bool p2p;
7046bbc7c35SJouni Malinen 
705e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
706e5348a1eSVasanthakumar Thiagarajan 
707bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
708bdf5396bSKalle Valo 	struct {
7099b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
710c807b30dSKalle Valo 		struct completion fwlog_completion;
711c807b30dSKalle Valo 		bool fwlog_open;
712c807b30dSKalle Valo 
713939f1cceSKalle Valo 		u32 fwlog_mask;
7149b9a4f2aSKalle Valo 
71591d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
716252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
717252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
7189a730834SKalle Valo 
7199a730834SKalle Valo 		struct {
7209a730834SKalle Valo 			unsigned int invalid_rate;
7219a730834SKalle Valo 		} war_stats;
7224b28a80dSJouni Malinen 
7234b28a80dSJouni Malinen 		u8 *roam_tbl;
7244b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
725ff0b0075SJouni Malinen 
726ff0b0075SJouni Malinen 		u8 keepalive;
727ff0b0075SJouni Malinen 		u8 disc_timeout;
728bdf5396bSKalle Valo 	} debug;
729bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
730bdcd8170SKalle Valo };
731bdcd8170SKalle Valo 
732d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
733bdcd8170SKalle Valo {
734108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
735bdcd8170SKalle Valo }
736bdcd8170SKalle Valo 
737bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
738bc07ddb2SKalle Valo 					  u32 item_offset)
739bc07ddb2SKalle Valo {
740bc07ddb2SKalle Valo 	u32 addr = 0;
741bc07ddb2SKalle Valo 
742bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
743bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
744bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
745bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
746bc07ddb2SKalle Valo 
747bc07ddb2SKalle Valo 	return addr;
748bc07ddb2SKalle Valo }
749bc07ddb2SKalle Valo 
750bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
751bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
752bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
753bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
754bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
755bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
756bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
75763de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
75863de1112SKalle Valo 			struct list_head *packet_queue);
759bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
760bdcd8170SKalle Valo 					       struct htc_packet *packet);
761bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
762bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
763f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
764addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
765addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
766addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
767bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
768e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
769bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
770bdcd8170SKalle Valo 
771bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
772bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
773bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
774bdcd8170SKalle Valo 
7757baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
776c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
777c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
778bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
779bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
780bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
781bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
782bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
783bdcd8170SKalle Valo 					    int len);
784bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
7851d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
786bdcd8170SKalle Valo 
7876765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
788bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
789bdcd8170SKalle Valo 
790bdcd8170SKalle Valo void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver);
791bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
792bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
793240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
794bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
795bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
796bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
797bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
798240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
799240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
800572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
801c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
802240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
803bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
804bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
805240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
806bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
807240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
808240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
809bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
810bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
811bdcd8170SKalle Valo 
812240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
813bdcd8170SKalle Valo 
814240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
815240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
816240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
817240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
818bdcd8170SKalle Valo 			     u8 win_sz);
819bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
820bdcd8170SKalle Valo 
8216db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
8226db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
823e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
824990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
82555055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
8265fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
8275fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
82845eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
82945eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
83045eaa78fSKalle Valo 
831a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
8325fe4dffbSKalle Valo 
83345eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
83445eaa78fSKalle Valo int ath6kl_core_init(struct ath6kl *ar);
83545eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
83645eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
83745eaa78fSKalle Valo 
838bdcd8170SKalle Valo #endif /* CORE_H */
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