1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
100d97c121bSVasanthakumar Thiagarajan 	/* Firmware has support to override rsn cap of rsn ie */
101d97c121bSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102d97c121bSVasanthakumar Thiagarajan 
10397e0496dSKalle Valo 	/* this needs to be last */
10497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
10597e0496dSKalle Valo };
10697e0496dSKalle Valo 
10797e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
10897e0496dSKalle Valo 
10950d41234SKalle Valo struct ath6kl_fw_ie {
11050d41234SKalle Valo 	__le32 id;
11150d41234SKalle Valo 	__le32 len;
11250d41234SKalle Valo 	u8 data[0];
11350d41234SKalle Valo };
11450d41234SKalle Valo 
115c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
11665a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
117c0038972SKalle Valo 
118bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1190d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
120bdcd8170SKalle Valo 
121bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1220d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1230d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
124c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
125c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
126c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
127c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
128c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1292023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
1300d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1312023dbb8STim Gardner 			AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
132bdcd8170SKalle Valo 
133bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1340d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
135c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
136c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
137c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
138c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
139cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
140cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
141c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1422023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
1430d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
1442023dbb8STim Gardner 			AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
145bdcd8170SKalle Valo 
14631024d99SKevin Fang /* AR6004 1.0 definitions */
1470d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
148c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
149c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1502023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE         AR6004_HW_1_0_FW_DIR "/bdata.bin"
1510d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
1522023dbb8STim Gardner 	AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
153d5720e59SKalle Valo 
154d5720e59SKalle Valo /* AR6004 1.1 definitions */
1550d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
156c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
157c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1582023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE         AR6004_HW_1_1_FW_DIR "/bdata.bin"
1590d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
1602023dbb8STim Gardner 	AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
16131024d99SKevin Fang 
1626146ca69SRay Chen /* AR6004 1.2 definitions */
1636146ca69SRay Chen #define AR6004_HW_1_2_VERSION                 0x300007e8
1646146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR			"ath6k/AR6004/hw1.2"
1656146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE           "fw.ram.bin"
1662023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE         AR6004_HW_1_2_FW_DIR "/bdata.bin"
1676146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
1682023dbb8STim Gardner 	AR6004_HW_1_2_FW_DIR "/bdata.bin"
1696146ca69SRay Chen 
170bdcd8170SKalle Valo /* Per STA data, used in AP mode */
171bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
172bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
173bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
174c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
175c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
176bdcd8170SKalle Valo 
177bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
178bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
179bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
180bdcd8170SKalle Valo 
181bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
182bdcd8170SKalle Valo 
183bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
184bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
185bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
186bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
187bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
188bdcd8170SKalle Valo 
189bdcd8170SKalle Valo #define NUM_OF_TIDS         8
190bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
191bdcd8170SKalle Valo 
192bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
193bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
194bdcd8170SKalle Valo 
195bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
196bdcd8170SKalle Valo 
197bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
198bdcd8170SKalle Valo 
199bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT     400	/* in ms */
200bdcd8170SKalle Valo 
201bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
202bdcd8170SKalle Valo 
203bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
204bdcd8170SKalle Valo 
2058f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
206ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
207ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
208ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
2098f46fccdSRaja Mani 
210bdcd8170SKalle Valo /* configuration lags */
211bdcd8170SKalle Valo /*
212bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
213bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
214bdcd8170SKalle Valo  * sending (Re)Assoc req.
215bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
216bdcd8170SKalle Valo  * module state transition failure events which happen during
217bdcd8170SKalle Valo  * scan, to the host.
218bdcd8170SKalle Valo  */
219bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
220bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
221bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
222bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
223e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
224bdcd8170SKalle Valo 
225c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
226c86e4f44SAarthi Thiruvengadam 
227bdcd8170SKalle Valo enum wlan_low_pwr_state {
228bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
229bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
230bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
231bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
232bdcd8170SKalle Valo };
233bdcd8170SKalle Valo 
234bdcd8170SKalle Valo enum sme_state {
235bdcd8170SKalle Valo 	SME_DISCONNECTED,
236bdcd8170SKalle Valo 	SME_CONNECTING,
237bdcd8170SKalle Valo 	SME_CONNECTED
238bdcd8170SKalle Valo };
239bdcd8170SKalle Valo 
240bdcd8170SKalle Valo struct skb_hold_q {
241bdcd8170SKalle Valo 	struct sk_buff *skb;
242bdcd8170SKalle Valo 	bool is_amsdu;
243bdcd8170SKalle Valo 	u16 seq_no;
244bdcd8170SKalle Valo };
245bdcd8170SKalle Valo 
246bdcd8170SKalle Valo struct rxtid {
247bdcd8170SKalle Valo 	bool aggr;
248bdcd8170SKalle Valo 	bool progress;
249bdcd8170SKalle Valo 	bool timer_mon;
250bdcd8170SKalle Valo 	u16 win_sz;
251bdcd8170SKalle Valo 	u16 seq_next;
252bdcd8170SKalle Valo 	u32 hold_q_sz;
253bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
254bdcd8170SKalle Valo 	struct sk_buff_head q;
25512eb9444SKalle Valo 
25612eb9444SKalle Valo 	/*
25712eb9444SKalle Valo 	 * FIXME: No clue what this should protect. Apparently it should
25812eb9444SKalle Valo 	 * protect some of the fields above but they are also accessed
25912eb9444SKalle Valo 	 * without taking the lock.
26012eb9444SKalle Valo 	 */
261bdcd8170SKalle Valo 	spinlock_t lock;
262bdcd8170SKalle Valo };
263bdcd8170SKalle Valo 
264bdcd8170SKalle Valo struct rxtid_stats {
265bdcd8170SKalle Valo 	u32 num_into_aggr;
266bdcd8170SKalle Valo 	u32 num_dups;
267bdcd8170SKalle Valo 	u32 num_oow;
268bdcd8170SKalle Valo 	u32 num_mpdu;
269bdcd8170SKalle Valo 	u32 num_amsdu;
270bdcd8170SKalle Valo 	u32 num_delivered;
271bdcd8170SKalle Valo 	u32 num_timeouts;
272bdcd8170SKalle Valo 	u32 num_hole;
273bdcd8170SKalle Valo 	u32 num_bar;
274bdcd8170SKalle Valo };
275bdcd8170SKalle Valo 
2767baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
277bdcd8170SKalle Valo 	u8 aggr_sz;
278bdcd8170SKalle Valo 	u8 timer_scheduled;
279bdcd8170SKalle Valo 	struct timer_list timer;
280bdcd8170SKalle Valo 	struct net_device *dev;
281bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
282bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
2837baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
2847baef812SVasanthakumar Thiagarajan };
2857baef812SVasanthakumar Thiagarajan 
2867baef812SVasanthakumar Thiagarajan struct aggr_info {
2877baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
2887baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
289bdcd8170SKalle Valo };
290bdcd8170SKalle Valo 
291bdcd8170SKalle Valo struct ath6kl_wep_key {
292bdcd8170SKalle Valo 	u8 key_index;
293bdcd8170SKalle Valo 	u8 key_len;
294bdcd8170SKalle Valo 	u8 key[64];
295bdcd8170SKalle Valo };
296bdcd8170SKalle Valo 
297bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
298bdcd8170SKalle Valo 
299bdcd8170SKalle Valo struct ath6kl_key {
300bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
301bdcd8170SKalle Valo 	u8 key_len;
302bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
303bdcd8170SKalle Valo 	u8 seq_len;
304bdcd8170SKalle Valo 	u32 cipher;
305bdcd8170SKalle Valo };
306bdcd8170SKalle Valo 
307bdcd8170SKalle Valo struct ath6kl_node_mapping {
308bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
309bdcd8170SKalle Valo 	u8 ep_id;
310bdcd8170SKalle Valo 	u8 tx_pend;
311bdcd8170SKalle Valo };
312bdcd8170SKalle Valo 
313bdcd8170SKalle Valo struct ath6kl_cookie {
314bdcd8170SKalle Valo 	struct sk_buff *skb;
315bdcd8170SKalle Valo 	u32 map_no;
316bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
317bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
318bdcd8170SKalle Valo };
319bdcd8170SKalle Valo 
320d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
321d0ff7383SNaveen Gangadharan 	struct list_head list;
322d0ff7383SNaveen Gangadharan 	u32 freq;
323d0ff7383SNaveen Gangadharan 	u32 wait;
324d0ff7383SNaveen Gangadharan 	u32 id;
325d0ff7383SNaveen Gangadharan 	bool no_cck;
326d0ff7383SNaveen Gangadharan 	size_t len;
327d0ff7383SNaveen Gangadharan 	u8 buf[0];
328d0ff7383SNaveen Gangadharan };
329d0ff7383SNaveen Gangadharan 
330bdcd8170SKalle Valo struct ath6kl_sta {
331bdcd8170SKalle Valo 	u16 sta_flags;
332bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
333bdcd8170SKalle Valo 	u8 aid;
334bdcd8170SKalle Valo 	u8 keymgmt;
335bdcd8170SKalle Valo 	u8 ucipher;
336bdcd8170SKalle Valo 	u8 auth;
337bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
338bdcd8170SKalle Valo 	struct sk_buff_head psq;
33912eb9444SKalle Valo 
34012eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
341bdcd8170SKalle Valo 	spinlock_t psq_lock;
34212eb9444SKalle Valo 
343d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
344d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
345c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
346c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3471d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
348bdcd8170SKalle Valo };
349bdcd8170SKalle Valo 
350bdcd8170SKalle Valo struct ath6kl_version {
351bdcd8170SKalle Valo 	u32 target_ver;
352bdcd8170SKalle Valo 	u32 wlan_ver;
353bdcd8170SKalle Valo 	u32 abi_ver;
354bdcd8170SKalle Valo };
355bdcd8170SKalle Valo 
356bdcd8170SKalle Valo struct ath6kl_bmi {
357bdcd8170SKalle Valo 	u32 cmd_credits;
358bdcd8170SKalle Valo 	bool done_sent;
359bdcd8170SKalle Valo 	u8 *cmd_buf;
3601f4c894dSKalle Valo 	u32 max_data_size;
3611f4c894dSKalle Valo 	u32 max_cmd_size;
362bdcd8170SKalle Valo };
363bdcd8170SKalle Valo 
364bdcd8170SKalle Valo struct target_stats {
365bdcd8170SKalle Valo 	u64 tx_pkt;
366bdcd8170SKalle Valo 	u64 tx_byte;
367bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
368bdcd8170SKalle Valo 	u64 tx_ucast_byte;
369bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
370bdcd8170SKalle Valo 	u64 tx_mcast_byte;
371bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
372bdcd8170SKalle Valo 	u64 tx_bcast_byte;
373bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
374bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
375bdcd8170SKalle Valo 
376bdcd8170SKalle Valo 	u64 tx_err;
377bdcd8170SKalle Valo 	u64 tx_fail_cnt;
378bdcd8170SKalle Valo 	u64 tx_retry_cnt;
379bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
380bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
381bdcd8170SKalle Valo 
382bdcd8170SKalle Valo 	u64 rx_pkt;
383bdcd8170SKalle Valo 	u64 rx_byte;
384bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
385bdcd8170SKalle Valo 	u64 rx_ucast_byte;
386bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
387bdcd8170SKalle Valo 	u64 rx_mcast_byte;
388bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
389bdcd8170SKalle Valo 	u64 rx_bcast_byte;
390bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
391bdcd8170SKalle Valo 
392bdcd8170SKalle Valo 	u64 rx_err;
393bdcd8170SKalle Valo 	u64 rx_crc_err;
394bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
395bdcd8170SKalle Valo 	u64 rx_decrypt_err;
396bdcd8170SKalle Valo 	u64 rx_dupl_frame;
397bdcd8170SKalle Valo 
398bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
399bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
400bdcd8170SKalle Valo 	u64 tkip_replays;
401bdcd8170SKalle Valo 	u64 tkip_fmt_err;
402bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
403bdcd8170SKalle Valo 	u64 ccmp_replays;
404bdcd8170SKalle Valo 
405bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
406bdcd8170SKalle Valo 
407bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
408bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
409bdcd8170SKalle Valo 	u64 cs_connect_cnt;
410bdcd8170SKalle Valo 	u64 cs_discon_cnt;
411bdcd8170SKalle Valo 
412bdcd8170SKalle Valo 	s32 tx_ucast_rate;
413bdcd8170SKalle Valo 	s32 rx_ucast_rate;
414bdcd8170SKalle Valo 
415bdcd8170SKalle Valo 	u32 lq_val;
416bdcd8170SKalle Valo 
417bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
418bdcd8170SKalle Valo 	u16 wow_evt_discarded;
419bdcd8170SKalle Valo 
420bdcd8170SKalle Valo 	s16 noise_floor_calib;
421bdcd8170SKalle Valo 	s16 cs_rssi;
422bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
423bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
424bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
425bdcd8170SKalle Valo 	u8 cs_snr;
426bdcd8170SKalle Valo 
427bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
428bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
429bdcd8170SKalle Valo 
430bdcd8170SKalle Valo 	u32 arp_received;
431bdcd8170SKalle Valo 	u32 arp_matched;
432bdcd8170SKalle Valo 	u32 arp_replied;
433bdcd8170SKalle Valo };
434bdcd8170SKalle Valo 
435bdcd8170SKalle Valo struct ath6kl_mbox_info {
436bdcd8170SKalle Valo 	u32 htc_addr;
437bdcd8170SKalle Valo 	u32 htc_ext_addr;
438bdcd8170SKalle Valo 	u32 htc_ext_sz;
439bdcd8170SKalle Valo 
440bdcd8170SKalle Valo 	u32 block_size;
441bdcd8170SKalle Valo 
442bdcd8170SKalle Valo 	u32 gmbox_addr;
443bdcd8170SKalle Valo 
444bdcd8170SKalle Valo 	u32 gmbox_sz;
445bdcd8170SKalle Valo };
446bdcd8170SKalle Valo 
447bdcd8170SKalle Valo /*
448bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
449bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
450bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
451bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
452bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
453bdcd8170SKalle Valo  */
454bdcd8170SKalle Valo 
455bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
456bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
457bdcd8170SKalle Valo 
458bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
459bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
460bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
461bdcd8170SKalle Valo 
4629a5b1318SJouni Malinen /* Initial group key for AP mode */
463bdcd8170SKalle Valo struct ath6kl_req_key {
4649a5b1318SJouni Malinen 	bool valid;
4659a5b1318SJouni Malinen 	u8 key_index;
4669a5b1318SJouni Malinen 	int key_type;
4679a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
4689a5b1318SJouni Malinen 	u8 key_len;
469bdcd8170SKalle Valo };
470bdcd8170SKalle Valo 
47177eab1e9SKalle Valo enum ath6kl_hif_type {
47277eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
47377eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
47477eab1e9SKalle Valo };
47577eab1e9SKalle Valo 
476e76ac2bfSKalle Valo enum ath6kl_htc_type {
477e76ac2bfSKalle Valo 	ATH6KL_HTC_TYPE_MBOX,
478636f8288SKalle Valo 	ATH6KL_HTC_TYPE_PIPE,
479e76ac2bfSKalle Valo };
480e76ac2bfSKalle Valo 
48180abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
48280abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
48380abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
48480abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
48580abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
48680abaf9bSVasanthakumar Thiagarajan };
48780abaf9bSVasanthakumar Thiagarajan 
488df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap {
489df90b369SVasanthakumar Thiagarajan 	bool ht_enable;
490df90b369SVasanthakumar Thiagarajan 	u8 ampdu_factor;
491df90b369SVasanthakumar Thiagarajan 	unsigned short cap_info;
492df90b369SVasanthakumar Thiagarajan };
493df90b369SVasanthakumar Thiagarajan 
49471f96ee6SKalle Valo /*
49571f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
49671f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
49771f96ee6SKalle Valo  */
498b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
499334234b5SVasanthakumar Thiagarajan 
50059c98449SVasanthakumar Thiagarajan /* vif flags info */
50159c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
50259c98449SVasanthakumar Thiagarajan 	CONNECTED,
50359c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
50459c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
50559c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
50659c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
50759c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
50859c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
50959c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
51059c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
511b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
512081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
5136251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_ON,
5146251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_OFF,
51559c98449SVasanthakumar Thiagarajan };
51659c98449SVasanthakumar Thiagarajan 
517108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
518990bd915SVasanthakumar Thiagarajan 	struct list_head list;
519108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
520108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
521108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
522478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
523478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
524334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
52559c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5263450334fSVasanthakumar Thiagarajan 	int ssid_len;
5273450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5283450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5293450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5303450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5313450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5323450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5333450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5343450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
535f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
536f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5378c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5388c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
539f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
540f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5416f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5426f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5432132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
544df90b369SVasanthakumar Thiagarajan 	struct ath6kl_htcap htcap;
54510509f90SKalle Valo 
546de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
54710509f90SKalle Valo 	struct timer_list sched_scan_timer;
54810509f90SKalle Valo 
54914ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
55014ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
551cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
5521052261eSJouni Malinen 	u32 last_roc_id;
5531052261eSJouni Malinen 	u32 last_cancel_roc_id;
554cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
555cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
556cf5333d7SVasanthakumar Thiagarajan 	u16 next_chan;
557df90b369SVasanthakumar Thiagarajan 	enum nl80211_channel_type next_ch_type;
558df90b369SVasanthakumar Thiagarajan 	enum ieee80211_band next_ch_band;
559cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
5608f46fccdSRaja Mani 	u16 listen_intvl_t;
561ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
562eb38987eSRaja Mani 	u16 bg_scan_period;
563cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
564b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
565b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
566c4f7863eSThomas Pedersen 	struct wmi_connect_cmd profile;
56780abaf9bSVasanthakumar Thiagarajan 
56880abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
569108438bcSVasanthakumar Thiagarajan };
570108438bcSVasanthakumar Thiagarajan 
5716cb3c714SRaja Mani #define WOW_LIST_ID		0
5726cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
5736cb3c714SRaja Mani 
57410509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
57510509f90SKalle Valo 
576bdcd8170SKalle Valo /* Flag info */
57759c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
57859c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
57959c98449SVasanthakumar Thiagarajan 	WMI_READY,
58059c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
58159c98449SVasanthakumar Thiagarajan 	TESTMODE,
58259c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
58359c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
58459c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
5855fe4dffbSKalle Valo 	FIRST_BOOT,
58659c98449SVasanthakumar Thiagarajan };
587bdcd8170SKalle Valo 
58876a9fbe2SKalle Valo enum ath6kl_state {
58976a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
59076a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
591390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
592390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
59376a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
594b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
595dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
59610509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
59776a9fbe2SKalle Valo };
59876a9fbe2SKalle Valo 
599bdcd8170SKalle Valo struct ath6kl {
600bdcd8170SKalle Valo 	struct device *dev;
601be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
60276a9fbe2SKalle Valo 
60376a9fbe2SKalle Valo 	enum ath6kl_state state;
6045f1127ffSKalle Valo 	unsigned int testmode;
60576a9fbe2SKalle Valo 
606bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
607bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
608e76ac2bfSKalle Valo 	const struct ath6kl_htc_ops *htc_ops;
609bdcd8170SKalle Valo 	struct wmi *wmi;
610bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
611bdcd8170SKalle Valo 	int total_tx_data_pend;
612bdcd8170SKalle Valo 	struct htc_target *htc_target;
61377eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
614bdcd8170SKalle Valo 	void *hif_priv;
615990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
616990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
617990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
61855055976SVasanthakumar Thiagarajan 	u8 num_vif;
619368b1b0fSKalle Valo 	unsigned int vif_max;
6203226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
62155055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
62212eb9444SKalle Valo 
62312eb9444SKalle Valo 	/*
62412eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
62512eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
62612eb9444SKalle Valo 	 */
627bdcd8170SKalle Valo 	spinlock_t lock;
62812eb9444SKalle Valo 
629bdcd8170SKalle Valo 	struct semaphore sem;
630e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
631bdcd8170SKalle Valo 	struct ath6kl_version version;
632bdcd8170SKalle Valo 	u32 target_type;
633bdcd8170SKalle Valo 	u8 tx_pwr;
634bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
635bdcd8170SKalle Valo 	u8 ibss_ps_enable;
63655055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
637bdcd8170SKalle Valo 	u8 node_num;
638bdcd8170SKalle Valo 	u8 next_ep_id;
639bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
640bdcd8170SKalle Valo 	u32 cookie_count;
641bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
642bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
643bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
644bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
645bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
646bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
6473c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
648bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
649bdcd8170SKalle Valo 	u32 user_key_ctrl;
650bdcd8170SKalle Valo 	u8 usr_bss_filter;
651bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
652bdcd8170SKalle Valo 	u8 sta_list_index;
653bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
654bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
655c4f7863eSThomas Pedersen 	u32 want_ch_switch;
65612eb9444SKalle Valo 
65712eb9444SKalle Valo 	/*
65812eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
65912eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
66012eb9444SKalle Valo 	 */
661bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
66212eb9444SKalle Valo 
663bdcd8170SKalle Valo 	u8 intra_bss;
664bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
665bdcd8170SKalle Valo 	u8 ap_country_code[3];
666bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
667bdcd8170SKalle Valo 	u8 rx_meta_ver;
668bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
669d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
670bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
671003353b0SKalle Valo 	struct {
672003353b0SKalle Valo 		void *rx_report;
673003353b0SKalle Valo 		size_t rx_report_len;
674003353b0SKalle Valo 	} tm;
675003353b0SKalle Valo 
676856f4b31SKalle Valo 	struct ath6kl_hw {
677856f4b31SKalle Valo 		u32 id;
678293badf4SKalle Valo 		const char *name;
679a01ac414SKalle Valo 		u32 dataset_patch_addr;
680a01ac414SKalle Valo 		u32 app_load_addr;
681a01ac414SKalle Valo 		u32 app_start_override_addr;
682991b27eaSKalle Valo 		u32 board_ext_data_addr;
683991b27eaSKalle Valo 		u32 reserved_ram_size;
6840d4d72bfSKalle Valo 		u32 board_addr;
68539586bf2SRyan Hsu 		u32 refclk_hz;
68639586bf2SRyan Hsu 		u32 uarttx_pin;
687cd23c1c9SAlex Yang 		u32 testscript_addr;
688d92917e4SThomas Pedersen 		enum wmi_phy_cap cap;
689d1a9421dSKalle Valo 
690c0038972SKalle Valo 		struct ath6kl_hw_fw {
691c0038972SKalle Valo 			const char *dir;
692c0038972SKalle Valo 			const char *otp;
693d1a9421dSKalle Valo 			const char *fw;
694c0038972SKalle Valo 			const char *tcmd;
695c0038972SKalle Valo 			const char *patch;
696cd23c1c9SAlex Yang 			const char *utf;
697cd23c1c9SAlex Yang 			const char *testscript;
698c0038972SKalle Valo 		} fw;
699c0038972SKalle Valo 
700d1a9421dSKalle Valo 		const char *fw_board;
701d1a9421dSKalle Valo 		const char *fw_default_board;
702a01ac414SKalle Valo 	} hw;
703a01ac414SKalle Valo 
704bdcd8170SKalle Valo 	u16 conf_flags;
705e390af77SRaja Mani 	u16 suspend_mode;
7061e9a905dSRaja Mani 	u16 wow_suspend_mode;
707bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
708bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
709bdcd8170SKalle Valo 
710bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
711bdcd8170SKalle Valo 	unsigned long flag;
712bdcd8170SKalle Valo 
713bdcd8170SKalle Valo 	u8 *fw_board;
714bdcd8170SKalle Valo 	size_t fw_board_len;
715bdcd8170SKalle Valo 
716bdcd8170SKalle Valo 	u8 *fw_otp;
717bdcd8170SKalle Valo 	size_t fw_otp_len;
718bdcd8170SKalle Valo 
719bdcd8170SKalle Valo 	u8 *fw;
720bdcd8170SKalle Valo 	size_t fw_len;
721bdcd8170SKalle Valo 
722bdcd8170SKalle Valo 	u8 *fw_patch;
723bdcd8170SKalle Valo 	size_t fw_patch_len;
724bdcd8170SKalle Valo 
725cd23c1c9SAlex Yang 	u8 *fw_testscript;
726cd23c1c9SAlex Yang 	size_t fw_testscript_len;
727cd23c1c9SAlex Yang 
72865a8b4ccSKalle Valo 	unsigned int fw_api;
72997e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
73097e0496dSKalle Valo 
731bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7327c3075e9SVasanthakumar Thiagarajan 
733d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7346a7c9badSJouni Malinen 
7356bbc7c35SJouni Malinen 	bool p2p;
7366bbc7c35SJouni Malinen 
737e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
738e5348a1eSVasanthakumar Thiagarajan 
739bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
740bdf5396bSKalle Valo 	struct {
7419b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
742c807b30dSKalle Valo 		struct completion fwlog_completion;
743c807b30dSKalle Valo 		bool fwlog_open;
744c807b30dSKalle Valo 
745939f1cceSKalle Valo 		u32 fwlog_mask;
7469b9a4f2aSKalle Valo 
74791d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
748252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
749252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
7509a730834SKalle Valo 
7519a730834SKalle Valo 		struct {
7529a730834SKalle Valo 			unsigned int invalid_rate;
7539a730834SKalle Valo 		} war_stats;
7544b28a80dSJouni Malinen 
7554b28a80dSJouni Malinen 		u8 *roam_tbl;
7564b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
757ff0b0075SJouni Malinen 
758ff0b0075SJouni Malinen 		u8 keepalive;
759ff0b0075SJouni Malinen 		u8 disc_timeout;
760bdf5396bSKalle Valo 	} debug;
761bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
762bdcd8170SKalle Valo };
763bdcd8170SKalle Valo 
764d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
765bdcd8170SKalle Valo {
766108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
767bdcd8170SKalle Valo }
768bdcd8170SKalle Valo 
769bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
770bc07ddb2SKalle Valo 					  u32 item_offset)
771bc07ddb2SKalle Valo {
772bc07ddb2SKalle Valo 	u32 addr = 0;
773bc07ddb2SKalle Valo 
774bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
775bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
776bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
777bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
778bc07ddb2SKalle Valo 
779bc07ddb2SKalle Valo 	return addr;
780bc07ddb2SKalle Valo }
781bc07ddb2SKalle Valo 
782bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
783bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
784bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
785bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
786bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
787bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
788bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
78963de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
79063de1112SKalle Valo 			struct list_head *packet_queue);
791bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
792bdcd8170SKalle Valo 					       struct htc_packet *packet);
793bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
794bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
795f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
796addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
797addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
798addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
799bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
800e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
801bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
802bdcd8170SKalle Valo 
803bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
804bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
805bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
806bdcd8170SKalle Valo 
8077baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
808c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
809c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
810bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
811bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
812bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
813bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
814bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
815bdcd8170SKalle Valo 					    int len);
816bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
8171d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
818bdcd8170SKalle Valo 
8196765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
820bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
821bdcd8170SKalle Valo 
822d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
823d92917e4SThomas Pedersen 			enum wmi_phy_cap cap);
824bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
825bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
826240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
827bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
828bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
829bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
830bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
831240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
832240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
833572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
834c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
835240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
836bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
837bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
838240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
839bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
840240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
841240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
842bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
843bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
844bdcd8170SKalle Valo 
845240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
846bdcd8170SKalle Valo 
847240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
848240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
849240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
850240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
851bdcd8170SKalle Valo 			     u8 win_sz);
852bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
853bdcd8170SKalle Valo 
8546db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
8556db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
856e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
857990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
85855055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
8595fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
8605fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
86145eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
86245eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
86345eaa78fSKalle Valo 
864a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
8655fe4dffbSKalle Valo 
866636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
867636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
868636f8288SKalle Valo 
86945eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
870e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
87145eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
87245eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
87345eaa78fSKalle Valo 
874bdcd8170SKalle Valo #endif /* CORE_H */
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