1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
3bdcd8170SKalle Valo  *
4bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
5bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
6bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
7bdcd8170SKalle Valo  *
8bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15bdcd8170SKalle Valo  */
16bdcd8170SKalle Valo 
17bdcd8170SKalle Valo #ifndef CORE_H
18bdcd8170SKalle Valo #define CORE_H
19bdcd8170SKalle Valo 
20bdcd8170SKalle Valo #include <linux/etherdevice.h>
21bdcd8170SKalle Valo #include <linux/rtnetlink.h>
22bdcd8170SKalle Valo #include <linux/firmware.h>
23bdcd8170SKalle Valo #include <linux/sched.h>
24bdf5396bSKalle Valo #include <linux/circ_buf.h>
25bdcd8170SKalle Valo #include <net/cfg80211.h>
26bdcd8170SKalle Valo #include "htc.h"
27bdcd8170SKalle Valo #include "wmi.h"
28bdcd8170SKalle Valo #include "bmi.h"
29bc07ddb2SKalle Valo #include "target.h"
30bdcd8170SKalle Valo 
31bdcd8170SKalle Valo #define MAX_ATH6KL                        1
32bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
33bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
34bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
35bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
37bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
38bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
39bdcd8170SKalle Valo 
40bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
42bdcd8170SKalle Valo 
43bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
44bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
45bdcd8170SKalle Valo #define MAX_NODE_NUM           15
46bdcd8170SKalle Valo 
471df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
481df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
491df94a85SVasanthakumar Thiagarajan 
50bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
51bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
52bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
53bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
54bdcd8170SKalle Valo 
55bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
56bdcd8170SKalle Valo 
57bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
58bdcd8170SKalle Valo #define A_DEFAULT_LISTEN_INTERVAL         100
59bdcd8170SKalle Valo #define A_MAX_WOW_LISTEN_INTERVAL         1000
60bdcd8170SKalle Valo 
6150d41234SKalle Valo /* includes also the null byte */
6250d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6350d41234SKalle Valo 
6450d41234SKalle Valo enum ath6kl_fw_ie_type {
6550d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
6650d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
6750d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
6850d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
6950d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
708a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7197e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
721b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7303ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
74368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
7550d41234SKalle Valo };
7650d41234SKalle Valo 
7797e0496dSKalle Valo enum ath6kl_fw_capability {
7897e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
7910509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8097e0496dSKalle Valo 
813ca9d1fcSAarthi Thiruvengadam 	/*
823ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
833ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
843ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
853ca9d1fcSAarthi Thiruvengadam 	 */
863ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
873ca9d1fcSAarthi Thiruvengadam 
8897e0496dSKalle Valo 	/* this needs to be last */
8997e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
9097e0496dSKalle Valo };
9197e0496dSKalle Valo 
9297e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
9397e0496dSKalle Valo 
9450d41234SKalle Valo struct ath6kl_fw_ie {
9550d41234SKalle Valo 	__le32 id;
9650d41234SKalle Valo 	__le32 len;
9750d41234SKalle Valo 	u8 data[0];
9850d41234SKalle Valo };
9950d41234SKalle Valo 
100bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1010d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
102bdcd8170SKalle Valo 
103bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1040d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1050d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
1060d0192baSKalle Valo #define AR6003_HW_2_0_OTP_FILE "ath6k/AR6003/hw2.0/otp.bin.z77"
1070d0192baSKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athwlan.bin.z77"
1080d0192baSKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athtcmd_ram.bin"
1090d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_FILE "ath6k/AR6003/hw2.0/data.patch.bin"
1100d0192baSKalle Valo #define AR6003_HW_2_0_FIRMWARE_2_FILE "ath6k/AR6003/hw2.0/fw-2.bin"
1110d0192baSKalle Valo #define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin"
1120d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1130d0192baSKalle Valo 			"ath6k/AR6003/hw2.0/bdata.SD31.bin"
114bdcd8170SKalle Valo 
115bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1160d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
1170d0192baSKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "ath6k/AR6003/hw2.1.1/otp.bin"
1180d0192baSKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/athwlan.bin"
1190d0192baSKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE \
1200d0192baSKalle Valo 			"ath6k/AR6003/hw2.1.1/athtcmd_ram.bin"
1210d0192baSKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "ath6k/AR6003/hw2.1.1/data.patch.bin"
1220d0192baSKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_2_FILE "ath6k/AR6003/hw2.1.1/fw-2.bin"
1230d0192baSKalle Valo #define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin"
1240d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
125bdcd8170SKalle Valo 			"ath6k/AR6003/hw2.1.1/bdata.SD31.bin"
126bdcd8170SKalle Valo 
12731024d99SKevin Fang /* AR6004 1.0 definitions */
1280d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
1290d0192baSKalle Valo #define AR6004_HW_1_0_FIRMWARE_2_FILE         "ath6k/AR6004/hw1.0/fw-2.bin"
1300d0192baSKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE           "ath6k/AR6004/hw1.0/fw.ram.bin"
1310d0192baSKalle Valo #define AR6004_HW_1_0_BOARD_DATA_FILE         "ath6k/AR6004/hw1.0/bdata.bin"
1320d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
133d5720e59SKalle Valo 	"ath6k/AR6004/hw1.0/bdata.DB132.bin"
134d5720e59SKalle Valo 
135d5720e59SKalle Valo /* AR6004 1.1 definitions */
1360d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
1370d0192baSKalle Valo #define AR6004_HW_1_1_FIRMWARE_2_FILE         "ath6k/AR6004/hw1.1/fw-2.bin"
1380d0192baSKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE           "ath6k/AR6004/hw1.1/fw.ram.bin"
1390d0192baSKalle Valo #define AR6004_HW_1_1_BOARD_DATA_FILE         "ath6k/AR6004/hw1.1/bdata.bin"
1400d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
141d5720e59SKalle Valo 	"ath6k/AR6004/hw1.1/bdata.DB132.bin"
14231024d99SKevin Fang 
143bdcd8170SKalle Valo /* Per STA data, used in AP mode */
144bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
145bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
146bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
147bdcd8170SKalle Valo 
148bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
149bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
150bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
151bdcd8170SKalle Valo 
152bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
153bdcd8170SKalle Valo 
154bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
155bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
156bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
157bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
158bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
159bdcd8170SKalle Valo 
160bdcd8170SKalle Valo #define NUM_OF_TIDS         8
161bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
162bdcd8170SKalle Valo 
163bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
164bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
165bdcd8170SKalle Valo 
166bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
167bdcd8170SKalle Valo 
168bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
169bdcd8170SKalle Valo 
170bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT     400	/* in ms */
171bdcd8170SKalle Valo 
172bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
173bdcd8170SKalle Valo 
174bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
175bdcd8170SKalle Valo 
176bdcd8170SKalle Valo /* configuration lags */
177bdcd8170SKalle Valo /*
178bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
179bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
180bdcd8170SKalle Valo  * sending (Re)Assoc req.
181bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
182bdcd8170SKalle Valo  * module state transition failure events which happen during
183bdcd8170SKalle Valo  * scan, to the host.
184bdcd8170SKalle Valo  */
185bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
186bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
187bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
188bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
1898277de15SKalle Valo #define ATH6KL_CONF_SUSPEND_CUTPOWER		BIT(4)
190bdcd8170SKalle Valo 
191bdcd8170SKalle Valo enum wlan_low_pwr_state {
192bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
193bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
194bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
195bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
196bdcd8170SKalle Valo };
197bdcd8170SKalle Valo 
198bdcd8170SKalle Valo enum sme_state {
199bdcd8170SKalle Valo 	SME_DISCONNECTED,
200bdcd8170SKalle Valo 	SME_CONNECTING,
201bdcd8170SKalle Valo 	SME_CONNECTED
202bdcd8170SKalle Valo };
203bdcd8170SKalle Valo 
204bdcd8170SKalle Valo struct skb_hold_q {
205bdcd8170SKalle Valo 	struct sk_buff *skb;
206bdcd8170SKalle Valo 	bool is_amsdu;
207bdcd8170SKalle Valo 	u16 seq_no;
208bdcd8170SKalle Valo };
209bdcd8170SKalle Valo 
210bdcd8170SKalle Valo struct rxtid {
211bdcd8170SKalle Valo 	bool aggr;
212bdcd8170SKalle Valo 	bool progress;
213bdcd8170SKalle Valo 	bool timer_mon;
214bdcd8170SKalle Valo 	u16 win_sz;
215bdcd8170SKalle Valo 	u16 seq_next;
216bdcd8170SKalle Valo 	u32 hold_q_sz;
217bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
218bdcd8170SKalle Valo 	struct sk_buff_head q;
219bdcd8170SKalle Valo 	spinlock_t lock;
220bdcd8170SKalle Valo };
221bdcd8170SKalle Valo 
222bdcd8170SKalle Valo struct rxtid_stats {
223bdcd8170SKalle Valo 	u32 num_into_aggr;
224bdcd8170SKalle Valo 	u32 num_dups;
225bdcd8170SKalle Valo 	u32 num_oow;
226bdcd8170SKalle Valo 	u32 num_mpdu;
227bdcd8170SKalle Valo 	u32 num_amsdu;
228bdcd8170SKalle Valo 	u32 num_delivered;
229bdcd8170SKalle Valo 	u32 num_timeouts;
230bdcd8170SKalle Valo 	u32 num_hole;
231bdcd8170SKalle Valo 	u32 num_bar;
232bdcd8170SKalle Valo };
233bdcd8170SKalle Valo 
234bdcd8170SKalle Valo struct aggr_info {
235bdcd8170SKalle Valo 	u8 aggr_sz;
236bdcd8170SKalle Valo 	u8 timer_scheduled;
237bdcd8170SKalle Valo 	struct timer_list timer;
238bdcd8170SKalle Valo 	struct net_device *dev;
239bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
240bdcd8170SKalle Valo 	struct sk_buff_head free_q;
241bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
242bdcd8170SKalle Valo };
243bdcd8170SKalle Valo 
244bdcd8170SKalle Valo struct ath6kl_wep_key {
245bdcd8170SKalle Valo 	u8 key_index;
246bdcd8170SKalle Valo 	u8 key_len;
247bdcd8170SKalle Valo 	u8 key[64];
248bdcd8170SKalle Valo };
249bdcd8170SKalle Valo 
250bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
251bdcd8170SKalle Valo 
252bdcd8170SKalle Valo struct ath6kl_key {
253bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
254bdcd8170SKalle Valo 	u8 key_len;
255bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
256bdcd8170SKalle Valo 	u8 seq_len;
257bdcd8170SKalle Valo 	u32 cipher;
258bdcd8170SKalle Valo };
259bdcd8170SKalle Valo 
260bdcd8170SKalle Valo struct ath6kl_node_mapping {
261bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
262bdcd8170SKalle Valo 	u8 ep_id;
263bdcd8170SKalle Valo 	u8 tx_pend;
264bdcd8170SKalle Valo };
265bdcd8170SKalle Valo 
266bdcd8170SKalle Valo struct ath6kl_cookie {
267bdcd8170SKalle Valo 	struct sk_buff *skb;
268bdcd8170SKalle Valo 	u32 map_no;
269bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
270bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
271bdcd8170SKalle Valo };
272bdcd8170SKalle Valo 
273bdcd8170SKalle Valo struct ath6kl_sta {
274bdcd8170SKalle Valo 	u16 sta_flags;
275bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
276bdcd8170SKalle Valo 	u8 aid;
277bdcd8170SKalle Valo 	u8 keymgmt;
278bdcd8170SKalle Valo 	u8 ucipher;
279bdcd8170SKalle Valo 	u8 auth;
280bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
281bdcd8170SKalle Valo 	struct sk_buff_head psq;
282bdcd8170SKalle Valo 	spinlock_t psq_lock;
283bdcd8170SKalle Valo };
284bdcd8170SKalle Valo 
285bdcd8170SKalle Valo struct ath6kl_version {
286bdcd8170SKalle Valo 	u32 target_ver;
287bdcd8170SKalle Valo 	u32 wlan_ver;
288bdcd8170SKalle Valo 	u32 abi_ver;
289bdcd8170SKalle Valo };
290bdcd8170SKalle Valo 
291bdcd8170SKalle Valo struct ath6kl_bmi {
292bdcd8170SKalle Valo 	u32 cmd_credits;
293bdcd8170SKalle Valo 	bool done_sent;
294bdcd8170SKalle Valo 	u8 *cmd_buf;
2951f4c894dSKalle Valo 	u32 max_data_size;
2961f4c894dSKalle Valo 	u32 max_cmd_size;
297bdcd8170SKalle Valo };
298bdcd8170SKalle Valo 
299bdcd8170SKalle Valo struct target_stats {
300bdcd8170SKalle Valo 	u64 tx_pkt;
301bdcd8170SKalle Valo 	u64 tx_byte;
302bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
303bdcd8170SKalle Valo 	u64 tx_ucast_byte;
304bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
305bdcd8170SKalle Valo 	u64 tx_mcast_byte;
306bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
307bdcd8170SKalle Valo 	u64 tx_bcast_byte;
308bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
309bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
310bdcd8170SKalle Valo 
311bdcd8170SKalle Valo 	u64 tx_err;
312bdcd8170SKalle Valo 	u64 tx_fail_cnt;
313bdcd8170SKalle Valo 	u64 tx_retry_cnt;
314bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
315bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
316bdcd8170SKalle Valo 
317bdcd8170SKalle Valo 	u64 rx_pkt;
318bdcd8170SKalle Valo 	u64 rx_byte;
319bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
320bdcd8170SKalle Valo 	u64 rx_ucast_byte;
321bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
322bdcd8170SKalle Valo 	u64 rx_mcast_byte;
323bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
324bdcd8170SKalle Valo 	u64 rx_bcast_byte;
325bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
326bdcd8170SKalle Valo 
327bdcd8170SKalle Valo 	u64 rx_err;
328bdcd8170SKalle Valo 	u64 rx_crc_err;
329bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
330bdcd8170SKalle Valo 	u64 rx_decrypt_err;
331bdcd8170SKalle Valo 	u64 rx_dupl_frame;
332bdcd8170SKalle Valo 
333bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
334bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
335bdcd8170SKalle Valo 	u64 tkip_replays;
336bdcd8170SKalle Valo 	u64 tkip_fmt_err;
337bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
338bdcd8170SKalle Valo 	u64 ccmp_replays;
339bdcd8170SKalle Valo 
340bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
341bdcd8170SKalle Valo 
342bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
343bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
344bdcd8170SKalle Valo 	u64 cs_connect_cnt;
345bdcd8170SKalle Valo 	u64 cs_discon_cnt;
346bdcd8170SKalle Valo 
347bdcd8170SKalle Valo 	s32 tx_ucast_rate;
348bdcd8170SKalle Valo 	s32 rx_ucast_rate;
349bdcd8170SKalle Valo 
350bdcd8170SKalle Valo 	u32 lq_val;
351bdcd8170SKalle Valo 
352bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
353bdcd8170SKalle Valo 	u16 wow_evt_discarded;
354bdcd8170SKalle Valo 
355bdcd8170SKalle Valo 	s16 noise_floor_calib;
356bdcd8170SKalle Valo 	s16 cs_rssi;
357bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
358bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
359bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
360bdcd8170SKalle Valo 	u8 cs_snr;
361bdcd8170SKalle Valo 
362bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
363bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
364bdcd8170SKalle Valo 
365bdcd8170SKalle Valo 	u32 arp_received;
366bdcd8170SKalle Valo 	u32 arp_matched;
367bdcd8170SKalle Valo 	u32 arp_replied;
368bdcd8170SKalle Valo };
369bdcd8170SKalle Valo 
370bdcd8170SKalle Valo struct ath6kl_mbox_info {
371bdcd8170SKalle Valo 	u32 htc_addr;
372bdcd8170SKalle Valo 	u32 htc_ext_addr;
373bdcd8170SKalle Valo 	u32 htc_ext_sz;
374bdcd8170SKalle Valo 
375bdcd8170SKalle Valo 	u32 block_size;
376bdcd8170SKalle Valo 
377bdcd8170SKalle Valo 	u32 gmbox_addr;
378bdcd8170SKalle Valo 
379bdcd8170SKalle Valo 	u32 gmbox_sz;
380bdcd8170SKalle Valo };
381bdcd8170SKalle Valo 
382bdcd8170SKalle Valo /*
383bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
384bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
385bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
386bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
387bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
388bdcd8170SKalle Valo  */
389bdcd8170SKalle Valo 
390bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
391bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
392bdcd8170SKalle Valo 
393bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
394bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
395bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
396bdcd8170SKalle Valo 
3979a5b1318SJouni Malinen /* Initial group key for AP mode */
398bdcd8170SKalle Valo struct ath6kl_req_key {
3999a5b1318SJouni Malinen 	bool valid;
4009a5b1318SJouni Malinen 	u8 key_index;
4019a5b1318SJouni Malinen 	int key_type;
4029a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
4039a5b1318SJouni Malinen 	u8 key_len;
404bdcd8170SKalle Valo };
405bdcd8170SKalle Valo 
40677eab1e9SKalle Valo enum ath6kl_hif_type {
40777eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
40877eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
40977eab1e9SKalle Valo };
41077eab1e9SKalle Valo 
41171f96ee6SKalle Valo /*
41271f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
41371f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
41471f96ee6SKalle Valo  */
415b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
416334234b5SVasanthakumar Thiagarajan 
41759c98449SVasanthakumar Thiagarajan /* vif flags info */
41859c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
41959c98449SVasanthakumar Thiagarajan 	CONNECTED,
42059c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
42159c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
42259c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
42359c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
42459c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
42559c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
42659c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
42759c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
428b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
42959c98449SVasanthakumar Thiagarajan };
43059c98449SVasanthakumar Thiagarajan 
431108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
432990bd915SVasanthakumar Thiagarajan 	struct list_head list;
433108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
434108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
435108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
436478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
437478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
438334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
43959c98449SVasanthakumar Thiagarajan 	unsigned long flags;
4403450334fSVasanthakumar Thiagarajan 	int ssid_len;
4413450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
4423450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
4433450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
4443450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
4453450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
4463450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
4473450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
4483450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
449f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
450f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
4518c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
4528c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
453f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
454f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
4556f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
4566f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
4572132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
45810509f90SKalle Valo 
459de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
46010509f90SKalle Valo 	struct timer_list sched_scan_timer;
46110509f90SKalle Valo 
46214ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
46314ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
464cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
4651052261eSJouni Malinen 	u32 last_roc_id;
4661052261eSJouni Malinen 	u32 last_cancel_roc_id;
467cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
468cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
469cf5333d7SVasanthakumar Thiagarajan 	u16 next_chan;
470cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
471cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
472b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
473b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
474108438bcSVasanthakumar Thiagarajan };
475108438bcSVasanthakumar Thiagarajan 
4766cb3c714SRaja Mani #define WOW_LIST_ID		0
4776cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
4786cb3c714SRaja Mani 
47910509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
48010509f90SKalle Valo 
481bdcd8170SKalle Valo /* Flag info */
48259c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
48359c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
48459c98449SVasanthakumar Thiagarajan 	WMI_READY,
48559c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
48659c98449SVasanthakumar Thiagarajan 	TESTMODE,
48759c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
48859c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
48959c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
4905fe4dffbSKalle Valo 	FIRST_BOOT,
49159c98449SVasanthakumar Thiagarajan };
492bdcd8170SKalle Valo 
49376a9fbe2SKalle Valo enum ath6kl_state {
49476a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
49576a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
49676a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
497b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
498dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
49910509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
50076a9fbe2SKalle Valo };
50176a9fbe2SKalle Valo 
502bdcd8170SKalle Valo struct ath6kl {
503bdcd8170SKalle Valo 	struct device *dev;
504be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
50576a9fbe2SKalle Valo 
50676a9fbe2SKalle Valo 	enum ath6kl_state state;
50776a9fbe2SKalle Valo 
508bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
509bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
510bdcd8170SKalle Valo 	struct wmi *wmi;
511bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
512bdcd8170SKalle Valo 	int total_tx_data_pend;
513bdcd8170SKalle Valo 	struct htc_target *htc_target;
51477eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
515bdcd8170SKalle Valo 	void *hif_priv;
516990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
517990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
518990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
51955055976SVasanthakumar Thiagarajan 	u8 num_vif;
520368b1b0fSKalle Valo 	unsigned int vif_max;
5213226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
52255055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
523bdcd8170SKalle Valo 	spinlock_t lock;
524bdcd8170SKalle Valo 	struct semaphore sem;
525bdcd8170SKalle Valo 	u16 listen_intvl_b;
526bdcd8170SKalle Valo 	u16 listen_intvl_t;
527e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
528bdcd8170SKalle Valo 	struct ath6kl_version version;
529bdcd8170SKalle Valo 	u32 target_type;
530bdcd8170SKalle Valo 	u8 tx_pwr;
531bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
532bdcd8170SKalle Valo 	u8 ibss_ps_enable;
53355055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
534bdcd8170SKalle Valo 	u8 node_num;
535bdcd8170SKalle Valo 	u8 next_ep_id;
536bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
537bdcd8170SKalle Valo 	u32 cookie_count;
538bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
539bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
540bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
541bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
542bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
543bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
5443c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
545bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
546bdcd8170SKalle Valo 	u32 user_key_ctrl;
547bdcd8170SKalle Valo 	u8 usr_bss_filter;
548bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
549bdcd8170SKalle Valo 	u8 sta_list_index;
550bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
551bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
552bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
553bdcd8170SKalle Valo 	u8 intra_bss;
554bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
555bdcd8170SKalle Valo 	u8 ap_country_code[3];
556bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
557bdcd8170SKalle Valo 	u8 rx_meta_ver;
558bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
559d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
560bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
561003353b0SKalle Valo 	struct {
562003353b0SKalle Valo 		void *rx_report;
563003353b0SKalle Valo 		size_t rx_report_len;
564003353b0SKalle Valo 	} tm;
565003353b0SKalle Valo 
566856f4b31SKalle Valo 	struct ath6kl_hw {
567856f4b31SKalle Valo 		u32 id;
568293badf4SKalle Valo 		const char *name;
569a01ac414SKalle Valo 		u32 dataset_patch_addr;
570a01ac414SKalle Valo 		u32 app_load_addr;
571a01ac414SKalle Valo 		u32 app_start_override_addr;
572991b27eaSKalle Valo 		u32 board_ext_data_addr;
573991b27eaSKalle Valo 		u32 reserved_ram_size;
5740d4d72bfSKalle Valo 		u32 board_addr;
57539586bf2SRyan Hsu 		u32 refclk_hz;
57639586bf2SRyan Hsu 		u32 uarttx_pin;
577d1a9421dSKalle Valo 
578d1a9421dSKalle Valo 		const char *fw_otp;
579d1a9421dSKalle Valo 		const char *fw;
580d1a9421dSKalle Valo 		const char *fw_tcmd;
581d1a9421dSKalle Valo 		const char *fw_patch;
582d1a9421dSKalle Valo 		const char *fw_api2;
583d1a9421dSKalle Valo 		const char *fw_board;
584d1a9421dSKalle Valo 		const char *fw_default_board;
585a01ac414SKalle Valo 	} hw;
586a01ac414SKalle Valo 
587bdcd8170SKalle Valo 	u16 conf_flags;
588bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
589bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
590bdcd8170SKalle Valo 
591bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
592bdcd8170SKalle Valo 	unsigned long flag;
593bdcd8170SKalle Valo 
594bdcd8170SKalle Valo 	u8 *fw_board;
595bdcd8170SKalle Valo 	size_t fw_board_len;
596bdcd8170SKalle Valo 
597bdcd8170SKalle Valo 	u8 *fw_otp;
598bdcd8170SKalle Valo 	size_t fw_otp_len;
599bdcd8170SKalle Valo 
600bdcd8170SKalle Valo 	u8 *fw;
601bdcd8170SKalle Valo 	size_t fw_len;
602bdcd8170SKalle Valo 
603bdcd8170SKalle Valo 	u8 *fw_patch;
604bdcd8170SKalle Valo 	size_t fw_patch_len;
605bdcd8170SKalle Valo 
60697e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
60797e0496dSKalle Valo 
608bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
6097c3075e9SVasanthakumar Thiagarajan 
610d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
6116a7c9badSJouni Malinen 
6126bbc7c35SJouni Malinen 	bool p2p;
6136bbc7c35SJouni Malinen 
614bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
615bdf5396bSKalle Valo 	struct {
616bdf5396bSKalle Valo 		struct circ_buf fwlog_buf;
617bdf5396bSKalle Valo 		spinlock_t fwlog_lock;
618bdf5396bSKalle Valo 		void *fwlog_tmp;
619939f1cceSKalle Valo 		u32 fwlog_mask;
62091d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
621252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
622252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
6239a730834SKalle Valo 
6249a730834SKalle Valo 		struct {
6259a730834SKalle Valo 			unsigned int invalid_rate;
6269a730834SKalle Valo 		} war_stats;
6274b28a80dSJouni Malinen 
6284b28a80dSJouni Malinen 		u8 *roam_tbl;
6294b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
630ff0b0075SJouni Malinen 
631ff0b0075SJouni Malinen 		u8 keepalive;
632ff0b0075SJouni Malinen 		u8 disc_timeout;
633bdf5396bSKalle Valo 	} debug;
634bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
635bdcd8170SKalle Valo };
636bdcd8170SKalle Valo 
637d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
638bdcd8170SKalle Valo {
639108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
640bdcd8170SKalle Valo }
641bdcd8170SKalle Valo 
642bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
643bc07ddb2SKalle Valo 					  u32 item_offset)
644bc07ddb2SKalle Valo {
645bc07ddb2SKalle Valo 	u32 addr = 0;
646bc07ddb2SKalle Valo 
647bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
648bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
649bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
650bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
651bc07ddb2SKalle Valo 
652bc07ddb2SKalle Valo 	return addr;
653bc07ddb2SKalle Valo }
654bc07ddb2SKalle Valo 
655bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
656bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
657bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
658bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
659bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
660bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
661bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
662bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue);
663bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
664bdcd8170SKalle Valo 					       struct htc_packet *packet);
665bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
666bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
667f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
668addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
669addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
670addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
671bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
672e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
673bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
674bdcd8170SKalle Valo 
675bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
676bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
677bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
678bdcd8170SKalle Valo 
679bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev);
680bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
681bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
682bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
683bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
684bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
685bdcd8170SKalle Valo 					    int len);
686bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
687bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info);
688bdcd8170SKalle Valo 
6896765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 * node_addr);
690bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
691bdcd8170SKalle Valo 
692bdcd8170SKalle Valo void ath6kl_ready_event(void *devt, u8 * datap, u32 sw_ver, u32 abi_ver);
693bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
694bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
695240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
696bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
697bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
698bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
699bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
700240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
701240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
702572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
703572e27c0SJouni Malinen 				u8 assoc_req_len, u8 *assoc_info);
704240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
705bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
706bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
707240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
708bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
709240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
710240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
711bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
712bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
713bdcd8170SKalle Valo 
714240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
715bdcd8170SKalle Valo 
716240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
717240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
718240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
719240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
720bdcd8170SKalle Valo 			     u8 win_sz);
721bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
722bdcd8170SKalle Valo 
7236db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
7246db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
725e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
726108438bcSVasanthakumar Thiagarajan void ath6kl_deinit_if_data(struct ath6kl_vif *vif);
7278dafb70eSVasanthakumar Thiagarajan void ath6kl_core_free(struct ath6kl *ar);
728990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
72955055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
7305fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
7315fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
732a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
7335fe4dffbSKalle Valo 
734bdcd8170SKalle Valo #endif /* CORE_H */
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