1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2010-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo  *
5bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo  *
9bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo  */
17bdcd8170SKalle Valo 
18bdcd8170SKalle Valo #ifndef CORE_H
19bdcd8170SKalle Valo #define CORE_H
20bdcd8170SKalle Valo 
21bdcd8170SKalle Valo #include <linux/etherdevice.h>
22bdcd8170SKalle Valo #include <linux/rtnetlink.h>
23bdcd8170SKalle Valo #include <linux/firmware.h>
24bdcd8170SKalle Valo #include <linux/sched.h>
25bdf5396bSKalle Valo #include <linux/circ_buf.h>
26bdcd8170SKalle Valo #include <net/cfg80211.h>
27bdcd8170SKalle Valo #include "htc.h"
28bdcd8170SKalle Valo #include "wmi.h"
29bdcd8170SKalle Valo #include "bmi.h"
30bc07ddb2SKalle Valo #include "target.h"
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo #define MAX_ATH6KL                        1
33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS             16
34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE                1664
35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS       4
36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD     3
37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE     (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN	1508
39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN	46
40bdcd8170SKalle Valo 
41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT     0
42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN      1
43bdcd8170SKalle Valo 
44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT      10
45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS   4
46bdcd8170SKalle Valo #define MAX_NODE_NUM           15
47bdcd8170SKalle Valo 
48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME		0xFFFF
49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC		0x4
50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK		0xF
51c1762a3fSThirumalai Pachamuthu 
521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */
531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3
541df94a85SVasanthakumar Thiagarajan 
55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM                180
57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM                 18	/* 10% of MAX_COOKIE_NUM */
58bdcd8170SKalle Valo #define MAX_COOKIE_NUM                 (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
59bdcd8170SKalle Valo 
60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL               10000  /* in msec */
63bdcd8170SKalle Valo 
6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */
6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL		50 /* in ms */
6613423c31SVasanthakumar Thiagarajan 
6750d41234SKalle Valo /* includes also the null byte */
6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC               "QCA-ATH6KL"
6950d41234SKalle Valo 
7050d41234SKalle Valo enum ath6kl_fw_ie_type {
7150d41234SKalle Valo 	ATH6KL_FW_IE_FW_VERSION = 0,
7250d41234SKalle Valo 	ATH6KL_FW_IE_TIMESTAMP = 1,
7350d41234SKalle Valo 	ATH6KL_FW_IE_OTP_IMAGE = 2,
7450d41234SKalle Valo 	ATH6KL_FW_IE_FW_IMAGE = 3,
7550d41234SKalle Valo 	ATH6KL_FW_IE_PATCH_IMAGE = 4,
768a137480SKalle Valo 	ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
7797e0496dSKalle Valo 	ATH6KL_FW_IE_CAPABILITIES = 6,
781b4304daSKalle Valo 	ATH6KL_FW_IE_PATCH_ADDR = 7,
7903ef0250SKalle Valo 	ATH6KL_FW_IE_BOARD_ADDR = 8,
80368b1b0fSKalle Valo 	ATH6KL_FW_IE_VIF_MAX = 9,
8150d41234SKalle Valo };
8250d41234SKalle Valo 
8397e0496dSKalle Valo enum ath6kl_fw_capability {
8497e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
8510509f90SKalle Valo 	ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
8697e0496dSKalle Valo 
873ca9d1fcSAarthi Thiruvengadam 	/*
883ca9d1fcSAarthi Thiruvengadam 	 * Firmware is capable of supporting P2P mgmt operations on a
893ca9d1fcSAarthi Thiruvengadam 	 * station interface. After group formation, the station
903ca9d1fcSAarthi Thiruvengadam 	 * interface will become a P2P client/GO interface as the case may be
913ca9d1fcSAarthi Thiruvengadam 	 */
923ca9d1fcSAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
933ca9d1fcSAarthi Thiruvengadam 
9403bdeb0dSVasanthakumar Thiagarajan 	/*
9503bdeb0dSVasanthakumar Thiagarajan 	 * Firmware has support to cleanup inactive stations
9603bdeb0dSVasanthakumar Thiagarajan 	 * in AP mode.
9703bdeb0dSVasanthakumar Thiagarajan 	 */
9803bdeb0dSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
9903bdeb0dSVasanthakumar Thiagarajan 
100d97c121bSVasanthakumar Thiagarajan 	/* Firmware has support to override rsn cap of rsn ie */
101d97c121bSVasanthakumar Thiagarajan 	ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
102d97c121bSVasanthakumar Thiagarajan 
1036821d4f0SNaveen Gangadharan 	/*
1046821d4f0SNaveen Gangadharan 	 * Multicast support in WOW and host awake mode.
1056821d4f0SNaveen Gangadharan 	 * Allow all multicast in host awake mode.
1066821d4f0SNaveen Gangadharan 	 * Apply multicast filter in WOW mode.
1076821d4f0SNaveen Gangadharan 	 */
1086821d4f0SNaveen Gangadharan 	ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
1096821d4f0SNaveen Gangadharan 
110c422d52dSThomas Pedersen 	/* Firmware supports enhanced bmiss detection */
111c422d52dSThomas Pedersen 	ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
112c422d52dSThomas Pedersen 
113dd45b759SNaveen Singh 	/*
114dd45b759SNaveen Singh 	 * FW supports matching of ssid in schedule scan
115dd45b759SNaveen Singh 	 */
116dd45b759SNaveen Singh 	ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
117dd45b759SNaveen Singh 
11885b20fc2SThomas Pedersen 	/* Firmware supports filtering BSS results by RSSI */
11985b20fc2SThomas Pedersen 	ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
12085b20fc2SThomas Pedersen 
121c95dcb59SAarthi Thiruvengadam 	/* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */
122c95dcb59SAarthi Thiruvengadam 	ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
123c95dcb59SAarthi Thiruvengadam 
124279b2862SThomas Pedersen 	/* Firmware supports TX error rate notification */
125279b2862SThomas Pedersen 	ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY,
126279b2862SThomas Pedersen 
12797e0496dSKalle Valo 	/* this needs to be last */
12897e0496dSKalle Valo 	ATH6KL_FW_CAPABILITY_MAX,
12997e0496dSKalle Valo };
13097e0496dSKalle Valo 
13197e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
13297e0496dSKalle Valo 
13350d41234SKalle Valo struct ath6kl_fw_ie {
13450d41234SKalle Valo 	__le32 id;
13550d41234SKalle Valo 	__le32 len;
13650d41234SKalle Valo 	u8 data[0];
13750d41234SKalle Valo };
13850d41234SKalle Valo 
13906e360acSBala Shanmugam enum ath6kl_hw_flags {
14006e360acSBala Shanmugam 	ATH6KL_HW_FLAG_64BIT_RATES	= BIT(0),
14106e360acSBala Shanmugam };
14206e360acSBala Shanmugam 
143c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin"
14465a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin"
145c0038972SKalle Valo 
146bdcd8170SKalle Valo /* AR6003 1.0 definitions */
1470d0192baSKalle Valo #define AR6003_HW_1_0_VERSION                 0x300002ba
148bdcd8170SKalle Valo 
149bdcd8170SKalle Valo /* AR6003 2.0 definitions */
1500d0192baSKalle Valo #define AR6003_HW_2_0_VERSION                 0x30000384
1510d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS  0x57e910
152c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR			"ath6k/AR6003/hw2.0"
153c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE			"otp.bin.z77"
154c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE		"athwlan.bin.z77"
155c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
156c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE		"data.patch.bin"
1572023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
1580d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
1592023dbb8STim Gardner 			AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
160bdcd8170SKalle Valo 
161bdcd8170SKalle Valo /* AR6003 3.0 definitions */
1620d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION                 0x30000582
163c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR			"ath6k/AR6003/hw2.1.1"
164c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE		"otp.bin"
165c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE		"athwlan.bin"
166c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE	"athtcmd_ram.bin"
167cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE	"utf.bin"
168cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE	"nullTestFlow.bin"
169c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE		"data.patch.bin"
1702023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
1710d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE	\
1722023dbb8STim Gardner 			AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
173bdcd8170SKalle Valo 
17431024d99SKevin Fang /* AR6004 1.0 definitions */
1750d0192baSKalle Valo #define AR6004_HW_1_0_VERSION                 0x30000623
176c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR			"ath6k/AR6004/hw1.0"
177c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE		"fw.ram.bin"
1782023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE         AR6004_HW_1_0_FW_DIR "/bdata.bin"
1790d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
1802023dbb8STim Gardner 	AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
181d5720e59SKalle Valo 
182d5720e59SKalle Valo /* AR6004 1.1 definitions */
1830d0192baSKalle Valo #define AR6004_HW_1_1_VERSION                 0x30000001
184c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR			"ath6k/AR6004/hw1.1"
185c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE		"fw.ram.bin"
1862023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE         AR6004_HW_1_1_FW_DIR "/bdata.bin"
1870d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
1882023dbb8STim Gardner 	AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
18931024d99SKevin Fang 
1906146ca69SRay Chen /* AR6004 1.2 definitions */
1916146ca69SRay Chen #define AR6004_HW_1_2_VERSION                 0x300007e8
1926146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR			"ath6k/AR6004/hw1.2"
1936146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE           "fw.ram.bin"
1942023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE         AR6004_HW_1_2_FW_DIR "/bdata.bin"
1956146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
1962023dbb8STim Gardner 	AR6004_HW_1_2_FW_DIR "/bdata.bin"
1976146ca69SRay Chen 
198bf744f11SBala Shanmugam /* AR6004 1.3 definitions */
199bf744f11SBala Shanmugam #define AR6004_HW_1_3_VERSION			0x31c8088a
200bf744f11SBala Shanmugam #define AR6004_HW_1_3_FW_DIR			"ath6k/AR6004/hw1.3"
201bf744f11SBala Shanmugam #define AR6004_HW_1_3_FIRMWARE_FILE		"fw.ram.bin"
202bf744f11SBala Shanmugam #define AR6004_HW_1_3_BOARD_DATA_FILE		"ath6k/AR6004/hw1.3/bdata.bin"
203bf744f11SBala Shanmugam #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE	"ath6k/AR6004/hw1.3/bdata.bin"
204bf744f11SBala Shanmugam 
205bdcd8170SKalle Valo /* Per STA data, used in AP mode */
206bdcd8170SKalle Valo #define STA_PS_AWAKE		BIT(0)
207bdcd8170SKalle Valo #define	STA_PS_SLEEP		BIT(1)
208bdcd8170SKalle Valo #define	STA_PS_POLLED		BIT(2)
209c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER     BIT(3)
210c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP        BIT(4)
211bdcd8170SKalle Valo 
212bdcd8170SKalle Valo /* HTC TX packet tagging definitions */
213bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
214bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG       (ATH6KL_CONTROL_PKT_TAG + 1)
215bdcd8170SKalle Valo 
216bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16
217bdcd8170SKalle Valo 
218bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y)          ((x) % (y))
219bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x) + 1), (y))
220bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x) - 1), (y))
221bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO		0xFFF
222bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x)		(((x) + 1) & ATH6KL_MAX_SEQ_NO)
223bdcd8170SKalle Valo 
224bdcd8170SKalle Valo #define NUM_OF_TIDS         8
225bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT     8
226bdcd8170SKalle Valo 
227bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN     2
228bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX     8
229bdcd8170SKalle Valo 
230bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x)   ((_x) << 1)
231bdcd8170SKalle Valo 
232bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS    16
233bdcd8170SKalle Valo 
2347940bad5SVasanthakumar Thiagarajan #define AGGR_RX_TIMEOUT     100	/* in ms */
235bdcd8170SKalle Valo 
236bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ)
237bdcd8170SKalle Valo 
238bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99
239bdcd8170SKalle Valo 
2408f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL	100 /* in TUs */
241ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME	1500
242ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL	300 /* in TUs */
243ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME		5000
2448f46fccdSRaja Mani 
245bdcd8170SKalle Valo /* configuration lags */
246bdcd8170SKalle Valo /*
247bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
248bdcd8170SKalle Valo  * ERP IE of beacon to determine the short premable support when
249bdcd8170SKalle Valo  * sending (Re)Assoc req.
250bdcd8170SKalle Valo  * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
251bdcd8170SKalle Valo  * module state transition failure events which happen during
252bdcd8170SKalle Valo  * scan, to the host.
253bdcd8170SKalle Valo  */
254bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER		BIT(0)
255bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN  BIT(1)
256bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N			BIT(2)
257bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST		BIT(3)
258e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG			BIT(4)
259bdcd8170SKalle Valo 
260c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN			7 /* DIRECT- */
261c86e4f44SAarthi Thiruvengadam 
262bdcd8170SKalle Valo enum wlan_low_pwr_state {
263bdcd8170SKalle Valo 	WLAN_POWER_STATE_ON,
264bdcd8170SKalle Valo 	WLAN_POWER_STATE_CUT_PWR,
265bdcd8170SKalle Valo 	WLAN_POWER_STATE_DEEP_SLEEP,
266bdcd8170SKalle Valo 	WLAN_POWER_STATE_WOW
267bdcd8170SKalle Valo };
268bdcd8170SKalle Valo 
269bdcd8170SKalle Valo enum sme_state {
270bdcd8170SKalle Valo 	SME_DISCONNECTED,
271bdcd8170SKalle Valo 	SME_CONNECTING,
272bdcd8170SKalle Valo 	SME_CONNECTED
273bdcd8170SKalle Valo };
274bdcd8170SKalle Valo 
275bdcd8170SKalle Valo struct skb_hold_q {
276bdcd8170SKalle Valo 	struct sk_buff *skb;
277bdcd8170SKalle Valo 	bool is_amsdu;
278bdcd8170SKalle Valo 	u16 seq_no;
279bdcd8170SKalle Valo };
280bdcd8170SKalle Valo 
281bdcd8170SKalle Valo struct rxtid {
282bdcd8170SKalle Valo 	bool aggr;
283bdcd8170SKalle Valo 	bool timer_mon;
284bdcd8170SKalle Valo 	u16 win_sz;
285bdcd8170SKalle Valo 	u16 seq_next;
286bdcd8170SKalle Valo 	u32 hold_q_sz;
287bdcd8170SKalle Valo 	struct skb_hold_q *hold_q;
288bdcd8170SKalle Valo 	struct sk_buff_head q;
28912eb9444SKalle Valo 
29012eb9444SKalle Valo 	/*
2910faf7458SVasanthakumar Thiagarajan 	 * lock mainly protects seq_next and hold_q. Movement of seq_next
2920faf7458SVasanthakumar Thiagarajan 	 * needs to be protected between aggr_timeout() and
2930faf7458SVasanthakumar Thiagarajan 	 * aggr_process_recv_frm(). hold_q will be holding the pending
2940faf7458SVasanthakumar Thiagarajan 	 * reorder frames and it's access should also be protected.
2950faf7458SVasanthakumar Thiagarajan 	 * Some of the other fields like hold_q_sz, win_sz and aggr are
2960faf7458SVasanthakumar Thiagarajan 	 * initialized/reset when receiving addba/delba req, also while
2970faf7458SVasanthakumar Thiagarajan 	 * deleting aggr state all the pending buffers are flushed before
2980faf7458SVasanthakumar Thiagarajan 	 * resetting these fields, so there should not be any race in accessing
2990faf7458SVasanthakumar Thiagarajan 	 * these fields.
30012eb9444SKalle Valo 	 */
301bdcd8170SKalle Valo 	spinlock_t lock;
302bdcd8170SKalle Valo };
303bdcd8170SKalle Valo 
304bdcd8170SKalle Valo struct rxtid_stats {
305bdcd8170SKalle Valo 	u32 num_into_aggr;
306bdcd8170SKalle Valo 	u32 num_dups;
307bdcd8170SKalle Valo 	u32 num_oow;
308bdcd8170SKalle Valo 	u32 num_mpdu;
309bdcd8170SKalle Valo 	u32 num_amsdu;
310bdcd8170SKalle Valo 	u32 num_delivered;
311bdcd8170SKalle Valo 	u32 num_timeouts;
312bdcd8170SKalle Valo 	u32 num_hole;
313bdcd8170SKalle Valo 	u32 num_bar;
314bdcd8170SKalle Valo };
315bdcd8170SKalle Valo 
3167baef812SVasanthakumar Thiagarajan struct aggr_info_conn {
317bdcd8170SKalle Valo 	u8 aggr_sz;
318bdcd8170SKalle Valo 	u8 timer_scheduled;
319bdcd8170SKalle Valo 	struct timer_list timer;
320bdcd8170SKalle Valo 	struct net_device *dev;
321bdcd8170SKalle Valo 	struct rxtid rx_tid[NUM_OF_TIDS];
322bdcd8170SKalle Valo 	struct rxtid_stats stat[NUM_OF_TIDS];
3237baef812SVasanthakumar Thiagarajan 	struct aggr_info *aggr_info;
3247baef812SVasanthakumar Thiagarajan };
3257baef812SVasanthakumar Thiagarajan 
3267baef812SVasanthakumar Thiagarajan struct aggr_info {
3277baef812SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
3287baef812SVasanthakumar Thiagarajan 	struct sk_buff_head rx_amsdu_freeq;
329bdcd8170SKalle Valo };
330bdcd8170SKalle Valo 
331bdcd8170SKalle Valo struct ath6kl_wep_key {
332bdcd8170SKalle Valo 	u8 key_index;
333bdcd8170SKalle Valo 	u8 key_len;
334bdcd8170SKalle Valo 	u8 key[64];
335bdcd8170SKalle Valo };
336bdcd8170SKalle Valo 
337bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8
338bdcd8170SKalle Valo 
339bdcd8170SKalle Valo struct ath6kl_key {
340bdcd8170SKalle Valo 	u8 key[WLAN_MAX_KEY_LEN];
341bdcd8170SKalle Valo 	u8 key_len;
342bdcd8170SKalle Valo 	u8 seq[ATH6KL_KEY_SEQ_LEN];
343bdcd8170SKalle Valo 	u8 seq_len;
344bdcd8170SKalle Valo 	u32 cipher;
345bdcd8170SKalle Valo };
346bdcd8170SKalle Valo 
347bdcd8170SKalle Valo struct ath6kl_node_mapping {
348bdcd8170SKalle Valo 	u8 mac_addr[ETH_ALEN];
349bdcd8170SKalle Valo 	u8 ep_id;
350bdcd8170SKalle Valo 	u8 tx_pend;
351bdcd8170SKalle Valo };
352bdcd8170SKalle Valo 
353bdcd8170SKalle Valo struct ath6kl_cookie {
354bdcd8170SKalle Valo 	struct sk_buff *skb;
355bdcd8170SKalle Valo 	u32 map_no;
356bdcd8170SKalle Valo 	struct htc_packet htc_pkt;
357bdcd8170SKalle Valo 	struct ath6kl_cookie *arc_list_next;
358bdcd8170SKalle Valo };
359bdcd8170SKalle Valo 
360d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff {
361d0ff7383SNaveen Gangadharan 	struct list_head list;
362d0ff7383SNaveen Gangadharan 	u32 freq;
363d0ff7383SNaveen Gangadharan 	u32 wait;
364d0ff7383SNaveen Gangadharan 	u32 id;
365d0ff7383SNaveen Gangadharan 	bool no_cck;
366d0ff7383SNaveen Gangadharan 	size_t len;
367d0ff7383SNaveen Gangadharan 	u8 buf[0];
368d0ff7383SNaveen Gangadharan };
369d0ff7383SNaveen Gangadharan 
370bdcd8170SKalle Valo struct ath6kl_sta {
371bdcd8170SKalle Valo 	u16 sta_flags;
372bdcd8170SKalle Valo 	u8 mac[ETH_ALEN];
373bdcd8170SKalle Valo 	u8 aid;
374bdcd8170SKalle Valo 	u8 keymgmt;
375bdcd8170SKalle Valo 	u8 ucipher;
376bdcd8170SKalle Valo 	u8 auth;
377bdcd8170SKalle Valo 	u8 wpa_ie[ATH6KL_MAX_IE];
378bdcd8170SKalle Valo 	struct sk_buff_head psq;
37912eb9444SKalle Valo 
38012eb9444SKalle Valo 	/* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
381bdcd8170SKalle Valo 	spinlock_t psq_lock;
38212eb9444SKalle Valo 
383d0ff7383SNaveen Gangadharan 	struct list_head mgmt_psq;
384d0ff7383SNaveen Gangadharan 	size_t mgmt_psq_len;
385c1762a3fSThirumalai Pachamuthu 	u8 apsd_info;
386c1762a3fSThirumalai Pachamuthu 	struct sk_buff_head apsdq;
3871d2a4456SVasanthakumar Thiagarajan 	struct aggr_info_conn *aggr_conn;
388bdcd8170SKalle Valo };
389bdcd8170SKalle Valo 
390bdcd8170SKalle Valo struct ath6kl_version {
391bdcd8170SKalle Valo 	u32 target_ver;
392bdcd8170SKalle Valo 	u32 wlan_ver;
393bdcd8170SKalle Valo 	u32 abi_ver;
394bdcd8170SKalle Valo };
395bdcd8170SKalle Valo 
396bdcd8170SKalle Valo struct ath6kl_bmi {
397bdcd8170SKalle Valo 	u32 cmd_credits;
398bdcd8170SKalle Valo 	bool done_sent;
399bdcd8170SKalle Valo 	u8 *cmd_buf;
4001f4c894dSKalle Valo 	u32 max_data_size;
4011f4c894dSKalle Valo 	u32 max_cmd_size;
402bdcd8170SKalle Valo };
403bdcd8170SKalle Valo 
404bdcd8170SKalle Valo struct target_stats {
405bdcd8170SKalle Valo 	u64 tx_pkt;
406bdcd8170SKalle Valo 	u64 tx_byte;
407bdcd8170SKalle Valo 	u64 tx_ucast_pkt;
408bdcd8170SKalle Valo 	u64 tx_ucast_byte;
409bdcd8170SKalle Valo 	u64 tx_mcast_pkt;
410bdcd8170SKalle Valo 	u64 tx_mcast_byte;
411bdcd8170SKalle Valo 	u64 tx_bcast_pkt;
412bdcd8170SKalle Valo 	u64 tx_bcast_byte;
413bdcd8170SKalle Valo 	u64 tx_rts_success_cnt;
414bdcd8170SKalle Valo 	u64 tx_pkt_per_ac[4];
415bdcd8170SKalle Valo 
416bdcd8170SKalle Valo 	u64 tx_err;
417bdcd8170SKalle Valo 	u64 tx_fail_cnt;
418bdcd8170SKalle Valo 	u64 tx_retry_cnt;
419bdcd8170SKalle Valo 	u64 tx_mult_retry_cnt;
420bdcd8170SKalle Valo 	u64 tx_rts_fail_cnt;
421bdcd8170SKalle Valo 
422bdcd8170SKalle Valo 	u64 rx_pkt;
423bdcd8170SKalle Valo 	u64 rx_byte;
424bdcd8170SKalle Valo 	u64 rx_ucast_pkt;
425bdcd8170SKalle Valo 	u64 rx_ucast_byte;
426bdcd8170SKalle Valo 	u64 rx_mcast_pkt;
427bdcd8170SKalle Valo 	u64 rx_mcast_byte;
428bdcd8170SKalle Valo 	u64 rx_bcast_pkt;
429bdcd8170SKalle Valo 	u64 rx_bcast_byte;
430bdcd8170SKalle Valo 	u64 rx_frgment_pkt;
431bdcd8170SKalle Valo 
432bdcd8170SKalle Valo 	u64 rx_err;
433bdcd8170SKalle Valo 	u64 rx_crc_err;
434bdcd8170SKalle Valo 	u64 rx_key_cache_miss;
435bdcd8170SKalle Valo 	u64 rx_decrypt_err;
436bdcd8170SKalle Valo 	u64 rx_dupl_frame;
437bdcd8170SKalle Valo 
438bdcd8170SKalle Valo 	u64 tkip_local_mic_fail;
439bdcd8170SKalle Valo 	u64 tkip_cnter_measures_invoked;
440bdcd8170SKalle Valo 	u64 tkip_replays;
441bdcd8170SKalle Valo 	u64 tkip_fmt_err;
442bdcd8170SKalle Valo 	u64 ccmp_fmt_err;
443bdcd8170SKalle Valo 	u64 ccmp_replays;
444bdcd8170SKalle Valo 
445bdcd8170SKalle Valo 	u64 pwr_save_fail_cnt;
446bdcd8170SKalle Valo 
447bdcd8170SKalle Valo 	u64 cs_bmiss_cnt;
448bdcd8170SKalle Valo 	u64 cs_low_rssi_cnt;
449bdcd8170SKalle Valo 	u64 cs_connect_cnt;
450bdcd8170SKalle Valo 	u64 cs_discon_cnt;
451bdcd8170SKalle Valo 
452bdcd8170SKalle Valo 	s32 tx_ucast_rate;
453bdcd8170SKalle Valo 	s32 rx_ucast_rate;
454bdcd8170SKalle Valo 
455bdcd8170SKalle Valo 	u32 lq_val;
456bdcd8170SKalle Valo 
457bdcd8170SKalle Valo 	u32 wow_pkt_dropped;
458bdcd8170SKalle Valo 	u16 wow_evt_discarded;
459bdcd8170SKalle Valo 
460bdcd8170SKalle Valo 	s16 noise_floor_calib;
461bdcd8170SKalle Valo 	s16 cs_rssi;
462bdcd8170SKalle Valo 	s16 cs_ave_beacon_rssi;
463bdcd8170SKalle Valo 	u8 cs_ave_beacon_snr;
464bdcd8170SKalle Valo 	u8 cs_last_roam_msec;
465bdcd8170SKalle Valo 	u8 cs_snr;
466bdcd8170SKalle Valo 
467bdcd8170SKalle Valo 	u8 wow_host_pkt_wakeups;
468bdcd8170SKalle Valo 	u8 wow_host_evt_wakeups;
469bdcd8170SKalle Valo 
470bdcd8170SKalle Valo 	u32 arp_received;
471bdcd8170SKalle Valo 	u32 arp_matched;
472bdcd8170SKalle Valo 	u32 arp_replied;
473bdcd8170SKalle Valo };
474bdcd8170SKalle Valo 
475bdcd8170SKalle Valo struct ath6kl_mbox_info {
476bdcd8170SKalle Valo 	u32 htc_addr;
477bdcd8170SKalle Valo 	u32 htc_ext_addr;
478bdcd8170SKalle Valo 	u32 htc_ext_sz;
479bdcd8170SKalle Valo 
480bdcd8170SKalle Valo 	u32 block_size;
481bdcd8170SKalle Valo 
482bdcd8170SKalle Valo 	u32 gmbox_addr;
483bdcd8170SKalle Valo 
484bdcd8170SKalle Valo 	u32 gmbox_sz;
485bdcd8170SKalle Valo };
486bdcd8170SKalle Valo 
487bdcd8170SKalle Valo /*
488bdcd8170SKalle Valo  * 802.11i defines an extended IV for use with non-WEP ciphers.
489bdcd8170SKalle Valo  * When the EXTIV bit is set in the key id byte an additional
490bdcd8170SKalle Valo  * 4 bytes immediately follow the IV for TKIP.  For CCMP the
491bdcd8170SKalle Valo  * EXTIV bit is likewise set but the 8 bytes represent the
492bdcd8170SKalle Valo  * CCMP header rather than IV+extended-IV.
493bdcd8170SKalle Valo  */
494bdcd8170SKalle Valo 
495bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16
496bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8)	/* space for both tx and rx */
497bdcd8170SKalle Valo 
498bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT  0x01
499bdcd8170SKalle Valo #define ATH6KL_KEY_RECV  0x02
500bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT   0x80	/* default xmit key */
501bdcd8170SKalle Valo 
5029a5b1318SJouni Malinen /* Initial group key for AP mode */
503bdcd8170SKalle Valo struct ath6kl_req_key {
5049a5b1318SJouni Malinen 	bool valid;
5059a5b1318SJouni Malinen 	u8 key_index;
5069a5b1318SJouni Malinen 	int key_type;
5079a5b1318SJouni Malinen 	u8 key[WLAN_MAX_KEY_LEN];
5089a5b1318SJouni Malinen 	u8 key_len;
509bdcd8170SKalle Valo };
510bdcd8170SKalle Valo 
51177eab1e9SKalle Valo enum ath6kl_hif_type {
51277eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_SDIO,
51377eab1e9SKalle Valo 	ATH6KL_HIF_TYPE_USB,
51477eab1e9SKalle Valo };
51577eab1e9SKalle Valo 
516e76ac2bfSKalle Valo enum ath6kl_htc_type {
517e76ac2bfSKalle Valo 	ATH6KL_HTC_TYPE_MBOX,
518636f8288SKalle Valo 	ATH6KL_HTC_TYPE_PIPE,
519e76ac2bfSKalle Valo };
520e76ac2bfSKalle Valo 
52180abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */
52280abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
52380abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter {
52480abaf9bSVasanthakumar Thiagarajan 	struct list_head list;
52580abaf9bSVasanthakumar Thiagarajan 	char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
52680abaf9bSVasanthakumar Thiagarajan };
52780abaf9bSVasanthakumar Thiagarajan 
528df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap {
529df90b369SVasanthakumar Thiagarajan 	bool ht_enable;
530df90b369SVasanthakumar Thiagarajan 	u8 ampdu_factor;
531df90b369SVasanthakumar Thiagarajan 	unsigned short cap_info;
532df90b369SVasanthakumar Thiagarajan };
533df90b369SVasanthakumar Thiagarajan 
53471f96ee6SKalle Valo /*
53571f96ee6SKalle Valo  * Driver's maximum limit, note that some firmwares support only one vif
53671f96ee6SKalle Valo  * and the runtime (current) limit must be checked from ar->vif_max.
53771f96ee6SKalle Valo  */
538b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX	3
539334234b5SVasanthakumar Thiagarajan 
54059c98449SVasanthakumar Thiagarajan /* vif flags info */
54159c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state {
54259c98449SVasanthakumar Thiagarajan 	CONNECTED,
54359c98449SVasanthakumar Thiagarajan 	CONNECT_PEND,
54459c98449SVasanthakumar Thiagarajan 	WMM_ENABLED,
54559c98449SVasanthakumar Thiagarajan 	NETQ_STOPPED,
54659c98449SVasanthakumar Thiagarajan 	DTIM_EXPIRED,
54759c98449SVasanthakumar Thiagarajan 	NETDEV_REGISTERED,
54859c98449SVasanthakumar Thiagarajan 	CLEAR_BSSFILTER_ON_BEACON,
54959c98449SVasanthakumar Thiagarajan 	DTIM_PERIOD_AVAIL,
55059c98449SVasanthakumar Thiagarajan 	WLAN_ENABLED,
551b95907a7SVasanthakumar Thiagarajan 	STATS_UPDATE_PEND,
552081c7a84SRaja Mani 	HOST_SLEEP_MODE_CMD_PROCESSED,
5536251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_ON,
5546251d801SNaveen Gangadharan 	NETDEV_MCAST_ALL_OFF,
55559c98449SVasanthakumar Thiagarajan };
55659c98449SVasanthakumar Thiagarajan 
557108438bcSVasanthakumar Thiagarajan struct ath6kl_vif {
558990bd915SVasanthakumar Thiagarajan 	struct list_head list;
559108438bcSVasanthakumar Thiagarajan 	struct wireless_dev wdev;
560108438bcSVasanthakumar Thiagarajan 	struct net_device *ndev;
561108438bcSVasanthakumar Thiagarajan 	struct ath6kl *ar;
562478ac027SVasanthakumar Thiagarajan 	/* Lock to protect vif specific net_stats and flags */
563478ac027SVasanthakumar Thiagarajan 	spinlock_t if_lock;
564334234b5SVasanthakumar Thiagarajan 	u8 fw_vif_idx;
56559c98449SVasanthakumar Thiagarajan 	unsigned long flags;
5663450334fSVasanthakumar Thiagarajan 	int ssid_len;
5673450334fSVasanthakumar Thiagarajan 	u8 ssid[IEEE80211_MAX_SSID_LEN];
5683450334fSVasanthakumar Thiagarajan 	u8 dot11_auth_mode;
5693450334fSVasanthakumar Thiagarajan 	u8 auth_mode;
5703450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto;
5713450334fSVasanthakumar Thiagarajan 	u8 prwise_crypto_len;
5723450334fSVasanthakumar Thiagarajan 	u8 grp_crypto;
5733450334fSVasanthakumar Thiagarajan 	u8 grp_crypto_len;
5743450334fSVasanthakumar Thiagarajan 	u8 def_txkey_index;
575f5938f24SVasanthakumar Thiagarajan 	u8 next_mode;
576f5938f24SVasanthakumar Thiagarajan 	u8 nw_type;
5778c8b65e3SVasanthakumar Thiagarajan 	u8 bssid[ETH_ALEN];
5788c8b65e3SVasanthakumar Thiagarajan 	u8 req_bssid[ETH_ALEN];
579f74bac54SVasanthakumar Thiagarajan 	u16 ch_hint;
580f74bac54SVasanthakumar Thiagarajan 	u16 bss_ch;
5816f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
5826f2a73f9SVasanthakumar Thiagarajan 	struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
5832132c69cSVasanthakumar Thiagarajan 	struct aggr_info *aggr_cntxt;
58467b3f129SKiran Reddy 	struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
58510509f90SKalle Valo 
586de3ad713SVasanthakumar Thiagarajan 	struct timer_list disconnect_timer;
58710509f90SKalle Valo 	struct timer_list sched_scan_timer;
58810509f90SKalle Valo 
58914ee6f6bSVasanthakumar Thiagarajan 	struct cfg80211_scan_request *scan_req;
59014ee6f6bSVasanthakumar Thiagarajan 	enum sme_state sme_state;
591cf5333d7SVasanthakumar Thiagarajan 	int reconnect_flag;
5921052261eSJouni Malinen 	u32 last_roc_id;
5931052261eSJouni Malinen 	u32 last_cancel_roc_id;
594cf5333d7SVasanthakumar Thiagarajan 	u32 send_action_id;
595cf5333d7SVasanthakumar Thiagarajan 	bool probe_req_report;
596cf5333d7SVasanthakumar Thiagarajan 	u16 assoc_bss_beacon_int;
5978f46fccdSRaja Mani 	u16 listen_intvl_t;
598ce0dc0cfSRaja Mani 	u16 bmiss_time_t;
599279b2862SThomas Pedersen 	u32 txe_intvl;
600eb38987eSRaja Mani 	u16 bg_scan_period;
601cf5333d7SVasanthakumar Thiagarajan 	u8 assoc_bss_dtim_period;
602b95907a7SVasanthakumar Thiagarajan 	struct net_device_stats net_stats;
603b95907a7SVasanthakumar Thiagarajan 	struct target_stats target_stats;
604c4f7863eSThomas Pedersen 	struct wmi_connect_cmd profile;
60580abaf9bSVasanthakumar Thiagarajan 
60680abaf9bSVasanthakumar Thiagarajan 	struct list_head mc_filter;
607108438bcSVasanthakumar Thiagarajan };
608108438bcSVasanthakumar Thiagarajan 
60971bbc994SJohannes Berg static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
61071bbc994SJohannes Berg {
61171bbc994SJohannes Berg 	return container_of(wdev, struct ath6kl_vif, wdev);
61271bbc994SJohannes Berg }
61371bbc994SJohannes Berg 
6146cb3c714SRaja Mani #define WOW_LIST_ID		0
6156cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY	500 /* ms */
6166cb3c714SRaja Mani 
61710509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
61810509f90SKalle Valo 
619bdcd8170SKalle Valo /* Flag info */
62059c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state {
62159c98449SVasanthakumar Thiagarajan 	WMI_ENABLED,
62259c98449SVasanthakumar Thiagarajan 	WMI_READY,
62359c98449SVasanthakumar Thiagarajan 	WMI_CTRL_EP_FULL,
62459c98449SVasanthakumar Thiagarajan 	TESTMODE,
62559c98449SVasanthakumar Thiagarajan 	DESTROY_IN_PROGRESS,
62659c98449SVasanthakumar Thiagarajan 	SKIP_SCAN,
62759c98449SVasanthakumar Thiagarajan 	ROAM_TBL_PEND,
6285fe4dffbSKalle Valo 	FIRST_BOOT,
62959c98449SVasanthakumar Thiagarajan };
630bdcd8170SKalle Valo 
63176a9fbe2SKalle Valo enum ath6kl_state {
63276a9fbe2SKalle Valo 	ATH6KL_STATE_OFF,
63376a9fbe2SKalle Valo 	ATH6KL_STATE_ON,
634390a8c8fSRaja Mani 	ATH6KL_STATE_SUSPENDING,
635390a8c8fSRaja Mani 	ATH6KL_STATE_RESUMING,
63676a9fbe2SKalle Valo 	ATH6KL_STATE_DEEPSLEEP,
637b4b2a0b1SKalle Valo 	ATH6KL_STATE_CUTPOWER,
638dd6c0c63SRaja Mani 	ATH6KL_STATE_WOW,
63910509f90SKalle Valo 	ATH6KL_STATE_SCHED_SCAN,
64076a9fbe2SKalle Valo };
64176a9fbe2SKalle Valo 
642bdcd8170SKalle Valo struct ath6kl {
643bdcd8170SKalle Valo 	struct device *dev;
644be98e3a4SVasanthakumar Thiagarajan 	struct wiphy *wiphy;
64576a9fbe2SKalle Valo 
64676a9fbe2SKalle Valo 	enum ath6kl_state state;
6475f1127ffSKalle Valo 	unsigned int testmode;
64876a9fbe2SKalle Valo 
649bdcd8170SKalle Valo 	struct ath6kl_bmi bmi;
650bdcd8170SKalle Valo 	const struct ath6kl_hif_ops *hif_ops;
651e76ac2bfSKalle Valo 	const struct ath6kl_htc_ops *htc_ops;
652bdcd8170SKalle Valo 	struct wmi *wmi;
653bdcd8170SKalle Valo 	int tx_pending[ENDPOINT_MAX];
654bdcd8170SKalle Valo 	int total_tx_data_pend;
655bdcd8170SKalle Valo 	struct htc_target *htc_target;
65677eab1e9SKalle Valo 	enum ath6kl_hif_type hif_type;
657bdcd8170SKalle Valo 	void *hif_priv;
658990bd915SVasanthakumar Thiagarajan 	struct list_head vif_list;
659990bd915SVasanthakumar Thiagarajan 	/* Lock to avoid race in vif_list entries among add/del/traverse */
660990bd915SVasanthakumar Thiagarajan 	spinlock_t list_lock;
66155055976SVasanthakumar Thiagarajan 	u8 num_vif;
662368b1b0fSKalle Valo 	unsigned int vif_max;
6633226f68aSVasanthakumar Thiagarajan 	u8 max_norm_iface;
66455055976SVasanthakumar Thiagarajan 	u8 avail_idx_map;
66512eb9444SKalle Valo 
66612eb9444SKalle Valo 	/*
66712eb9444SKalle Valo 	 * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
66812eb9444SKalle Valo 	 * calls, tx_pending and total_tx_data_pend.
66912eb9444SKalle Valo 	 */
670bdcd8170SKalle Valo 	spinlock_t lock;
67112eb9444SKalle Valo 
672bdcd8170SKalle Valo 	struct semaphore sem;
673e5090444SVivek Natarajan 	u8 lrssi_roam_threshold;
674bdcd8170SKalle Valo 	struct ath6kl_version version;
675bdcd8170SKalle Valo 	u32 target_type;
676bdcd8170SKalle Valo 	u8 tx_pwr;
677bdcd8170SKalle Valo 	struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
678bdcd8170SKalle Valo 	u8 ibss_ps_enable;
67955055976SVasanthakumar Thiagarajan 	bool ibss_if_active;
680bdcd8170SKalle Valo 	u8 node_num;
681bdcd8170SKalle Valo 	u8 next_ep_id;
682bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie_list;
683bdcd8170SKalle Valo 	u32 cookie_count;
684bdcd8170SKalle Valo 	enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
685bdcd8170SKalle Valo 	bool ac_stream_active[WMM_NUM_AC];
686bdcd8170SKalle Valo 	u8 ac_stream_pri_map[WMM_NUM_AC];
687bdcd8170SKalle Valo 	u8 hiac_stream_active_pri;
688bdcd8170SKalle Valo 	u8 ep2ac_map[ENDPOINT_MAX];
689bdcd8170SKalle Valo 	enum htc_endpoint_id ctrl_ep;
6903c370398SKalle Valo 	struct ath6kl_htc_credit_info credit_state_info;
691bdcd8170SKalle Valo 	u32 connect_ctrl_flags;
692bdcd8170SKalle Valo 	u32 user_key_ctrl;
693bdcd8170SKalle Valo 	u8 usr_bss_filter;
694bdcd8170SKalle Valo 	struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
695bdcd8170SKalle Valo 	u8 sta_list_index;
696bdcd8170SKalle Valo 	struct ath6kl_req_key ap_mode_bkey;
697bdcd8170SKalle Valo 	struct sk_buff_head mcastpsq;
698c4f7863eSThomas Pedersen 	u32 want_ch_switch;
69912eb9444SKalle Valo 
70012eb9444SKalle Valo 	/*
70112eb9444SKalle Valo 	 * FIXME: protects access to mcastpsq but is actually useless as
70212eb9444SKalle Valo 	 * all skbe_queue_*() functions provide serialisation themselves
70312eb9444SKalle Valo 	 */
704bdcd8170SKalle Valo 	spinlock_t mcastpsq_lock;
70512eb9444SKalle Valo 
706bdcd8170SKalle Valo 	u8 intra_bss;
707bdcd8170SKalle Valo 	struct wmi_ap_mode_stat ap_stats;
708bdcd8170SKalle Valo 	u8 ap_country_code[3];
709bdcd8170SKalle Valo 	struct list_head amsdu_rx_buffer_queue;
710bdcd8170SKalle Valo 	u8 rx_meta_ver;
711bdcd8170SKalle Valo 	enum wlan_low_pwr_state wlan_pwr_state;
712d66ea4f9SVasanthakumar Thiagarajan 	u8 mac_addr[ETH_ALEN];
713bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE  4
714003353b0SKalle Valo 	struct {
715003353b0SKalle Valo 		void *rx_report;
716003353b0SKalle Valo 		size_t rx_report_len;
717003353b0SKalle Valo 	} tm;
718003353b0SKalle Valo 
719856f4b31SKalle Valo 	struct ath6kl_hw {
720856f4b31SKalle Valo 		u32 id;
721293badf4SKalle Valo 		const char *name;
722a01ac414SKalle Valo 		u32 dataset_patch_addr;
723a01ac414SKalle Valo 		u32 app_load_addr;
724a01ac414SKalle Valo 		u32 app_start_override_addr;
725991b27eaSKalle Valo 		u32 board_ext_data_addr;
726991b27eaSKalle Valo 		u32 reserved_ram_size;
7270d4d72bfSKalle Valo 		u32 board_addr;
72839586bf2SRyan Hsu 		u32 refclk_hz;
72939586bf2SRyan Hsu 		u32 uarttx_pin;
730cd23c1c9SAlex Yang 		u32 testscript_addr;
731d92917e4SThomas Pedersen 		enum wmi_phy_cap cap;
732d1a9421dSKalle Valo 
73306e360acSBala Shanmugam 		u32 flags;
73406e360acSBala Shanmugam 
735c0038972SKalle Valo 		struct ath6kl_hw_fw {
736c0038972SKalle Valo 			const char *dir;
737c0038972SKalle Valo 			const char *otp;
738d1a9421dSKalle Valo 			const char *fw;
739c0038972SKalle Valo 			const char *tcmd;
740c0038972SKalle Valo 			const char *patch;
741cd23c1c9SAlex Yang 			const char *utf;
742cd23c1c9SAlex Yang 			const char *testscript;
743c0038972SKalle Valo 		} fw;
744c0038972SKalle Valo 
745d1a9421dSKalle Valo 		const char *fw_board;
746d1a9421dSKalle Valo 		const char *fw_default_board;
747a01ac414SKalle Valo 	} hw;
748a01ac414SKalle Valo 
749bdcd8170SKalle Valo 	u16 conf_flags;
750e390af77SRaja Mani 	u16 suspend_mode;
7511e9a905dSRaja Mani 	u16 wow_suspend_mode;
752bdcd8170SKalle Valo 	wait_queue_head_t event_wq;
753bdcd8170SKalle Valo 	struct ath6kl_mbox_info mbox_info;
754bdcd8170SKalle Valo 
755bdcd8170SKalle Valo 	struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
756bdcd8170SKalle Valo 	unsigned long flag;
757bdcd8170SKalle Valo 
758bdcd8170SKalle Valo 	u8 *fw_board;
759bdcd8170SKalle Valo 	size_t fw_board_len;
760bdcd8170SKalle Valo 
761bdcd8170SKalle Valo 	u8 *fw_otp;
762bdcd8170SKalle Valo 	size_t fw_otp_len;
763bdcd8170SKalle Valo 
764bdcd8170SKalle Valo 	u8 *fw;
765bdcd8170SKalle Valo 	size_t fw_len;
766bdcd8170SKalle Valo 
767bdcd8170SKalle Valo 	u8 *fw_patch;
768bdcd8170SKalle Valo 	size_t fw_patch_len;
769bdcd8170SKalle Valo 
770cd23c1c9SAlex Yang 	u8 *fw_testscript;
771cd23c1c9SAlex Yang 	size_t fw_testscript_len;
772cd23c1c9SAlex Yang 
77365a8b4ccSKalle Valo 	unsigned int fw_api;
77497e0496dSKalle Valo 	unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
77597e0496dSKalle Valo 
776bdcd8170SKalle Valo 	struct workqueue_struct *ath6kl_wq;
7777c3075e9SVasanthakumar Thiagarajan 
778d999ba3eSVasanthakumar Thiagarajan 	struct dentry *debugfs_phy;
7796a7c9badSJouni Malinen 
7806bbc7c35SJouni Malinen 	bool p2p;
7816bbc7c35SJouni Malinen 
782e5348a1eSVasanthakumar Thiagarajan 	bool wiphy_registered;
783e5348a1eSVasanthakumar Thiagarajan 
784bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG
785bdf5396bSKalle Valo 	struct {
7869b9a4f2aSKalle Valo 		struct sk_buff_head fwlog_queue;
787c807b30dSKalle Valo 		struct completion fwlog_completion;
788c807b30dSKalle Valo 		bool fwlog_open;
789c807b30dSKalle Valo 
790939f1cceSKalle Valo 		u32 fwlog_mask;
7919b9a4f2aSKalle Valo 
79291d57de5SVasanthakumar Thiagarajan 		unsigned int dbgfs_diag_reg;
793252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_addr_wr;
794252c068bSVasanthakumar Thiagarajan 		u32 diag_reg_val_wr;
7959a730834SKalle Valo 
7969a730834SKalle Valo 		struct {
7979a730834SKalle Valo 			unsigned int invalid_rate;
7989a730834SKalle Valo 		} war_stats;
7994b28a80dSJouni Malinen 
8004b28a80dSJouni Malinen 		u8 *roam_tbl;
8014b28a80dSJouni Malinen 		unsigned int roam_tbl_len;
802ff0b0075SJouni Malinen 
803ff0b0075SJouni Malinen 		u8 keepalive;
804ff0b0075SJouni Malinen 		u8 disc_timeout;
805bdf5396bSKalle Valo 	} debug;
806bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */
807bdcd8170SKalle Valo };
808bdcd8170SKalle Valo 
809d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
810bdcd8170SKalle Valo {
811108438bcSVasanthakumar Thiagarajan 	return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
812bdcd8170SKalle Valo }
813bdcd8170SKalle Valo 
814bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
815bc07ddb2SKalle Valo 					  u32 item_offset)
816bc07ddb2SKalle Valo {
817bc07ddb2SKalle Valo 	u32 addr = 0;
818bc07ddb2SKalle Valo 
819bc07ddb2SKalle Valo 	if (ar->target_type == TARGET_TYPE_AR6003)
820bc07ddb2SKalle Valo 		addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
821bc07ddb2SKalle Valo 	else if (ar->target_type == TARGET_TYPE_AR6004)
822bc07ddb2SKalle Valo 		addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
823bc07ddb2SKalle Valo 
824bc07ddb2SKalle Valo 	return addr;
825bc07ddb2SKalle Valo }
826bc07ddb2SKalle Valo 
827bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar);
828bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr);
829bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr);
830bdcd8170SKalle Valo void init_netdev(struct net_device *dev);
831bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar);
832bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar);
833bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
83463de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context,
83563de1112SKalle Valo 			struct list_head *packet_queue);
836bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
837bdcd8170SKalle Valo 					       struct htc_packet *packet);
838bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar);
839bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
840f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
841addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
842addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
843addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
844bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar);
845e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif);
846bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar);
847bdcd8170SKalle Valo 
848bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
849bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
850bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
851bdcd8170SKalle Valo 
8527baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif);
853c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
854c8651541SVasanthakumar Thiagarajan 		    struct aggr_info_conn *aggr_conn);
855bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target,
856bdcd8170SKalle Valo 		      enum htc_endpoint_id endpoint);
857bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
858bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
859bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
860bdcd8170SKalle Valo 					    int len);
861bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info);
8621d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn);
863bdcd8170SKalle Valo 
8646765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
865bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
866bdcd8170SKalle Valo 
867d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
868d92917e4SThomas Pedersen 			enum wmi_phy_cap cap);
869bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
870bdcd8170SKalle Valo 		      enum htc_endpoint_id eid);
871240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
872bdcd8170SKalle Valo 			  u8 *bssid, u16 listen_int,
873bdcd8170SKalle Valo 			  u16 beacon_int, enum network_type net_type,
874bdcd8170SKalle Valo 			  u8 beacon_ie_len, u8 assoc_req_len,
875bdcd8170SKalle Valo 			  u8 assoc_resp_len, u8 *assoc_info);
876240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
877240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
878572e27c0SJouni Malinen 				u8 keymgmt, u8 ucipher, u8 auth,
879c1762a3fSThirumalai Pachamuthu 				u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
880240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
881bdcd8170SKalle Valo 			     u8 *bssid, u8 assoc_resp_len,
882bdcd8170SKalle Valo 			     u8 *assoc_info, u16 prot_reason_status);
883240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
884bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
885240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
886240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
887bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
888bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
889bdcd8170SKalle Valo 
890240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
891bdcd8170SKalle Valo 
892240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
893240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif);
894240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
895240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
896bdcd8170SKalle Valo 			     u8 win_sz);
897bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev);
898bdcd8170SKalle Valo 
8996db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
9006db8fa53SVasanthakumar Thiagarajan 			 bool wait_fot_compltn, bool cold_reset);
901e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif);
902990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
90355055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
9045fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar);
9055fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar);
90645eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
90745eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar);
90845eaa78fSKalle Valo 
909a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar);
9105fe4dffbSKalle Valo 
911636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
912636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
913636f8288SKalle Valo 
91445eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev);
915e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
91645eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar);
91745eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar);
91845eaa78fSKalle Valo 
919bdcd8170SKalle Valo #endif /* CORE_H */
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