1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2010-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef CORE_H 19bdcd8170SKalle Valo #define CORE_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #include <linux/etherdevice.h> 22bdcd8170SKalle Valo #include <linux/rtnetlink.h> 23bdcd8170SKalle Valo #include <linux/firmware.h> 24bdcd8170SKalle Valo #include <linux/sched.h> 25bdf5396bSKalle Valo #include <linux/circ_buf.h> 26bdcd8170SKalle Valo #include <net/cfg80211.h> 27bdcd8170SKalle Valo #include "htc.h" 28bdcd8170SKalle Valo #include "wmi.h" 29bdcd8170SKalle Valo #include "bmi.h" 30bc07ddb2SKalle Valo #include "target.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define MAX_ATH6KL 1 33bdcd8170SKalle Valo #define ATH6KL_MAX_RX_BUFFERS 16 34bdcd8170SKalle Valo #define ATH6KL_BUFFER_SIZE 1664 35bdcd8170SKalle Valo #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4 36bdcd8170SKalle Valo #define ATH6KL_AMSDU_REFILL_THRESHOLD 3 37bdcd8170SKalle Valo #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) 38bdcd8170SKalle Valo #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 39bdcd8170SKalle Valo #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_INIT 0 42bdcd8170SKalle Valo #define USER_SAVEDKEYS_STAT_RUN 1 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define ATH6KL_TX_TIMEOUT 10 45bdcd8170SKalle Valo #define ATH6KL_MAX_ENDPOINTS 4 46bdcd8170SKalle Valo #define MAX_NODE_NUM 15 47bdcd8170SKalle Valo 48c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_ALL_FRAME 0xFFFF 49c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_NUM_OF_AC 0x4 50c1762a3fSThirumalai Pachamuthu #define ATH6KL_APSD_FRAME_MASK 0xF 51c1762a3fSThirumalai Pachamuthu 521df94a85SVasanthakumar Thiagarajan /* Extra bytes for htc header alignment */ 531df94a85SVasanthakumar Thiagarajan #define ATH6KL_HTC_ALIGN_BYTES 3 541df94a85SVasanthakumar Thiagarajan 55bdcd8170SKalle Valo /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ 56bdcd8170SKalle Valo #define MAX_DEF_COOKIE_NUM 180 57bdcd8170SKalle Valo #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */ 58bdcd8170SKalle Valo #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) 59bdcd8170SKalle Valo 60bdcd8170SKalle Valo #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define DISCON_TIMER_INTVAL 10000 /* in msec */ 63bdcd8170SKalle Valo 6413423c31SVasanthakumar Thiagarajan /* Channel dwell time in fg scan */ 6513423c31SVasanthakumar Thiagarajan #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */ 6613423c31SVasanthakumar Thiagarajan 6750d41234SKalle Valo /* includes also the null byte */ 6850d41234SKalle Valo #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL" 6950d41234SKalle Valo 7050d41234SKalle Valo enum ath6kl_fw_ie_type { 7150d41234SKalle Valo ATH6KL_FW_IE_FW_VERSION = 0, 7250d41234SKalle Valo ATH6KL_FW_IE_TIMESTAMP = 1, 7350d41234SKalle Valo ATH6KL_FW_IE_OTP_IMAGE = 2, 7450d41234SKalle Valo ATH6KL_FW_IE_FW_IMAGE = 3, 7550d41234SKalle Valo ATH6KL_FW_IE_PATCH_IMAGE = 4, 768a137480SKalle Valo ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5, 7797e0496dSKalle Valo ATH6KL_FW_IE_CAPABILITIES = 6, 781b4304daSKalle Valo ATH6KL_FW_IE_PATCH_ADDR = 7, 7903ef0250SKalle Valo ATH6KL_FW_IE_BOARD_ADDR = 8, 80368b1b0fSKalle Valo ATH6KL_FW_IE_VIF_MAX = 9, 8150d41234SKalle Valo }; 8250d41234SKalle Valo 8397e0496dSKalle Valo enum ath6kl_fw_capability { 8497e0496dSKalle Valo ATH6KL_FW_CAPABILITY_HOST_P2P = 0, 8510509f90SKalle Valo ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1, 8697e0496dSKalle Valo 873ca9d1fcSAarthi Thiruvengadam /* 883ca9d1fcSAarthi Thiruvengadam * Firmware is capable of supporting P2P mgmt operations on a 893ca9d1fcSAarthi Thiruvengadam * station interface. After group formation, the station 903ca9d1fcSAarthi Thiruvengadam * interface will become a P2P client/GO interface as the case may be 913ca9d1fcSAarthi Thiruvengadam */ 923ca9d1fcSAarthi Thiruvengadam ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX, 933ca9d1fcSAarthi Thiruvengadam 9403bdeb0dSVasanthakumar Thiagarajan /* 9503bdeb0dSVasanthakumar Thiagarajan * Firmware has support to cleanup inactive stations 9603bdeb0dSVasanthakumar Thiagarajan * in AP mode. 9703bdeb0dSVasanthakumar Thiagarajan */ 9803bdeb0dSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT, 9903bdeb0dSVasanthakumar Thiagarajan 100d97c121bSVasanthakumar Thiagarajan /* Firmware has support to override rsn cap of rsn ie */ 101d97c121bSVasanthakumar Thiagarajan ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE, 102d97c121bSVasanthakumar Thiagarajan 1036821d4f0SNaveen Gangadharan /* 1046821d4f0SNaveen Gangadharan * Multicast support in WOW and host awake mode. 1056821d4f0SNaveen Gangadharan * Allow all multicast in host awake mode. 1066821d4f0SNaveen Gangadharan * Apply multicast filter in WOW mode. 1076821d4f0SNaveen Gangadharan */ 1086821d4f0SNaveen Gangadharan ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER, 1096821d4f0SNaveen Gangadharan 110c422d52dSThomas Pedersen /* Firmware supports enhanced bmiss detection */ 111c422d52dSThomas Pedersen ATH6KL_FW_CAPABILITY_BMISS_ENHANCE, 112c422d52dSThomas Pedersen 113dd45b759SNaveen Singh /* 114dd45b759SNaveen Singh * FW supports matching of ssid in schedule scan 115dd45b759SNaveen Singh */ 116dd45b759SNaveen Singh ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST, 117dd45b759SNaveen Singh 11897e0496dSKalle Valo /* this needs to be last */ 11997e0496dSKalle Valo ATH6KL_FW_CAPABILITY_MAX, 12097e0496dSKalle Valo }; 12197e0496dSKalle Valo 12297e0496dSKalle Valo #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32) 12397e0496dSKalle Valo 12450d41234SKalle Valo struct ath6kl_fw_ie { 12550d41234SKalle Valo __le32 id; 12650d41234SKalle Valo __le32 len; 12750d41234SKalle Valo u8 data[0]; 12850d41234SKalle Valo }; 12950d41234SKalle Valo 13006e360acSBala Shanmugam enum ath6kl_hw_flags { 13106e360acSBala Shanmugam ATH6KL_HW_FLAG_64BIT_RATES = BIT(0), 13206e360acSBala Shanmugam }; 13306e360acSBala Shanmugam 134c0038972SKalle Valo #define ATH6KL_FW_API2_FILE "fw-2.bin" 13565a8b4ccSKalle Valo #define ATH6KL_FW_API3_FILE "fw-3.bin" 136c0038972SKalle Valo 137bdcd8170SKalle Valo /* AR6003 1.0 definitions */ 1380d0192baSKalle Valo #define AR6003_HW_1_0_VERSION 0x300002ba 139bdcd8170SKalle Valo 140bdcd8170SKalle Valo /* AR6003 2.0 definitions */ 1410d0192baSKalle Valo #define AR6003_HW_2_0_VERSION 0x30000384 1420d0192baSKalle Valo #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910 143c0038972SKalle Valo #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0" 144c0038972SKalle Valo #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77" 145c0038972SKalle Valo #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77" 146c0038972SKalle Valo #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 147c0038972SKalle Valo #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin" 1482023dbb8STim Gardner #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin" 1490d0192baSKalle Valo #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \ 1502023dbb8STim Gardner AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin" 151bdcd8170SKalle Valo 152bdcd8170SKalle Valo /* AR6003 3.0 definitions */ 1530d0192baSKalle Valo #define AR6003_HW_2_1_1_VERSION 0x30000582 154c0038972SKalle Valo #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1" 155c0038972SKalle Valo #define AR6003_HW_2_1_1_OTP_FILE "otp.bin" 156c0038972SKalle Valo #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin" 157c0038972SKalle Valo #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin" 158cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin" 159cd23c1c9SAlex Yang #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin" 160c0038972SKalle Valo #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin" 1612023dbb8STim Gardner #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin" 1620d0192baSKalle Valo #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \ 1632023dbb8STim Gardner AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin" 164bdcd8170SKalle Valo 16531024d99SKevin Fang /* AR6004 1.0 definitions */ 1660d0192baSKalle Valo #define AR6004_HW_1_0_VERSION 0x30000623 167c0038972SKalle Valo #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0" 168c0038972SKalle Valo #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin" 1692023dbb8STim Gardner #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin" 1700d0192baSKalle Valo #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \ 1712023dbb8STim Gardner AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin" 172d5720e59SKalle Valo 173d5720e59SKalle Valo /* AR6004 1.1 definitions */ 1740d0192baSKalle Valo #define AR6004_HW_1_1_VERSION 0x30000001 175c0038972SKalle Valo #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1" 176c0038972SKalle Valo #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin" 1772023dbb8STim Gardner #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin" 1780d0192baSKalle Valo #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \ 1792023dbb8STim Gardner AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin" 18031024d99SKevin Fang 1816146ca69SRay Chen /* AR6004 1.2 definitions */ 1826146ca69SRay Chen #define AR6004_HW_1_2_VERSION 0x300007e8 1836146ca69SRay Chen #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2" 1846146ca69SRay Chen #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin" 1852023dbb8STim Gardner #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin" 1866146ca69SRay Chen #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \ 1872023dbb8STim Gardner AR6004_HW_1_2_FW_DIR "/bdata.bin" 1886146ca69SRay Chen 189bdcd8170SKalle Valo /* Per STA data, used in AP mode */ 190bdcd8170SKalle Valo #define STA_PS_AWAKE BIT(0) 191bdcd8170SKalle Valo #define STA_PS_SLEEP BIT(1) 192bdcd8170SKalle Valo #define STA_PS_POLLED BIT(2) 193c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_TRIGGER BIT(3) 194c1762a3fSThirumalai Pachamuthu #define STA_PS_APSD_EOSP BIT(4) 195bdcd8170SKalle Valo 196bdcd8170SKalle Valo /* HTC TX packet tagging definitions */ 197bdcd8170SKalle Valo #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED 198bdcd8170SKalle Valo #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1) 199bdcd8170SKalle Valo 200bdcd8170SKalle Valo #define AR6003_CUST_DATA_SIZE 16 201bdcd8170SKalle Valo 202bdcd8170SKalle Valo #define AGGR_WIN_IDX(x, y) ((x) % (y)) 203bdcd8170SKalle Valo #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y)) 204bdcd8170SKalle Valo #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y)) 205bdcd8170SKalle Valo #define ATH6KL_MAX_SEQ_NO 0xFFF 206bdcd8170SKalle Valo #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO) 207bdcd8170SKalle Valo 208bdcd8170SKalle Valo #define NUM_OF_TIDS 8 209bdcd8170SKalle Valo #define AGGR_SZ_DEFAULT 8 210bdcd8170SKalle Valo 211bdcd8170SKalle Valo #define AGGR_WIN_SZ_MIN 2 212bdcd8170SKalle Valo #define AGGR_WIN_SZ_MAX 8 213bdcd8170SKalle Valo 214bdcd8170SKalle Valo #define TID_WINDOW_SZ(_x) ((_x) << 1) 215bdcd8170SKalle Valo 216bdcd8170SKalle Valo #define AGGR_NUM_OF_FREE_NETBUFS 16 217bdcd8170SKalle Valo 218bdcd8170SKalle Valo #define AGGR_RX_TIMEOUT 400 /* in ms */ 219bdcd8170SKalle Valo 220bdcd8170SKalle Valo #define WMI_TIMEOUT (2 * HZ) 221bdcd8170SKalle Valo 222bdcd8170SKalle Valo #define MBOX_YIELD_LIMIT 99 223bdcd8170SKalle Valo 2248f46fccdSRaja Mani #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */ 225ce0dc0cfSRaja Mani #define ATH6KL_DEFAULT_BMISS_TIME 1500 226ce0dc0cfSRaja Mani #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */ 227ce0dc0cfSRaja Mani #define ATH6KL_MAX_BMISS_TIME 5000 2288f46fccdSRaja Mani 229bdcd8170SKalle Valo /* configuration lags */ 230bdcd8170SKalle Valo /* 231bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in 232bdcd8170SKalle Valo * ERP IE of beacon to determine the short premable support when 233bdcd8170SKalle Valo * sending (Re)Assoc req. 234bdcd8170SKalle Valo * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power 235bdcd8170SKalle Valo * module state transition failure events which happen during 236bdcd8170SKalle Valo * scan, to the host. 237bdcd8170SKalle Valo */ 238bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) 239bdcd8170SKalle Valo #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) 240bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_11N BIT(2) 241bdcd8170SKalle Valo #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) 242e390af77SRaja Mani #define ATH6KL_CONF_UART_DEBUG BIT(4) 243bdcd8170SKalle Valo 244c86e4f44SAarthi Thiruvengadam #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */ 245c86e4f44SAarthi Thiruvengadam 246bdcd8170SKalle Valo enum wlan_low_pwr_state { 247bdcd8170SKalle Valo WLAN_POWER_STATE_ON, 248bdcd8170SKalle Valo WLAN_POWER_STATE_CUT_PWR, 249bdcd8170SKalle Valo WLAN_POWER_STATE_DEEP_SLEEP, 250bdcd8170SKalle Valo WLAN_POWER_STATE_WOW 251bdcd8170SKalle Valo }; 252bdcd8170SKalle Valo 253bdcd8170SKalle Valo enum sme_state { 254bdcd8170SKalle Valo SME_DISCONNECTED, 255bdcd8170SKalle Valo SME_CONNECTING, 256bdcd8170SKalle Valo SME_CONNECTED 257bdcd8170SKalle Valo }; 258bdcd8170SKalle Valo 259bdcd8170SKalle Valo struct skb_hold_q { 260bdcd8170SKalle Valo struct sk_buff *skb; 261bdcd8170SKalle Valo bool is_amsdu; 262bdcd8170SKalle Valo u16 seq_no; 263bdcd8170SKalle Valo }; 264bdcd8170SKalle Valo 265bdcd8170SKalle Valo struct rxtid { 266bdcd8170SKalle Valo bool aggr; 267bdcd8170SKalle Valo bool progress; 268bdcd8170SKalle Valo bool timer_mon; 269bdcd8170SKalle Valo u16 win_sz; 270bdcd8170SKalle Valo u16 seq_next; 271bdcd8170SKalle Valo u32 hold_q_sz; 272bdcd8170SKalle Valo struct skb_hold_q *hold_q; 273bdcd8170SKalle Valo struct sk_buff_head q; 27412eb9444SKalle Valo 27512eb9444SKalle Valo /* 2760faf7458SVasanthakumar Thiagarajan * lock mainly protects seq_next and hold_q. Movement of seq_next 2770faf7458SVasanthakumar Thiagarajan * needs to be protected between aggr_timeout() and 2780faf7458SVasanthakumar Thiagarajan * aggr_process_recv_frm(). hold_q will be holding the pending 2790faf7458SVasanthakumar Thiagarajan * reorder frames and it's access should also be protected. 2800faf7458SVasanthakumar Thiagarajan * Some of the other fields like hold_q_sz, win_sz and aggr are 2810faf7458SVasanthakumar Thiagarajan * initialized/reset when receiving addba/delba req, also while 2820faf7458SVasanthakumar Thiagarajan * deleting aggr state all the pending buffers are flushed before 2830faf7458SVasanthakumar Thiagarajan * resetting these fields, so there should not be any race in accessing 2840faf7458SVasanthakumar Thiagarajan * these fields. 28512eb9444SKalle Valo */ 286bdcd8170SKalle Valo spinlock_t lock; 287bdcd8170SKalle Valo }; 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo struct rxtid_stats { 290bdcd8170SKalle Valo u32 num_into_aggr; 291bdcd8170SKalle Valo u32 num_dups; 292bdcd8170SKalle Valo u32 num_oow; 293bdcd8170SKalle Valo u32 num_mpdu; 294bdcd8170SKalle Valo u32 num_amsdu; 295bdcd8170SKalle Valo u32 num_delivered; 296bdcd8170SKalle Valo u32 num_timeouts; 297bdcd8170SKalle Valo u32 num_hole; 298bdcd8170SKalle Valo u32 num_bar; 299bdcd8170SKalle Valo }; 300bdcd8170SKalle Valo 3017baef812SVasanthakumar Thiagarajan struct aggr_info_conn { 302bdcd8170SKalle Valo u8 aggr_sz; 303bdcd8170SKalle Valo u8 timer_scheduled; 304bdcd8170SKalle Valo struct timer_list timer; 305bdcd8170SKalle Valo struct net_device *dev; 306bdcd8170SKalle Valo struct rxtid rx_tid[NUM_OF_TIDS]; 307bdcd8170SKalle Valo struct rxtid_stats stat[NUM_OF_TIDS]; 3087baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_info; 3097baef812SVasanthakumar Thiagarajan }; 3107baef812SVasanthakumar Thiagarajan 3117baef812SVasanthakumar Thiagarajan struct aggr_info { 3127baef812SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 3137baef812SVasanthakumar Thiagarajan struct sk_buff_head rx_amsdu_freeq; 314bdcd8170SKalle Valo }; 315bdcd8170SKalle Valo 316bdcd8170SKalle Valo struct ath6kl_wep_key { 317bdcd8170SKalle Valo u8 key_index; 318bdcd8170SKalle Valo u8 key_len; 319bdcd8170SKalle Valo u8 key[64]; 320bdcd8170SKalle Valo }; 321bdcd8170SKalle Valo 322bdcd8170SKalle Valo #define ATH6KL_KEY_SEQ_LEN 8 323bdcd8170SKalle Valo 324bdcd8170SKalle Valo struct ath6kl_key { 325bdcd8170SKalle Valo u8 key[WLAN_MAX_KEY_LEN]; 326bdcd8170SKalle Valo u8 key_len; 327bdcd8170SKalle Valo u8 seq[ATH6KL_KEY_SEQ_LEN]; 328bdcd8170SKalle Valo u8 seq_len; 329bdcd8170SKalle Valo u32 cipher; 330bdcd8170SKalle Valo }; 331bdcd8170SKalle Valo 332bdcd8170SKalle Valo struct ath6kl_node_mapping { 333bdcd8170SKalle Valo u8 mac_addr[ETH_ALEN]; 334bdcd8170SKalle Valo u8 ep_id; 335bdcd8170SKalle Valo u8 tx_pend; 336bdcd8170SKalle Valo }; 337bdcd8170SKalle Valo 338bdcd8170SKalle Valo struct ath6kl_cookie { 339bdcd8170SKalle Valo struct sk_buff *skb; 340bdcd8170SKalle Valo u32 map_no; 341bdcd8170SKalle Valo struct htc_packet htc_pkt; 342bdcd8170SKalle Valo struct ath6kl_cookie *arc_list_next; 343bdcd8170SKalle Valo }; 344bdcd8170SKalle Valo 345d0ff7383SNaveen Gangadharan struct ath6kl_mgmt_buff { 346d0ff7383SNaveen Gangadharan struct list_head list; 347d0ff7383SNaveen Gangadharan u32 freq; 348d0ff7383SNaveen Gangadharan u32 wait; 349d0ff7383SNaveen Gangadharan u32 id; 350d0ff7383SNaveen Gangadharan bool no_cck; 351d0ff7383SNaveen Gangadharan size_t len; 352d0ff7383SNaveen Gangadharan u8 buf[0]; 353d0ff7383SNaveen Gangadharan }; 354d0ff7383SNaveen Gangadharan 355bdcd8170SKalle Valo struct ath6kl_sta { 356bdcd8170SKalle Valo u16 sta_flags; 357bdcd8170SKalle Valo u8 mac[ETH_ALEN]; 358bdcd8170SKalle Valo u8 aid; 359bdcd8170SKalle Valo u8 keymgmt; 360bdcd8170SKalle Valo u8 ucipher; 361bdcd8170SKalle Valo u8 auth; 362bdcd8170SKalle Valo u8 wpa_ie[ATH6KL_MAX_IE]; 363bdcd8170SKalle Valo struct sk_buff_head psq; 36412eb9444SKalle Valo 36512eb9444SKalle Valo /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */ 366bdcd8170SKalle Valo spinlock_t psq_lock; 36712eb9444SKalle Valo 368d0ff7383SNaveen Gangadharan struct list_head mgmt_psq; 369d0ff7383SNaveen Gangadharan size_t mgmt_psq_len; 370c1762a3fSThirumalai Pachamuthu u8 apsd_info; 371c1762a3fSThirumalai Pachamuthu struct sk_buff_head apsdq; 3721d2a4456SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn; 373bdcd8170SKalle Valo }; 374bdcd8170SKalle Valo 375bdcd8170SKalle Valo struct ath6kl_version { 376bdcd8170SKalle Valo u32 target_ver; 377bdcd8170SKalle Valo u32 wlan_ver; 378bdcd8170SKalle Valo u32 abi_ver; 379bdcd8170SKalle Valo }; 380bdcd8170SKalle Valo 381bdcd8170SKalle Valo struct ath6kl_bmi { 382bdcd8170SKalle Valo u32 cmd_credits; 383bdcd8170SKalle Valo bool done_sent; 384bdcd8170SKalle Valo u8 *cmd_buf; 3851f4c894dSKalle Valo u32 max_data_size; 3861f4c894dSKalle Valo u32 max_cmd_size; 387bdcd8170SKalle Valo }; 388bdcd8170SKalle Valo 389bdcd8170SKalle Valo struct target_stats { 390bdcd8170SKalle Valo u64 tx_pkt; 391bdcd8170SKalle Valo u64 tx_byte; 392bdcd8170SKalle Valo u64 tx_ucast_pkt; 393bdcd8170SKalle Valo u64 tx_ucast_byte; 394bdcd8170SKalle Valo u64 tx_mcast_pkt; 395bdcd8170SKalle Valo u64 tx_mcast_byte; 396bdcd8170SKalle Valo u64 tx_bcast_pkt; 397bdcd8170SKalle Valo u64 tx_bcast_byte; 398bdcd8170SKalle Valo u64 tx_rts_success_cnt; 399bdcd8170SKalle Valo u64 tx_pkt_per_ac[4]; 400bdcd8170SKalle Valo 401bdcd8170SKalle Valo u64 tx_err; 402bdcd8170SKalle Valo u64 tx_fail_cnt; 403bdcd8170SKalle Valo u64 tx_retry_cnt; 404bdcd8170SKalle Valo u64 tx_mult_retry_cnt; 405bdcd8170SKalle Valo u64 tx_rts_fail_cnt; 406bdcd8170SKalle Valo 407bdcd8170SKalle Valo u64 rx_pkt; 408bdcd8170SKalle Valo u64 rx_byte; 409bdcd8170SKalle Valo u64 rx_ucast_pkt; 410bdcd8170SKalle Valo u64 rx_ucast_byte; 411bdcd8170SKalle Valo u64 rx_mcast_pkt; 412bdcd8170SKalle Valo u64 rx_mcast_byte; 413bdcd8170SKalle Valo u64 rx_bcast_pkt; 414bdcd8170SKalle Valo u64 rx_bcast_byte; 415bdcd8170SKalle Valo u64 rx_frgment_pkt; 416bdcd8170SKalle Valo 417bdcd8170SKalle Valo u64 rx_err; 418bdcd8170SKalle Valo u64 rx_crc_err; 419bdcd8170SKalle Valo u64 rx_key_cache_miss; 420bdcd8170SKalle Valo u64 rx_decrypt_err; 421bdcd8170SKalle Valo u64 rx_dupl_frame; 422bdcd8170SKalle Valo 423bdcd8170SKalle Valo u64 tkip_local_mic_fail; 424bdcd8170SKalle Valo u64 tkip_cnter_measures_invoked; 425bdcd8170SKalle Valo u64 tkip_replays; 426bdcd8170SKalle Valo u64 tkip_fmt_err; 427bdcd8170SKalle Valo u64 ccmp_fmt_err; 428bdcd8170SKalle Valo u64 ccmp_replays; 429bdcd8170SKalle Valo 430bdcd8170SKalle Valo u64 pwr_save_fail_cnt; 431bdcd8170SKalle Valo 432bdcd8170SKalle Valo u64 cs_bmiss_cnt; 433bdcd8170SKalle Valo u64 cs_low_rssi_cnt; 434bdcd8170SKalle Valo u64 cs_connect_cnt; 435bdcd8170SKalle Valo u64 cs_discon_cnt; 436bdcd8170SKalle Valo 437bdcd8170SKalle Valo s32 tx_ucast_rate; 438bdcd8170SKalle Valo s32 rx_ucast_rate; 439bdcd8170SKalle Valo 440bdcd8170SKalle Valo u32 lq_val; 441bdcd8170SKalle Valo 442bdcd8170SKalle Valo u32 wow_pkt_dropped; 443bdcd8170SKalle Valo u16 wow_evt_discarded; 444bdcd8170SKalle Valo 445bdcd8170SKalle Valo s16 noise_floor_calib; 446bdcd8170SKalle Valo s16 cs_rssi; 447bdcd8170SKalle Valo s16 cs_ave_beacon_rssi; 448bdcd8170SKalle Valo u8 cs_ave_beacon_snr; 449bdcd8170SKalle Valo u8 cs_last_roam_msec; 450bdcd8170SKalle Valo u8 cs_snr; 451bdcd8170SKalle Valo 452bdcd8170SKalle Valo u8 wow_host_pkt_wakeups; 453bdcd8170SKalle Valo u8 wow_host_evt_wakeups; 454bdcd8170SKalle Valo 455bdcd8170SKalle Valo u32 arp_received; 456bdcd8170SKalle Valo u32 arp_matched; 457bdcd8170SKalle Valo u32 arp_replied; 458bdcd8170SKalle Valo }; 459bdcd8170SKalle Valo 460bdcd8170SKalle Valo struct ath6kl_mbox_info { 461bdcd8170SKalle Valo u32 htc_addr; 462bdcd8170SKalle Valo u32 htc_ext_addr; 463bdcd8170SKalle Valo u32 htc_ext_sz; 464bdcd8170SKalle Valo 465bdcd8170SKalle Valo u32 block_size; 466bdcd8170SKalle Valo 467bdcd8170SKalle Valo u32 gmbox_addr; 468bdcd8170SKalle Valo 469bdcd8170SKalle Valo u32 gmbox_sz; 470bdcd8170SKalle Valo }; 471bdcd8170SKalle Valo 472bdcd8170SKalle Valo /* 473bdcd8170SKalle Valo * 802.11i defines an extended IV for use with non-WEP ciphers. 474bdcd8170SKalle Valo * When the EXTIV bit is set in the key id byte an additional 475bdcd8170SKalle Valo * 4 bytes immediately follow the IV for TKIP. For CCMP the 476bdcd8170SKalle Valo * EXTIV bit is likewise set but the 8 bytes represent the 477bdcd8170SKalle Valo * CCMP header rather than IV+extended-IV. 478bdcd8170SKalle Valo */ 479bdcd8170SKalle Valo 480bdcd8170SKalle Valo #define ATH6KL_KEYBUF_SIZE 16 481bdcd8170SKalle Valo #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */ 482bdcd8170SKalle Valo 483bdcd8170SKalle Valo #define ATH6KL_KEY_XMIT 0x01 484bdcd8170SKalle Valo #define ATH6KL_KEY_RECV 0x02 485bdcd8170SKalle Valo #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */ 486bdcd8170SKalle Valo 4879a5b1318SJouni Malinen /* Initial group key for AP mode */ 488bdcd8170SKalle Valo struct ath6kl_req_key { 4899a5b1318SJouni Malinen bool valid; 4909a5b1318SJouni Malinen u8 key_index; 4919a5b1318SJouni Malinen int key_type; 4929a5b1318SJouni Malinen u8 key[WLAN_MAX_KEY_LEN]; 4939a5b1318SJouni Malinen u8 key_len; 494bdcd8170SKalle Valo }; 495bdcd8170SKalle Valo 49677eab1e9SKalle Valo enum ath6kl_hif_type { 49777eab1e9SKalle Valo ATH6KL_HIF_TYPE_SDIO, 49877eab1e9SKalle Valo ATH6KL_HIF_TYPE_USB, 49977eab1e9SKalle Valo }; 50077eab1e9SKalle Valo 501e76ac2bfSKalle Valo enum ath6kl_htc_type { 502e76ac2bfSKalle Valo ATH6KL_HTC_TYPE_MBOX, 503636f8288SKalle Valo ATH6KL_HTC_TYPE_PIPE, 504e76ac2bfSKalle Valo }; 505e76ac2bfSKalle Valo 50680abaf9bSVasanthakumar Thiagarajan /* Max number of filters that hw supports */ 50780abaf9bSVasanthakumar Thiagarajan #define ATH6K_MAX_MC_FILTERS_PER_LIST 7 50880abaf9bSVasanthakumar Thiagarajan struct ath6kl_mc_filter { 50980abaf9bSVasanthakumar Thiagarajan struct list_head list; 51080abaf9bSVasanthakumar Thiagarajan char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE]; 51180abaf9bSVasanthakumar Thiagarajan }; 51280abaf9bSVasanthakumar Thiagarajan 513df90b369SVasanthakumar Thiagarajan struct ath6kl_htcap { 514df90b369SVasanthakumar Thiagarajan bool ht_enable; 515df90b369SVasanthakumar Thiagarajan u8 ampdu_factor; 516df90b369SVasanthakumar Thiagarajan unsigned short cap_info; 517df90b369SVasanthakumar Thiagarajan }; 518df90b369SVasanthakumar Thiagarajan 51971f96ee6SKalle Valo /* 52071f96ee6SKalle Valo * Driver's maximum limit, note that some firmwares support only one vif 52171f96ee6SKalle Valo * and the runtime (current) limit must be checked from ar->vif_max. 52271f96ee6SKalle Valo */ 523b64de356SVasanthakumar Thiagarajan #define ATH6KL_VIF_MAX 3 524334234b5SVasanthakumar Thiagarajan 52559c98449SVasanthakumar Thiagarajan /* vif flags info */ 52659c98449SVasanthakumar Thiagarajan enum ath6kl_vif_state { 52759c98449SVasanthakumar Thiagarajan CONNECTED, 52859c98449SVasanthakumar Thiagarajan CONNECT_PEND, 52959c98449SVasanthakumar Thiagarajan WMM_ENABLED, 53059c98449SVasanthakumar Thiagarajan NETQ_STOPPED, 53159c98449SVasanthakumar Thiagarajan DTIM_EXPIRED, 53259c98449SVasanthakumar Thiagarajan NETDEV_REGISTERED, 53359c98449SVasanthakumar Thiagarajan CLEAR_BSSFILTER_ON_BEACON, 53459c98449SVasanthakumar Thiagarajan DTIM_PERIOD_AVAIL, 53559c98449SVasanthakumar Thiagarajan WLAN_ENABLED, 536b95907a7SVasanthakumar Thiagarajan STATS_UPDATE_PEND, 537081c7a84SRaja Mani HOST_SLEEP_MODE_CMD_PROCESSED, 5386251d801SNaveen Gangadharan NETDEV_MCAST_ALL_ON, 5396251d801SNaveen Gangadharan NETDEV_MCAST_ALL_OFF, 54059c98449SVasanthakumar Thiagarajan }; 54159c98449SVasanthakumar Thiagarajan 542108438bcSVasanthakumar Thiagarajan struct ath6kl_vif { 543990bd915SVasanthakumar Thiagarajan struct list_head list; 544108438bcSVasanthakumar Thiagarajan struct wireless_dev wdev; 545108438bcSVasanthakumar Thiagarajan struct net_device *ndev; 546108438bcSVasanthakumar Thiagarajan struct ath6kl *ar; 547478ac027SVasanthakumar Thiagarajan /* Lock to protect vif specific net_stats and flags */ 548478ac027SVasanthakumar Thiagarajan spinlock_t if_lock; 549334234b5SVasanthakumar Thiagarajan u8 fw_vif_idx; 55059c98449SVasanthakumar Thiagarajan unsigned long flags; 5513450334fSVasanthakumar Thiagarajan int ssid_len; 5523450334fSVasanthakumar Thiagarajan u8 ssid[IEEE80211_MAX_SSID_LEN]; 5533450334fSVasanthakumar Thiagarajan u8 dot11_auth_mode; 5543450334fSVasanthakumar Thiagarajan u8 auth_mode; 5553450334fSVasanthakumar Thiagarajan u8 prwise_crypto; 5563450334fSVasanthakumar Thiagarajan u8 prwise_crypto_len; 5573450334fSVasanthakumar Thiagarajan u8 grp_crypto; 5583450334fSVasanthakumar Thiagarajan u8 grp_crypto_len; 5593450334fSVasanthakumar Thiagarajan u8 def_txkey_index; 560f5938f24SVasanthakumar Thiagarajan u8 next_mode; 561f5938f24SVasanthakumar Thiagarajan u8 nw_type; 5628c8b65e3SVasanthakumar Thiagarajan u8 bssid[ETH_ALEN]; 5638c8b65e3SVasanthakumar Thiagarajan u8 req_bssid[ETH_ALEN]; 564f74bac54SVasanthakumar Thiagarajan u16 ch_hint; 565f74bac54SVasanthakumar Thiagarajan u16 bss_ch; 5666f2a73f9SVasanthakumar Thiagarajan struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1]; 5676f2a73f9SVasanthakumar Thiagarajan struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1]; 5682132c69cSVasanthakumar Thiagarajan struct aggr_info *aggr_cntxt; 56967b3f129SKiran Reddy struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS]; 57010509f90SKalle Valo 571de3ad713SVasanthakumar Thiagarajan struct timer_list disconnect_timer; 57210509f90SKalle Valo struct timer_list sched_scan_timer; 57310509f90SKalle Valo 57414ee6f6bSVasanthakumar Thiagarajan struct cfg80211_scan_request *scan_req; 57514ee6f6bSVasanthakumar Thiagarajan enum sme_state sme_state; 576cf5333d7SVasanthakumar Thiagarajan int reconnect_flag; 5771052261eSJouni Malinen u32 last_roc_id; 5781052261eSJouni Malinen u32 last_cancel_roc_id; 579cf5333d7SVasanthakumar Thiagarajan u32 send_action_id; 580cf5333d7SVasanthakumar Thiagarajan bool probe_req_report; 581cf5333d7SVasanthakumar Thiagarajan u16 next_chan; 582df90b369SVasanthakumar Thiagarajan enum nl80211_channel_type next_ch_type; 583df90b369SVasanthakumar Thiagarajan enum ieee80211_band next_ch_band; 584cf5333d7SVasanthakumar Thiagarajan u16 assoc_bss_beacon_int; 5858f46fccdSRaja Mani u16 listen_intvl_t; 586ce0dc0cfSRaja Mani u16 bmiss_time_t; 587eb38987eSRaja Mani u16 bg_scan_period; 588cf5333d7SVasanthakumar Thiagarajan u8 assoc_bss_dtim_period; 589b95907a7SVasanthakumar Thiagarajan struct net_device_stats net_stats; 590b95907a7SVasanthakumar Thiagarajan struct target_stats target_stats; 591c4f7863eSThomas Pedersen struct wmi_connect_cmd profile; 59280abaf9bSVasanthakumar Thiagarajan 59380abaf9bSVasanthakumar Thiagarajan struct list_head mc_filter; 594108438bcSVasanthakumar Thiagarajan }; 595108438bcSVasanthakumar Thiagarajan 5966cb3c714SRaja Mani #define WOW_LIST_ID 0 5976cb3c714SRaja Mani #define WOW_HOST_REQ_DELAY 500 /* ms */ 5986cb3c714SRaja Mani 59910509f90SKalle Valo #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */ 60010509f90SKalle Valo 601bdcd8170SKalle Valo /* Flag info */ 60259c98449SVasanthakumar Thiagarajan enum ath6kl_dev_state { 60359c98449SVasanthakumar Thiagarajan WMI_ENABLED, 60459c98449SVasanthakumar Thiagarajan WMI_READY, 60559c98449SVasanthakumar Thiagarajan WMI_CTRL_EP_FULL, 60659c98449SVasanthakumar Thiagarajan TESTMODE, 60759c98449SVasanthakumar Thiagarajan DESTROY_IN_PROGRESS, 60859c98449SVasanthakumar Thiagarajan SKIP_SCAN, 60959c98449SVasanthakumar Thiagarajan ROAM_TBL_PEND, 6105fe4dffbSKalle Valo FIRST_BOOT, 61159c98449SVasanthakumar Thiagarajan }; 612bdcd8170SKalle Valo 61376a9fbe2SKalle Valo enum ath6kl_state { 61476a9fbe2SKalle Valo ATH6KL_STATE_OFF, 61576a9fbe2SKalle Valo ATH6KL_STATE_ON, 616390a8c8fSRaja Mani ATH6KL_STATE_SUSPENDING, 617390a8c8fSRaja Mani ATH6KL_STATE_RESUMING, 61876a9fbe2SKalle Valo ATH6KL_STATE_DEEPSLEEP, 619b4b2a0b1SKalle Valo ATH6KL_STATE_CUTPOWER, 620dd6c0c63SRaja Mani ATH6KL_STATE_WOW, 62110509f90SKalle Valo ATH6KL_STATE_SCHED_SCAN, 62276a9fbe2SKalle Valo }; 62376a9fbe2SKalle Valo 624bdcd8170SKalle Valo struct ath6kl { 625bdcd8170SKalle Valo struct device *dev; 626be98e3a4SVasanthakumar Thiagarajan struct wiphy *wiphy; 62776a9fbe2SKalle Valo 62876a9fbe2SKalle Valo enum ath6kl_state state; 6295f1127ffSKalle Valo unsigned int testmode; 63076a9fbe2SKalle Valo 631bdcd8170SKalle Valo struct ath6kl_bmi bmi; 632bdcd8170SKalle Valo const struct ath6kl_hif_ops *hif_ops; 633e76ac2bfSKalle Valo const struct ath6kl_htc_ops *htc_ops; 634bdcd8170SKalle Valo struct wmi *wmi; 635bdcd8170SKalle Valo int tx_pending[ENDPOINT_MAX]; 636bdcd8170SKalle Valo int total_tx_data_pend; 637bdcd8170SKalle Valo struct htc_target *htc_target; 63877eab1e9SKalle Valo enum ath6kl_hif_type hif_type; 639bdcd8170SKalle Valo void *hif_priv; 640990bd915SVasanthakumar Thiagarajan struct list_head vif_list; 641990bd915SVasanthakumar Thiagarajan /* Lock to avoid race in vif_list entries among add/del/traverse */ 642990bd915SVasanthakumar Thiagarajan spinlock_t list_lock; 64355055976SVasanthakumar Thiagarajan u8 num_vif; 644368b1b0fSKalle Valo unsigned int vif_max; 6453226f68aSVasanthakumar Thiagarajan u8 max_norm_iface; 64655055976SVasanthakumar Thiagarajan u8 avail_idx_map; 64712eb9444SKalle Valo 64812eb9444SKalle Valo /* 64912eb9444SKalle Valo * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie() 65012eb9444SKalle Valo * calls, tx_pending and total_tx_data_pend. 65112eb9444SKalle Valo */ 652bdcd8170SKalle Valo spinlock_t lock; 65312eb9444SKalle Valo 654bdcd8170SKalle Valo struct semaphore sem; 655e5090444SVivek Natarajan u8 lrssi_roam_threshold; 656bdcd8170SKalle Valo struct ath6kl_version version; 657bdcd8170SKalle Valo u32 target_type; 658bdcd8170SKalle Valo u8 tx_pwr; 659bdcd8170SKalle Valo struct ath6kl_node_mapping node_map[MAX_NODE_NUM]; 660bdcd8170SKalle Valo u8 ibss_ps_enable; 66155055976SVasanthakumar Thiagarajan bool ibss_if_active; 662bdcd8170SKalle Valo u8 node_num; 663bdcd8170SKalle Valo u8 next_ep_id; 664bdcd8170SKalle Valo struct ath6kl_cookie *cookie_list; 665bdcd8170SKalle Valo u32 cookie_count; 666bdcd8170SKalle Valo enum htc_endpoint_id ac2ep_map[WMM_NUM_AC]; 667bdcd8170SKalle Valo bool ac_stream_active[WMM_NUM_AC]; 668bdcd8170SKalle Valo u8 ac_stream_pri_map[WMM_NUM_AC]; 669bdcd8170SKalle Valo u8 hiac_stream_active_pri; 670bdcd8170SKalle Valo u8 ep2ac_map[ENDPOINT_MAX]; 671bdcd8170SKalle Valo enum htc_endpoint_id ctrl_ep; 6723c370398SKalle Valo struct ath6kl_htc_credit_info credit_state_info; 673bdcd8170SKalle Valo u32 connect_ctrl_flags; 674bdcd8170SKalle Valo u32 user_key_ctrl; 675bdcd8170SKalle Valo u8 usr_bss_filter; 676bdcd8170SKalle Valo struct ath6kl_sta sta_list[AP_MAX_NUM_STA]; 677bdcd8170SKalle Valo u8 sta_list_index; 678bdcd8170SKalle Valo struct ath6kl_req_key ap_mode_bkey; 679bdcd8170SKalle Valo struct sk_buff_head mcastpsq; 680c4f7863eSThomas Pedersen u32 want_ch_switch; 68112eb9444SKalle Valo 68212eb9444SKalle Valo /* 68312eb9444SKalle Valo * FIXME: protects access to mcastpsq but is actually useless as 68412eb9444SKalle Valo * all skbe_queue_*() functions provide serialisation themselves 68512eb9444SKalle Valo */ 686bdcd8170SKalle Valo spinlock_t mcastpsq_lock; 68712eb9444SKalle Valo 688bdcd8170SKalle Valo u8 intra_bss; 689bdcd8170SKalle Valo struct wmi_ap_mode_stat ap_stats; 690bdcd8170SKalle Valo u8 ap_country_code[3]; 691bdcd8170SKalle Valo struct list_head amsdu_rx_buffer_queue; 692bdcd8170SKalle Valo u8 rx_meta_ver; 693bdcd8170SKalle Valo enum wlan_low_pwr_state wlan_pwr_state; 694d66ea4f9SVasanthakumar Thiagarajan u8 mac_addr[ETH_ALEN]; 695bdcd8170SKalle Valo #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4 696003353b0SKalle Valo struct { 697003353b0SKalle Valo void *rx_report; 698003353b0SKalle Valo size_t rx_report_len; 699003353b0SKalle Valo } tm; 700003353b0SKalle Valo 701856f4b31SKalle Valo struct ath6kl_hw { 702856f4b31SKalle Valo u32 id; 703293badf4SKalle Valo const char *name; 704a01ac414SKalle Valo u32 dataset_patch_addr; 705a01ac414SKalle Valo u32 app_load_addr; 706a01ac414SKalle Valo u32 app_start_override_addr; 707991b27eaSKalle Valo u32 board_ext_data_addr; 708991b27eaSKalle Valo u32 reserved_ram_size; 7090d4d72bfSKalle Valo u32 board_addr; 71039586bf2SRyan Hsu u32 refclk_hz; 71139586bf2SRyan Hsu u32 uarttx_pin; 712cd23c1c9SAlex Yang u32 testscript_addr; 713d92917e4SThomas Pedersen enum wmi_phy_cap cap; 714d1a9421dSKalle Valo 71506e360acSBala Shanmugam u32 flags; 71606e360acSBala Shanmugam 717c0038972SKalle Valo struct ath6kl_hw_fw { 718c0038972SKalle Valo const char *dir; 719c0038972SKalle Valo const char *otp; 720d1a9421dSKalle Valo const char *fw; 721c0038972SKalle Valo const char *tcmd; 722c0038972SKalle Valo const char *patch; 723cd23c1c9SAlex Yang const char *utf; 724cd23c1c9SAlex Yang const char *testscript; 725c0038972SKalle Valo } fw; 726c0038972SKalle Valo 727d1a9421dSKalle Valo const char *fw_board; 728d1a9421dSKalle Valo const char *fw_default_board; 729a01ac414SKalle Valo } hw; 730a01ac414SKalle Valo 731bdcd8170SKalle Valo u16 conf_flags; 732e390af77SRaja Mani u16 suspend_mode; 7331e9a905dSRaja Mani u16 wow_suspend_mode; 734bdcd8170SKalle Valo wait_queue_head_t event_wq; 735bdcd8170SKalle Valo struct ath6kl_mbox_info mbox_info; 736bdcd8170SKalle Valo 737bdcd8170SKalle Valo struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM]; 738bdcd8170SKalle Valo unsigned long flag; 739bdcd8170SKalle Valo 740bdcd8170SKalle Valo u8 *fw_board; 741bdcd8170SKalle Valo size_t fw_board_len; 742bdcd8170SKalle Valo 743bdcd8170SKalle Valo u8 *fw_otp; 744bdcd8170SKalle Valo size_t fw_otp_len; 745bdcd8170SKalle Valo 746bdcd8170SKalle Valo u8 *fw; 747bdcd8170SKalle Valo size_t fw_len; 748bdcd8170SKalle Valo 749bdcd8170SKalle Valo u8 *fw_patch; 750bdcd8170SKalle Valo size_t fw_patch_len; 751bdcd8170SKalle Valo 752cd23c1c9SAlex Yang u8 *fw_testscript; 753cd23c1c9SAlex Yang size_t fw_testscript_len; 754cd23c1c9SAlex Yang 75565a8b4ccSKalle Valo unsigned int fw_api; 75697e0496dSKalle Valo unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN]; 75797e0496dSKalle Valo 758bdcd8170SKalle Valo struct workqueue_struct *ath6kl_wq; 7597c3075e9SVasanthakumar Thiagarajan 760d999ba3eSVasanthakumar Thiagarajan struct dentry *debugfs_phy; 7616a7c9badSJouni Malinen 7626bbc7c35SJouni Malinen bool p2p; 7636bbc7c35SJouni Malinen 764e5348a1eSVasanthakumar Thiagarajan bool wiphy_registered; 765e5348a1eSVasanthakumar Thiagarajan 766bdf5396bSKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 767bdf5396bSKalle Valo struct { 7689b9a4f2aSKalle Valo struct sk_buff_head fwlog_queue; 769c807b30dSKalle Valo struct completion fwlog_completion; 770c807b30dSKalle Valo bool fwlog_open; 771c807b30dSKalle Valo 772939f1cceSKalle Valo u32 fwlog_mask; 7739b9a4f2aSKalle Valo 77491d57de5SVasanthakumar Thiagarajan unsigned int dbgfs_diag_reg; 775252c068bSVasanthakumar Thiagarajan u32 diag_reg_addr_wr; 776252c068bSVasanthakumar Thiagarajan u32 diag_reg_val_wr; 7779a730834SKalle Valo 7789a730834SKalle Valo struct { 7799a730834SKalle Valo unsigned int invalid_rate; 7809a730834SKalle Valo } war_stats; 7814b28a80dSJouni Malinen 7824b28a80dSJouni Malinen u8 *roam_tbl; 7834b28a80dSJouni Malinen unsigned int roam_tbl_len; 784ff0b0075SJouni Malinen 785ff0b0075SJouni Malinen u8 keepalive; 786ff0b0075SJouni Malinen u8 disc_timeout; 787bdf5396bSKalle Valo } debug; 788bdf5396bSKalle Valo #endif /* CONFIG_ATH6KL_DEBUG */ 789bdcd8170SKalle Valo }; 790bdcd8170SKalle Valo 791d6d5c06cSKalle Valo static inline struct ath6kl *ath6kl_priv(struct net_device *dev) 792bdcd8170SKalle Valo { 793108438bcSVasanthakumar Thiagarajan return ((struct ath6kl_vif *) netdev_priv(dev))->ar; 794bdcd8170SKalle Valo } 795bdcd8170SKalle Valo 796bc07ddb2SKalle Valo static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar, 797bc07ddb2SKalle Valo u32 item_offset) 798bc07ddb2SKalle Valo { 799bc07ddb2SKalle Valo u32 addr = 0; 800bc07ddb2SKalle Valo 801bc07ddb2SKalle Valo if (ar->target_type == TARGET_TYPE_AR6003) 802bc07ddb2SKalle Valo addr = ATH6KL_AR6003_HI_START_ADDR + item_offset; 803bc07ddb2SKalle Valo else if (ar->target_type == TARGET_TYPE_AR6004) 804bc07ddb2SKalle Valo addr = ATH6KL_AR6004_HI_START_ADDR + item_offset; 805bc07ddb2SKalle Valo 806bc07ddb2SKalle Valo return addr; 807bc07ddb2SKalle Valo } 808bc07ddb2SKalle Valo 809bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar); 810bdcd8170SKalle Valo void ath6kl_detect_error(unsigned long ptr); 811bdcd8170SKalle Valo void disconnect_timer_handler(unsigned long ptr); 812bdcd8170SKalle Valo void init_netdev(struct net_device *dev); 813bdcd8170SKalle Valo void ath6kl_cookie_init(struct ath6kl *ar); 814bdcd8170SKalle Valo void ath6kl_cookie_cleanup(struct ath6kl *ar); 815bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet); 81663de1112SKalle Valo void ath6kl_tx_complete(struct htc_target *context, 81763de1112SKalle Valo struct list_head *packet_queue); 818bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 819bdcd8170SKalle Valo struct htc_packet *packet); 820bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar); 821bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar); 822f9ea0753SVasanthakumar Thiagarajan int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value); 823addb44beSKalle Valo int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length); 824addb44beSKalle Valo int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value); 825addb44beSKalle Valo int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length); 826bc07ddb2SKalle Valo int ath6kl_read_fwlogs(struct ath6kl *ar); 827e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif); 828bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar); 829bdcd8170SKalle Valo 830bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar); 831bdcd8170SKalle Valo void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie); 832bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev); 833bdcd8170SKalle Valo 8347baef812SVasanthakumar Thiagarajan struct aggr_info *aggr_init(struct ath6kl_vif *vif); 835c8651541SVasanthakumar Thiagarajan void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info, 836c8651541SVasanthakumar Thiagarajan struct aggr_info_conn *aggr_conn); 837bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, 838bdcd8170SKalle Valo enum htc_endpoint_id endpoint); 839bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count); 840bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 841bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 842bdcd8170SKalle Valo int len); 843bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info); 8441d2a4456SVasanthakumar Thiagarajan void aggr_reset_state(struct aggr_info_conn *aggr_conn); 845bdcd8170SKalle Valo 8466765d0aaSVasanthakumar Thiagarajan struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr); 847bdcd8170SKalle Valo struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid); 848bdcd8170SKalle Valo 849d92917e4SThomas Pedersen void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver, 850d92917e4SThomas Pedersen enum wmi_phy_cap cap); 851bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 852bdcd8170SKalle Valo enum htc_endpoint_id eid); 853240d2799SVasanthakumar Thiagarajan void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel, 854bdcd8170SKalle Valo u8 *bssid, u16 listen_int, 855bdcd8170SKalle Valo u16 beacon_int, enum network_type net_type, 856bdcd8170SKalle Valo u8 beacon_ie_len, u8 assoc_req_len, 857bdcd8170SKalle Valo u8 assoc_resp_len, u8 *assoc_info); 858240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel); 859240d2799SVasanthakumar Thiagarajan void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr, 860572e27c0SJouni Malinen u8 keymgmt, u8 ucipher, u8 auth, 861c1762a3fSThirumalai Pachamuthu u8 assoc_req_len, u8 *assoc_info, u8 apsd_info); 862240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason, 863bdcd8170SKalle Valo u8 *bssid, u8 assoc_resp_len, 864bdcd8170SKalle Valo u8 *assoc_info, u16 prot_reason_status); 865240d2799SVasanthakumar Thiagarajan void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast); 866bdcd8170SKalle Valo void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr); 867240d2799SVasanthakumar Thiagarajan void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status); 868240d2799SVasanthakumar Thiagarajan void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len); 869bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active); 870bdcd8170SKalle Valo enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac); 871bdcd8170SKalle Valo 872240d2799SVasanthakumar Thiagarajan void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid); 873bdcd8170SKalle Valo 874240d2799SVasanthakumar Thiagarajan void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif); 875240d2799SVasanthakumar Thiagarajan void ath6kl_disconnect(struct ath6kl_vif *vif); 876240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid); 877240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 878bdcd8170SKalle Valo u8 win_sz); 879bdcd8170SKalle Valo void ath6kl_wakeup_event(void *dev); 880bdcd8170SKalle Valo 8816db8fa53SVasanthakumar Thiagarajan void ath6kl_reset_device(struct ath6kl *ar, u32 target_type, 8826db8fa53SVasanthakumar Thiagarajan bool wait_fot_compltn, bool cold_reset); 883e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif); 884990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar); 88555055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready); 8865fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar); 8875fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar); 88845eaa78fSKalle Valo int ath6kl_init_fetch_firmwares(struct ath6kl *ar); 88945eaa78fSKalle Valo int ath6kl_init_hw_params(struct ath6kl *ar); 89045eaa78fSKalle Valo 891a918fb3cSRaja Mani void ath6kl_check_wow_status(struct ath6kl *ar); 8925fe4dffbSKalle Valo 893636f8288SKalle Valo void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb); 894636f8288SKalle Valo void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe); 895636f8288SKalle Valo 89645eaa78fSKalle Valo struct ath6kl *ath6kl_core_create(struct device *dev); 897e76ac2bfSKalle Valo int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type); 89845eaa78fSKalle Valo void ath6kl_core_cleanup(struct ath6kl *ar); 89945eaa78fSKalle Valo void ath6kl_core_destroy(struct ath6kl *ar); 90045eaa78fSKalle Valo 901bdcd8170SKalle Valo #endif /* CORE_H */ 902