1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 */ 21 22 #define _ATH5K_RESET 23 24 /*****************************\ 25 Reset functions and helpers 26 \*****************************/ 27 28 #include <linux/pci.h> /* To determine if a card is pci-e */ 29 #include <linux/log2.h> 30 #include "ath5k.h" 31 #include "reg.h" 32 #include "base.h" 33 #include "debug.h" 34 35 /** 36 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 37 * 38 * @ah: the &struct ath5k_hw 39 * @channel: the currently set channel upon reset 40 * 41 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 42 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset(). 43 * 44 * Since delta slope is floating point we split it on its exponent and 45 * mantissa and provide these values on hw. 46 * 47 * For more infos i think this patent is related 48 * http://www.freepatentsonline.com/7184495.html 49 */ 50 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 51 struct ieee80211_channel *channel) 52 { 53 /* Get exponent and mantissa and set it */ 54 u32 coef_scaled, coef_exp, coef_man, 55 ds_coef_exp, ds_coef_man, clock; 56 57 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 58 !(channel->hw_value & CHANNEL_OFDM)); 59 60 /* Get coefficient 61 * ALGO: coef = (5 * clock * carrier_freq) / 2) 62 * we scale coef by shifting clock value by 24 for 63 * better precision since we use integers */ 64 /* TODO: Half/quarter rate */ 65 clock = ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO); 66 67 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 68 69 /* Get exponent 70 * ALGO: coef_exp = 14 - highest set bit position */ 71 coef_exp = ilog2(coef_scaled); 72 73 /* Doesn't make sense if it's zero*/ 74 if (!coef_scaled || !coef_exp) 75 return -EINVAL; 76 77 /* Note: we've shifted coef_scaled by 24 */ 78 coef_exp = 14 - (coef_exp - 24); 79 80 81 /* Get mantissa (significant digits) 82 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 83 coef_man = coef_scaled + 84 (1 << (24 - coef_exp - 1)); 85 86 /* Calculate delta slope coefficient exponent 87 * and mantissa (remove scaling) and set them on hw */ 88 ds_coef_man = coef_man >> (24 - coef_exp); 89 ds_coef_exp = coef_exp - 16; 90 91 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 92 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 94 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 95 96 return 0; 97 } 98 99 100 /* 101 * index into rates for control rates, we can set it up like this because 102 * this is only used for AR5212 and we know it supports G mode 103 */ 104 static const unsigned int control_rates[] = 105 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }; 106 107 /** 108 * ath5k_hw_write_rate_duration - fill rate code to duration table 109 * 110 * @ah: the &struct ath5k_hw 111 * @mode: one of enum ath5k_driver_mode 112 * 113 * Write the rate code to duration table upon hw reset. This is a helper for 114 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on 115 * the hardware, based on current mode, for each rate. The rates which are 116 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 117 * different rate code so we write their value twice (one for long preample 118 * and one for short). 119 * 120 * Note: Band doesn't matter here, if we set the values for OFDM it works 121 * on both a and g modes. So all we have to do is set values for all g rates 122 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/ 123 * quarter rate mode, we need to use another set of bitrates (that's why we 124 * need the mode parameter) but we don't handle these proprietary modes yet. 125 */ 126 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, 127 unsigned int mode) 128 { 129 struct ath5k_softc *sc = ah->ah_sc; 130 struct ieee80211_rate *rate; 131 unsigned int i; 132 133 /* Write rate duration table */ 134 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) { 135 u32 reg; 136 u16 tx_time; 137 138 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]]; 139 140 /* Set ACK timeout */ 141 reg = AR5K_RATE_DUR(rate->hw_value); 142 143 /* An ACK frame consists of 10 bytes. If you add the FCS, 144 * which ieee80211_generic_frame_duration() adds, 145 * its 14 bytes. Note we use the control rate and not the 146 * actual rate for this rate. See mac80211 tx.c 147 * ieee80211_duration() for a brief description of 148 * what rate we should choose to TX ACKs. */ 149 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw, 150 sc->vif, 10, rate)); 151 152 ath5k_hw_reg_write(ah, tx_time, reg); 153 154 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 155 continue; 156 157 /* 158 * We're not distinguishing short preamble here, 159 * This is true, all we'll get is a longer value here 160 * which is not necessarilly bad. We could use 161 * export ieee80211_frame_duration() but that needs to be 162 * fixed first to be properly used by mac802111 drivers: 163 * 164 * - remove erp stuff and let the routine figure ofdm 165 * erp rates 166 * - remove passing argument ieee80211_local as 167 * drivers don't have access to it 168 * - move drivers using ieee80211_generic_frame_duration() 169 * to this 170 */ 171 ath5k_hw_reg_write(ah, tx_time, 172 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 173 } 174 } 175 176 /* 177 * Reset chipset 178 */ 179 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) 180 { 181 int ret; 182 u32 mask = val ? val : ~0U; 183 184 ATH5K_TRACE(ah->ah_sc); 185 186 /* Read-and-clear RX Descriptor Pointer*/ 187 ath5k_hw_reg_read(ah, AR5K_RXDP); 188 189 /* 190 * Reset the device and wait until success 191 */ 192 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); 193 194 /* Wait at least 128 PCI clocks */ 195 udelay(15); 196 197 if (ah->ah_version == AR5K_AR5210) { 198 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 199 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 200 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 201 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 202 } else { 203 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 204 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 205 } 206 207 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); 208 209 /* 210 * Reset configuration register (for hw byte-swap). Note that this 211 * is only set for big endian. We do the necessary magic in 212 * AR5K_INIT_CFG. 213 */ 214 if ((val & AR5K_RESET_CTL_PCU) == 0) 215 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); 216 217 return ret; 218 } 219 220 /* 221 * Sleep control 222 */ 223 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 224 bool set_chip, u16 sleep_duration) 225 { 226 unsigned int i; 227 u32 staid, data; 228 229 ATH5K_TRACE(ah->ah_sc); 230 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); 231 232 switch (mode) { 233 case AR5K_PM_AUTO: 234 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; 235 /* fallthrough */ 236 case AR5K_PM_NETWORK_SLEEP: 237 if (set_chip) 238 ath5k_hw_reg_write(ah, 239 AR5K_SLEEP_CTL_SLE_ALLOW | 240 sleep_duration, 241 AR5K_SLEEP_CTL); 242 243 staid |= AR5K_STA_ID1_PWR_SV; 244 break; 245 246 case AR5K_PM_FULL_SLEEP: 247 if (set_chip) 248 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, 249 AR5K_SLEEP_CTL); 250 251 staid |= AR5K_STA_ID1_PWR_SV; 252 break; 253 254 case AR5K_PM_AWAKE: 255 256 staid &= ~AR5K_STA_ID1_PWR_SV; 257 258 if (!set_chip) 259 goto commit; 260 261 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL); 262 263 /* If card is down we 'll get 0xffff... so we 264 * need to clean this up before we write the register 265 */ 266 if (data & 0xffc00000) 267 data = 0; 268 else 269 /* Preserve sleep duration etc */ 270 data = data & ~AR5K_SLEEP_CTL_SLE; 271 272 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 273 AR5K_SLEEP_CTL); 274 udelay(15); 275 276 for (i = 200; i > 0; i--) { 277 /* Check if the chip did wake up */ 278 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & 279 AR5K_PCICFG_SPWR_DN) == 0) 280 break; 281 282 /* Wait a bit and retry */ 283 udelay(50); 284 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 285 AR5K_SLEEP_CTL); 286 } 287 288 /* Fail if the chip didn't wake up */ 289 if (i == 0) 290 return -EIO; 291 292 break; 293 294 default: 295 return -EINVAL; 296 } 297 298 commit: 299 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); 300 301 return 0; 302 } 303 304 /* 305 * Put device on hold 306 * 307 * Put MAC and Baseband on warm reset and 308 * keep that state (don't clean sleep control 309 * register). After this MAC and Baseband are 310 * disabled and a full reset is needed to come 311 * back. This way we save as much power as possible 312 * without puting the card on full sleep. 313 */ 314 int ath5k_hw_on_hold(struct ath5k_hw *ah) 315 { 316 struct pci_dev *pdev = ah->ah_sc->pdev; 317 u32 bus_flags; 318 int ret; 319 320 /* Make sure device is awake */ 321 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 322 if (ret) { 323 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 324 return ret; 325 } 326 327 /* 328 * Put chipset on warm reset... 329 * 330 * Note: puting PCI core on warm reset on PCI-E cards 331 * results card to hang and always return 0xffff... so 332 * we ingore that flag for PCI-E cards. On PCI cards 333 * this flag gets cleared after 64 PCI clocks. 334 */ 335 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 336 337 if (ah->ah_version == AR5K_AR5210) { 338 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 339 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 340 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 341 mdelay(2); 342 } else { 343 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 344 AR5K_RESET_CTL_BASEBAND | bus_flags); 345 } 346 347 if (ret) { 348 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n"); 349 return -EIO; 350 } 351 352 /* ...wakeup again!*/ 353 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 354 if (ret) { 355 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n"); 356 return ret; 357 } 358 359 return ret; 360 } 361 362 /* 363 * Bring up MAC + PHY Chips and program PLL 364 * TODO: Half/Quarter rate support 365 */ 366 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 367 { 368 struct pci_dev *pdev = ah->ah_sc->pdev; 369 u32 turbo, mode, clock, bus_flags; 370 int ret; 371 372 turbo = 0; 373 mode = 0; 374 clock = 0; 375 376 ATH5K_TRACE(ah->ah_sc); 377 378 /* Wakeup the device */ 379 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 380 if (ret) { 381 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 382 return ret; 383 } 384 385 /* 386 * Put chipset on warm reset... 387 * 388 * Note: puting PCI core on warm reset on PCI-E cards 389 * results card to hang and always return 0xffff... so 390 * we ingore that flag for PCI-E cards. On PCI cards 391 * this flag gets cleared after 64 PCI clocks. 392 */ 393 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 394 395 if (ah->ah_version == AR5K_AR5210) { 396 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 397 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 398 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 399 mdelay(2); 400 } else { 401 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 402 AR5K_RESET_CTL_BASEBAND | bus_flags); 403 } 404 405 if (ret) { 406 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n"); 407 return -EIO; 408 } 409 410 /* ...wakeup again!...*/ 411 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 412 if (ret) { 413 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n"); 414 return ret; 415 } 416 417 /* ...clear reset control register and pull device out of 418 * warm reset */ 419 if (ath5k_hw_nic_reset(ah, 0)) { 420 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); 421 return -EIO; 422 } 423 424 /* On initialization skip PLL programming since we don't have 425 * a channel / mode set yet */ 426 if (initial) 427 return 0; 428 429 if (ah->ah_version != AR5K_AR5210) { 430 /* 431 * Get channel mode flags 432 */ 433 434 if (ah->ah_radio >= AR5K_RF5112) { 435 mode = AR5K_PHY_MODE_RAD_RF5112; 436 clock = AR5K_PHY_PLL_RF5112; 437 } else { 438 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ 439 clock = AR5K_PHY_PLL_RF5111; /*Zero*/ 440 } 441 442 if (flags & CHANNEL_2GHZ) { 443 mode |= AR5K_PHY_MODE_FREQ_2GHZ; 444 clock |= AR5K_PHY_PLL_44MHZ; 445 446 if (flags & CHANNEL_CCK) { 447 mode |= AR5K_PHY_MODE_MOD_CCK; 448 } else if (flags & CHANNEL_OFDM) { 449 /* XXX Dynamic OFDM/CCK is not supported by the 450 * AR5211 so we set MOD_OFDM for plain g (no 451 * CCK headers) operation. We need to test 452 * this, 5211 might support ofdm-only g after 453 * all, there are also initial register values 454 * in the code for g mode (see initvals.c). */ 455 if (ah->ah_version == AR5K_AR5211) 456 mode |= AR5K_PHY_MODE_MOD_OFDM; 457 else 458 mode |= AR5K_PHY_MODE_MOD_DYN; 459 } else { 460 ATH5K_ERR(ah->ah_sc, 461 "invalid radio modulation mode\n"); 462 return -EINVAL; 463 } 464 } else if (flags & CHANNEL_5GHZ) { 465 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 466 467 if (ah->ah_radio == AR5K_RF5413) 468 clock = AR5K_PHY_PLL_40MHZ_5413; 469 else 470 clock |= AR5K_PHY_PLL_40MHZ; 471 472 if (flags & CHANNEL_OFDM) 473 mode |= AR5K_PHY_MODE_MOD_OFDM; 474 else { 475 ATH5K_ERR(ah->ah_sc, 476 "invalid radio modulation mode\n"); 477 return -EINVAL; 478 } 479 } else { 480 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n"); 481 return -EINVAL; 482 } 483 484 if (flags & CHANNEL_TURBO) 485 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 486 } else { /* Reset the device */ 487 488 /* ...enable Atheros turbo mode if requested */ 489 if (flags & CHANNEL_TURBO) 490 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 491 AR5K_PHY_TURBO); 492 } 493 494 if (ah->ah_version != AR5K_AR5210) { 495 496 /* ...update PLL if needed */ 497 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) { 498 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); 499 udelay(300); 500 } 501 502 /* ...set the PHY operating mode */ 503 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); 504 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); 505 } 506 507 return 0; 508 } 509 510 /* 511 * If there is an external 32KHz crystal available, use it 512 * as ref. clock instead of 32/40MHz clock and baseband clocks 513 * to save power during sleep or restore normal 32/40MHz 514 * operation. 515 * 516 * XXX: When operating on 32KHz certain PHY registers (27 - 31, 517 * 123 - 127) require delay on access. 518 */ 519 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) 520 { 521 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 522 u32 scal, spending, usec32; 523 524 /* Only set 32KHz settings if we have an external 525 * 32KHz crystal present */ 526 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) || 527 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) && 528 enable) { 529 530 /* 1 usec/cycle */ 531 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1); 532 /* Set up tsf increment on each cycle */ 533 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61); 534 535 /* Set baseband sleep control registers 536 * and sleep control rate */ 537 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 538 539 if ((ah->ah_radio == AR5K_RF5112) || 540 (ah->ah_radio == AR5K_RF5413) || 541 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 542 spending = 0x14; 543 else 544 spending = 0x18; 545 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 546 547 if ((ah->ah_radio == AR5K_RF5112) || 548 (ah->ah_radio == AR5K_RF5413) || 549 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 550 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); 551 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL); 552 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK); 553 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY); 554 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 555 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02); 556 } else { 557 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); 558 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL); 559 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK); 560 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY); 561 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 562 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03); 563 } 564 565 /* Enable sleep clock operation */ 566 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, 567 AR5K_PCICFG_SLEEP_CLOCK_EN); 568 569 } else { 570 571 /* Disable sleep clock operation and 572 * restore default parameters */ 573 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, 574 AR5K_PCICFG_SLEEP_CLOCK_EN); 575 576 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 577 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0); 578 579 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 580 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); 581 582 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 583 scal = AR5K_PHY_SCAL_32MHZ_2417; 584 else if (ee->ee_is_hb63) 585 scal = AR5K_PHY_SCAL_32MHZ_HB63; 586 else 587 scal = AR5K_PHY_SCAL_32MHZ; 588 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 589 590 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); 591 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); 592 593 if ((ah->ah_radio == AR5K_RF5112) || 594 (ah->ah_radio == AR5K_RF5413) || 595 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 596 spending = 0x14; 597 else 598 spending = 0x18; 599 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 600 601 if ((ah->ah_radio == AR5K_RF5112) || 602 (ah->ah_radio == AR5K_RF5413)) 603 usec32 = 39; 604 else 605 usec32 = 31; 606 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32); 607 608 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); 609 } 610 return; 611 } 612 613 /* TODO: Half/Quarter rate */ 614 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, 615 struct ieee80211_channel *channel) 616 { 617 if (ah->ah_version == AR5K_AR5212 && 618 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 619 620 /* Setup ADC control */ 621 ath5k_hw_reg_write(ah, 622 (AR5K_REG_SM(2, 623 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) | 624 AR5K_REG_SM(2, 625 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) | 626 AR5K_PHY_ADC_CTL_PWD_DAC_OFF | 627 AR5K_PHY_ADC_CTL_PWD_ADC_OFF), 628 AR5K_PHY_ADC_CTL); 629 630 631 632 /* Disable barker RSSI threshold */ 633 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 634 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR); 635 636 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 637 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2); 638 639 /* Set the mute mask */ 640 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); 641 } 642 643 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */ 644 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B) 645 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH); 646 647 /* Enable DCU double buffering */ 648 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B) 649 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 650 AR5K_TXCFG_DCU_DBL_BUF_DIS); 651 652 /* Set DAC/ADC delays */ 653 if (ah->ah_version == AR5K_AR5212) { 654 u32 scal; 655 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 656 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 657 scal = AR5K_PHY_SCAL_32MHZ_2417; 658 else if (ee->ee_is_hb63) 659 scal = AR5K_PHY_SCAL_32MHZ_HB63; 660 else 661 scal = AR5K_PHY_SCAL_32MHZ; 662 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 663 } 664 665 /* Set fast ADC */ 666 if ((ah->ah_radio == AR5K_RF5413) || 667 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 668 u32 fast_adc = true; 669 670 if (channel->center_freq == 2462 || 671 channel->center_freq == 2467) 672 fast_adc = 0; 673 674 /* Only update if needed */ 675 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc) 676 ath5k_hw_reg_write(ah, fast_adc, 677 AR5K_PHY_FAST_ADC); 678 } 679 680 /* Fix for first revision of the RF5112 RF chipset */ 681 if (ah->ah_radio == AR5K_RF5112 && 682 ah->ah_radio_5ghz_revision < 683 AR5K_SREV_RAD_5112A) { 684 u32 data; 685 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, 686 AR5K_PHY_CCKTXCTL); 687 if (channel->hw_value & CHANNEL_5GHZ) 688 data = 0xffb81020; 689 else 690 data = 0xffb80d20; 691 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); 692 } 693 694 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 695 u32 usec_reg; 696 /* 5311 has different tx/rx latency masks 697 * from 5211, since we deal 5311 the same 698 * as 5211 when setting initvals, shift 699 * values here to their proper locations */ 700 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211); 701 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 | 702 AR5K_USEC_32 | 703 AR5K_USEC_TX_LATENCY_5211 | 704 AR5K_REG_SM(29, 705 AR5K_USEC_RX_LATENCY_5210)), 706 AR5K_USEC_5211); 707 /* Clear QCU/DCU clock gating register */ 708 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); 709 /* Set DAC/ADC delays */ 710 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); 711 /* Enable PCU FIFO corruption ECO */ 712 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 713 AR5K_DIAG_SW_ECO_ENABLE); 714 } 715 } 716 717 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, 718 struct ieee80211_channel *channel, u8 *ant, u8 ee_mode) 719 { 720 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 721 s16 cck_ofdm_pwr_delta; 722 723 /* Adjust power delta for channel 14 */ 724 if (channel->center_freq == 2484) 725 cck_ofdm_pwr_delta = 726 ((ee->ee_cck_ofdm_power_delta - 727 ee->ee_scaled_cck_delta) * 2) / 10; 728 else 729 cck_ofdm_pwr_delta = 730 (ee->ee_cck_ofdm_power_delta * 2) / 10; 731 732 /* Set CCK to OFDM power delta on tx power 733 * adjustment register */ 734 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 735 if (channel->hw_value == CHANNEL_G) 736 ath5k_hw_reg_write(ah, 737 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1), 738 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) | 739 AR5K_REG_SM((cck_ofdm_pwr_delta * -1), 740 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX), 741 AR5K_PHY_TX_PWR_ADJ); 742 else 743 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ); 744 } else { 745 /* For older revs we scale power on sw during tx power 746 * setup */ 747 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta; 748 ah->ah_txpower.txp_cck_ofdm_gainf_delta = 749 ee->ee_cck_ofdm_gain_delta; 750 } 751 752 /* Set antenna idle switch table */ 753 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 754 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 755 (ah->ah_ant_ctl[ee_mode][0] | 756 AR5K_PHY_ANT_CTL_TXRX_EN)); 757 758 /* Set antenna switch tables */ 759 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]], 760 AR5K_PHY_ANT_SWITCH_TABLE_0); 761 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]], 762 AR5K_PHY_ANT_SWITCH_TABLE_1); 763 764 /* Noise floor threshold */ 765 ath5k_hw_reg_write(ah, 766 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), 767 AR5K_PHY_NFTHRES); 768 769 if ((channel->hw_value & CHANNEL_TURBO) && 770 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) { 771 /* Switch settling time (Turbo) */ 772 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 773 AR5K_PHY_SETTLING_SWITCH, 774 ee->ee_switch_settling_turbo[ee_mode]); 775 776 /* Tx/Rx attenuation (Turbo) */ 777 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 778 AR5K_PHY_GAIN_TXRX_ATTEN, 779 ee->ee_atn_tx_rx_turbo[ee_mode]); 780 781 /* ADC/PGA desired size (Turbo) */ 782 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 783 AR5K_PHY_DESIRED_SIZE_ADC, 784 ee->ee_adc_desired_size_turbo[ee_mode]); 785 786 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 787 AR5K_PHY_DESIRED_SIZE_PGA, 788 ee->ee_pga_desired_size_turbo[ee_mode]); 789 790 /* Tx/Rx margin (Turbo) */ 791 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 792 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 793 ee->ee_margin_tx_rx_turbo[ee_mode]); 794 795 } else { 796 /* Switch settling time */ 797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 798 AR5K_PHY_SETTLING_SWITCH, 799 ee->ee_switch_settling[ee_mode]); 800 801 /* Tx/Rx attenuation */ 802 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 803 AR5K_PHY_GAIN_TXRX_ATTEN, 804 ee->ee_atn_tx_rx[ee_mode]); 805 806 /* ADC/PGA desired size */ 807 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 808 AR5K_PHY_DESIRED_SIZE_ADC, 809 ee->ee_adc_desired_size[ee_mode]); 810 811 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 812 AR5K_PHY_DESIRED_SIZE_PGA, 813 ee->ee_pga_desired_size[ee_mode]); 814 815 /* Tx/Rx margin */ 816 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) 817 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 818 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 819 ee->ee_margin_tx_rx[ee_mode]); 820 } 821 822 /* XPA delays */ 823 ath5k_hw_reg_write(ah, 824 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 825 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 826 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 827 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4); 828 829 /* XLNA delay */ 830 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3, 831 AR5K_PHY_RF_CTL3_TXE2XLNA_ON, 832 ee->ee_tx_end2xlna_enable[ee_mode]); 833 834 /* Thresh64 (ANI) */ 835 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF, 836 AR5K_PHY_NF_THRESH62, 837 ee->ee_thr_62[ee_mode]); 838 839 840 /* False detect backoff for channels 841 * that have spur noise. Write the new 842 * cyclic power RSSI threshold. */ 843 if (ath5k_hw_chan_has_spur_noise(ah, channel)) 844 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 845 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 846 AR5K_INIT_CYCRSSI_THR1 + 847 ee->ee_false_detect[ee_mode]); 848 else 849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 850 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 851 AR5K_INIT_CYCRSSI_THR1); 852 853 /* I/Q correction 854 * TODO: Per channel i/q infos ? */ 855 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 856 AR5K_PHY_IQ_CORR_ENABLE | 857 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | 858 ee->ee_q_cal[ee_mode]); 859 860 /* Heavy clipping -disable for now */ 861 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) 862 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); 863 864 return; 865 } 866 867 /* 868 * Main reset function 869 */ 870 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 871 struct ieee80211_channel *channel, bool change_channel) 872 { 873 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo; 874 u32 phy_tst1; 875 u8 mode, freq, ee_mode, ant[2]; 876 int i, ret; 877 878 ATH5K_TRACE(ah->ah_sc); 879 880 s_ant = 0; 881 ee_mode = 0; 882 staid1_flags = 0; 883 tsf_up = 0; 884 tsf_lo = 0; 885 freq = 0; 886 mode = 0; 887 888 /* 889 * Save some registers before a reset 890 */ 891 /*DCU/Antenna selection not available on 5210*/ 892 if (ah->ah_version != AR5K_AR5210) { 893 894 switch (channel->hw_value & CHANNEL_MODES) { 895 case CHANNEL_A: 896 mode = AR5K_MODE_11A; 897 freq = AR5K_INI_RFGAIN_5GHZ; 898 ee_mode = AR5K_EEPROM_MODE_11A; 899 break; 900 case CHANNEL_G: 901 mode = AR5K_MODE_11G; 902 freq = AR5K_INI_RFGAIN_2GHZ; 903 ee_mode = AR5K_EEPROM_MODE_11G; 904 break; 905 case CHANNEL_B: 906 mode = AR5K_MODE_11B; 907 freq = AR5K_INI_RFGAIN_2GHZ; 908 ee_mode = AR5K_EEPROM_MODE_11B; 909 break; 910 case CHANNEL_T: 911 mode = AR5K_MODE_11A_TURBO; 912 freq = AR5K_INI_RFGAIN_5GHZ; 913 ee_mode = AR5K_EEPROM_MODE_11A; 914 break; 915 case CHANNEL_TG: 916 if (ah->ah_version == AR5K_AR5211) { 917 ATH5K_ERR(ah->ah_sc, 918 "TurboG mode not available on 5211"); 919 return -EINVAL; 920 } 921 mode = AR5K_MODE_11G_TURBO; 922 freq = AR5K_INI_RFGAIN_2GHZ; 923 ee_mode = AR5K_EEPROM_MODE_11G; 924 break; 925 case CHANNEL_XR: 926 if (ah->ah_version == AR5K_AR5211) { 927 ATH5K_ERR(ah->ah_sc, 928 "XR mode not available on 5211"); 929 return -EINVAL; 930 } 931 mode = AR5K_MODE_XR; 932 freq = AR5K_INI_RFGAIN_5GHZ; 933 ee_mode = AR5K_EEPROM_MODE_11A; 934 break; 935 default: 936 ATH5K_ERR(ah->ah_sc, 937 "invalid channel: %d\n", channel->center_freq); 938 return -EINVAL; 939 } 940 941 if (change_channel) { 942 /* 943 * Save frame sequence count 944 * For revs. after Oahu, only save 945 * seq num for DCU 0 (Global seq num) 946 */ 947 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 948 949 for (i = 0; i < 10; i++) 950 s_seq[i] = ath5k_hw_reg_read(ah, 951 AR5K_QUEUE_DCU_SEQNUM(i)); 952 953 } else { 954 s_seq[0] = ath5k_hw_reg_read(ah, 955 AR5K_QUEUE_DCU_SEQNUM(0)); 956 } 957 958 /* TSF accelerates on AR5211 durring reset 959 * As a workaround save it here and restore 960 * it later so that it's back in time after 961 * reset. This way it'll get re-synced on the 962 * next beacon without breaking ad-hoc. 963 * 964 * On AR5212 TSF is almost preserved across a 965 * reset so it stays back in time anyway and 966 * we don't have to save/restore it. 967 * 968 * XXX: Since this breaks power saving we have 969 * to disable power saving until we receive the 970 * next beacon, so we can resync beacon timers */ 971 if (ah->ah_version == AR5K_AR5211) { 972 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 973 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 974 } 975 } 976 977 /* Save default antenna */ 978 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 979 980 if (ah->ah_version == AR5K_AR5212) { 981 /* Restore normal 32/40MHz clock operation 982 * to avoid register access delay on certain 983 * PHY registers */ 984 ath5k_hw_set_sleep_clock(ah, false); 985 986 /* Since we are going to write rf buffer 987 * check if we have any pending gain_F 988 * optimization settings */ 989 if (change_channel && ah->ah_rf_banks != NULL) 990 ath5k_hw_gainf_calibrate(ah); 991 } 992 } 993 994 /*GPIOs*/ 995 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & 996 AR5K_PCICFG_LEDSTATE; 997 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 998 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 999 1000 /* AR5K_STA_ID1 flags, only preserve antenna 1001 * settings and ack/cts rate mode */ 1002 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 1003 (AR5K_STA_ID1_DEFAULT_ANTENNA | 1004 AR5K_STA_ID1_DESC_ANTENNA | 1005 AR5K_STA_ID1_RTS_DEF_ANTENNA | 1006 AR5K_STA_ID1_ACKCTS_6MB | 1007 AR5K_STA_ID1_BASE_RATE_11B | 1008 AR5K_STA_ID1_SELFGEN_DEF_ANT); 1009 1010 /* Wakeup the device */ 1011 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false); 1012 if (ret) 1013 return ret; 1014 1015 /* 1016 * Initialize operating mode 1017 */ 1018 ah->ah_op_mode = op_mode; 1019 1020 /* PHY access enable */ 1021 if (ah->ah_mac_srev >= AR5K_SREV_AR5211) 1022 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1023 else 1024 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, 1025 AR5K_PHY(0)); 1026 1027 /* Write initial settings */ 1028 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 1029 if (ret) 1030 return ret; 1031 1032 /* 1033 * 5211/5212 Specific 1034 */ 1035 if (ah->ah_version != AR5K_AR5210) { 1036 1037 /* 1038 * Write initial RF gain settings 1039 * This should work for both 5111/5112 1040 */ 1041 ret = ath5k_hw_rfgain_init(ah, freq); 1042 if (ret) 1043 return ret; 1044 1045 mdelay(1); 1046 1047 /* 1048 * Tweak initval settings for revised 1049 * chipsets and add some more config 1050 * bits 1051 */ 1052 ath5k_hw_tweak_initval_settings(ah, channel); 1053 1054 /* 1055 * Set TX power 1056 */ 1057 ret = ath5k_hw_txpower(ah, channel, ee_mode, 1058 ah->ah_txpower.txp_max_pwr / 2); 1059 if (ret) 1060 return ret; 1061 1062 /* Write rate duration table only on AR5212 and if 1063 * virtual interface has already been brought up 1064 * XXX: rethink this after new mode changes to 1065 * mac80211 are integrated */ 1066 if (ah->ah_version == AR5K_AR5212 && 1067 ah->ah_sc->vif != NULL) 1068 ath5k_hw_write_rate_duration(ah, mode); 1069 1070 /* 1071 * Write RF buffer 1072 */ 1073 ret = ath5k_hw_rfregs_init(ah, channel, mode); 1074 if (ret) 1075 return ret; 1076 1077 1078 /* Write OFDM timings on 5212*/ 1079 if (ah->ah_version == AR5K_AR5212 && 1080 channel->hw_value & CHANNEL_OFDM) { 1081 struct ath5k_eeprom_info *ee = 1082 &ah->ah_capabilities.cap_eeprom; 1083 1084 ret = ath5k_hw_write_ofdm_timings(ah, channel); 1085 if (ret) 1086 return ret; 1087 1088 /* Note: According to docs we can have a newer 1089 * EEPROM on old hardware, so we need to verify 1090 * that our hardware is new enough to have spur 1091 * mitigation registers (delta phase etc) */ 1092 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 || 1093 (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1094 ee->ee_version >= AR5K_EEPROM_VERSION_5_3)) 1095 ath5k_hw_set_spur_mitigation_filter(ah, 1096 channel); 1097 } 1098 1099 /*Enable/disable 802.11b mode on 5111 1100 (enable 2111 frequency converter + CCK)*/ 1101 if (ah->ah_radio == AR5K_RF5111) { 1102 if (mode == AR5K_MODE_11B) 1103 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 1104 AR5K_TXCFG_B_MODE); 1105 else 1106 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 1107 AR5K_TXCFG_B_MODE); 1108 } 1109 1110 /* 1111 * In case a fixed antenna was set as default 1112 * use the same switch table twice. 1113 */ 1114 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1115 ant[0] = ant[1] = AR5K_ANT_SWTABLE_A; 1116 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1117 ant[0] = ant[1] = AR5K_ANT_SWTABLE_B; 1118 else { 1119 ant[0] = AR5K_ANT_SWTABLE_A; 1120 ant[1] = AR5K_ANT_SWTABLE_B; 1121 } 1122 1123 /* Commit values from EEPROM */ 1124 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode); 1125 1126 } else { 1127 /* 1128 * For 5210 we do all initialization using 1129 * initvals, so we don't have to modify 1130 * any settings (5210 also only supports 1131 * a/aturbo modes) 1132 */ 1133 mdelay(1); 1134 /* Disable phy and wait */ 1135 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1136 mdelay(1); 1137 } 1138 1139 /* 1140 * Restore saved values 1141 */ 1142 1143 /*DCU/Antenna selection not available on 5210*/ 1144 if (ah->ah_version != AR5K_AR5210) { 1145 1146 if (change_channel) { 1147 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 1148 for (i = 0; i < 10; i++) 1149 ath5k_hw_reg_write(ah, s_seq[i], 1150 AR5K_QUEUE_DCU_SEQNUM(i)); 1151 } else { 1152 ath5k_hw_reg_write(ah, s_seq[0], 1153 AR5K_QUEUE_DCU_SEQNUM(0)); 1154 } 1155 1156 1157 if (ah->ah_version == AR5K_AR5211) { 1158 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32); 1159 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); 1160 } 1161 } 1162 1163 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); 1164 } 1165 1166 /* Ledstate */ 1167 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); 1168 1169 /* Gpio settings */ 1170 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); 1171 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); 1172 1173 /* Restore sta_id flags and preserve our mac address*/ 1174 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id), 1175 AR5K_STA_ID0); 1176 ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id), 1177 AR5K_STA_ID1); 1178 1179 1180 /* 1181 * Configure PCU 1182 */ 1183 1184 /* Restore bssid and bssid mask */ 1185 /* XXX: add ah->aid once mac80211 gives this to us */ 1186 ath5k_hw_set_associd(ah, ah->ah_bssid, 0); 1187 1188 /* Set PCU config */ 1189 ath5k_hw_set_opmode(ah); 1190 1191 /* Clear any pending interrupts 1192 * PISR/SISR Not available on 5210 */ 1193 if (ah->ah_version != AR5K_AR5210) 1194 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); 1195 1196 /* Set RSSI/BRSSI thresholds 1197 * 1198 * Note: If we decide to set this value 1199 * dynamicaly, have in mind that when AR5K_RSSI_THR 1200 * register is read it might return 0x40 if we haven't 1201 * wrote anything to it plus BMISS RSSI threshold is zeroed. 1202 * So doing a save/restore procedure here isn't the right 1203 * choice. Instead store it on ath5k_hw */ 1204 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 1205 AR5K_TUNE_BMISS_THRES << 1206 AR5K_RSSI_THR_BMISS_S), 1207 AR5K_RSSI_THR); 1208 1209 /* MIC QoS support */ 1210 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 1211 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 1212 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 1213 } 1214 1215 /* QoS NOACK Policy */ 1216 if (ah->ah_version == AR5K_AR5212) { 1217 ath5k_hw_reg_write(ah, 1218 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 1219 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 1220 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 1221 AR5K_QOS_NOACK); 1222 } 1223 1224 1225 /* 1226 * Configure PHY 1227 */ 1228 1229 /* Set channel on PHY */ 1230 ret = ath5k_hw_channel(ah, channel); 1231 if (ret) 1232 return ret; 1233 1234 /* 1235 * Enable the PHY and wait until completion 1236 * This includes BaseBand and Synthesizer 1237 * activation. 1238 */ 1239 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1240 1241 /* 1242 * On 5211+ read activation -> rx delay 1243 * and use it. 1244 * 1245 * TODO: Half/quarter rate support 1246 */ 1247 if (ah->ah_version != AR5K_AR5210) { 1248 u32 delay; 1249 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 1250 AR5K_PHY_RX_DELAY_M; 1251 delay = (channel->hw_value & CHANNEL_CCK) ? 1252 ((delay << 2) / 22) : (delay / 10); 1253 1254 udelay(100 + (2 * delay)); 1255 } else { 1256 mdelay(1); 1257 } 1258 1259 /* 1260 * Perform ADC test to see if baseband is ready 1261 * Set tx hold and check adc test register 1262 */ 1263 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 1264 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 1265 for (i = 0; i <= 20; i++) { 1266 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 1267 break; 1268 udelay(200); 1269 } 1270 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 1271 1272 /* 1273 * Start automatic gain control calibration 1274 * 1275 * During AGC calibration RX path is re-routed to 1276 * a power detector so we don't receive anything. 1277 * 1278 * This method is used to calibrate some static offsets 1279 * used together with on-the fly I/Q calibration (the 1280 * one performed via ath5k_hw_phy_calibrate), that doesn't 1281 * interrupt rx path. 1282 * 1283 * While rx path is re-routed to the power detector we also 1284 * start a noise floor calibration, to measure the 1285 * card's noise floor (the noise we measure when we are not 1286 * transmiting or receiving anything). 1287 * 1288 * If we are in a noisy environment AGC calibration may time 1289 * out and/or noise floor calibration might timeout. 1290 */ 1291 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1292 AR5K_PHY_AGCCTL_CAL); 1293 1294 /* At the same time start I/Q calibration for QAM constellation 1295 * -no need for CCK- */ 1296 ah->ah_calibration = false; 1297 if (!(mode == AR5K_MODE_11B)) { 1298 ah->ah_calibration = true; 1299 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1300 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1301 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1302 AR5K_PHY_IQ_RUN); 1303 } 1304 1305 /* Wait for gain calibration to finish (we check for I/Q calibration 1306 * during ath5k_phy_calibrate) */ 1307 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1308 AR5K_PHY_AGCCTL_CAL, 0, false)) { 1309 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 1310 channel->center_freq); 1311 } 1312 1313 /* 1314 * If we run NF calibration before AGC, it always times out. 1315 * Binary HAL starts NF and AGC calibration at the same time 1316 * and only waits for AGC to finish. Also if AGC or NF cal. 1317 * times out, reset doesn't fail on binary HAL. I believe 1318 * that's wrong because since rx path is routed to a detector, 1319 * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211 1320 * enables noise floor calibration after offset calibration and if noise 1321 * floor calibration fails, reset fails. I believe that's 1322 * a better approach, we just need to find a polling interval 1323 * that suits best, even if reset continues we need to make 1324 * sure that rx path is ready. 1325 */ 1326 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1327 1328 /* Restore antenna mode */ 1329 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 1330 1331 /* 1332 * Configure QCUs/DCUs 1333 */ 1334 1335 /* TODO: HW Compression support for data queues */ 1336 /* TODO: Burst prefetch for data queues */ 1337 1338 /* 1339 * Reset queues and start beacon timers at the end of the reset routine 1340 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping 1341 * Note: If we want we can assign multiple qcus on one dcu. 1342 */ 1343 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) { 1344 ret = ath5k_hw_reset_tx_queue(ah, i); 1345 if (ret) { 1346 ATH5K_ERR(ah->ah_sc, 1347 "failed to reset TX queue #%d\n", i); 1348 return ret; 1349 } 1350 } 1351 1352 1353 /* 1354 * Configure DMA/Interrupts 1355 */ 1356 1357 /* 1358 * Set Rx/Tx DMA Configuration 1359 * 1360 * Set standard DMA size (128). Note that 1361 * a DMA size of 512 causes rx overruns and tx errors 1362 * on pci-e cards (tested on 5424 but since rx overruns 1363 * also occur on 5416/5418 with madwifi we set 128 1364 * for all PCI-E cards to be safe). 1365 * 1366 * XXX: need to check 5210 for this 1367 * TODO: Check out tx triger level, it's always 64 on dumps but I 1368 * guess we can tweak it and see how it goes ;-) 1369 */ 1370 if (ah->ah_version != AR5K_AR5210) { 1371 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 1372 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); 1373 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, 1374 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); 1375 } 1376 1377 /* Pre-enable interrupts on 5211/5212*/ 1378 if (ah->ah_version != AR5K_AR5210) 1379 ath5k_hw_set_imr(ah, ah->ah_imr); 1380 1381 /* Enable 32KHz clock function for AR5212+ chips 1382 * Set clocks to 32KHz operation and use an 1383 * external 32KHz crystal when sleeping if one 1384 * exists */ 1385 if (ah->ah_version == AR5K_AR5212) 1386 ath5k_hw_set_sleep_clock(ah, true); 1387 1388 /* 1389 * Disable beacons and reset the register 1390 */ 1391 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | 1392 AR5K_BEACON_RESET_TSF); 1393 1394 return 0; 1395 } 1396 1397 #undef _ATH5K_RESET 1398