1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 */ 21 22 #define _ATH5K_RESET 23 24 /*****************************\ 25 Reset functions and helpers 26 \*****************************/ 27 28 #include <asm/unaligned.h> 29 30 #include <linux/pci.h> /* To determine if a card is pci-e */ 31 #include <linux/log2.h> 32 #include "ath5k.h" 33 #include "reg.h" 34 #include "base.h" 35 #include "debug.h" 36 37 /** 38 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 39 * 40 * @ah: the &struct ath5k_hw 41 * @channel: the currently set channel upon reset 42 * 43 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 44 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset(). 45 * 46 * Since delta slope is floating point we split it on its exponent and 47 * mantissa and provide these values on hw. 48 * 49 * For more infos i think this patent is related 50 * http://www.freepatentsonline.com/7184495.html 51 */ 52 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 53 struct ieee80211_channel *channel) 54 { 55 /* Get exponent and mantissa and set it */ 56 u32 coef_scaled, coef_exp, coef_man, 57 ds_coef_exp, ds_coef_man, clock; 58 59 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 60 !(channel->hw_value & CHANNEL_OFDM)); 61 62 /* Get coefficient 63 * ALGO: coef = (5 * clock * carrier_freq) / 2) 64 * we scale coef by shifting clock value by 24 for 65 * better precision since we use integers */ 66 /* TODO: Half/quarter rate */ 67 clock = ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO); 68 69 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 70 71 /* Get exponent 72 * ALGO: coef_exp = 14 - highest set bit position */ 73 coef_exp = ilog2(coef_scaled); 74 75 /* Doesn't make sense if it's zero*/ 76 if (!coef_scaled || !coef_exp) 77 return -EINVAL; 78 79 /* Note: we've shifted coef_scaled by 24 */ 80 coef_exp = 14 - (coef_exp - 24); 81 82 83 /* Get mantissa (significant digits) 84 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 85 coef_man = coef_scaled + 86 (1 << (24 - coef_exp - 1)); 87 88 /* Calculate delta slope coefficient exponent 89 * and mantissa (remove scaling) and set them on hw */ 90 ds_coef_man = coef_man >> (24 - coef_exp); 91 ds_coef_exp = coef_exp - 16; 92 93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 94 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 95 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 96 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 97 98 return 0; 99 } 100 101 102 /* 103 * index into rates for control rates, we can set it up like this because 104 * this is only used for AR5212 and we know it supports G mode 105 */ 106 static const unsigned int control_rates[] = 107 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }; 108 109 /** 110 * ath5k_hw_write_rate_duration - fill rate code to duration table 111 * 112 * @ah: the &struct ath5k_hw 113 * @mode: one of enum ath5k_driver_mode 114 * 115 * Write the rate code to duration table upon hw reset. This is a helper for 116 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on 117 * the hardware, based on current mode, for each rate. The rates which are 118 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 119 * different rate code so we write their value twice (one for long preample 120 * and one for short). 121 * 122 * Note: Band doesn't matter here, if we set the values for OFDM it works 123 * on both a and g modes. So all we have to do is set values for all g rates 124 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/ 125 * quarter rate mode, we need to use another set of bitrates (that's why we 126 * need the mode parameter) but we don't handle these proprietary modes yet. 127 */ 128 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, 129 unsigned int mode) 130 { 131 struct ath5k_softc *sc = ah->ah_sc; 132 struct ieee80211_rate *rate; 133 unsigned int i; 134 135 /* Write rate duration table */ 136 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) { 137 u32 reg; 138 u16 tx_time; 139 140 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]]; 141 142 /* Set ACK timeout */ 143 reg = AR5K_RATE_DUR(rate->hw_value); 144 145 /* An ACK frame consists of 10 bytes. If you add the FCS, 146 * which ieee80211_generic_frame_duration() adds, 147 * its 14 bytes. Note we use the control rate and not the 148 * actual rate for this rate. See mac80211 tx.c 149 * ieee80211_duration() for a brief description of 150 * what rate we should choose to TX ACKs. */ 151 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw, 152 sc->vif, 10, rate)); 153 154 ath5k_hw_reg_write(ah, tx_time, reg); 155 156 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 157 continue; 158 159 /* 160 * We're not distinguishing short preamble here, 161 * This is true, all we'll get is a longer value here 162 * which is not necessarilly bad. We could use 163 * export ieee80211_frame_duration() but that needs to be 164 * fixed first to be properly used by mac802111 drivers: 165 * 166 * - remove erp stuff and let the routine figure ofdm 167 * erp rates 168 * - remove passing argument ieee80211_local as 169 * drivers don't have access to it 170 * - move drivers using ieee80211_generic_frame_duration() 171 * to this 172 */ 173 ath5k_hw_reg_write(ah, tx_time, 174 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 175 } 176 } 177 178 /* 179 * Reset chipset 180 */ 181 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) 182 { 183 int ret; 184 u32 mask = val ? val : ~0U; 185 186 ATH5K_TRACE(ah->ah_sc); 187 188 /* Read-and-clear RX Descriptor Pointer*/ 189 ath5k_hw_reg_read(ah, AR5K_RXDP); 190 191 /* 192 * Reset the device and wait until success 193 */ 194 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); 195 196 /* Wait at least 128 PCI clocks */ 197 udelay(15); 198 199 if (ah->ah_version == AR5K_AR5210) { 200 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 201 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 202 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 203 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 204 } else { 205 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 206 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 207 } 208 209 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); 210 211 /* 212 * Reset configuration register (for hw byte-swap). Note that this 213 * is only set for big endian. We do the necessary magic in 214 * AR5K_INIT_CFG. 215 */ 216 if ((val & AR5K_RESET_CTL_PCU) == 0) 217 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); 218 219 return ret; 220 } 221 222 /* 223 * Sleep control 224 */ 225 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 226 bool set_chip, u16 sleep_duration) 227 { 228 unsigned int i; 229 u32 staid, data; 230 231 ATH5K_TRACE(ah->ah_sc); 232 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); 233 234 switch (mode) { 235 case AR5K_PM_AUTO: 236 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; 237 /* fallthrough */ 238 case AR5K_PM_NETWORK_SLEEP: 239 if (set_chip) 240 ath5k_hw_reg_write(ah, 241 AR5K_SLEEP_CTL_SLE_ALLOW | 242 sleep_duration, 243 AR5K_SLEEP_CTL); 244 245 staid |= AR5K_STA_ID1_PWR_SV; 246 break; 247 248 case AR5K_PM_FULL_SLEEP: 249 if (set_chip) 250 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, 251 AR5K_SLEEP_CTL); 252 253 staid |= AR5K_STA_ID1_PWR_SV; 254 break; 255 256 case AR5K_PM_AWAKE: 257 258 staid &= ~AR5K_STA_ID1_PWR_SV; 259 260 if (!set_chip) 261 goto commit; 262 263 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL); 264 265 /* If card is down we 'll get 0xffff... so we 266 * need to clean this up before we write the register 267 */ 268 if (data & 0xffc00000) 269 data = 0; 270 else 271 /* Preserve sleep duration etc */ 272 data = data & ~AR5K_SLEEP_CTL_SLE; 273 274 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 275 AR5K_SLEEP_CTL); 276 udelay(15); 277 278 for (i = 200; i > 0; i--) { 279 /* Check if the chip did wake up */ 280 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & 281 AR5K_PCICFG_SPWR_DN) == 0) 282 break; 283 284 /* Wait a bit and retry */ 285 udelay(50); 286 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 287 AR5K_SLEEP_CTL); 288 } 289 290 /* Fail if the chip didn't wake up */ 291 if (i == 0) 292 return -EIO; 293 294 break; 295 296 default: 297 return -EINVAL; 298 } 299 300 commit: 301 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); 302 303 return 0; 304 } 305 306 /* 307 * Put device on hold 308 * 309 * Put MAC and Baseband on warm reset and 310 * keep that state (don't clean sleep control 311 * register). After this MAC and Baseband are 312 * disabled and a full reset is needed to come 313 * back. This way we save as much power as possible 314 * without puting the card on full sleep. 315 */ 316 int ath5k_hw_on_hold(struct ath5k_hw *ah) 317 { 318 struct pci_dev *pdev = ah->ah_sc->pdev; 319 u32 bus_flags; 320 int ret; 321 322 /* Make sure device is awake */ 323 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 324 if (ret) { 325 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 326 return ret; 327 } 328 329 /* 330 * Put chipset on warm reset... 331 * 332 * Note: puting PCI core on warm reset on PCI-E cards 333 * results card to hang and always return 0xffff... so 334 * we ingore that flag for PCI-E cards. On PCI cards 335 * this flag gets cleared after 64 PCI clocks. 336 */ 337 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 338 339 if (ah->ah_version == AR5K_AR5210) { 340 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 341 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 342 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 343 mdelay(2); 344 } else { 345 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 346 AR5K_RESET_CTL_BASEBAND | bus_flags); 347 } 348 349 if (ret) { 350 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n"); 351 return -EIO; 352 } 353 354 /* ...wakeup again!*/ 355 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 356 if (ret) { 357 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n"); 358 return ret; 359 } 360 361 return ret; 362 } 363 364 /* 365 * Bring up MAC + PHY Chips and program PLL 366 * TODO: Half/Quarter rate support 367 */ 368 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 369 { 370 struct pci_dev *pdev = ah->ah_sc->pdev; 371 u32 turbo, mode, clock, bus_flags; 372 int ret; 373 374 turbo = 0; 375 mode = 0; 376 clock = 0; 377 378 ATH5K_TRACE(ah->ah_sc); 379 380 /* Wakeup the device */ 381 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 382 if (ret) { 383 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 384 return ret; 385 } 386 387 /* 388 * Put chipset on warm reset... 389 * 390 * Note: puting PCI core on warm reset on PCI-E cards 391 * results card to hang and always return 0xffff... so 392 * we ingore that flag for PCI-E cards. On PCI cards 393 * this flag gets cleared after 64 PCI clocks. 394 */ 395 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 396 397 if (ah->ah_version == AR5K_AR5210) { 398 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 399 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 400 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 401 mdelay(2); 402 } else { 403 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 404 AR5K_RESET_CTL_BASEBAND | bus_flags); 405 } 406 407 if (ret) { 408 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n"); 409 return -EIO; 410 } 411 412 /* ...wakeup again!...*/ 413 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 414 if (ret) { 415 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n"); 416 return ret; 417 } 418 419 /* ...clear reset control register and pull device out of 420 * warm reset */ 421 if (ath5k_hw_nic_reset(ah, 0)) { 422 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); 423 return -EIO; 424 } 425 426 /* On initialization skip PLL programming since we don't have 427 * a channel / mode set yet */ 428 if (initial) 429 return 0; 430 431 if (ah->ah_version != AR5K_AR5210) { 432 /* 433 * Get channel mode flags 434 */ 435 436 if (ah->ah_radio >= AR5K_RF5112) { 437 mode = AR5K_PHY_MODE_RAD_RF5112; 438 clock = AR5K_PHY_PLL_RF5112; 439 } else { 440 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ 441 clock = AR5K_PHY_PLL_RF5111; /*Zero*/ 442 } 443 444 if (flags & CHANNEL_2GHZ) { 445 mode |= AR5K_PHY_MODE_FREQ_2GHZ; 446 clock |= AR5K_PHY_PLL_44MHZ; 447 448 if (flags & CHANNEL_CCK) { 449 mode |= AR5K_PHY_MODE_MOD_CCK; 450 } else if (flags & CHANNEL_OFDM) { 451 /* XXX Dynamic OFDM/CCK is not supported by the 452 * AR5211 so we set MOD_OFDM for plain g (no 453 * CCK headers) operation. We need to test 454 * this, 5211 might support ofdm-only g after 455 * all, there are also initial register values 456 * in the code for g mode (see initvals.c). */ 457 if (ah->ah_version == AR5K_AR5211) 458 mode |= AR5K_PHY_MODE_MOD_OFDM; 459 else 460 mode |= AR5K_PHY_MODE_MOD_DYN; 461 } else { 462 ATH5K_ERR(ah->ah_sc, 463 "invalid radio modulation mode\n"); 464 return -EINVAL; 465 } 466 } else if (flags & CHANNEL_5GHZ) { 467 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 468 469 if (ah->ah_radio == AR5K_RF5413) 470 clock = AR5K_PHY_PLL_40MHZ_5413; 471 else 472 clock |= AR5K_PHY_PLL_40MHZ; 473 474 if (flags & CHANNEL_OFDM) 475 mode |= AR5K_PHY_MODE_MOD_OFDM; 476 else { 477 ATH5K_ERR(ah->ah_sc, 478 "invalid radio modulation mode\n"); 479 return -EINVAL; 480 } 481 } else { 482 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n"); 483 return -EINVAL; 484 } 485 486 if (flags & CHANNEL_TURBO) 487 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 488 } else { /* Reset the device */ 489 490 /* ...enable Atheros turbo mode if requested */ 491 if (flags & CHANNEL_TURBO) 492 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 493 AR5K_PHY_TURBO); 494 } 495 496 if (ah->ah_version != AR5K_AR5210) { 497 498 /* ...update PLL if needed */ 499 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) { 500 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); 501 udelay(300); 502 } 503 504 /* ...set the PHY operating mode */ 505 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); 506 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); 507 } 508 509 return 0; 510 } 511 512 /* 513 * If there is an external 32KHz crystal available, use it 514 * as ref. clock instead of 32/40MHz clock and baseband clocks 515 * to save power during sleep or restore normal 32/40MHz 516 * operation. 517 * 518 * XXX: When operating on 32KHz certain PHY registers (27 - 31, 519 * 123 - 127) require delay on access. 520 */ 521 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) 522 { 523 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 524 u32 scal, spending, usec32; 525 526 /* Only set 32KHz settings if we have an external 527 * 32KHz crystal present */ 528 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) || 529 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) && 530 enable) { 531 532 /* 1 usec/cycle */ 533 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1); 534 /* Set up tsf increment on each cycle */ 535 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61); 536 537 /* Set baseband sleep control registers 538 * and sleep control rate */ 539 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 540 541 if ((ah->ah_radio == AR5K_RF5112) || 542 (ah->ah_radio == AR5K_RF5413) || 543 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 544 spending = 0x14; 545 else 546 spending = 0x18; 547 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 548 549 if ((ah->ah_radio == AR5K_RF5112) || 550 (ah->ah_radio == AR5K_RF5413) || 551 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 552 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); 553 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL); 554 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK); 555 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY); 556 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 557 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02); 558 } else { 559 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); 560 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL); 561 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK); 562 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY); 563 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 564 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03); 565 } 566 567 /* Enable sleep clock operation */ 568 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, 569 AR5K_PCICFG_SLEEP_CLOCK_EN); 570 571 } else { 572 573 /* Disable sleep clock operation and 574 * restore default parameters */ 575 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, 576 AR5K_PCICFG_SLEEP_CLOCK_EN); 577 578 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 579 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0); 580 581 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 582 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); 583 584 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 585 scal = AR5K_PHY_SCAL_32MHZ_2417; 586 else if (ee->ee_is_hb63) 587 scal = AR5K_PHY_SCAL_32MHZ_HB63; 588 else 589 scal = AR5K_PHY_SCAL_32MHZ; 590 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 591 592 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); 593 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); 594 595 if ((ah->ah_radio == AR5K_RF5112) || 596 (ah->ah_radio == AR5K_RF5413) || 597 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 598 spending = 0x14; 599 else 600 spending = 0x18; 601 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 602 603 if ((ah->ah_radio == AR5K_RF5112) || 604 (ah->ah_radio == AR5K_RF5413)) 605 usec32 = 39; 606 else 607 usec32 = 31; 608 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32); 609 610 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); 611 } 612 return; 613 } 614 615 /* TODO: Half/Quarter rate */ 616 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, 617 struct ieee80211_channel *channel) 618 { 619 if (ah->ah_version == AR5K_AR5212 && 620 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 621 622 /* Setup ADC control */ 623 ath5k_hw_reg_write(ah, 624 (AR5K_REG_SM(2, 625 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) | 626 AR5K_REG_SM(2, 627 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) | 628 AR5K_PHY_ADC_CTL_PWD_DAC_OFF | 629 AR5K_PHY_ADC_CTL_PWD_ADC_OFF), 630 AR5K_PHY_ADC_CTL); 631 632 633 634 /* Disable barker RSSI threshold */ 635 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 636 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR); 637 638 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 639 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2); 640 641 /* Set the mute mask */ 642 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); 643 } 644 645 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */ 646 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B) 647 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH); 648 649 /* Enable DCU double buffering */ 650 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B) 651 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 652 AR5K_TXCFG_DCU_DBL_BUF_DIS); 653 654 /* Set DAC/ADC delays */ 655 if (ah->ah_version == AR5K_AR5212) { 656 u32 scal; 657 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 658 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 659 scal = AR5K_PHY_SCAL_32MHZ_2417; 660 else if (ee->ee_is_hb63) 661 scal = AR5K_PHY_SCAL_32MHZ_HB63; 662 else 663 scal = AR5K_PHY_SCAL_32MHZ; 664 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 665 } 666 667 /* Set fast ADC */ 668 if ((ah->ah_radio == AR5K_RF5413) || 669 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 670 u32 fast_adc = true; 671 672 if (channel->center_freq == 2462 || 673 channel->center_freq == 2467) 674 fast_adc = 0; 675 676 /* Only update if needed */ 677 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc) 678 ath5k_hw_reg_write(ah, fast_adc, 679 AR5K_PHY_FAST_ADC); 680 } 681 682 /* Fix for first revision of the RF5112 RF chipset */ 683 if (ah->ah_radio == AR5K_RF5112 && 684 ah->ah_radio_5ghz_revision < 685 AR5K_SREV_RAD_5112A) { 686 u32 data; 687 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, 688 AR5K_PHY_CCKTXCTL); 689 if (channel->hw_value & CHANNEL_5GHZ) 690 data = 0xffb81020; 691 else 692 data = 0xffb80d20; 693 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); 694 } 695 696 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 697 u32 usec_reg; 698 /* 5311 has different tx/rx latency masks 699 * from 5211, since we deal 5311 the same 700 * as 5211 when setting initvals, shift 701 * values here to their proper locations */ 702 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211); 703 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 | 704 AR5K_USEC_32 | 705 AR5K_USEC_TX_LATENCY_5211 | 706 AR5K_REG_SM(29, 707 AR5K_USEC_RX_LATENCY_5210)), 708 AR5K_USEC_5211); 709 /* Clear QCU/DCU clock gating register */ 710 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); 711 /* Set DAC/ADC delays */ 712 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); 713 /* Enable PCU FIFO corruption ECO */ 714 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 715 AR5K_DIAG_SW_ECO_ENABLE); 716 } 717 } 718 719 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, 720 struct ieee80211_channel *channel, u8 *ant, u8 ee_mode) 721 { 722 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 723 s16 cck_ofdm_pwr_delta; 724 725 /* Adjust power delta for channel 14 */ 726 if (channel->center_freq == 2484) 727 cck_ofdm_pwr_delta = 728 ((ee->ee_cck_ofdm_power_delta - 729 ee->ee_scaled_cck_delta) * 2) / 10; 730 else 731 cck_ofdm_pwr_delta = 732 (ee->ee_cck_ofdm_power_delta * 2) / 10; 733 734 /* Set CCK to OFDM power delta on tx power 735 * adjustment register */ 736 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 737 if (channel->hw_value == CHANNEL_G) 738 ath5k_hw_reg_write(ah, 739 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1), 740 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) | 741 AR5K_REG_SM((cck_ofdm_pwr_delta * -1), 742 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX), 743 AR5K_PHY_TX_PWR_ADJ); 744 else 745 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ); 746 } else { 747 /* For older revs we scale power on sw during tx power 748 * setup */ 749 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta; 750 ah->ah_txpower.txp_cck_ofdm_gainf_delta = 751 ee->ee_cck_ofdm_gain_delta; 752 } 753 754 /* Set antenna idle switch table */ 755 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 756 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 757 (ah->ah_ant_ctl[ee_mode][0] | 758 AR5K_PHY_ANT_CTL_TXRX_EN)); 759 760 /* Set antenna switch tables */ 761 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]], 762 AR5K_PHY_ANT_SWITCH_TABLE_0); 763 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]], 764 AR5K_PHY_ANT_SWITCH_TABLE_1); 765 766 /* Noise floor threshold */ 767 ath5k_hw_reg_write(ah, 768 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), 769 AR5K_PHY_NFTHRES); 770 771 if ((channel->hw_value & CHANNEL_TURBO) && 772 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) { 773 /* Switch settling time (Turbo) */ 774 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 775 AR5K_PHY_SETTLING_SWITCH, 776 ee->ee_switch_settling_turbo[ee_mode]); 777 778 /* Tx/Rx attenuation (Turbo) */ 779 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 780 AR5K_PHY_GAIN_TXRX_ATTEN, 781 ee->ee_atn_tx_rx_turbo[ee_mode]); 782 783 /* ADC/PGA desired size (Turbo) */ 784 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 785 AR5K_PHY_DESIRED_SIZE_ADC, 786 ee->ee_adc_desired_size_turbo[ee_mode]); 787 788 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 789 AR5K_PHY_DESIRED_SIZE_PGA, 790 ee->ee_pga_desired_size_turbo[ee_mode]); 791 792 /* Tx/Rx margin (Turbo) */ 793 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 794 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 795 ee->ee_margin_tx_rx_turbo[ee_mode]); 796 797 } else { 798 /* Switch settling time */ 799 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 800 AR5K_PHY_SETTLING_SWITCH, 801 ee->ee_switch_settling[ee_mode]); 802 803 /* Tx/Rx attenuation */ 804 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 805 AR5K_PHY_GAIN_TXRX_ATTEN, 806 ee->ee_atn_tx_rx[ee_mode]); 807 808 /* ADC/PGA desired size */ 809 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 810 AR5K_PHY_DESIRED_SIZE_ADC, 811 ee->ee_adc_desired_size[ee_mode]); 812 813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 814 AR5K_PHY_DESIRED_SIZE_PGA, 815 ee->ee_pga_desired_size[ee_mode]); 816 817 /* Tx/Rx margin */ 818 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) 819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 820 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 821 ee->ee_margin_tx_rx[ee_mode]); 822 } 823 824 /* XPA delays */ 825 ath5k_hw_reg_write(ah, 826 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 827 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 828 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 829 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4); 830 831 /* XLNA delay */ 832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3, 833 AR5K_PHY_RF_CTL3_TXE2XLNA_ON, 834 ee->ee_tx_end2xlna_enable[ee_mode]); 835 836 /* Thresh64 (ANI) */ 837 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF, 838 AR5K_PHY_NF_THRESH62, 839 ee->ee_thr_62[ee_mode]); 840 841 842 /* False detect backoff for channels 843 * that have spur noise. Write the new 844 * cyclic power RSSI threshold. */ 845 if (ath5k_hw_chan_has_spur_noise(ah, channel)) 846 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 847 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 848 AR5K_INIT_CYCRSSI_THR1 + 849 ee->ee_false_detect[ee_mode]); 850 else 851 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 852 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 853 AR5K_INIT_CYCRSSI_THR1); 854 855 /* I/Q correction 856 * TODO: Per channel i/q infos ? */ 857 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 858 AR5K_PHY_IQ_CORR_ENABLE | 859 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | 860 ee->ee_q_cal[ee_mode]); 861 862 /* Heavy clipping -disable for now */ 863 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) 864 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); 865 866 return; 867 } 868 869 /* 870 * Main reset function 871 */ 872 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 873 struct ieee80211_channel *channel, bool change_channel) 874 { 875 struct ath_common *common = ath5k_hw_common(ah); 876 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo; 877 u32 phy_tst1; 878 u8 mode, freq, ee_mode, ant[2]; 879 int i, ret; 880 881 ATH5K_TRACE(ah->ah_sc); 882 883 s_ant = 0; 884 ee_mode = 0; 885 staid1_flags = 0; 886 tsf_up = 0; 887 tsf_lo = 0; 888 freq = 0; 889 mode = 0; 890 891 /* 892 * Save some registers before a reset 893 */ 894 /*DCU/Antenna selection not available on 5210*/ 895 if (ah->ah_version != AR5K_AR5210) { 896 897 switch (channel->hw_value & CHANNEL_MODES) { 898 case CHANNEL_A: 899 mode = AR5K_MODE_11A; 900 freq = AR5K_INI_RFGAIN_5GHZ; 901 ee_mode = AR5K_EEPROM_MODE_11A; 902 break; 903 case CHANNEL_G: 904 mode = AR5K_MODE_11G; 905 freq = AR5K_INI_RFGAIN_2GHZ; 906 ee_mode = AR5K_EEPROM_MODE_11G; 907 break; 908 case CHANNEL_B: 909 mode = AR5K_MODE_11B; 910 freq = AR5K_INI_RFGAIN_2GHZ; 911 ee_mode = AR5K_EEPROM_MODE_11B; 912 break; 913 case CHANNEL_T: 914 mode = AR5K_MODE_11A_TURBO; 915 freq = AR5K_INI_RFGAIN_5GHZ; 916 ee_mode = AR5K_EEPROM_MODE_11A; 917 break; 918 case CHANNEL_TG: 919 if (ah->ah_version == AR5K_AR5211) { 920 ATH5K_ERR(ah->ah_sc, 921 "TurboG mode not available on 5211"); 922 return -EINVAL; 923 } 924 mode = AR5K_MODE_11G_TURBO; 925 freq = AR5K_INI_RFGAIN_2GHZ; 926 ee_mode = AR5K_EEPROM_MODE_11G; 927 break; 928 case CHANNEL_XR: 929 if (ah->ah_version == AR5K_AR5211) { 930 ATH5K_ERR(ah->ah_sc, 931 "XR mode not available on 5211"); 932 return -EINVAL; 933 } 934 mode = AR5K_MODE_XR; 935 freq = AR5K_INI_RFGAIN_5GHZ; 936 ee_mode = AR5K_EEPROM_MODE_11A; 937 break; 938 default: 939 ATH5K_ERR(ah->ah_sc, 940 "invalid channel: %d\n", channel->center_freq); 941 return -EINVAL; 942 } 943 944 if (change_channel) { 945 /* 946 * Save frame sequence count 947 * For revs. after Oahu, only save 948 * seq num for DCU 0 (Global seq num) 949 */ 950 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 951 952 for (i = 0; i < 10; i++) 953 s_seq[i] = ath5k_hw_reg_read(ah, 954 AR5K_QUEUE_DCU_SEQNUM(i)); 955 956 } else { 957 s_seq[0] = ath5k_hw_reg_read(ah, 958 AR5K_QUEUE_DCU_SEQNUM(0)); 959 } 960 961 /* TSF accelerates on AR5211 durring reset 962 * As a workaround save it here and restore 963 * it later so that it's back in time after 964 * reset. This way it'll get re-synced on the 965 * next beacon without breaking ad-hoc. 966 * 967 * On AR5212 TSF is almost preserved across a 968 * reset so it stays back in time anyway and 969 * we don't have to save/restore it. 970 * 971 * XXX: Since this breaks power saving we have 972 * to disable power saving until we receive the 973 * next beacon, so we can resync beacon timers */ 974 if (ah->ah_version == AR5K_AR5211) { 975 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 976 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 977 } 978 } 979 980 /* Save default antenna */ 981 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 982 983 if (ah->ah_version == AR5K_AR5212) { 984 /* Restore normal 32/40MHz clock operation 985 * to avoid register access delay on certain 986 * PHY registers */ 987 ath5k_hw_set_sleep_clock(ah, false); 988 989 /* Since we are going to write rf buffer 990 * check if we have any pending gain_F 991 * optimization settings */ 992 if (change_channel && ah->ah_rf_banks != NULL) 993 ath5k_hw_gainf_calibrate(ah); 994 } 995 } 996 997 /*GPIOs*/ 998 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & 999 AR5K_PCICFG_LEDSTATE; 1000 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 1001 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 1002 1003 /* AR5K_STA_ID1 flags, only preserve antenna 1004 * settings and ack/cts rate mode */ 1005 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 1006 (AR5K_STA_ID1_DEFAULT_ANTENNA | 1007 AR5K_STA_ID1_DESC_ANTENNA | 1008 AR5K_STA_ID1_RTS_DEF_ANTENNA | 1009 AR5K_STA_ID1_ACKCTS_6MB | 1010 AR5K_STA_ID1_BASE_RATE_11B | 1011 AR5K_STA_ID1_SELFGEN_DEF_ANT); 1012 1013 /* Wakeup the device */ 1014 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false); 1015 if (ret) 1016 return ret; 1017 1018 /* 1019 * Initialize operating mode 1020 */ 1021 ah->ah_op_mode = op_mode; 1022 1023 /* PHY access enable */ 1024 if (ah->ah_mac_srev >= AR5K_SREV_AR5211) 1025 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1026 else 1027 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, 1028 AR5K_PHY(0)); 1029 1030 /* Write initial settings */ 1031 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 1032 if (ret) 1033 return ret; 1034 1035 /* 1036 * 5211/5212 Specific 1037 */ 1038 if (ah->ah_version != AR5K_AR5210) { 1039 1040 /* 1041 * Write initial RF gain settings 1042 * This should work for both 5111/5112 1043 */ 1044 ret = ath5k_hw_rfgain_init(ah, freq); 1045 if (ret) 1046 return ret; 1047 1048 mdelay(1); 1049 1050 /* 1051 * Tweak initval settings for revised 1052 * chipsets and add some more config 1053 * bits 1054 */ 1055 ath5k_hw_tweak_initval_settings(ah, channel); 1056 1057 /* 1058 * Set TX power 1059 */ 1060 ret = ath5k_hw_txpower(ah, channel, ee_mode, 1061 ah->ah_txpower.txp_max_pwr / 2); 1062 if (ret) 1063 return ret; 1064 1065 /* Write rate duration table only on AR5212 and if 1066 * virtual interface has already been brought up 1067 * XXX: rethink this after new mode changes to 1068 * mac80211 are integrated */ 1069 if (ah->ah_version == AR5K_AR5212 && 1070 ah->ah_sc->vif != NULL) 1071 ath5k_hw_write_rate_duration(ah, mode); 1072 1073 /* 1074 * Write RF buffer 1075 */ 1076 ret = ath5k_hw_rfregs_init(ah, channel, mode); 1077 if (ret) 1078 return ret; 1079 1080 1081 /* Write OFDM timings on 5212*/ 1082 if (ah->ah_version == AR5K_AR5212 && 1083 channel->hw_value & CHANNEL_OFDM) { 1084 struct ath5k_eeprom_info *ee = 1085 &ah->ah_capabilities.cap_eeprom; 1086 1087 ret = ath5k_hw_write_ofdm_timings(ah, channel); 1088 if (ret) 1089 return ret; 1090 1091 /* Note: According to docs we can have a newer 1092 * EEPROM on old hardware, so we need to verify 1093 * that our hardware is new enough to have spur 1094 * mitigation registers (delta phase etc) */ 1095 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 || 1096 (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1097 ee->ee_version >= AR5K_EEPROM_VERSION_5_3)) 1098 ath5k_hw_set_spur_mitigation_filter(ah, 1099 channel); 1100 } 1101 1102 /*Enable/disable 802.11b mode on 5111 1103 (enable 2111 frequency converter + CCK)*/ 1104 if (ah->ah_radio == AR5K_RF5111) { 1105 if (mode == AR5K_MODE_11B) 1106 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 1107 AR5K_TXCFG_B_MODE); 1108 else 1109 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 1110 AR5K_TXCFG_B_MODE); 1111 } 1112 1113 /* 1114 * In case a fixed antenna was set as default 1115 * use the same switch table twice. 1116 */ 1117 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1118 ant[0] = ant[1] = AR5K_ANT_SWTABLE_A; 1119 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1120 ant[0] = ant[1] = AR5K_ANT_SWTABLE_B; 1121 else { 1122 ant[0] = AR5K_ANT_SWTABLE_A; 1123 ant[1] = AR5K_ANT_SWTABLE_B; 1124 } 1125 1126 /* Commit values from EEPROM */ 1127 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode); 1128 1129 } else { 1130 /* 1131 * For 5210 we do all initialization using 1132 * initvals, so we don't have to modify 1133 * any settings (5210 also only supports 1134 * a/aturbo modes) 1135 */ 1136 mdelay(1); 1137 /* Disable phy and wait */ 1138 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1139 mdelay(1); 1140 } 1141 1142 /* 1143 * Restore saved values 1144 */ 1145 1146 /*DCU/Antenna selection not available on 5210*/ 1147 if (ah->ah_version != AR5K_AR5210) { 1148 1149 if (change_channel) { 1150 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 1151 for (i = 0; i < 10; i++) 1152 ath5k_hw_reg_write(ah, s_seq[i], 1153 AR5K_QUEUE_DCU_SEQNUM(i)); 1154 } else { 1155 ath5k_hw_reg_write(ah, s_seq[0], 1156 AR5K_QUEUE_DCU_SEQNUM(0)); 1157 } 1158 1159 1160 if (ah->ah_version == AR5K_AR5211) { 1161 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32); 1162 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); 1163 } 1164 } 1165 1166 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); 1167 } 1168 1169 /* Ledstate */ 1170 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); 1171 1172 /* Gpio settings */ 1173 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); 1174 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); 1175 1176 /* Restore sta_id flags and preserve our mac address*/ 1177 ath5k_hw_reg_write(ah, 1178 get_unaligned_le32(common->macaddr), 1179 AR5K_STA_ID0); 1180 ath5k_hw_reg_write(ah, 1181 staid1_flags | get_unaligned_le16(common->macaddr + 4), 1182 AR5K_STA_ID1); 1183 1184 1185 /* 1186 * Configure PCU 1187 */ 1188 1189 /* Restore bssid and bssid mask */ 1190 ath5k_hw_set_associd(ah); 1191 1192 /* Set PCU config */ 1193 ath5k_hw_set_opmode(ah); 1194 1195 /* Clear any pending interrupts 1196 * PISR/SISR Not available on 5210 */ 1197 if (ah->ah_version != AR5K_AR5210) 1198 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); 1199 1200 /* Set RSSI/BRSSI thresholds 1201 * 1202 * Note: If we decide to set this value 1203 * dynamicaly, have in mind that when AR5K_RSSI_THR 1204 * register is read it might return 0x40 if we haven't 1205 * wrote anything to it plus BMISS RSSI threshold is zeroed. 1206 * So doing a save/restore procedure here isn't the right 1207 * choice. Instead store it on ath5k_hw */ 1208 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 1209 AR5K_TUNE_BMISS_THRES << 1210 AR5K_RSSI_THR_BMISS_S), 1211 AR5K_RSSI_THR); 1212 1213 /* MIC QoS support */ 1214 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 1215 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 1216 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 1217 } 1218 1219 /* QoS NOACK Policy */ 1220 if (ah->ah_version == AR5K_AR5212) { 1221 ath5k_hw_reg_write(ah, 1222 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 1223 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 1224 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 1225 AR5K_QOS_NOACK); 1226 } 1227 1228 1229 /* 1230 * Configure PHY 1231 */ 1232 1233 /* Set channel on PHY */ 1234 ret = ath5k_hw_channel(ah, channel); 1235 if (ret) 1236 return ret; 1237 1238 /* 1239 * Enable the PHY and wait until completion 1240 * This includes BaseBand and Synthesizer 1241 * activation. 1242 */ 1243 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1244 1245 /* 1246 * On 5211+ read activation -> rx delay 1247 * and use it. 1248 * 1249 * TODO: Half/quarter rate support 1250 */ 1251 if (ah->ah_version != AR5K_AR5210) { 1252 u32 delay; 1253 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 1254 AR5K_PHY_RX_DELAY_M; 1255 delay = (channel->hw_value & CHANNEL_CCK) ? 1256 ((delay << 2) / 22) : (delay / 10); 1257 1258 udelay(100 + (2 * delay)); 1259 } else { 1260 mdelay(1); 1261 } 1262 1263 /* 1264 * Perform ADC test to see if baseband is ready 1265 * Set tx hold and check adc test register 1266 */ 1267 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 1268 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 1269 for (i = 0; i <= 20; i++) { 1270 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 1271 break; 1272 udelay(200); 1273 } 1274 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 1275 1276 /* 1277 * Start automatic gain control calibration 1278 * 1279 * During AGC calibration RX path is re-routed to 1280 * a power detector so we don't receive anything. 1281 * 1282 * This method is used to calibrate some static offsets 1283 * used together with on-the fly I/Q calibration (the 1284 * one performed via ath5k_hw_phy_calibrate), that doesn't 1285 * interrupt rx path. 1286 * 1287 * While rx path is re-routed to the power detector we also 1288 * start a noise floor calibration, to measure the 1289 * card's noise floor (the noise we measure when we are not 1290 * transmiting or receiving anything). 1291 * 1292 * If we are in a noisy environment AGC calibration may time 1293 * out and/or noise floor calibration might timeout. 1294 */ 1295 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1296 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 1297 1298 /* At the same time start I/Q calibration for QAM constellation 1299 * -no need for CCK- */ 1300 ah->ah_calibration = false; 1301 if (!(mode == AR5K_MODE_11B)) { 1302 ah->ah_calibration = true; 1303 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1304 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1305 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1306 AR5K_PHY_IQ_RUN); 1307 } 1308 1309 /* Wait for gain calibration to finish (we check for I/Q calibration 1310 * during ath5k_phy_calibrate) */ 1311 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1312 AR5K_PHY_AGCCTL_CAL, 0, false)) { 1313 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 1314 channel->center_freq); 1315 } 1316 1317 /* Restore antenna mode */ 1318 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 1319 1320 /* 1321 * Configure QCUs/DCUs 1322 */ 1323 1324 /* TODO: HW Compression support for data queues */ 1325 /* TODO: Burst prefetch for data queues */ 1326 1327 /* 1328 * Reset queues and start beacon timers at the end of the reset routine 1329 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping 1330 * Note: If we want we can assign multiple qcus on one dcu. 1331 */ 1332 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) { 1333 ret = ath5k_hw_reset_tx_queue(ah, i); 1334 if (ret) { 1335 ATH5K_ERR(ah->ah_sc, 1336 "failed to reset TX queue #%d\n", i); 1337 return ret; 1338 } 1339 } 1340 1341 1342 /* 1343 * Configure DMA/Interrupts 1344 */ 1345 1346 /* 1347 * Set Rx/Tx DMA Configuration 1348 * 1349 * Set standard DMA size (128). Note that 1350 * a DMA size of 512 causes rx overruns and tx errors 1351 * on pci-e cards (tested on 5424 but since rx overruns 1352 * also occur on 5416/5418 with madwifi we set 128 1353 * for all PCI-E cards to be safe). 1354 * 1355 * XXX: need to check 5210 for this 1356 * TODO: Check out tx triger level, it's always 64 on dumps but I 1357 * guess we can tweak it and see how it goes ;-) 1358 */ 1359 if (ah->ah_version != AR5K_AR5210) { 1360 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 1361 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); 1362 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, 1363 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); 1364 } 1365 1366 /* Pre-enable interrupts on 5211/5212*/ 1367 if (ah->ah_version != AR5K_AR5210) 1368 ath5k_hw_set_imr(ah, ah->ah_imr); 1369 1370 /* Enable 32KHz clock function for AR5212+ chips 1371 * Set clocks to 32KHz operation and use an 1372 * external 32KHz crystal when sleeping if one 1373 * exists */ 1374 if (ah->ah_version == AR5K_AR5212) 1375 ath5k_hw_set_sleep_clock(ah, true); 1376 1377 /* 1378 * Disable beacons and reset the register 1379 */ 1380 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | 1381 AR5K_BEACON_RESET_TSF); 1382 1383 return 0; 1384 } 1385 1386 #undef _ATH5K_RESET 1387