1 /* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 26 #include "ath5k.h" 27 #include "reg.h" 28 #include "base.h" 29 #include "rfbuffer.h" 30 #include "rfgain.h" 31 32 33 /******************\ 34 * Helper functions * 35 \******************/ 36 37 /* 38 * Get the PHY Chip revision 39 */ 40 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 41 { 42 unsigned int i; 43 u32 srev; 44 u16 ret; 45 46 /* 47 * Set the radio chip access register 48 */ 49 switch (chan) { 50 case CHANNEL_2GHZ: 51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 52 break; 53 case CHANNEL_5GHZ: 54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 55 break; 56 default: 57 return 0; 58 } 59 60 mdelay(2); 61 62 /* ...wait until PHY is ready and read the selected radio revision */ 63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 64 65 for (i = 0; i < 8; i++) 66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 67 68 if (ah->ah_version == AR5K_AR5210) { 69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 71 } else { 72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 74 ((srev & 0x0f) << 4), 8); 75 } 76 77 /* Reset to the 5GHz mode */ 78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 79 80 return ret; 81 } 82 83 /* 84 * Check if a channel is supported 85 */ 86 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 87 { 88 /* Check if the channel is in our supported range */ 89 if (flags & CHANNEL_2GHZ) { 90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 92 return true; 93 } else if (flags & CHANNEL_5GHZ) 94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 96 return true; 97 98 return false; 99 } 100 101 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 102 struct ieee80211_channel *channel) 103 { 104 u8 refclk_freq; 105 106 if ((ah->ah_radio == AR5K_RF5112) || 107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 109 refclk_freq = 40; 110 else 111 refclk_freq = 32; 112 113 if ((channel->center_freq % refclk_freq != 0) && 114 ((channel->center_freq % refclk_freq < 10) || 115 (channel->center_freq % refclk_freq > 22))) 116 return true; 117 else 118 return false; 119 } 120 121 /* 122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 123 */ 124 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 125 const struct ath5k_rf_reg *rf_regs, 126 u32 val, u8 reg_id, bool set) 127 { 128 const struct ath5k_rf_reg *rfreg = NULL; 129 u8 offset, bank, num_bits, col, position; 130 u16 entry; 131 u32 mask, data, last_bit, bits_shifted, first_bit; 132 u32 *rfb; 133 s32 bits_left; 134 int i; 135 136 data = 0; 137 rfb = ah->ah_rf_banks; 138 139 for (i = 0; i < ah->ah_rf_regs_count; i++) { 140 if (rf_regs[i].index == reg_id) { 141 rfreg = &rf_regs[i]; 142 break; 143 } 144 } 145 146 if (rfb == NULL || rfreg == NULL) { 147 ATH5K_PRINTF("Rf register not found!\n"); 148 /* should not happen */ 149 return 0; 150 } 151 152 bank = rfreg->bank; 153 num_bits = rfreg->field.len; 154 first_bit = rfreg->field.pos; 155 col = rfreg->field.col; 156 157 /* first_bit is an offset from bank's 158 * start. Since we have all banks on 159 * the same array, we use this offset 160 * to mark each bank's start */ 161 offset = ah->ah_offset[bank]; 162 163 /* Boundary check */ 164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 165 ATH5K_PRINTF("invalid values at offset %u\n", offset); 166 return 0; 167 } 168 169 entry = ((first_bit - 1) / 8) + offset; 170 position = (first_bit - 1) % 8; 171 172 if (set) 173 data = ath5k_hw_bitswap(val, num_bits); 174 175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 176 position = 0, entry++) { 177 178 last_bit = (position + bits_left > 8) ? 8 : 179 position + bits_left; 180 181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 182 (col * 8); 183 184 if (set) { 185 rfb[entry] &= ~mask; 186 rfb[entry] |= ((data << position) << (col * 8)) & mask; 187 data >>= (8 - position); 188 } else { 189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 190 << bits_shifted; 191 bits_shifted += last_bit - position; 192 } 193 194 bits_left -= 8 - position; 195 } 196 197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 198 199 return data; 200 } 201 202 /** 203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 204 * 205 * @ah: the &struct ath5k_hw 206 * @channel: the currently set channel upon reset 207 * 208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 210 * 211 * Since delta slope is floating point we split it on its exponent and 212 * mantissa and provide these values on hw. 213 * 214 * For more infos i think this patent is related 215 * http://www.freepatentsonline.com/7184495.html 216 */ 217 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 218 struct ieee80211_channel *channel) 219 { 220 /* Get exponent and mantissa and set it */ 221 u32 coef_scaled, coef_exp, coef_man, 222 ds_coef_exp, ds_coef_man, clock; 223 224 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 225 !(channel->hw_value & CHANNEL_OFDM)); 226 227 /* Get coefficient 228 * ALGO: coef = (5 * clock / carrier_freq) / 2 229 * we scale coef by shifting clock value by 24 for 230 * better precision since we use integers */ 231 switch (ah->ah_bwmode) { 232 case AR5K_BWMODE_40MHZ: 233 clock = 40 * 2; 234 break; 235 case AR5K_BWMODE_10MHZ: 236 clock = 40 / 2; 237 break; 238 case AR5K_BWMODE_5MHZ: 239 clock = 40 / 4; 240 break; 241 default: 242 clock = 40; 243 break; 244 } 245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 246 247 /* Get exponent 248 * ALGO: coef_exp = 14 - highest set bit position */ 249 coef_exp = ilog2(coef_scaled); 250 251 /* Doesn't make sense if it's zero*/ 252 if (!coef_scaled || !coef_exp) 253 return -EINVAL; 254 255 /* Note: we've shifted coef_scaled by 24 */ 256 coef_exp = 14 - (coef_exp - 24); 257 258 259 /* Get mantissa (significant digits) 260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 261 coef_man = coef_scaled + 262 (1 << (24 - coef_exp - 1)); 263 264 /* Calculate delta slope coefficient exponent 265 * and mantissa (remove scaling) and set them on hw */ 266 ds_coef_man = coef_man >> (24 - coef_exp); 267 ds_coef_exp = coef_exp - 16; 268 269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 273 274 return 0; 275 } 276 277 int ath5k_hw_phy_disable(struct ath5k_hw *ah) 278 { 279 /*Just a try M.F.*/ 280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 281 282 return 0; 283 } 284 285 /* 286 * Wait for synth to settle 287 */ 288 static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 289 struct ieee80211_channel *channel) 290 { 291 /* 292 * On 5211+ read activation -> rx delay 293 * and use it (100ns steps). 294 */ 295 if (ah->ah_version != AR5K_AR5210) { 296 u32 delay; 297 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 298 AR5K_PHY_RX_DELAY_M; 299 delay = (channel->hw_value & CHANNEL_CCK) ? 300 ((delay << 2) / 22) : (delay / 10); 301 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 302 delay = delay << 1; 303 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 304 delay = delay << 2; 305 /* XXX: /2 on turbo ? Let's be safe 306 * for now */ 307 udelay(100 + delay); 308 } else { 309 mdelay(1); 310 } 311 } 312 313 314 /**********************\ 315 * RF Gain optimization * 316 \**********************/ 317 318 /* 319 * This code is used to optimize RF gain on different environments 320 * (temperature mostly) based on feedback from a power detector. 321 * 322 * It's only used on RF5111 and RF5112, later RF chips seem to have 323 * auto adjustment on hw -notice they have a much smaller BANK 7 and 324 * no gain optimization ladder-. 325 * 326 * For more infos check out this patent doc 327 * http://www.freepatentsonline.com/7400691.html 328 * 329 * This paper describes power drops as seen on the receiver due to 330 * probe packets 331 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 332 * %20of%20Power%20Control.pdf 333 * 334 * And this is the MadWiFi bug entry related to the above 335 * http://madwifi-project.org/ticket/1659 336 * with various measurements and diagrams 337 * 338 * TODO: Deal with power drops due to probes by setting an apropriate 339 * tx power on the probe packets ! Make this part of the calibration process. 340 */ 341 342 /* Initialize ah_gain durring attach */ 343 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 344 { 345 /* Initialize the gain optimization values */ 346 switch (ah->ah_radio) { 347 case AR5K_RF5111: 348 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 349 ah->ah_gain.g_low = 20; 350 ah->ah_gain.g_high = 35; 351 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 352 break; 353 case AR5K_RF5112: 354 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 355 ah->ah_gain.g_low = 20; 356 ah->ah_gain.g_high = 85; 357 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 358 break; 359 default: 360 return -EINVAL; 361 } 362 363 return 0; 364 } 365 366 /* Schedule a gain probe check on the next transmited packet. 367 * That means our next packet is going to be sent with lower 368 * tx power and a Peak to Average Power Detector (PAPD) will try 369 * to measure the gain. 370 * 371 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 372 * just after we enable the probe so that we don't mess with 373 * standard traffic ? Maybe it's time to use sw interrupts and 374 * a probe tasklet !!! 375 */ 376 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 377 { 378 379 /* Skip if gain calibration is inactive or 380 * we already handle a probe request */ 381 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 382 return; 383 384 /* Send the packet with 2dB below max power as 385 * patent doc suggest */ 386 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 387 AR5K_PHY_PAPD_PROBE_TXPOWER) | 388 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 389 390 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 391 392 } 393 394 /* Calculate gain_F measurement correction 395 * based on the current step for RF5112 rev. 2 */ 396 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 397 { 398 u32 mix, step; 399 u32 *rf; 400 const struct ath5k_gain_opt *go; 401 const struct ath5k_gain_opt_step *g_step; 402 const struct ath5k_rf_reg *rf_regs; 403 404 /* Only RF5112 Rev. 2 supports it */ 405 if ((ah->ah_radio != AR5K_RF5112) || 406 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 407 return 0; 408 409 go = &rfgain_opt_5112; 410 rf_regs = rf_regs_5112a; 411 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 412 413 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 414 415 if (ah->ah_rf_banks == NULL) 416 return 0; 417 418 rf = ah->ah_rf_banks; 419 ah->ah_gain.g_f_corr = 0; 420 421 /* No VGA (Variable Gain Amplifier) override, skip */ 422 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 423 return 0; 424 425 /* Mix gain stepping */ 426 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 427 428 /* Mix gain override */ 429 mix = g_step->gos_param[0]; 430 431 switch (mix) { 432 case 3: 433 ah->ah_gain.g_f_corr = step * 2; 434 break; 435 case 2: 436 ah->ah_gain.g_f_corr = (step - 5) * 2; 437 break; 438 case 1: 439 ah->ah_gain.g_f_corr = step; 440 break; 441 default: 442 ah->ah_gain.g_f_corr = 0; 443 break; 444 } 445 446 return ah->ah_gain.g_f_corr; 447 } 448 449 /* Check if current gain_F measurement is in the range of our 450 * power detector windows. If we get a measurement outside range 451 * we know it's not accurate (detectors can't measure anything outside 452 * their detection window) so we must ignore it */ 453 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 454 { 455 const struct ath5k_rf_reg *rf_regs; 456 u32 step, mix_ovr, level[4]; 457 u32 *rf; 458 459 if (ah->ah_rf_banks == NULL) 460 return false; 461 462 rf = ah->ah_rf_banks; 463 464 if (ah->ah_radio == AR5K_RF5111) { 465 466 rf_regs = rf_regs_5111; 467 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 468 469 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 470 false); 471 472 level[0] = 0; 473 level[1] = (step == 63) ? 50 : step + 4; 474 level[2] = (step != 63) ? 64 : level[0]; 475 level[3] = level[2] + 50 ; 476 477 ah->ah_gain.g_high = level[3] - 478 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 479 ah->ah_gain.g_low = level[0] + 480 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 481 } else { 482 483 rf_regs = rf_regs_5112; 484 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 485 486 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 487 false); 488 489 level[0] = level[2] = 0; 490 491 if (mix_ovr == 1) { 492 level[1] = level[3] = 83; 493 } else { 494 level[1] = level[3] = 107; 495 ah->ah_gain.g_high = 55; 496 } 497 } 498 499 return (ah->ah_gain.g_current >= level[0] && 500 ah->ah_gain.g_current <= level[1]) || 501 (ah->ah_gain.g_current >= level[2] && 502 ah->ah_gain.g_current <= level[3]); 503 } 504 505 /* Perform gain_F adjustment by choosing the right set 506 * of parameters from RF gain optimization ladder */ 507 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 508 { 509 const struct ath5k_gain_opt *go; 510 const struct ath5k_gain_opt_step *g_step; 511 int ret = 0; 512 513 switch (ah->ah_radio) { 514 case AR5K_RF5111: 515 go = &rfgain_opt_5111; 516 break; 517 case AR5K_RF5112: 518 go = &rfgain_opt_5112; 519 break; 520 default: 521 return 0; 522 } 523 524 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 525 526 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 527 528 /* Reached maximum */ 529 if (ah->ah_gain.g_step_idx == 0) 530 return -1; 531 532 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 533 ah->ah_gain.g_target >= ah->ah_gain.g_high && 534 ah->ah_gain.g_step_idx > 0; 535 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 536 ah->ah_gain.g_target -= 2 * 537 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 538 g_step->gos_gain); 539 540 ret = 1; 541 goto done; 542 } 543 544 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 545 546 /* Reached minimum */ 547 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 548 return -2; 549 550 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 551 ah->ah_gain.g_target <= ah->ah_gain.g_low && 552 ah->ah_gain.g_step_idx < go->go_steps_count-1; 553 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 554 ah->ah_gain.g_target -= 2 * 555 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 556 g_step->gos_gain); 557 558 ret = 2; 559 goto done; 560 } 561 562 done: 563 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 564 "ret %d, gain step %u, current gain %u, target gain %u\n", 565 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 566 ah->ah_gain.g_target); 567 568 return ret; 569 } 570 571 /* Main callback for thermal RF gain calibration engine 572 * Check for a new gain reading and schedule an adjustment 573 * if needed. 574 * 575 * TODO: Use sw interrupt to schedule reset if gain_F needs 576 * adjustment */ 577 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 578 { 579 u32 data, type; 580 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 581 582 if (ah->ah_rf_banks == NULL || 583 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 584 return AR5K_RFGAIN_INACTIVE; 585 586 /* No check requested, either engine is inactive 587 * or an adjustment is already requested */ 588 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 589 goto done; 590 591 /* Read the PAPD (Peak to Average Power Detector) 592 * register */ 593 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 594 595 /* No probe is scheduled, read gain_F measurement */ 596 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 597 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 598 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 599 600 /* If tx packet is CCK correct the gain_F measurement 601 * by cck ofdm gain delta */ 602 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 603 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 604 ah->ah_gain.g_current += 605 ee->ee_cck_ofdm_gain_delta; 606 else 607 ah->ah_gain.g_current += 608 AR5K_GAIN_CCK_PROBE_CORR; 609 } 610 611 /* Further correct gain_F measurement for 612 * RF5112A radios */ 613 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 614 ath5k_hw_rf_gainf_corr(ah); 615 ah->ah_gain.g_current = 616 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 617 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 618 0; 619 } 620 621 /* Check if measurement is ok and if we need 622 * to adjust gain, schedule a gain adjustment, 623 * else switch back to the acive state */ 624 if (ath5k_hw_rf_check_gainf_readback(ah) && 625 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 626 ath5k_hw_rf_gainf_adjust(ah)) { 627 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 628 } else { 629 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 630 } 631 } 632 633 done: 634 return ah->ah_gain.g_state; 635 } 636 637 /* Write initial RF gain table to set the RF sensitivity 638 * this one works on all RF chips and has nothing to do 639 * with gain_F calibration */ 640 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 641 { 642 const struct ath5k_ini_rfgain *ath5k_rfg; 643 unsigned int i, size, index; 644 645 switch (ah->ah_radio) { 646 case AR5K_RF5111: 647 ath5k_rfg = rfgain_5111; 648 size = ARRAY_SIZE(rfgain_5111); 649 break; 650 case AR5K_RF5112: 651 ath5k_rfg = rfgain_5112; 652 size = ARRAY_SIZE(rfgain_5112); 653 break; 654 case AR5K_RF2413: 655 ath5k_rfg = rfgain_2413; 656 size = ARRAY_SIZE(rfgain_2413); 657 break; 658 case AR5K_RF2316: 659 ath5k_rfg = rfgain_2316; 660 size = ARRAY_SIZE(rfgain_2316); 661 break; 662 case AR5K_RF5413: 663 ath5k_rfg = rfgain_5413; 664 size = ARRAY_SIZE(rfgain_5413); 665 break; 666 case AR5K_RF2317: 667 case AR5K_RF2425: 668 ath5k_rfg = rfgain_2425; 669 size = ARRAY_SIZE(rfgain_2425); 670 break; 671 default: 672 return -EINVAL; 673 } 674 675 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0; 676 677 for (i = 0; i < size; i++) { 678 AR5K_REG_WAIT(i); 679 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], 680 (u32)ath5k_rfg[i].rfg_register); 681 } 682 683 return 0; 684 } 685 686 687 688 /********************\ 689 * RF Registers setup * 690 \********************/ 691 692 /* 693 * Setup RF registers by writing RF buffer on hw 694 */ 695 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 696 struct ieee80211_channel *channel, unsigned int mode) 697 { 698 const struct ath5k_rf_reg *rf_regs; 699 const struct ath5k_ini_rfbuffer *ini_rfb; 700 const struct ath5k_gain_opt *go = NULL; 701 const struct ath5k_gain_opt_step *g_step; 702 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 703 u8 ee_mode = 0; 704 u32 *rfb; 705 int i, obdb = -1, bank = -1; 706 707 switch (ah->ah_radio) { 708 case AR5K_RF5111: 709 rf_regs = rf_regs_5111; 710 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 711 ini_rfb = rfb_5111; 712 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 713 go = &rfgain_opt_5111; 714 break; 715 case AR5K_RF5112: 716 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 717 rf_regs = rf_regs_5112a; 718 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 719 ini_rfb = rfb_5112a; 720 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 721 } else { 722 rf_regs = rf_regs_5112; 723 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 724 ini_rfb = rfb_5112; 725 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 726 } 727 go = &rfgain_opt_5112; 728 break; 729 case AR5K_RF2413: 730 rf_regs = rf_regs_2413; 731 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 732 ini_rfb = rfb_2413; 733 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 734 break; 735 case AR5K_RF2316: 736 rf_regs = rf_regs_2316; 737 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 738 ini_rfb = rfb_2316; 739 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 740 break; 741 case AR5K_RF5413: 742 rf_regs = rf_regs_5413; 743 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 744 ini_rfb = rfb_5413; 745 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 746 break; 747 case AR5K_RF2317: 748 rf_regs = rf_regs_2425; 749 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 750 ini_rfb = rfb_2317; 751 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 752 break; 753 case AR5K_RF2425: 754 rf_regs = rf_regs_2425; 755 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 756 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 757 ini_rfb = rfb_2425; 758 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 759 } else { 760 ini_rfb = rfb_2417; 761 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 762 } 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 /* If it's the first time we set RF buffer, allocate 769 * ah->ah_rf_banks based on ah->ah_rf_banks_size 770 * we set above */ 771 if (ah->ah_rf_banks == NULL) { 772 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 773 GFP_KERNEL); 774 if (ah->ah_rf_banks == NULL) { 775 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 776 return -ENOMEM; 777 } 778 } 779 780 /* Copy values to modify them */ 781 rfb = ah->ah_rf_banks; 782 783 for (i = 0; i < ah->ah_rf_banks_size; i++) { 784 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 785 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 786 return -EINVAL; 787 } 788 789 /* Bank changed, write down the offset */ 790 if (bank != ini_rfb[i].rfb_bank) { 791 bank = ini_rfb[i].rfb_bank; 792 ah->ah_offset[bank] = i; 793 } 794 795 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 796 } 797 798 /* Set Output and Driver bias current (OB/DB) */ 799 if (channel->hw_value & CHANNEL_2GHZ) { 800 801 if (channel->hw_value & CHANNEL_CCK) 802 ee_mode = AR5K_EEPROM_MODE_11B; 803 else 804 ee_mode = AR5K_EEPROM_MODE_11G; 805 806 /* For RF511X/RF211X combination we 807 * use b_OB and b_DB parameters stored 808 * in eeprom on ee->ee_ob[ee_mode][0] 809 * 810 * For all other chips we use OB/DB for 2Ghz 811 * stored in the b/g modal section just like 812 * 802.11a on ee->ee_ob[ee_mode][1] */ 813 if ((ah->ah_radio == AR5K_RF5111) || 814 (ah->ah_radio == AR5K_RF5112)) 815 obdb = 0; 816 else 817 obdb = 1; 818 819 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 820 AR5K_RF_OB_2GHZ, true); 821 822 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 823 AR5K_RF_DB_2GHZ, true); 824 825 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 826 } else if ((channel->hw_value & CHANNEL_5GHZ) || 827 (ah->ah_radio == AR5K_RF5111)) { 828 829 /* For 11a, Turbo and XR we need to choose 830 * OB/DB based on frequency range */ 831 ee_mode = AR5K_EEPROM_MODE_11A; 832 obdb = channel->center_freq >= 5725 ? 3 : 833 (channel->center_freq >= 5500 ? 2 : 834 (channel->center_freq >= 5260 ? 1 : 835 (channel->center_freq > 4000 ? 0 : -1))); 836 837 if (obdb < 0) 838 return -EINVAL; 839 840 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 841 AR5K_RF_OB_5GHZ, true); 842 843 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 844 AR5K_RF_DB_5GHZ, true); 845 } 846 847 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 848 849 /* Set turbo mode (N/A on RF5413) */ 850 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && 851 (ah->ah_radio != AR5K_RF5413)) 852 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); 853 854 /* Bank Modifications (chip-specific) */ 855 if (ah->ah_radio == AR5K_RF5111) { 856 857 /* Set gain_F settings according to current step */ 858 if (channel->hw_value & CHANNEL_OFDM) { 859 860 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 861 AR5K_PHY_FRAME_CTL_TX_CLIP, 862 g_step->gos_param[0]); 863 864 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 865 AR5K_RF_PWD_90, true); 866 867 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 868 AR5K_RF_PWD_84, true); 869 870 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 871 AR5K_RF_RFGAIN_SEL, true); 872 873 /* We programmed gain_F parameters, switch back 874 * to active state */ 875 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 876 877 } 878 879 /* Bank 6/7 setup */ 880 881 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 882 AR5K_RF_PWD_XPD, true); 883 884 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 885 AR5K_RF_XPD_GAIN, true); 886 887 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 888 AR5K_RF_GAIN_I, true); 889 890 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 891 AR5K_RF_PLO_SEL, true); 892 893 /* Tweak power detectors for half/quarter rate support */ 894 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 895 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 896 u8 wait_i; 897 898 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 899 AR5K_RF_WAIT_S, true); 900 901 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 902 0x1f : 0x10; 903 904 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 905 AR5K_RF_WAIT_I, true); 906 ath5k_hw_rfb_op(ah, rf_regs, 3, 907 AR5K_RF_MAX_TIME, true); 908 909 } 910 } 911 912 if (ah->ah_radio == AR5K_RF5112) { 913 914 /* Set gain_F settings according to current step */ 915 if (channel->hw_value & CHANNEL_OFDM) { 916 917 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 918 AR5K_RF_MIXGAIN_OVR, true); 919 920 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 921 AR5K_RF_PWD_138, true); 922 923 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 924 AR5K_RF_PWD_137, true); 925 926 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 927 AR5K_RF_PWD_136, true); 928 929 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 930 AR5K_RF_PWD_132, true); 931 932 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 933 AR5K_RF_PWD_131, true); 934 935 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 936 AR5K_RF_PWD_130, true); 937 938 /* We programmed gain_F parameters, switch back 939 * to active state */ 940 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 941 } 942 943 /* Bank 6/7 setup */ 944 945 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 946 AR5K_RF_XPD_SEL, true); 947 948 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 949 /* Rev. 1 supports only one xpd */ 950 ath5k_hw_rfb_op(ah, rf_regs, 951 ee->ee_x_gain[ee_mode], 952 AR5K_RF_XPD_GAIN, true); 953 954 } else { 955 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 956 if (ee->ee_pd_gains[ee_mode] > 1) { 957 ath5k_hw_rfb_op(ah, rf_regs, 958 pdg_curve_to_idx[0], 959 AR5K_RF_PD_GAIN_LO, true); 960 ath5k_hw_rfb_op(ah, rf_regs, 961 pdg_curve_to_idx[1], 962 AR5K_RF_PD_GAIN_HI, true); 963 } else { 964 ath5k_hw_rfb_op(ah, rf_regs, 965 pdg_curve_to_idx[0], 966 AR5K_RF_PD_GAIN_LO, true); 967 ath5k_hw_rfb_op(ah, rf_regs, 968 pdg_curve_to_idx[0], 969 AR5K_RF_PD_GAIN_HI, true); 970 } 971 972 /* Lower synth voltage on Rev 2 */ 973 ath5k_hw_rfb_op(ah, rf_regs, 2, 974 AR5K_RF_HIGH_VC_CP, true); 975 976 ath5k_hw_rfb_op(ah, rf_regs, 2, 977 AR5K_RF_MID_VC_CP, true); 978 979 ath5k_hw_rfb_op(ah, rf_regs, 2, 980 AR5K_RF_LOW_VC_CP, true); 981 982 ath5k_hw_rfb_op(ah, rf_regs, 2, 983 AR5K_RF_PUSH_UP, true); 984 985 /* Decrease power consumption on 5213+ BaseBand */ 986 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 987 ath5k_hw_rfb_op(ah, rf_regs, 1, 988 AR5K_RF_PAD2GND, true); 989 990 ath5k_hw_rfb_op(ah, rf_regs, 1, 991 AR5K_RF_XB2_LVL, true); 992 993 ath5k_hw_rfb_op(ah, rf_regs, 1, 994 AR5K_RF_XB5_LVL, true); 995 996 ath5k_hw_rfb_op(ah, rf_regs, 1, 997 AR5K_RF_PWD_167, true); 998 999 ath5k_hw_rfb_op(ah, rf_regs, 1, 1000 AR5K_RF_PWD_166, true); 1001 } 1002 } 1003 1004 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 1005 AR5K_RF_GAIN_I, true); 1006 1007 /* Tweak power detector for half/quarter rates */ 1008 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 1009 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 1010 u8 pd_delay; 1011 1012 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 1013 0xf : 0x8; 1014 1015 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 1016 AR5K_RF_PD_PERIOD_A, true); 1017 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 1018 AR5K_RF_PD_DELAY_A, true); 1019 1020 } 1021 } 1022 1023 if (ah->ah_radio == AR5K_RF5413 && 1024 channel->hw_value & CHANNEL_2GHZ) { 1025 1026 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 1027 true); 1028 1029 /* Set optimum value for early revisions (on pci-e chips) */ 1030 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1031 ah->ah_mac_srev < AR5K_SREV_AR5413) 1032 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1033 AR5K_RF_PWD_ICLOBUF_2G, true); 1034 1035 } 1036 1037 /* Write RF banks on hw */ 1038 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1039 AR5K_REG_WAIT(i); 1040 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1041 } 1042 1043 return 0; 1044 } 1045 1046 1047 /**************************\ 1048 PHY/RF channel functions 1049 \**************************/ 1050 1051 /* 1052 * Convertion needed for RF5110 1053 */ 1054 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1055 { 1056 u32 athchan; 1057 1058 /* 1059 * Convert IEEE channel/MHz to an internal channel value used 1060 * by the AR5210 chipset. This has not been verified with 1061 * newer chipsets like the AR5212A who have a completely 1062 * different RF/PHY part. 1063 */ 1064 athchan = (ath5k_hw_bitswap( 1065 (ieee80211_frequency_to_channel( 1066 channel->center_freq) - 24) / 2, 5) 1067 << 1) | (1 << 6) | 0x1; 1068 return athchan; 1069 } 1070 1071 /* 1072 * Set channel on RF5110 1073 */ 1074 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1075 struct ieee80211_channel *channel) 1076 { 1077 u32 data; 1078 1079 /* 1080 * Set the channel and wait 1081 */ 1082 data = ath5k_hw_rf5110_chan2athchan(channel); 1083 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1084 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1085 mdelay(1); 1086 1087 return 0; 1088 } 1089 1090 /* 1091 * Convertion needed for 5111 1092 */ 1093 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1094 struct ath5k_athchan_2ghz *athchan) 1095 { 1096 int channel; 1097 1098 /* Cast this value to catch negative channel numbers (>= -19) */ 1099 channel = (int)ieee; 1100 1101 /* 1102 * Map 2GHz IEEE channel to 5GHz Atheros channel 1103 */ 1104 if (channel <= 13) { 1105 athchan->a2_athchan = 115 + channel; 1106 athchan->a2_flags = 0x46; 1107 } else if (channel == 14) { 1108 athchan->a2_athchan = 124; 1109 athchan->a2_flags = 0x44; 1110 } else if (channel >= 15 && channel <= 26) { 1111 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1112 athchan->a2_flags = 0x46; 1113 } else 1114 return -EINVAL; 1115 1116 return 0; 1117 } 1118 1119 /* 1120 * Set channel on 5111 1121 */ 1122 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1123 struct ieee80211_channel *channel) 1124 { 1125 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1126 unsigned int ath5k_channel = 1127 ieee80211_frequency_to_channel(channel->center_freq); 1128 u32 data0, data1, clock; 1129 int ret; 1130 1131 /* 1132 * Set the channel on the RF5111 radio 1133 */ 1134 data0 = data1 = 0; 1135 1136 if (channel->hw_value & CHANNEL_2GHZ) { 1137 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1138 ret = ath5k_hw_rf5111_chan2athchan( 1139 ieee80211_frequency_to_channel(channel->center_freq), 1140 &ath5k_channel_2ghz); 1141 if (ret) 1142 return ret; 1143 1144 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1145 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1146 << 5) | (1 << 4); 1147 } 1148 1149 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1150 clock = 1; 1151 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1152 (clock << 1) | (1 << 10) | 1; 1153 } else { 1154 clock = 0; 1155 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1156 << 2) | (clock << 1) | (1 << 10) | 1; 1157 } 1158 1159 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1160 AR5K_RF_BUFFER); 1161 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1162 AR5K_RF_BUFFER_CONTROL_3); 1163 1164 return 0; 1165 } 1166 1167 /* 1168 * Set channel on 5112 and newer 1169 */ 1170 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1171 struct ieee80211_channel *channel) 1172 { 1173 u32 data, data0, data1, data2; 1174 u16 c; 1175 1176 data = data0 = data1 = data2 = 0; 1177 c = channel->center_freq; 1178 1179 if (c < 4800) { 1180 if (!((c - 2224) % 5)) { 1181 data0 = ((2 * (c - 704)) - 3040) / 10; 1182 data1 = 1; 1183 } else if (!((c - 2192) % 5)) { 1184 data0 = ((2 * (c - 672)) - 3040) / 10; 1185 data1 = 0; 1186 } else 1187 return -EINVAL; 1188 1189 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1190 } else if ((c % 5) != 2 || c > 5435) { 1191 if (!(c % 20) && c >= 5120) { 1192 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1193 data2 = ath5k_hw_bitswap(3, 2); 1194 } else if (!(c % 10)) { 1195 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1196 data2 = ath5k_hw_bitswap(2, 2); 1197 } else if (!(c % 5)) { 1198 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1199 data2 = ath5k_hw_bitswap(1, 2); 1200 } else 1201 return -EINVAL; 1202 } else { 1203 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1204 data2 = ath5k_hw_bitswap(0, 2); 1205 } 1206 1207 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1208 1209 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1210 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1211 1212 return 0; 1213 } 1214 1215 /* 1216 * Set the channel on the RF2425 1217 */ 1218 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1219 struct ieee80211_channel *channel) 1220 { 1221 u32 data, data0, data2; 1222 u16 c; 1223 1224 data = data0 = data2 = 0; 1225 c = channel->center_freq; 1226 1227 if (c < 4800) { 1228 data0 = ath5k_hw_bitswap((c - 2272), 8); 1229 data2 = 0; 1230 /* ? 5GHz ? */ 1231 } else if ((c % 5) != 2 || c > 5435) { 1232 if (!(c % 20) && c < 5120) 1233 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1234 else if (!(c % 10)) 1235 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1236 else if (!(c % 5)) 1237 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1238 else 1239 return -EINVAL; 1240 data2 = ath5k_hw_bitswap(1, 2); 1241 } else { 1242 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1243 data2 = ath5k_hw_bitswap(0, 2); 1244 } 1245 1246 data = (data0 << 4) | data2 << 2 | 0x1001; 1247 1248 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1249 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1250 1251 return 0; 1252 } 1253 1254 /* 1255 * Set a channel on the radio chip 1256 */ 1257 static int ath5k_hw_channel(struct ath5k_hw *ah, 1258 struct ieee80211_channel *channel) 1259 { 1260 int ret; 1261 /* 1262 * Check bounds supported by the PHY (we don't care about regultory 1263 * restrictions at this point). Note: hw_value already has the band 1264 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1265 * of the band by that */ 1266 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1267 ATH5K_ERR(ah->ah_sc, 1268 "channel frequency (%u MHz) out of supported " 1269 "band range\n", 1270 channel->center_freq); 1271 return -EINVAL; 1272 } 1273 1274 /* 1275 * Set the channel and wait 1276 */ 1277 switch (ah->ah_radio) { 1278 case AR5K_RF5110: 1279 ret = ath5k_hw_rf5110_channel(ah, channel); 1280 break; 1281 case AR5K_RF5111: 1282 ret = ath5k_hw_rf5111_channel(ah, channel); 1283 break; 1284 case AR5K_RF2317: 1285 case AR5K_RF2425: 1286 ret = ath5k_hw_rf2425_channel(ah, channel); 1287 break; 1288 default: 1289 ret = ath5k_hw_rf5112_channel(ah, channel); 1290 break; 1291 } 1292 1293 if (ret) 1294 return ret; 1295 1296 /* Set JAPAN setting for channel 14 */ 1297 if (channel->center_freq == 2484) { 1298 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1299 AR5K_PHY_CCKTXCTL_JAPAN); 1300 } else { 1301 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1302 AR5K_PHY_CCKTXCTL_WORLD); 1303 } 1304 1305 ah->ah_current_channel = channel; 1306 1307 return 0; 1308 } 1309 1310 /*****************\ 1311 PHY calibration 1312 \*****************/ 1313 1314 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1315 { 1316 s32 val; 1317 1318 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1319 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1320 } 1321 1322 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1323 { 1324 int i; 1325 1326 ah->ah_nfcal_hist.index = 0; 1327 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1328 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1329 } 1330 1331 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1332 { 1333 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1334 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1335 hist->nfval[hist->index] = noise_floor; 1336 } 1337 1338 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1339 { 1340 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1341 s16 tmp; 1342 int i, j; 1343 1344 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1345 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1346 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1347 if (sort[j] > sort[j-1]) { 1348 tmp = sort[j]; 1349 sort[j] = sort[j-1]; 1350 sort[j-1] = tmp; 1351 } 1352 } 1353 } 1354 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1355 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1356 "cal %d:%d\n", i, sort[i]); 1357 } 1358 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1359 } 1360 1361 /* 1362 * When we tell the hardware to perform a noise floor calibration 1363 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1364 * sample-and-hold the minimum noise level seen at the antennas. 1365 * This value is then stored in a ring buffer of recently measured 1366 * noise floor values so we have a moving window of the last few 1367 * samples. 1368 * 1369 * The median of the values in the history is then loaded into the 1370 * hardware for its own use for RSSI and CCA measurements. 1371 */ 1372 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1373 { 1374 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1375 u32 val; 1376 s16 nf, threshold; 1377 u8 ee_mode; 1378 1379 /* keep last value if calibration hasn't completed */ 1380 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1381 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1382 "NF did not complete in calibration window\n"); 1383 1384 return; 1385 } 1386 1387 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel); 1388 1389 /* completed NF calibration, test threshold */ 1390 nf = ath5k_hw_read_measured_noise_floor(ah); 1391 threshold = ee->ee_noise_floor_thr[ee_mode]; 1392 1393 if (nf > threshold) { 1394 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1395 "noise floor failure detected; " 1396 "read %d, threshold %d\n", 1397 nf, threshold); 1398 1399 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1400 } 1401 1402 ath5k_hw_update_nfcal_hist(ah, nf); 1403 nf = ath5k_hw_get_median_noise_floor(ah); 1404 1405 /* load noise floor (in .5 dBm) so the hardware will use it */ 1406 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1407 val |= (nf * 2) & AR5K_PHY_NF_M; 1408 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1409 1410 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1411 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1412 1413 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1414 0, false); 1415 1416 /* 1417 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1418 * so that we're not capped by the median we just loaded. 1419 * This will be used as the initial value for the next noise 1420 * floor calibration. 1421 */ 1422 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1423 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1424 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1425 AR5K_PHY_AGCCTL_NF_EN | 1426 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1427 AR5K_PHY_AGCCTL_NF); 1428 1429 ah->ah_noise_floor = nf; 1430 1431 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1432 "noise floor calibrated: %d\n", nf); 1433 } 1434 1435 /* 1436 * Perform a PHY calibration on RF5110 1437 * -Fix BPSK/QAM Constellation (I/Q correction) 1438 */ 1439 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1440 struct ieee80211_channel *channel) 1441 { 1442 u32 phy_sig, phy_agc, phy_sat, beacon; 1443 int ret; 1444 1445 /* 1446 * Disable beacons and RX/TX queues, wait 1447 */ 1448 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1449 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1450 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1451 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1452 1453 mdelay(2); 1454 1455 /* 1456 * Set the channel (with AGC turned off) 1457 */ 1458 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1459 udelay(10); 1460 ret = ath5k_hw_channel(ah, channel); 1461 1462 /* 1463 * Activate PHY and wait 1464 */ 1465 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1466 mdelay(1); 1467 1468 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1469 1470 if (ret) 1471 return ret; 1472 1473 /* 1474 * Calibrate the radio chip 1475 */ 1476 1477 /* Remember normal state */ 1478 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1479 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1480 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1481 1482 /* Update radio registers */ 1483 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1484 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1485 1486 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1487 AR5K_PHY_AGCCOARSE_LO)) | 1488 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1489 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1490 1491 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1492 AR5K_PHY_ADCSAT_THR)) | 1493 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1494 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1495 1496 udelay(20); 1497 1498 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1499 udelay(10); 1500 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1501 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1502 1503 mdelay(1); 1504 1505 /* 1506 * Enable calibration and wait until completion 1507 */ 1508 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1509 1510 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1511 AR5K_PHY_AGCCTL_CAL, 0, false); 1512 1513 /* Reset to normal state */ 1514 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1515 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1516 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1517 1518 if (ret) { 1519 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1520 channel->center_freq); 1521 return ret; 1522 } 1523 1524 /* 1525 * Re-enable RX/TX and beacons 1526 */ 1527 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1528 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1529 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1530 1531 return 0; 1532 } 1533 1534 /* 1535 * Perform I/Q calibration on RF5111/5112 and newer chips 1536 */ 1537 static int 1538 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1539 { 1540 u32 i_pwr, q_pwr; 1541 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1542 int i; 1543 1544 if (!ah->ah_calibration || 1545 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1546 return 0; 1547 1548 /* Calibration has finished, get the results and re-run */ 1549 /* work around empty results which can apparently happen on 5212 */ 1550 for (i = 0; i <= 10; i++) { 1551 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1552 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1553 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1554 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1555 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1556 if (i_pwr && q_pwr) 1557 break; 1558 } 1559 1560 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1561 1562 if (ah->ah_version == AR5K_AR5211) 1563 q_coffd = q_pwr >> 6; 1564 else 1565 q_coffd = q_pwr >> 7; 1566 1567 /* protect against divide by 0 and loss of sign bits */ 1568 if (i_coffd == 0 || q_coffd < 2) 1569 return 0; 1570 1571 i_coff = (-iq_corr) / i_coffd; 1572 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1573 1574 if (ah->ah_version == AR5K_AR5211) 1575 q_coff = (i_pwr / q_coffd) - 64; 1576 else 1577 q_coff = (i_pwr / q_coffd) - 128; 1578 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1579 1580 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1581 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1582 i_coff, q_coff, i_coffd, q_coffd); 1583 1584 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1585 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1586 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1587 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1588 1589 /* Re-enable calibration -if we don't we'll commit 1590 * the same values again and again */ 1591 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1592 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1593 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1594 1595 return 0; 1596 } 1597 1598 /* 1599 * Perform a PHY calibration 1600 */ 1601 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1602 struct ieee80211_channel *channel) 1603 { 1604 int ret; 1605 1606 if (ah->ah_radio == AR5K_RF5110) 1607 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1608 else { 1609 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1610 ath5k_hw_request_rfgain_probe(ah); 1611 } 1612 1613 return ret; 1614 } 1615 1616 1617 /***************************\ 1618 * Spur mitigation functions * 1619 \***************************/ 1620 1621 static void 1622 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1623 struct ieee80211_channel *channel) 1624 { 1625 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1626 u32 mag_mask[4] = {0, 0, 0, 0}; 1627 u32 pilot_mask[2] = {0, 0}; 1628 /* Note: fbin values are scaled up by 2 */ 1629 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1630 s32 spur_delta_phase, spur_freq_sigma_delta; 1631 s32 spur_offset, num_symbols_x16; 1632 u8 num_symbol_offsets, i, freq_band; 1633 1634 /* Convert current frequency to fbin value (the same way channels 1635 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1636 * up by 2 so we can compare it later */ 1637 if (channel->hw_value & CHANNEL_2GHZ) { 1638 chan_fbin = (channel->center_freq - 2300) * 10; 1639 freq_band = AR5K_EEPROM_BAND_2GHZ; 1640 } else { 1641 chan_fbin = (channel->center_freq - 4900) * 10; 1642 freq_band = AR5K_EEPROM_BAND_5GHZ; 1643 } 1644 1645 /* Check if any spur_chan_fbin from EEPROM is 1646 * within our current channel's spur detection range */ 1647 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1648 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1649 /* XXX: Half/Quarter channels ?*/ 1650 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1651 spur_detection_window *= 2; 1652 1653 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1654 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1655 1656 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1657 * so it's zero if we got nothing from EEPROM */ 1658 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1659 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1660 break; 1661 } 1662 1663 if ((chan_fbin - spur_detection_window <= 1664 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1665 (chan_fbin + spur_detection_window >= 1666 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1667 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1668 break; 1669 } 1670 } 1671 1672 /* We need to enable spur filter for this channel */ 1673 if (spur_chan_fbin) { 1674 spur_offset = spur_chan_fbin - chan_fbin; 1675 /* 1676 * Calculate deltas: 1677 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1678 * spur_delta_phase -> spur_offset / chip_freq << 11 1679 * Note: Both values have 100Hz resolution 1680 */ 1681 switch (ah->ah_bwmode) { 1682 case AR5K_BWMODE_40MHZ: 1683 /* Both sample_freq and chip_freq are 80MHz */ 1684 spur_delta_phase = (spur_offset << 16) / 25; 1685 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1686 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1687 break; 1688 case AR5K_BWMODE_10MHZ: 1689 /* Both sample_freq and chip_freq are 20MHz (?) */ 1690 spur_delta_phase = (spur_offset << 18) / 25; 1691 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1692 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1693 case AR5K_BWMODE_5MHZ: 1694 /* Both sample_freq and chip_freq are 10MHz (?) */ 1695 spur_delta_phase = (spur_offset << 19) / 25; 1696 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1697 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1698 default: 1699 if (channel->hw_value == CHANNEL_A) { 1700 /* Both sample_freq and chip_freq are 40MHz */ 1701 spur_delta_phase = (spur_offset << 17) / 25; 1702 spur_freq_sigma_delta = 1703 (spur_delta_phase >> 10); 1704 symbol_width = 1705 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1706 } else { 1707 /* sample_freq -> 40MHz chip_freq -> 44MHz 1708 * (for b compatibility) */ 1709 spur_delta_phase = (spur_offset << 17) / 25; 1710 spur_freq_sigma_delta = 1711 (spur_offset << 8) / 55; 1712 symbol_width = 1713 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1714 } 1715 break; 1716 } 1717 1718 /* Calculate pilot and magnitude masks */ 1719 1720 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1721 * and divide by symbol_width to find how many symbols we have 1722 * Note: number of symbols is scaled up by 16 */ 1723 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1724 1725 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1726 if (!(num_symbols_x16 & 0xF)) 1727 /* _X_ */ 1728 num_symbol_offsets = 3; 1729 else 1730 /* _xx_ */ 1731 num_symbol_offsets = 4; 1732 1733 for (i = 0; i < num_symbol_offsets; i++) { 1734 1735 /* Calculate pilot mask */ 1736 s32 curr_sym_off = 1737 (num_symbols_x16 / 16) + i + 25; 1738 1739 /* Pilot magnitude mask seems to be a way to 1740 * declare the boundaries for our detection 1741 * window or something, it's 2 for the middle 1742 * value(s) where the symbol is expected to be 1743 * and 1 on the boundary values */ 1744 u8 plt_mag_map = 1745 (i == 0 || i == (num_symbol_offsets - 1)) 1746 ? 1 : 2; 1747 1748 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1749 if (curr_sym_off <= 25) 1750 pilot_mask[0] |= 1 << curr_sym_off; 1751 else if (curr_sym_off >= 27) 1752 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1753 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1754 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1755 1756 /* Calculate magnitude mask (for viterbi decoder) */ 1757 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1758 mag_mask[0] |= 1759 plt_mag_map << (curr_sym_off + 1) * 2; 1760 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1761 mag_mask[1] |= 1762 plt_mag_map << (curr_sym_off - 15) * 2; 1763 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1764 mag_mask[2] |= 1765 plt_mag_map << (curr_sym_off - 31) * 2; 1766 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1767 mag_mask[3] |= 1768 plt_mag_map << (curr_sym_off - 47) * 2; 1769 1770 } 1771 1772 /* Write settings on hw to enable spur filter */ 1773 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1774 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1775 /* XXX: Self correlator also ? */ 1776 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1777 AR5K_PHY_IQ_PILOT_MASK_EN | 1778 AR5K_PHY_IQ_CHAN_MASK_EN | 1779 AR5K_PHY_IQ_SPUR_FILT_EN); 1780 1781 /* Set delta phase and freq sigma delta */ 1782 ath5k_hw_reg_write(ah, 1783 AR5K_REG_SM(spur_delta_phase, 1784 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1785 AR5K_REG_SM(spur_freq_sigma_delta, 1786 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1787 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1788 AR5K_PHY_TIMING_11); 1789 1790 /* Write pilot masks */ 1791 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1792 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1793 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1794 pilot_mask[1]); 1795 1796 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1798 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1799 pilot_mask[1]); 1800 1801 /* Write magnitude masks */ 1802 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1803 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1804 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1805 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1806 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1807 mag_mask[3]); 1808 1809 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1810 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1811 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1812 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1813 AR5K_PHY_BIN_MASK2_4_MASK_4, 1814 mag_mask[3]); 1815 1816 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1817 AR5K_PHY_IQ_SPUR_FILT_EN) { 1818 /* Clean up spur mitigation settings and disable fliter */ 1819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1820 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1821 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1822 AR5K_PHY_IQ_PILOT_MASK_EN | 1823 AR5K_PHY_IQ_CHAN_MASK_EN | 1824 AR5K_PHY_IQ_SPUR_FILT_EN); 1825 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1826 1827 /* Clear pilot masks */ 1828 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1829 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1830 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1831 0); 1832 1833 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1835 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1836 0); 1837 1838 /* Clear magnitude masks */ 1839 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1840 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1841 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1842 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1843 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1844 0); 1845 1846 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1847 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1848 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1850 AR5K_PHY_BIN_MASK2_4_MASK_4, 1851 0); 1852 } 1853 } 1854 1855 1856 /*****************\ 1857 * Antenna control * 1858 \*****************/ 1859 1860 static void /*TODO:Boundary check*/ 1861 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1862 { 1863 if (ah->ah_version != AR5K_AR5210) 1864 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1865 } 1866 1867 /* 1868 * Enable/disable fast rx antenna diversity 1869 */ 1870 static void 1871 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1872 { 1873 switch (ee_mode) { 1874 case AR5K_EEPROM_MODE_11G: 1875 /* XXX: This is set to 1876 * disabled on initvals !!! */ 1877 case AR5K_EEPROM_MODE_11A: 1878 if (enable) 1879 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1880 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1881 else 1882 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1883 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1884 break; 1885 case AR5K_EEPROM_MODE_11B: 1886 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1887 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1888 break; 1889 default: 1890 return; 1891 } 1892 1893 if (enable) { 1894 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1895 AR5K_PHY_RESTART_DIV_GC, 4); 1896 1897 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1898 AR5K_PHY_FAST_ANT_DIV_EN); 1899 } else { 1900 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1901 AR5K_PHY_RESTART_DIV_GC, 0); 1902 1903 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1904 AR5K_PHY_FAST_ANT_DIV_EN); 1905 } 1906 } 1907 1908 void 1909 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1910 { 1911 u8 ant0, ant1; 1912 1913 /* 1914 * In case a fixed antenna was set as default 1915 * use the same switch table twice. 1916 */ 1917 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1918 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1919 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1920 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1921 else { 1922 ant0 = AR5K_ANT_SWTABLE_A; 1923 ant1 = AR5K_ANT_SWTABLE_B; 1924 } 1925 1926 /* Set antenna idle switch table */ 1927 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1928 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1929 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1930 AR5K_PHY_ANT_CTL_TXRX_EN)); 1931 1932 /* Set antenna switch tables */ 1933 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1934 AR5K_PHY_ANT_SWITCH_TABLE_0); 1935 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1936 AR5K_PHY_ANT_SWITCH_TABLE_1); 1937 } 1938 1939 /* 1940 * Set antenna operating mode 1941 */ 1942 void 1943 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1944 { 1945 struct ieee80211_channel *channel = ah->ah_current_channel; 1946 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1947 bool use_def_for_sg; 1948 int ee_mode; 1949 u8 def_ant, tx_ant; 1950 u32 sta_id1 = 0; 1951 1952 /* if channel is not initialized yet we can't set the antennas 1953 * so just store the mode. it will be set on the next reset */ 1954 if (channel == NULL) { 1955 ah->ah_ant_mode = ant_mode; 1956 return; 1957 } 1958 1959 def_ant = ah->ah_def_ant; 1960 1961 ee_mode = ath5k_eeprom_mode_from_channel(channel); 1962 if (ee_mode < 0) { 1963 ATH5K_ERR(ah->ah_sc, 1964 "invalid channel: %d\n", channel->center_freq); 1965 return; 1966 } 1967 1968 switch (ant_mode) { 1969 case AR5K_ANTMODE_DEFAULT: 1970 tx_ant = 0; 1971 use_def_for_tx = false; 1972 update_def_on_tx = false; 1973 use_def_for_rts = false; 1974 use_def_for_sg = false; 1975 fast_div = true; 1976 break; 1977 case AR5K_ANTMODE_FIXED_A: 1978 def_ant = 1; 1979 tx_ant = 1; 1980 use_def_for_tx = true; 1981 update_def_on_tx = false; 1982 use_def_for_rts = true; 1983 use_def_for_sg = true; 1984 fast_div = false; 1985 break; 1986 case AR5K_ANTMODE_FIXED_B: 1987 def_ant = 2; 1988 tx_ant = 2; 1989 use_def_for_tx = true; 1990 update_def_on_tx = false; 1991 use_def_for_rts = true; 1992 use_def_for_sg = true; 1993 fast_div = false; 1994 break; 1995 case AR5K_ANTMODE_SINGLE_AP: 1996 def_ant = 1; /* updated on tx */ 1997 tx_ant = 0; 1998 use_def_for_tx = true; 1999 update_def_on_tx = true; 2000 use_def_for_rts = true; 2001 use_def_for_sg = true; 2002 fast_div = true; 2003 break; 2004 case AR5K_ANTMODE_SECTOR_AP: 2005 tx_ant = 1; /* variable */ 2006 use_def_for_tx = false; 2007 update_def_on_tx = false; 2008 use_def_for_rts = true; 2009 use_def_for_sg = false; 2010 fast_div = false; 2011 break; 2012 case AR5K_ANTMODE_SECTOR_STA: 2013 tx_ant = 1; /* variable */ 2014 use_def_for_tx = true; 2015 update_def_on_tx = false; 2016 use_def_for_rts = true; 2017 use_def_for_sg = false; 2018 fast_div = true; 2019 break; 2020 case AR5K_ANTMODE_DEBUG: 2021 def_ant = 1; 2022 tx_ant = 2; 2023 use_def_for_tx = false; 2024 update_def_on_tx = false; 2025 use_def_for_rts = false; 2026 use_def_for_sg = false; 2027 fast_div = false; 2028 break; 2029 default: 2030 return; 2031 } 2032 2033 ah->ah_tx_ant = tx_ant; 2034 ah->ah_ant_mode = ant_mode; 2035 ah->ah_def_ant = def_ant; 2036 2037 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2038 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2039 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2040 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2041 2042 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2043 2044 if (sta_id1) 2045 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2046 2047 ath5k_hw_set_antenna_switch(ah, ee_mode); 2048 /* Note: set diversity before default antenna 2049 * because it won't work correctly */ 2050 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2051 ath5k_hw_set_def_antenna(ah, def_ant); 2052 } 2053 2054 2055 /****************\ 2056 * TX power setup * 2057 \****************/ 2058 2059 /* 2060 * Helper functions 2061 */ 2062 2063 /* 2064 * Do linear interpolation between two given (x, y) points 2065 */ 2066 static s16 2067 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2068 s16 y_left, s16 y_right) 2069 { 2070 s16 ratio, result; 2071 2072 /* Avoid divide by zero and skip interpolation 2073 * if we have the same point */ 2074 if ((x_left == x_right) || (y_left == y_right)) 2075 return y_left; 2076 2077 /* 2078 * Since we use ints and not fps, we need to scale up in 2079 * order to get a sane ratio value (or else we 'll eg. get 2080 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2081 * to have some accuracy both for 0.5 and 0.25 steps. 2082 */ 2083 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 2084 2085 /* Now scale down to be in range */ 2086 result = y_left + (ratio * (target - x_left) / 100); 2087 2088 return result; 2089 } 2090 2091 /* 2092 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2093 * 2094 * Since we have the top of the curve and we draw the line below 2095 * until we reach 1 (1 pcdac step) we need to know which point 2096 * (x value) that is so that we don't go below y axis and have negative 2097 * pcdac values when creating the curve, or fill the table with zeroes. 2098 */ 2099 static s16 2100 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2101 const s16 *pwrL, const s16 *pwrR) 2102 { 2103 s8 tmp; 2104 s16 min_pwrL, min_pwrR; 2105 s16 pwr_i; 2106 2107 /* Some vendors write the same pcdac value twice !!! */ 2108 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2109 return max(pwrL[0], pwrR[0]); 2110 2111 if (pwrL[0] == pwrL[1]) 2112 min_pwrL = pwrL[0]; 2113 else { 2114 pwr_i = pwrL[0]; 2115 do { 2116 pwr_i--; 2117 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2118 pwrL[0], pwrL[1], 2119 stepL[0], stepL[1]); 2120 } while (tmp > 1); 2121 2122 min_pwrL = pwr_i; 2123 } 2124 2125 if (pwrR[0] == pwrR[1]) 2126 min_pwrR = pwrR[0]; 2127 else { 2128 pwr_i = pwrR[0]; 2129 do { 2130 pwr_i--; 2131 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2132 pwrR[0], pwrR[1], 2133 stepR[0], stepR[1]); 2134 } while (tmp > 1); 2135 2136 min_pwrR = pwr_i; 2137 } 2138 2139 /* Keep the right boundary so that it works for both curves */ 2140 return max(min_pwrL, min_pwrR); 2141 } 2142 2143 /* 2144 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2145 * Power to PCDAC curve. 2146 * 2147 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2148 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2149 * PCDAC/PDADC step for each curve is 64 but we can write more than 2150 * one curves on hw so we can go up to 128 (which is the max step we 2151 * can write on the final table). 2152 * 2153 * We write y values (PCDAC/PDADC steps) on hw. 2154 */ 2155 static void 2156 ath5k_create_power_curve(s16 pmin, s16 pmax, 2157 const s16 *pwr, const u8 *vpd, 2158 u8 num_points, 2159 u8 *vpd_table, u8 type) 2160 { 2161 u8 idx[2] = { 0, 1 }; 2162 s16 pwr_i = 2*pmin; 2163 int i; 2164 2165 if (num_points < 2) 2166 return; 2167 2168 /* We want the whole line, so adjust boundaries 2169 * to cover the entire power range. Note that 2170 * power values are already 0.25dB so no need 2171 * to multiply pwr_i by 2 */ 2172 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2173 pwr_i = pmin; 2174 pmin = 0; 2175 pmax = 63; 2176 } 2177 2178 /* Find surrounding turning points (TPs) 2179 * and interpolate between them */ 2180 for (i = 0; (i <= (u16) (pmax - pmin)) && 2181 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2182 2183 /* We passed the right TP, move to the next set of TPs 2184 * if we pass the last TP, extrapolate above using the last 2185 * two TPs for ratio */ 2186 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2187 idx[0]++; 2188 idx[1]++; 2189 } 2190 2191 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2192 pwr[idx[0]], pwr[idx[1]], 2193 vpd[idx[0]], vpd[idx[1]]); 2194 2195 /* Increase by 0.5dB 2196 * (0.25 dB units) */ 2197 pwr_i += 2; 2198 } 2199 } 2200 2201 /* 2202 * Get the surrounding per-channel power calibration piers 2203 * for a given frequency so that we can interpolate between 2204 * them and come up with an apropriate dataset for our current 2205 * channel. 2206 */ 2207 static void 2208 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2209 struct ieee80211_channel *channel, 2210 struct ath5k_chan_pcal_info **pcinfo_l, 2211 struct ath5k_chan_pcal_info **pcinfo_r) 2212 { 2213 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2214 struct ath5k_chan_pcal_info *pcinfo; 2215 u8 idx_l, idx_r; 2216 u8 mode, max, i; 2217 u32 target = channel->center_freq; 2218 2219 idx_l = 0; 2220 idx_r = 0; 2221 2222 if (!(channel->hw_value & CHANNEL_OFDM)) { 2223 pcinfo = ee->ee_pwr_cal_b; 2224 mode = AR5K_EEPROM_MODE_11B; 2225 } else if (channel->hw_value & CHANNEL_2GHZ) { 2226 pcinfo = ee->ee_pwr_cal_g; 2227 mode = AR5K_EEPROM_MODE_11G; 2228 } else { 2229 pcinfo = ee->ee_pwr_cal_a; 2230 mode = AR5K_EEPROM_MODE_11A; 2231 } 2232 max = ee->ee_n_piers[mode] - 1; 2233 2234 /* Frequency is below our calibrated 2235 * range. Use the lowest power curve 2236 * we have */ 2237 if (target < pcinfo[0].freq) { 2238 idx_l = idx_r = 0; 2239 goto done; 2240 } 2241 2242 /* Frequency is above our calibrated 2243 * range. Use the highest power curve 2244 * we have */ 2245 if (target > pcinfo[max].freq) { 2246 idx_l = idx_r = max; 2247 goto done; 2248 } 2249 2250 /* Frequency is inside our calibrated 2251 * channel range. Pick the surrounding 2252 * calibration piers so that we can 2253 * interpolate */ 2254 for (i = 0; i <= max; i++) { 2255 2256 /* Frequency matches one of our calibration 2257 * piers, no need to interpolate, just use 2258 * that calibration pier */ 2259 if (pcinfo[i].freq == target) { 2260 idx_l = idx_r = i; 2261 goto done; 2262 } 2263 2264 /* We found a calibration pier that's above 2265 * frequency, use this pier and the previous 2266 * one to interpolate */ 2267 if (target < pcinfo[i].freq) { 2268 idx_r = i; 2269 idx_l = idx_r - 1; 2270 goto done; 2271 } 2272 } 2273 2274 done: 2275 *pcinfo_l = &pcinfo[idx_l]; 2276 *pcinfo_r = &pcinfo[idx_r]; 2277 } 2278 2279 /* 2280 * Get the surrounding per-rate power calibration data 2281 * for a given frequency and interpolate between power 2282 * values to set max target power supported by hw for 2283 * each rate. 2284 */ 2285 static void 2286 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2287 struct ieee80211_channel *channel, 2288 struct ath5k_rate_pcal_info *rates) 2289 { 2290 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2291 struct ath5k_rate_pcal_info *rpinfo; 2292 u8 idx_l, idx_r; 2293 u8 mode, max, i; 2294 u32 target = channel->center_freq; 2295 2296 idx_l = 0; 2297 idx_r = 0; 2298 2299 if (!(channel->hw_value & CHANNEL_OFDM)) { 2300 rpinfo = ee->ee_rate_tpwr_b; 2301 mode = AR5K_EEPROM_MODE_11B; 2302 } else if (channel->hw_value & CHANNEL_2GHZ) { 2303 rpinfo = ee->ee_rate_tpwr_g; 2304 mode = AR5K_EEPROM_MODE_11G; 2305 } else { 2306 rpinfo = ee->ee_rate_tpwr_a; 2307 mode = AR5K_EEPROM_MODE_11A; 2308 } 2309 max = ee->ee_rate_target_pwr_num[mode] - 1; 2310 2311 /* Get the surrounding calibration 2312 * piers - same as above */ 2313 if (target < rpinfo[0].freq) { 2314 idx_l = idx_r = 0; 2315 goto done; 2316 } 2317 2318 if (target > rpinfo[max].freq) { 2319 idx_l = idx_r = max; 2320 goto done; 2321 } 2322 2323 for (i = 0; i <= max; i++) { 2324 2325 if (rpinfo[i].freq == target) { 2326 idx_l = idx_r = i; 2327 goto done; 2328 } 2329 2330 if (target < rpinfo[i].freq) { 2331 idx_r = i; 2332 idx_l = idx_r - 1; 2333 goto done; 2334 } 2335 } 2336 2337 done: 2338 /* Now interpolate power value, based on the frequency */ 2339 rates->freq = target; 2340 2341 rates->target_power_6to24 = 2342 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2343 rpinfo[idx_r].freq, 2344 rpinfo[idx_l].target_power_6to24, 2345 rpinfo[idx_r].target_power_6to24); 2346 2347 rates->target_power_36 = 2348 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2349 rpinfo[idx_r].freq, 2350 rpinfo[idx_l].target_power_36, 2351 rpinfo[idx_r].target_power_36); 2352 2353 rates->target_power_48 = 2354 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2355 rpinfo[idx_r].freq, 2356 rpinfo[idx_l].target_power_48, 2357 rpinfo[idx_r].target_power_48); 2358 2359 rates->target_power_54 = 2360 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2361 rpinfo[idx_r].freq, 2362 rpinfo[idx_l].target_power_54, 2363 rpinfo[idx_r].target_power_54); 2364 } 2365 2366 /* 2367 * Get the max edge power for this channel if 2368 * we have such data from EEPROM's Conformance Test 2369 * Limits (CTL), and limit max power if needed. 2370 */ 2371 static void 2372 ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2373 struct ieee80211_channel *channel) 2374 { 2375 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2376 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2377 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2378 u8 *ctl_val = ee->ee_ctl; 2379 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2380 s16 edge_pwr = 0; 2381 u8 rep_idx; 2382 u8 i, ctl_mode; 2383 u8 ctl_idx = 0xFF; 2384 u32 target = channel->center_freq; 2385 2386 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2387 2388 switch (channel->hw_value & CHANNEL_MODES) { 2389 case CHANNEL_A: 2390 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2391 ctl_mode |= AR5K_CTL_TURBO; 2392 else 2393 ctl_mode |= AR5K_CTL_11A; 2394 break; 2395 case CHANNEL_G: 2396 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2397 ctl_mode |= AR5K_CTL_TURBOG; 2398 else 2399 ctl_mode |= AR5K_CTL_11G; 2400 break; 2401 case CHANNEL_B: 2402 ctl_mode |= AR5K_CTL_11B; 2403 break; 2404 case CHANNEL_XR: 2405 /* Fall through */ 2406 default: 2407 return; 2408 } 2409 2410 for (i = 0; i < ee->ee_ctls; i++) { 2411 if (ctl_val[i] == ctl_mode) { 2412 ctl_idx = i; 2413 break; 2414 } 2415 } 2416 2417 /* If we have a CTL dataset available grab it and find the 2418 * edge power for our frequency */ 2419 if (ctl_idx == 0xFF) 2420 return; 2421 2422 /* Edge powers are sorted by frequency from lower 2423 * to higher. Each CTL corresponds to 8 edge power 2424 * measurements. */ 2425 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2426 2427 /* Don't do boundaries check because we 2428 * might have more that one bands defined 2429 * for this mode */ 2430 2431 /* Get the edge power that's closer to our 2432 * frequency */ 2433 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2434 rep_idx += i; 2435 if (target <= rep[rep_idx].freq) 2436 edge_pwr = (s16) rep[rep_idx].edge; 2437 } 2438 2439 if (edge_pwr) 2440 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2441 } 2442 2443 2444 /* 2445 * Power to PCDAC table functions 2446 */ 2447 2448 /* 2449 * Fill Power to PCDAC table on RF5111 2450 * 2451 * No further processing is needed for RF5111, the only thing we have to 2452 * do is fill the values below and above calibration range since eeprom data 2453 * may not cover the entire PCDAC table. 2454 */ 2455 static void 2456 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2457 s16 *table_max) 2458 { 2459 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2460 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2461 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2462 s16 min_pwr, max_pwr; 2463 2464 /* Get table boundaries */ 2465 min_pwr = table_min[0]; 2466 pcdac_0 = pcdac_tmp[0]; 2467 2468 max_pwr = table_max[0]; 2469 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2470 2471 /* Extrapolate below minimum using pcdac_0 */ 2472 pcdac_i = 0; 2473 for (i = 0; i < min_pwr; i++) 2474 pcdac_out[pcdac_i++] = pcdac_0; 2475 2476 /* Copy values from pcdac_tmp */ 2477 pwr_idx = min_pwr; 2478 for (i = 0 ; pwr_idx <= max_pwr && 2479 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2480 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2481 pwr_idx++; 2482 } 2483 2484 /* Extrapolate above maximum */ 2485 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2486 pcdac_out[pcdac_i++] = pcdac_n; 2487 2488 } 2489 2490 /* 2491 * Combine available XPD Curves and fill Linear Power to PCDAC table 2492 * on RF5112 2493 * 2494 * RFX112 can have up to 2 curves (one for low txpower range and one for 2495 * higher txpower range). We need to put them both on pcdac_out and place 2496 * them in the correct location. In case we only have one curve available 2497 * just fit it on pcdac_out (it's supposed to cover the entire range of 2498 * available pwr levels since it's always the higher power curve). Extrapolate 2499 * below and above final table if needed. 2500 */ 2501 static void 2502 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2503 s16 *table_max, u8 pdcurves) 2504 { 2505 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2506 u8 *pcdac_low_pwr; 2507 u8 *pcdac_high_pwr; 2508 u8 *pcdac_tmp; 2509 u8 pwr; 2510 s16 max_pwr_idx; 2511 s16 min_pwr_idx; 2512 s16 mid_pwr_idx = 0; 2513 /* Edge flag turs on the 7nth bit on the PCDAC 2514 * to delcare the higher power curve (force values 2515 * to be greater than 64). If we only have one curve 2516 * we don't need to set this, if we have 2 curves and 2517 * fill the table backwards this can also be used to 2518 * switch from higher power curve to lower power curve */ 2519 u8 edge_flag; 2520 int i; 2521 2522 /* When we have only one curve available 2523 * that's the higher power curve. If we have 2524 * two curves the first is the high power curve 2525 * and the next is the low power curve. */ 2526 if (pdcurves > 1) { 2527 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2528 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2529 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2530 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2531 2532 /* If table size goes beyond 31.5dB, keep the 2533 * upper 31.5dB range when setting tx power. 2534 * Note: 126 = 31.5 dB in quarter dB steps */ 2535 if (table_max[0] - table_min[1] > 126) 2536 min_pwr_idx = table_max[0] - 126; 2537 else 2538 min_pwr_idx = table_min[1]; 2539 2540 /* Since we fill table backwards 2541 * start from high power curve */ 2542 pcdac_tmp = pcdac_high_pwr; 2543 2544 edge_flag = 0x40; 2545 } else { 2546 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2547 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2548 min_pwr_idx = table_min[0]; 2549 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2550 pcdac_tmp = pcdac_high_pwr; 2551 edge_flag = 0; 2552 } 2553 2554 /* This is used when setting tx power*/ 2555 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2556 2557 /* Fill Power to PCDAC table backwards */ 2558 pwr = max_pwr_idx; 2559 for (i = 63; i >= 0; i--) { 2560 /* Entering lower power range, reset 2561 * edge flag and set pcdac_tmp to lower 2562 * power curve.*/ 2563 if (edge_flag == 0x40 && 2564 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2565 edge_flag = 0x00; 2566 pcdac_tmp = pcdac_low_pwr; 2567 pwr = mid_pwr_idx/2; 2568 } 2569 2570 /* Don't go below 1, extrapolate below if we have 2571 * already swithced to the lower power curve -or 2572 * we only have one curve and edge_flag is zero 2573 * anyway */ 2574 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2575 while (i >= 0) { 2576 pcdac_out[i] = pcdac_out[i + 1]; 2577 i--; 2578 } 2579 break; 2580 } 2581 2582 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2583 2584 /* Extrapolate above if pcdac is greater than 2585 * 126 -this can happen because we OR pcdac_out 2586 * value with edge_flag on high power curve */ 2587 if (pcdac_out[i] > 126) 2588 pcdac_out[i] = 126; 2589 2590 /* Decrease by a 0.5dB step */ 2591 pwr--; 2592 } 2593 } 2594 2595 /* Write PCDAC values on hw */ 2596 static void 2597 ath5k_write_pcdac_table(struct ath5k_hw *ah) 2598 { 2599 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2600 int i; 2601 2602 /* 2603 * Write TX power values 2604 */ 2605 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2606 ath5k_hw_reg_write(ah, 2607 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2608 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2609 AR5K_PHY_PCDAC_TXPOWER(i)); 2610 } 2611 } 2612 2613 2614 /* 2615 * Power to PDADC table functions 2616 */ 2617 2618 /* 2619 * Set the gain boundaries and create final Power to PDADC table 2620 * 2621 * We can have up to 4 pd curves, we need to do a simmilar process 2622 * as we do for RF5112. This time we don't have an edge_flag but we 2623 * set the gain boundaries on a separate register. 2624 */ 2625 static void 2626 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2627 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2628 { 2629 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2630 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2631 u8 *pdadc_tmp; 2632 s16 pdadc_0; 2633 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2634 u8 pd_gain_overlap; 2635 2636 /* Note: Register value is initialized on initvals 2637 * there is no feedback from hw. 2638 * XXX: What about pd_gain_overlap from EEPROM ? */ 2639 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2640 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2641 2642 /* Create final PDADC table */ 2643 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2644 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2645 2646 if (pdg == pdcurves - 1) 2647 /* 2 dB boundary stretch for last 2648 * (higher power) curve */ 2649 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2650 else 2651 /* Set gain boundary in the middle 2652 * between this curve and the next one */ 2653 gain_boundaries[pdg] = 2654 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2655 2656 /* Sanity check in case our 2 db stretch got out of 2657 * range. */ 2658 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2659 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2660 2661 /* For the first curve (lower power) 2662 * start from 0 dB */ 2663 if (pdg == 0) 2664 pdadc_0 = 0; 2665 else 2666 /* For the other curves use the gain overlap */ 2667 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2668 pd_gain_overlap; 2669 2670 /* Force each power step to be at least 0.5 dB */ 2671 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2672 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2673 else 2674 pwr_step = 1; 2675 2676 /* If pdadc_0 is negative, we need to extrapolate 2677 * below this pdgain by a number of pwr_steps */ 2678 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2679 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2680 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2681 pdadc_0++; 2682 } 2683 2684 /* Set last pwr level, using gain boundaries */ 2685 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2686 /* Limit it to be inside pwr range */ 2687 table_size = pwr_max[pdg] - pwr_min[pdg]; 2688 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2689 2690 /* Fill pdadc_out table */ 2691 while (pdadc_0 < max_idx && pdadc_i < 128) 2692 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2693 2694 /* Need to extrapolate above this pdgain? */ 2695 if (pdadc_n <= max_idx) 2696 continue; 2697 2698 /* Force each power step to be at least 0.5 dB */ 2699 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2700 pwr_step = pdadc_tmp[table_size - 1] - 2701 pdadc_tmp[table_size - 2]; 2702 else 2703 pwr_step = 1; 2704 2705 /* Extrapolate above */ 2706 while ((pdadc_0 < (s16) pdadc_n) && 2707 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2708 s16 tmp = pdadc_tmp[table_size - 1] + 2709 (pdadc_0 - max_idx) * pwr_step; 2710 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2711 pdadc_0++; 2712 } 2713 } 2714 2715 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2716 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2717 pdg++; 2718 } 2719 2720 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2721 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2722 pdadc_i++; 2723 } 2724 2725 /* Set gain boundaries */ 2726 ath5k_hw_reg_write(ah, 2727 AR5K_REG_SM(pd_gain_overlap, 2728 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2729 AR5K_REG_SM(gain_boundaries[0], 2730 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2731 AR5K_REG_SM(gain_boundaries[1], 2732 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2733 AR5K_REG_SM(gain_boundaries[2], 2734 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2735 AR5K_REG_SM(gain_boundaries[3], 2736 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2737 AR5K_PHY_TPC_RG5); 2738 2739 /* Used for setting rate power table */ 2740 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2741 2742 } 2743 2744 /* Write PDADC values on hw */ 2745 static void 2746 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 2747 { 2748 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2749 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2750 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2751 u8 pdcurves = ee->ee_pd_gains[ee_mode]; 2752 u32 reg; 2753 u8 i; 2754 2755 /* Select the right pdgain curves */ 2756 2757 /* Clear current settings */ 2758 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2759 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2760 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2761 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2762 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2763 2764 /* 2765 * Use pd_gains curve from eeprom 2766 * 2767 * This overrides the default setting from initvals 2768 * in case some vendors (e.g. Zcomax) don't use the default 2769 * curves. If we don't honor their settings we 'll get a 2770 * 5dB (1 * gain overlap ?) drop. 2771 */ 2772 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2773 2774 switch (pdcurves) { 2775 case 3: 2776 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2777 /* Fall through */ 2778 case 2: 2779 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2780 /* Fall through */ 2781 case 1: 2782 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2783 break; 2784 } 2785 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2786 2787 /* 2788 * Write TX power values 2789 */ 2790 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2791 ath5k_hw_reg_write(ah, 2792 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2793 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2794 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2795 ((pdadc_out[4*i + 3] & 0xff) << 24), 2796 AR5K_PHY_PDADC_TXPOWER(i)); 2797 } 2798 } 2799 2800 2801 /* 2802 * Common code for PCDAC/PDADC tables 2803 */ 2804 2805 /* 2806 * This is the main function that uses all of the above 2807 * to set PCDAC/PDADC table on hw for the current channel. 2808 * This table is used for tx power calibration on the basband, 2809 * without it we get weird tx power levels and in some cases 2810 * distorted spectral mask 2811 */ 2812 static int 2813 ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2814 struct ieee80211_channel *channel, 2815 u8 ee_mode, u8 type) 2816 { 2817 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2818 struct ath5k_chan_pcal_info *pcinfo_L; 2819 struct ath5k_chan_pcal_info *pcinfo_R; 2820 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2821 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2822 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2823 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2824 u8 *tmpL; 2825 u8 *tmpR; 2826 u32 target = channel->center_freq; 2827 int pdg, i; 2828 2829 /* Get surounding freq piers for this channel */ 2830 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2831 &pcinfo_L, 2832 &pcinfo_R); 2833 2834 /* Loop over pd gain curves on 2835 * surounding freq piers by index */ 2836 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2837 2838 /* Fill curves in reverse order 2839 * from lower power (max gain) 2840 * to higher power. Use curve -> idx 2841 * backmapping we did on eeprom init */ 2842 u8 idx = pdg_curve_to_idx[pdg]; 2843 2844 /* Grab the needed curves by index */ 2845 pdg_L = &pcinfo_L->pd_curves[idx]; 2846 pdg_R = &pcinfo_R->pd_curves[idx]; 2847 2848 /* Initialize the temp tables */ 2849 tmpL = ah->ah_txpower.tmpL[pdg]; 2850 tmpR = ah->ah_txpower.tmpR[pdg]; 2851 2852 /* Set curve's x boundaries and create 2853 * curves so that they cover the same 2854 * range (if we don't do that one table 2855 * will have values on some range and the 2856 * other one won't have any so interpolation 2857 * will fail) */ 2858 table_min[pdg] = min(pdg_L->pd_pwr[0], 2859 pdg_R->pd_pwr[0]) / 2; 2860 2861 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2862 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2863 2864 /* Now create the curves on surrounding channels 2865 * and interpolate if needed to get the final 2866 * curve for this gain on this channel */ 2867 switch (type) { 2868 case AR5K_PWRTABLE_LINEAR_PCDAC: 2869 /* Override min/max so that we don't loose 2870 * accuracy (don't divide by 2) */ 2871 table_min[pdg] = min(pdg_L->pd_pwr[0], 2872 pdg_R->pd_pwr[0]); 2873 2874 table_max[pdg] = 2875 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2876 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2877 2878 /* Override minimum so that we don't get 2879 * out of bounds while extrapolating 2880 * below. Don't do this when we have 2 2881 * curves and we are on the high power curve 2882 * because table_min is ok in this case */ 2883 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2884 2885 table_min[pdg] = 2886 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2887 pdg_R->pd_step, 2888 pdg_L->pd_pwr, 2889 pdg_R->pd_pwr); 2890 2891 /* Don't go too low because we will 2892 * miss the upper part of the curve. 2893 * Note: 126 = 31.5dB (max power supported) 2894 * in 0.25dB units */ 2895 if (table_max[pdg] - table_min[pdg] > 126) 2896 table_min[pdg] = table_max[pdg] - 126; 2897 } 2898 2899 /* Fall through */ 2900 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2901 case AR5K_PWRTABLE_PWR_TO_PDADC: 2902 2903 ath5k_create_power_curve(table_min[pdg], 2904 table_max[pdg], 2905 pdg_L->pd_pwr, 2906 pdg_L->pd_step, 2907 pdg_L->pd_points, tmpL, type); 2908 2909 /* We are in a calibration 2910 * pier, no need to interpolate 2911 * between freq piers */ 2912 if (pcinfo_L == pcinfo_R) 2913 continue; 2914 2915 ath5k_create_power_curve(table_min[pdg], 2916 table_max[pdg], 2917 pdg_R->pd_pwr, 2918 pdg_R->pd_step, 2919 pdg_R->pd_points, tmpR, type); 2920 break; 2921 default: 2922 return -EINVAL; 2923 } 2924 2925 /* Interpolate between curves 2926 * of surounding freq piers to 2927 * get the final curve for this 2928 * pd gain. Re-use tmpL for interpolation 2929 * output */ 2930 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2931 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2932 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2933 (s16) pcinfo_L->freq, 2934 (s16) pcinfo_R->freq, 2935 (s16) tmpL[i], 2936 (s16) tmpR[i]); 2937 } 2938 } 2939 2940 /* Now we have a set of curves for this 2941 * channel on tmpL (x range is table_max - table_min 2942 * and y values are tmpL[pdg][]) sorted in the same 2943 * order as EEPROM (because we've used the backmapping). 2944 * So for RF5112 it's from higher power to lower power 2945 * and for RF2413 it's from lower power to higher power. 2946 * For RF5111 we only have one curve. */ 2947 2948 /* Fill min and max power levels for this 2949 * channel by interpolating the values on 2950 * surounding channels to complete the dataset */ 2951 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2952 (s16) pcinfo_L->freq, 2953 (s16) pcinfo_R->freq, 2954 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2955 2956 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2957 (s16) pcinfo_L->freq, 2958 (s16) pcinfo_R->freq, 2959 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2960 2961 /* Fill PCDAC/PDADC table */ 2962 switch (type) { 2963 case AR5K_PWRTABLE_LINEAR_PCDAC: 2964 /* For RF5112 we can have one or two curves 2965 * and each curve covers a certain power lvl 2966 * range so we need to do some more processing */ 2967 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2968 ee->ee_pd_gains[ee_mode]); 2969 2970 /* Set txp.offset so that we can 2971 * match max power value with max 2972 * table index */ 2973 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2974 break; 2975 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2976 /* We are done for RF5111 since it has only 2977 * one curve, just fit the curve on the table */ 2978 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2979 2980 /* No rate powertable adjustment for RF5111 */ 2981 ah->ah_txpower.txp_min_idx = 0; 2982 ah->ah_txpower.txp_offset = 0; 2983 break; 2984 case AR5K_PWRTABLE_PWR_TO_PDADC: 2985 /* Set PDADC boundaries and fill 2986 * final PDADC table */ 2987 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2988 ee->ee_pd_gains[ee_mode]); 2989 2990 /* Set txp.offset, note that table_min 2991 * can be negative */ 2992 ah->ah_txpower.txp_offset = table_min[0]; 2993 break; 2994 default: 2995 return -EINVAL; 2996 } 2997 2998 ah->ah_txpower.txp_setup = true; 2999 3000 return 0; 3001 } 3002 3003 /* Write power table for current channel to hw */ 3004 static void 3005 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 3006 { 3007 if (type == AR5K_PWRTABLE_PWR_TO_PDADC) 3008 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); 3009 else 3010 ath5k_write_pcdac_table(ah); 3011 } 3012 3013 /* 3014 * Per-rate tx power setting 3015 * 3016 * This is the code that sets the desired tx power (below 3017 * maximum) on hw for each rate (we also have TPC that sets 3018 * power per packet). We do that by providing an index on the 3019 * PCDAC/PDADC table we set up. 3020 */ 3021 3022 /* 3023 * Set rate power table 3024 * 3025 * For now we only limit txpower based on maximum tx power 3026 * supported by hw (what's inside rate_info). We need to limit 3027 * this even more, based on regulatory domain etc. 3028 * 3029 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3030 * and is indexed as follows: 3031 * rates[0] - rates[7] -> OFDM rates 3032 * rates[8] - rates[14] -> CCK rates 3033 * rates[15] -> XR rates (they all have the same power) 3034 */ 3035 static void 3036 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3037 struct ath5k_rate_pcal_info *rate_info, 3038 u8 ee_mode) 3039 { 3040 unsigned int i; 3041 u16 *rates; 3042 3043 /* max_pwr is power level we got from driver/user in 0.5dB 3044 * units, switch to 0.25dB units so we can compare */ 3045 max_pwr *= 2; 3046 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3047 3048 /* apply rate limits */ 3049 rates = ah->ah_txpower.txp_rates_power_table; 3050 3051 /* OFDM rates 6 to 24Mb/s */ 3052 for (i = 0; i < 5; i++) 3053 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3054 3055 /* Rest OFDM rates */ 3056 rates[5] = min(rates[0], rate_info->target_power_36); 3057 rates[6] = min(rates[0], rate_info->target_power_48); 3058 rates[7] = min(rates[0], rate_info->target_power_54); 3059 3060 /* CCK rates */ 3061 /* 1L */ 3062 rates[8] = min(rates[0], rate_info->target_power_6to24); 3063 /* 2L */ 3064 rates[9] = min(rates[0], rate_info->target_power_36); 3065 /* 2S */ 3066 rates[10] = min(rates[0], rate_info->target_power_36); 3067 /* 5L */ 3068 rates[11] = min(rates[0], rate_info->target_power_48); 3069 /* 5S */ 3070 rates[12] = min(rates[0], rate_info->target_power_48); 3071 /* 11L */ 3072 rates[13] = min(rates[0], rate_info->target_power_54); 3073 /* 11S */ 3074 rates[14] = min(rates[0], rate_info->target_power_54); 3075 3076 /* XR rates */ 3077 rates[15] = min(rates[0], rate_info->target_power_6to24); 3078 3079 /* CCK rates have different peak to average ratio 3080 * so we have to tweak their power so that gainf 3081 * correction works ok. For this we use OFDM to 3082 * CCK delta from eeprom */ 3083 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3084 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3085 for (i = 8; i <= 15; i++) 3086 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3087 3088 /* Now that we have all rates setup use table offset to 3089 * match the power range set by user with the power indices 3090 * on PCDAC/PDADC table */ 3091 for (i = 0; i < 16; i++) { 3092 rates[i] += ah->ah_txpower.txp_offset; 3093 /* Don't get out of bounds */ 3094 if (rates[i] > 63) 3095 rates[i] = 63; 3096 } 3097 3098 /* Min/max in 0.25dB units */ 3099 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3100 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; 3101 ah->ah_txpower.txp_ofdm = rates[7]; 3102 } 3103 3104 3105 /* 3106 * Set transmission power 3107 */ 3108 static int 3109 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3110 u8 txpower) 3111 { 3112 struct ath5k_rate_pcal_info rate_info; 3113 struct ieee80211_channel *curr_channel = ah->ah_current_channel; 3114 int ee_mode; 3115 u8 type; 3116 int ret; 3117 3118 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3119 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3120 return -EINVAL; 3121 } 3122 3123 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3124 if (ee_mode < 0) { 3125 ATH5K_ERR(ah->ah_sc, 3126 "invalid channel: %d\n", channel->center_freq); 3127 return -EINVAL; 3128 } 3129 3130 /* Initialize TX power table */ 3131 switch (ah->ah_radio) { 3132 case AR5K_RF5110: 3133 /* TODO */ 3134 return 0; 3135 case AR5K_RF5111: 3136 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3137 break; 3138 case AR5K_RF5112: 3139 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3140 break; 3141 case AR5K_RF2413: 3142 case AR5K_RF5413: 3143 case AR5K_RF2316: 3144 case AR5K_RF2317: 3145 case AR5K_RF2425: 3146 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3147 break; 3148 default: 3149 return -EINVAL; 3150 } 3151 3152 /* 3153 * If we don't change channel/mode skip tx powertable calculation 3154 * and use the cached one. 3155 */ 3156 if (!ah->ah_txpower.txp_setup || 3157 (channel->hw_value != curr_channel->hw_value) || 3158 (channel->center_freq != curr_channel->center_freq)) { 3159 /* Reset TX power values */ 3160 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3161 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3162 3163 /* Calculate the powertable */ 3164 ret = ath5k_setup_channel_powertable(ah, channel, 3165 ee_mode, type); 3166 if (ret) 3167 return ret; 3168 } 3169 3170 /* Write table on hw */ 3171 ath5k_write_channel_powertable(ah, ee_mode, type); 3172 3173 /* Limit max power if we have a CTL available */ 3174 ath5k_get_max_ctl_power(ah, channel); 3175 3176 /* FIXME: Antenna reduction stuff */ 3177 3178 /* FIXME: Limit power on turbo modes */ 3179 3180 /* FIXME: TPC scale reduction */ 3181 3182 /* Get surounding channels for per-rate power table 3183 * calibration */ 3184 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3185 3186 /* Setup rate power table */ 3187 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3188 3189 /* Write rate power table on hw */ 3190 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3191 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3192 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3193 3194 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3195 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3196 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3197 3198 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3199 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3200 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3201 3202 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3203 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3204 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3205 3206 /* FIXME: TPC support */ 3207 if (ah->ah_txpower.txp_tpc) { 3208 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3209 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3210 3211 ath5k_hw_reg_write(ah, 3212 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3213 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3214 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3215 AR5K_TPC); 3216 } else { 3217 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3218 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3219 } 3220 3221 return 0; 3222 } 3223 3224 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3225 { 3226 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3227 "changing txpower to %d\n", txpower); 3228 3229 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3230 } 3231 3232 /*************\ 3233 Init function 3234 \*************/ 3235 3236 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3237 u8 mode, bool fast) 3238 { 3239 struct ieee80211_channel *curr_channel; 3240 int ret, i; 3241 u32 phy_tst1; 3242 ret = 0; 3243 3244 /* 3245 * Sanity check for fast flag 3246 * Don't try fast channel change when changing modulation 3247 * mode/band. We check for chip compatibility on 3248 * ath5k_hw_reset. 3249 */ 3250 curr_channel = ah->ah_current_channel; 3251 if (fast && (channel->hw_value != curr_channel->hw_value)) 3252 return -EINVAL; 3253 3254 /* 3255 * On fast channel change we only set the synth parameters 3256 * while PHY is running, enable calibration and skip the rest. 3257 */ 3258 if (fast) { 3259 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3260 AR5K_PHY_RFBUS_REQ_REQUEST); 3261 for (i = 0; i < 100; i++) { 3262 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3263 break; 3264 udelay(5); 3265 } 3266 /* Failed */ 3267 if (i >= 100) 3268 return -EIO; 3269 3270 /* Set channel and wait for synth */ 3271 ret = ath5k_hw_channel(ah, channel); 3272 if (ret) 3273 return ret; 3274 3275 ath5k_hw_wait_for_synth(ah, channel); 3276 } 3277 3278 /* 3279 * Set TX power 3280 * 3281 * Note: We need to do that before we set 3282 * RF buffer settings on 5211/5212+ so that we 3283 * properly set curve indices. 3284 */ 3285 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ? 3286 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER); 3287 if (ret) 3288 return ret; 3289 3290 /* Write OFDM timings on 5212*/ 3291 if (ah->ah_version == AR5K_AR5212 && 3292 channel->hw_value & CHANNEL_OFDM) { 3293 3294 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3295 if (ret) 3296 return ret; 3297 3298 /* Spur info is available only from EEPROM versions 3299 * greater than 5.3, but the EEPROM routines will use 3300 * static values for older versions */ 3301 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3302 ath5k_hw_set_spur_mitigation_filter(ah, 3303 channel); 3304 } 3305 3306 /* If we used fast channel switching 3307 * we are done, release RF bus and 3308 * fire up NF calibration. 3309 * 3310 * Note: Only NF calibration due to 3311 * channel change, not AGC calibration 3312 * since AGC is still running ! 3313 */ 3314 if (fast) { 3315 /* 3316 * Release RF Bus grant 3317 */ 3318 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3319 AR5K_PHY_RFBUS_REQ_REQUEST); 3320 3321 /* 3322 * Start NF calibration 3323 */ 3324 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3325 AR5K_PHY_AGCCTL_NF); 3326 3327 return ret; 3328 } 3329 3330 /* 3331 * For 5210 we do all initialization using 3332 * initvals, so we don't have to modify 3333 * any settings (5210 also only supports 3334 * a/aturbo modes) 3335 */ 3336 if (ah->ah_version != AR5K_AR5210) { 3337 3338 /* 3339 * Write initial RF gain settings 3340 * This should work for both 5111/5112 3341 */ 3342 ret = ath5k_hw_rfgain_init(ah, channel->band); 3343 if (ret) 3344 return ret; 3345 3346 mdelay(1); 3347 3348 /* 3349 * Write RF buffer 3350 */ 3351 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3352 if (ret) 3353 return ret; 3354 3355 /*Enable/disable 802.11b mode on 5111 3356 (enable 2111 frequency converter + CCK)*/ 3357 if (ah->ah_radio == AR5K_RF5111) { 3358 if (mode == AR5K_MODE_11B) 3359 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3360 AR5K_TXCFG_B_MODE); 3361 else 3362 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3363 AR5K_TXCFG_B_MODE); 3364 } 3365 3366 } else if (ah->ah_version == AR5K_AR5210) { 3367 mdelay(1); 3368 /* Disable phy and wait */ 3369 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3370 mdelay(1); 3371 } 3372 3373 /* Set channel on PHY */ 3374 ret = ath5k_hw_channel(ah, channel); 3375 if (ret) 3376 return ret; 3377 3378 /* 3379 * Enable the PHY and wait until completion 3380 * This includes BaseBand and Synthesizer 3381 * activation. 3382 */ 3383 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3384 3385 ath5k_hw_wait_for_synth(ah, channel); 3386 3387 /* 3388 * Perform ADC test to see if baseband is ready 3389 * Set tx hold and check adc test register 3390 */ 3391 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3392 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3393 for (i = 0; i <= 20; i++) { 3394 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3395 break; 3396 udelay(200); 3397 } 3398 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3399 3400 /* 3401 * Start automatic gain control calibration 3402 * 3403 * During AGC calibration RX path is re-routed to 3404 * a power detector so we don't receive anything. 3405 * 3406 * This method is used to calibrate some static offsets 3407 * used together with on-the fly I/Q calibration (the 3408 * one performed via ath5k_hw_phy_calibrate), which doesn't 3409 * interrupt rx path. 3410 * 3411 * While rx path is re-routed to the power detector we also 3412 * start a noise floor calibration to measure the 3413 * card's noise floor (the noise we measure when we are not 3414 * transmitting or receiving anything). 3415 * 3416 * If we are in a noisy environment, AGC calibration may time 3417 * out and/or noise floor calibration might timeout. 3418 */ 3419 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3420 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3421 3422 /* At the same time start I/Q calibration for QAM constellation 3423 * -no need for CCK- */ 3424 ah->ah_calibration = false; 3425 if (!(mode == AR5K_MODE_11B)) { 3426 ah->ah_calibration = true; 3427 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3428 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3429 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3430 AR5K_PHY_IQ_RUN); 3431 } 3432 3433 /* Wait for gain calibration to finish (we check for I/Q calibration 3434 * during ath5k_phy_calibrate) */ 3435 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3436 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3437 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3438 channel->center_freq); 3439 } 3440 3441 /* Restore antenna mode */ 3442 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3443 3444 return ret; 3445 } 3446