1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 33 /** 34 * DOC: Protocol Control Unit (PCU) functions 35 * 36 * Protocol control unit is responsible to maintain various protocol 37 * properties before a frame is send and after a frame is received to/from 38 * baseband. To be more specific, PCU handles: 39 * 40 * - Buffering of RX and TX frames (after QCU/DCUs) 41 * 42 * - Encrypting and decrypting (using the built-in engine) 43 * 44 * - Generating ACKs, RTS/CTS frames 45 * 46 * - Maintaining TSF 47 * 48 * - FCS 49 * 50 * - Updating beacon data (with TSF etc) 51 * 52 * - Generating virtual CCA 53 * 54 * - RX/Multicast filtering 55 * 56 * - BSSID filtering 57 * 58 * - Various statistics 59 * 60 * -Different operating modes: AP, STA, IBSS 61 * 62 * Note: Most of these functions can be tweaked/bypassed so you can do 63 * them on sw above for debugging or research. For more infos check out PCU 64 * registers on reg.h. 65 */ 66 67 /** 68 * DOC: ACK rates 69 * 70 * AR5212+ can use higher rates for ack transmission 71 * based on current tx rate instead of the base rate. 72 * It does this to better utilize channel usage. 73 * There is a mapping between G rates (that cover both 74 * CCK and OFDM) and ack rates that we use when setting 75 * rate -> duration table. This mapping is hw-based so 76 * don't change anything. 77 * 78 * To enable this functionality we must set 79 * ah->ah_ack_bitrate_high to true else base rate is 80 * used (1Mb for CCK, 6Mb for OFDM). 81 */ 82 static const unsigned int ack_rates_high[] = 83 /* Tx -> ACK */ 84 /* 1Mb -> 1Mb */ { 0, 85 /* 2MB -> 2Mb */ 1, 86 /* 5.5Mb -> 2Mb */ 1, 87 /* 11Mb -> 2Mb */ 1, 88 /* 6Mb -> 6Mb */ 4, 89 /* 9Mb -> 6Mb */ 4, 90 /* 12Mb -> 12Mb */ 6, 91 /* 18Mb -> 12Mb */ 6, 92 /* 24Mb -> 24Mb */ 8, 93 /* 36Mb -> 24Mb */ 8, 94 /* 48Mb -> 24Mb */ 8, 95 /* 54Mb -> 24Mb */ 8 }; 96 97 /*******************\ 98 * Helper functions * 99 \*******************/ 100 101 /** 102 * ath5k_hw_get_frame_duration() - Get tx time of a frame 103 * @ah: The &struct ath5k_hw 104 * @band: One of enum nl80211_band 105 * @len: Frame's length in bytes 106 * @rate: The @struct ieee80211_rate 107 * @shortpre: Indicate short preample 108 * 109 * Calculate tx duration of a frame given it's rate and length 110 * It extends ieee80211_generic_frame_duration for non standard 111 * bwmodes. 112 */ 113 int 114 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band, 115 int len, struct ieee80211_rate *rate, bool shortpre) 116 { 117 int sifs, preamble, plcp_bits, sym_time; 118 int bitrate, bits, symbols, symbol_bits; 119 int dur; 120 121 /* Fallback */ 122 if (!ah->ah_bwmode) { 123 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, 124 NULL, band, len, rate); 125 126 /* subtract difference between long and short preamble */ 127 dur = le16_to_cpu(raw_dur); 128 if (shortpre) 129 dur -= 96; 130 131 return dur; 132 } 133 134 bitrate = rate->bitrate; 135 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; 136 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; 137 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; 138 139 switch (ah->ah_bwmode) { 140 case AR5K_BWMODE_40MHZ: 141 sifs = AR5K_INIT_SIFS_TURBO; 142 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; 143 break; 144 case AR5K_BWMODE_10MHZ: 145 sifs = AR5K_INIT_SIFS_HALF_RATE; 146 preamble *= 2; 147 sym_time *= 2; 148 bitrate = DIV_ROUND_UP(bitrate, 2); 149 break; 150 case AR5K_BWMODE_5MHZ: 151 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 152 preamble *= 4; 153 sym_time *= 4; 154 bitrate = DIV_ROUND_UP(bitrate, 4); 155 break; 156 default: 157 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 158 break; 159 } 160 161 bits = plcp_bits + (len << 3); 162 /* Bit rate is in 100Kbits */ 163 symbol_bits = bitrate * sym_time; 164 symbols = DIV_ROUND_UP(bits * 10, symbol_bits); 165 166 dur = sifs + preamble + (sym_time * symbols); 167 168 return dur; 169 } 170 171 /** 172 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode 173 * @ah: The &struct ath5k_hw 174 */ 175 unsigned int 176 ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 177 { 178 struct ieee80211_channel *channel = ah->ah_current_channel; 179 unsigned int slot_time; 180 181 switch (ah->ah_bwmode) { 182 case AR5K_BWMODE_40MHZ: 183 slot_time = AR5K_INIT_SLOT_TIME_TURBO; 184 break; 185 case AR5K_BWMODE_10MHZ: 186 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; 187 break; 188 case AR5K_BWMODE_5MHZ: 189 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; 190 break; 191 case AR5K_BWMODE_DEFAULT: 192 default: 193 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; 194 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) 195 slot_time = AR5K_INIT_SLOT_TIME_B; 196 break; 197 } 198 199 return slot_time; 200 } 201 202 /** 203 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode 204 * @ah: The &struct ath5k_hw 205 */ 206 unsigned int 207 ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 208 { 209 struct ieee80211_channel *channel = ah->ah_current_channel; 210 unsigned int sifs; 211 212 switch (ah->ah_bwmode) { 213 case AR5K_BWMODE_40MHZ: 214 sifs = AR5K_INIT_SIFS_TURBO; 215 break; 216 case AR5K_BWMODE_10MHZ: 217 sifs = AR5K_INIT_SIFS_HALF_RATE; 218 break; 219 case AR5K_BWMODE_5MHZ: 220 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 221 break; 222 case AR5K_BWMODE_DEFAULT: 223 default: 224 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 225 if (channel->band == NL80211_BAND_5GHZ) 226 sifs = AR5K_INIT_SIFS_DEFAULT_A; 227 break; 228 } 229 230 return sifs; 231 } 232 233 /** 234 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics) 235 * @ah: The &struct ath5k_hw 236 * 237 * Reads MIB counters from PCU and updates sw statistics. Is called after a 238 * MIB interrupt, because one of these counters might have reached their maximum 239 * and triggered the MIB interrupt, to let us read and clear the counter. 240 * 241 * NOTE: Is called in interrupt context! 242 */ 243 void 244 ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 245 { 246 struct ath5k_statistics *stats = &ah->stats; 247 248 /* Read-And-Clear */ 249 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 250 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 251 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 252 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 253 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 254 } 255 256 257 /******************\ 258 * ACK/CTS Timeouts * 259 \******************/ 260 261 /** 262 * ath5k_hw_write_rate_duration() - Fill rate code to duration table 263 * @ah: The &struct ath5k_hw 264 * 265 * Write the rate code to duration table upon hw reset. This is a helper for 266 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 267 * the hardware, based on current mode, for each rate. The rates which are 268 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 269 * different rate code so we write their value twice (one for long preamble 270 * and one for short). 271 * 272 * Note: Band doesn't matter here, if we set the values for OFDM it works 273 * on both a and g modes. So all we have to do is set values for all g rates 274 * that include all OFDM and CCK rates. 275 * 276 */ 277 static inline void 278 ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 279 { 280 struct ieee80211_rate *rate; 281 unsigned int i; 282 /* 802.11g covers both OFDM and CCK */ 283 u8 band = NL80211_BAND_2GHZ; 284 285 /* Write rate duration table */ 286 for (i = 0; i < ah->sbands[band].n_bitrates; i++) { 287 u32 reg; 288 u16 tx_time; 289 290 if (ah->ah_ack_bitrate_high) 291 rate = &ah->sbands[band].bitrates[ack_rates_high[i]]; 292 /* CCK -> 1Mb */ 293 else if (i < 4) 294 rate = &ah->sbands[band].bitrates[0]; 295 /* OFDM -> 6Mb */ 296 else 297 rate = &ah->sbands[band].bitrates[4]; 298 299 /* Set ACK timeout */ 300 reg = AR5K_RATE_DUR(rate->hw_value); 301 302 /* An ACK frame consists of 10 bytes. If you add the FCS, 303 * which ieee80211_generic_frame_duration() adds, 304 * its 14 bytes. Note we use the control rate and not the 305 * actual rate for this rate. See mac80211 tx.c 306 * ieee80211_duration() for a brief description of 307 * what rate we should choose to TX ACKs. */ 308 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, 309 rate, false); 310 311 ath5k_hw_reg_write(ah, tx_time, reg); 312 313 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 314 continue; 315 316 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true); 317 ath5k_hw_reg_write(ah, tx_time, 318 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 319 } 320 } 321 322 /** 323 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU 324 * @ah: The &struct ath5k_hw 325 * @timeout: Timeout in usec 326 */ 327 static int 328 ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 329 { 330 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 331 <= timeout) 332 return -EINVAL; 333 334 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 335 ath5k_hw_htoclock(ah, timeout)); 336 337 return 0; 338 } 339 340 /** 341 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU 342 * @ah: The &struct ath5k_hw 343 * @timeout: Timeout in usec 344 */ 345 static int 346 ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 347 { 348 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 349 <= timeout) 350 return -EINVAL; 351 352 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 353 ath5k_hw_htoclock(ah, timeout)); 354 355 return 0; 356 } 357 358 359 /*******************\ 360 * RX filter Control * 361 \*******************/ 362 363 /** 364 * ath5k_hw_set_lladdr() - Set station id 365 * @ah: The &struct ath5k_hw 366 * @mac: The card's mac address (array of octets) 367 * 368 * Set station id on hw using the provided mac address 369 */ 370 int 371 ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 372 { 373 struct ath_common *common = ath5k_hw_common(ah); 374 u32 low_id, high_id; 375 u32 pcu_reg; 376 377 /* Set new station ID */ 378 memcpy(common->macaddr, mac, ETH_ALEN); 379 380 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 381 382 low_id = get_unaligned_le32(mac); 383 high_id = get_unaligned_le16(mac + 4); 384 385 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 386 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 387 388 return 0; 389 } 390 391 /** 392 * ath5k_hw_set_bssid() - Set current BSSID on hw 393 * @ah: The &struct ath5k_hw 394 * 395 * Sets the current BSSID and BSSID mask we have from the 396 * common struct into the hardware 397 */ 398 void 399 ath5k_hw_set_bssid(struct ath5k_hw *ah) 400 { 401 struct ath_common *common = ath5k_hw_common(ah); 402 u16 tim_offset = 0; 403 404 /* 405 * Set BSSID mask on 5212 406 */ 407 if (ah->ah_version == AR5K_AR5212) 408 ath_hw_setbssidmask(common); 409 410 /* 411 * Set BSSID 412 */ 413 ath5k_hw_reg_write(ah, 414 get_unaligned_le32(common->curbssid), 415 AR5K_BSS_ID0); 416 ath5k_hw_reg_write(ah, 417 get_unaligned_le16(common->curbssid + 4) | 418 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 419 AR5K_BSS_ID1); 420 421 if (common->curaid == 0) { 422 ath5k_hw_disable_pspoll(ah); 423 return; 424 } 425 426 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 427 tim_offset ? tim_offset + 4 : 0); 428 429 ath5k_hw_enable_pspoll(ah, NULL, 0); 430 } 431 432 /** 433 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen 434 * @ah: The &struct ath5k_hw 435 * @mask: The BSSID mask to set (array of octets) 436 * 437 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU 438 * which bits of the interface's MAC address should be looked at when trying 439 * to decide which packets to ACK. In station mode and AP mode with a single 440 * BSS every bit matters since we lock to only one BSS. In AP mode with 441 * multiple BSSes (virtual interfaces) not every bit matters because hw must 442 * accept frames for all BSSes and so we tweak some bits of our mac address 443 * in order to have multiple BSSes. 444 * 445 * For more information check out ../hw.c of the common ath module. 446 */ 447 void 448 ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 449 { 450 struct ath_common *common = ath5k_hw_common(ah); 451 452 /* Cache bssid mask so that we can restore it 453 * on reset */ 454 memcpy(common->bssidmask, mask, ETH_ALEN); 455 if (ah->ah_version == AR5K_AR5212) 456 ath_hw_setbssidmask(common); 457 } 458 459 /** 460 * ath5k_hw_set_mcast_filter() - Set multicast filter 461 * @ah: The &struct ath5k_hw 462 * @filter0: Lower 32bits of muticast filter 463 * @filter1: Higher 16bits of multicast filter 464 */ 465 void 466 ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 467 { 468 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 469 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 470 } 471 472 /** 473 * ath5k_hw_get_rx_filter() - Get current rx filter 474 * @ah: The &struct ath5k_hw 475 * 476 * Returns the RX filter by reading rx filter and 477 * phy error filter registers. RX filter is used 478 * to set the allowed frame types that PCU will accept 479 * and pass to the driver. For a list of frame types 480 * check out reg.h. 481 */ 482 u32 483 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 484 { 485 u32 data, filter = 0; 486 487 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 488 489 /*Radar detection for 5212*/ 490 if (ah->ah_version == AR5K_AR5212) { 491 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 492 493 if (data & AR5K_PHY_ERR_FIL_RADAR) 494 filter |= AR5K_RX_FILTER_RADARERR; 495 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 496 filter |= AR5K_RX_FILTER_PHYERR; 497 } 498 499 return filter; 500 } 501 502 /** 503 * ath5k_hw_set_rx_filter() - Set rx filter 504 * @ah: The &struct ath5k_hw 505 * @filter: RX filter mask (see reg.h) 506 * 507 * Sets RX filter register and also handles PHY error filter 508 * register on 5212 and newer chips so that we have proper PHY 509 * error reporting. 510 */ 511 void 512 ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 513 { 514 u32 data = 0; 515 516 /* Set PHY error filter register on 5212*/ 517 if (ah->ah_version == AR5K_AR5212) { 518 if (filter & AR5K_RX_FILTER_RADARERR) 519 data |= AR5K_PHY_ERR_FIL_RADAR; 520 if (filter & AR5K_RX_FILTER_PHYERR) 521 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 522 } 523 524 /* 525 * The AR5210 uses promiscuous mode to detect radar activity 526 */ 527 if (ah->ah_version == AR5K_AR5210 && 528 (filter & AR5K_RX_FILTER_RADARERR)) { 529 filter &= ~AR5K_RX_FILTER_RADARERR; 530 filter |= AR5K_RX_FILTER_PROM; 531 } 532 533 /*Zero length DMA (phy error reporting) */ 534 if (data) 535 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 536 else 537 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 538 539 /*Write RX Filter register*/ 540 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 541 542 /*Write PHY error filter register on 5212*/ 543 if (ah->ah_version == AR5K_AR5212) 544 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 545 546 } 547 548 549 /****************\ 550 * Beacon control * 551 \****************/ 552 553 #define ATH5K_MAX_TSF_READ 10 554 555 /** 556 * ath5k_hw_get_tsf64() - Get the full 64bit TSF 557 * @ah: The &struct ath5k_hw 558 * 559 * Returns the current TSF 560 */ 561 u64 562 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 563 { 564 u32 tsf_lower, tsf_upper1, tsf_upper2; 565 int i; 566 unsigned long flags; 567 568 /* This code is time critical - we don't want to be interrupted here */ 569 local_irq_save(flags); 570 571 /* 572 * While reading TSF upper and then lower part, the clock is still 573 * counting (or jumping in case of IBSS merge) so we might get 574 * inconsistent values. To avoid this, we read the upper part again 575 * and check it has not been changed. We make the hypothesis that a 576 * maximum of 3 changes can happens in a row (we use 10 as a safe 577 * value). 578 * 579 * Impact on performance is pretty small, since in most cases, only 580 * 3 register reads are needed. 581 */ 582 583 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 584 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { 585 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 586 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 587 if (tsf_upper2 == tsf_upper1) 588 break; 589 tsf_upper1 = tsf_upper2; 590 } 591 592 local_irq_restore(flags); 593 594 WARN_ON(i == ATH5K_MAX_TSF_READ); 595 596 return ((u64)tsf_upper1 << 32) | tsf_lower; 597 } 598 599 #undef ATH5K_MAX_TSF_READ 600 601 /** 602 * ath5k_hw_set_tsf64() - Set a new 64bit TSF 603 * @ah: The &struct ath5k_hw 604 * @tsf64: The new 64bit TSF 605 * 606 * Sets the new TSF 607 */ 608 void 609 ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 610 { 611 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 612 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 613 } 614 615 /** 616 * ath5k_hw_reset_tsf() - Force a TSF reset 617 * @ah: The &struct ath5k_hw 618 * 619 * Forces a TSF reset on PCU 620 */ 621 void 622 ath5k_hw_reset_tsf(struct ath5k_hw *ah) 623 { 624 u32 val; 625 626 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 627 628 /* 629 * Each write to the RESET_TSF bit toggles a hardware internal 630 * signal to reset TSF, but if left high it will cause a TSF reset 631 * on the next chip reset as well. Thus we always write the value 632 * twice to clear the signal. 633 */ 634 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 635 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 636 } 637 638 /** 639 * ath5k_hw_init_beacon_timers() - Initialize beacon timers 640 * @ah: The &struct ath5k_hw 641 * @next_beacon: Next TBTT 642 * @interval: Current beacon interval 643 * 644 * This function is used to initialize beacon timers based on current 645 * operation mode and settings. 646 */ 647 void 648 ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 649 { 650 u32 timer1, timer2, timer3; 651 652 /* 653 * Set the additional timers by mode 654 */ 655 switch (ah->opmode) { 656 case NL80211_IFTYPE_MONITOR: 657 case NL80211_IFTYPE_STATION: 658 /* In STA mode timer1 is used as next wakeup 659 * timer and timer2 as next CFP duration start 660 * timer. Both in 1/8TUs. */ 661 /* TODO: PCF handling */ 662 if (ah->ah_version == AR5K_AR5210) { 663 timer1 = 0xffffffff; 664 timer2 = 0xffffffff; 665 } else { 666 timer1 = 0x0000ffff; 667 timer2 = 0x0007ffff; 668 } 669 /* Mark associated AP as PCF incapable for now */ 670 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 671 break; 672 case NL80211_IFTYPE_ADHOC: 673 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 674 fallthrough; 675 default: 676 /* On non-STA modes timer1 is used as next DMA 677 * beacon alert (DBA) timer and timer2 as next 678 * software beacon alert. Both in 1/8TUs. */ 679 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 680 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 681 break; 682 } 683 684 /* Timer3 marks the end of our ATIM window 685 * a zero length window is not allowed because 686 * we 'll get no beacons */ 687 timer3 = next_beacon + 1; 688 689 /* 690 * Set the beacon register and enable all timers. 691 */ 692 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 693 if (ah->opmode == NL80211_IFTYPE_AP || 694 ah->opmode == NL80211_IFTYPE_MESH_POINT) 695 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 696 697 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 698 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 699 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 700 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 701 702 /* Force a TSF reset if requested and enable beacons */ 703 if (interval & AR5K_BEACON_RESET_TSF) 704 ath5k_hw_reset_tsf(ah); 705 706 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 707 AR5K_BEACON_ENABLE), 708 AR5K_BEACON); 709 710 /* Flush any pending BMISS interrupts on ISR by 711 * performing a clear-on-write operation on PISR 712 * register for the BMISS bit (writing a bit on 713 * ISR toggles a reset for that bit and leaves 714 * the remaining bits intact) */ 715 if (ah->ah_version == AR5K_AR5210) 716 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 717 else 718 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 719 720 /* TODO: Set enhanced sleep registers on AR5212 721 * based on vif->bss_conf params, until then 722 * disable power save reporting.*/ 723 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 724 725 } 726 727 /** 728 * ath5k_check_timer_win() - Check if timer B is timer A + window 729 * @a: timer a (before b) 730 * @b: timer b (after a) 731 * @window: difference between a and b 732 * @intval: timers are increased by this interval 733 * 734 * This helper function checks if timer B is timer A + window and covers 735 * cases where timer A or B might have already been updated or wrapped 736 * around (Timers are 16 bit). 737 * 738 * Returns true if O.K. 739 */ 740 static inline bool 741 ath5k_check_timer_win(int a, int b, int window, int intval) 742 { 743 /* 744 * 1.) usually B should be A + window 745 * 2.) A already updated, B not updated yet 746 * 3.) A already updated and has wrapped around 747 * 4.) B has wrapped around 748 */ 749 if ((b - a == window) || /* 1.) */ 750 (a - b == intval - window) || /* 2.) */ 751 ((a | 0x10000) - b == intval - window) || /* 3.) */ 752 ((b | 0x10000) - a == window)) /* 4.) */ 753 return true; /* O.K. */ 754 return false; 755 } 756 757 /** 758 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct 759 * @ah: The &struct ath5k_hw 760 * @intval: beacon interval 761 * 762 * This is a workaround for IBSS mode 763 * 764 * The need for this function arises from the fact that we have 4 separate 765 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 766 * next beacon target time (NBTT), and that the HW updates these timers 767 * separately based on the current TSF value. The hardware increments each 768 * timer by the beacon interval, when the local TSF converted to TU is equal 769 * to the value stored in the timer. 770 * 771 * The reception of a beacon with the same BSSID can update the local HW TSF 772 * at any time - this is something we can't avoid. If the TSF jumps to a 773 * time which is later than the time stored in a timer, this timer will not 774 * be updated until the TSF in TU wraps around at 16 bit (the size of the 775 * timers) and reaches the time which is stored in the timer. 776 * 777 * The problem is that these timers are closely related to TIMER0 (NBTT) and 778 * that they define a time "window". When the TSF jumps between two timers 779 * (e.g. ATIM and NBTT), the one in the past will be left behind (not 780 * updated), while the one in the future will be updated every beacon 781 * interval. This causes the window to get larger, until the TSF wraps 782 * around as described above and the timer which was left behind gets 783 * updated again. But - because the beacon interval is usually not an exact 784 * divisor of the size of the timers (16 bit), an unwanted "window" between 785 * these timers has developed! 786 * 787 * This is especially important with the ATIM window, because during 788 * the ATIM window only ATIM frames and no data frames are allowed to be 789 * sent, which creates transmission pauses after each beacon. This symptom 790 * has been described as "ramping ping" because ping times increase linearly 791 * for some time and then drop down again. A wrong window on the DMA beacon 792 * timer has the same effect, so we check for these two conditions. 793 * 794 * Returns true if O.K. 795 */ 796 bool 797 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) 798 { 799 unsigned int nbtt, atim, dma; 800 801 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); 802 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); 803 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 804 805 /* NOTE: SWBA is different. Having a wrong window there does not 806 * stop us from sending data and this condition is caught by 807 * other means (SWBA interrupt) */ 808 809 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 810 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, 811 intval)) 812 return true; /* O.K. */ 813 return false; 814 } 815 816 /** 817 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class 818 * @ah: The &struct ath5k_hw 819 * @coverage_class: IEEE 802.11 coverage class number 820 * 821 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 822 */ 823 void 824 ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 825 { 826 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 827 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 828 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 829 int cts_timeout = ack_timeout; 830 831 ath5k_hw_set_ifs_intervals(ah, slot_time); 832 ath5k_hw_set_ack_timeout(ah, ack_timeout); 833 ath5k_hw_set_cts_timeout(ah, cts_timeout); 834 835 ah->ah_coverage_class = coverage_class; 836 } 837 838 /***************************\ 839 * Init/Start/Stop functions * 840 \***************************/ 841 842 /** 843 * ath5k_hw_start_rx_pcu() - Start RX engine 844 * @ah: The &struct ath5k_hw 845 * 846 * Starts RX engine on PCU so that hw can process RXed frames 847 * (ACK etc). 848 * 849 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 850 */ 851 void 852 ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 853 { 854 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 855 } 856 857 /** 858 * ath5k_hw_stop_rx_pcu() - Stop RX engine 859 * @ah: The &struct ath5k_hw 860 * 861 * Stops RX engine on PCU 862 */ 863 void 864 ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 865 { 866 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 867 } 868 869 /** 870 * ath5k_hw_set_opmode() - Set PCU operating mode 871 * @ah: The &struct ath5k_hw 872 * @op_mode: One of enum nl80211_iftype 873 * 874 * Configure PCU for the various operating modes (AP/STA etc) 875 */ 876 int 877 ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 878 { 879 struct ath_common *common = ath5k_hw_common(ah); 880 u32 pcu_reg, beacon_reg, low_id, high_id; 881 882 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 883 884 /* Preserve rest settings */ 885 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 886 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 887 | AR5K_STA_ID1_KEYSRCH_MODE 888 | (ah->ah_version == AR5K_AR5210 ? 889 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 890 891 beacon_reg = 0; 892 893 switch (op_mode) { 894 case NL80211_IFTYPE_ADHOC: 895 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 896 beacon_reg |= AR5K_BCR_ADHOC; 897 if (ah->ah_version == AR5K_AR5210) 898 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 899 else 900 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 901 break; 902 903 case NL80211_IFTYPE_AP: 904 case NL80211_IFTYPE_MESH_POINT: 905 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 906 beacon_reg |= AR5K_BCR_AP; 907 if (ah->ah_version == AR5K_AR5210) 908 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 909 else 910 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 911 break; 912 913 case NL80211_IFTYPE_STATION: 914 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 915 | (ah->ah_version == AR5K_AR5210 ? 916 AR5K_STA_ID1_PWR_SV : 0); 917 fallthrough; 918 case NL80211_IFTYPE_MONITOR: 919 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 920 | (ah->ah_version == AR5K_AR5210 ? 921 AR5K_STA_ID1_NO_PSPOLL : 0); 922 break; 923 924 default: 925 return -EINVAL; 926 } 927 928 /* 929 * Set PCU registers 930 */ 931 low_id = get_unaligned_le32(common->macaddr); 932 high_id = get_unaligned_le16(common->macaddr + 4); 933 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 934 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 935 936 /* 937 * Set Beacon Control Register on 5210 938 */ 939 if (ah->ah_version == AR5K_AR5210) 940 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 941 942 return 0; 943 } 944 945 /** 946 * ath5k_hw_pcu_init() - Initialize PCU 947 * @ah: The &struct ath5k_hw 948 * @op_mode: One of enum nl80211_iftype 949 * 950 * This function is used to initialize PCU by setting current 951 * operation mode and various other settings. 952 */ 953 void 954 ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 955 { 956 /* Set bssid and bssid mask */ 957 ath5k_hw_set_bssid(ah); 958 959 /* Set PCU config */ 960 ath5k_hw_set_opmode(ah, op_mode); 961 962 /* Write rate duration table only on AR5212 and if 963 * virtual interface has already been brought up 964 * XXX: rethink this after new mode changes to 965 * mac80211 are integrated */ 966 if (ah->ah_version == AR5K_AR5212 && 967 ah->nvifs) 968 ath5k_hw_write_rate_duration(ah); 969 970 /* Set RSSI/BRSSI thresholds 971 * 972 * Note: If we decide to set this value 973 * dynamically, have in mind that when AR5K_RSSI_THR 974 * register is read it might return 0x40 if we haven't 975 * wrote anything to it plus BMISS RSSI threshold is zeroed. 976 * So doing a save/restore procedure here isn't the right 977 * choice. Instead store it on ath5k_hw */ 978 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 979 AR5K_TUNE_BMISS_THRES << 980 AR5K_RSSI_THR_BMISS_S), 981 AR5K_RSSI_THR); 982 983 /* MIC QoS support */ 984 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 985 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 986 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 987 } 988 989 /* QoS NOACK Policy */ 990 if (ah->ah_version == AR5K_AR5212) { 991 ath5k_hw_reg_write(ah, 992 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 993 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 994 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 995 AR5K_QOS_NOACK); 996 } 997 998 /* Restore slot time and ACK timeouts */ 999 if (ah->ah_coverage_class > 0) 1000 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 1001 1002 /* Set ACK bitrate mode (see ack_rates_high) */ 1003 if (ah->ah_version == AR5K_AR5212) { 1004 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 1005 if (ah->ah_ack_bitrate_high) 1006 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 1007 else 1008 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 1009 } 1010 return; 1011 } 1012