1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 #include "base.h" 33 34 /* 35 * AR5212+ can use higher rates for ack transmition 36 * based on current tx rate instead of the base rate. 37 * It does this to better utilize channel usage. 38 * This is a mapping between G rates (that cover both 39 * CCK and OFDM) and ack rates that we use when setting 40 * rate -> duration table. This mapping is hw-based so 41 * don't change anything. 42 * 43 * To enable this functionality we must set 44 * ah->ah_ack_bitrate_high to true else base rate is 45 * used (1Mb for CCK, 6Mb for OFDM). 46 */ 47 static const unsigned int ack_rates_high[] = 48 /* Tx -> ACK */ 49 /* 1Mb -> 1Mb */ { 0, 50 /* 2MB -> 2Mb */ 1, 51 /* 5.5Mb -> 2Mb */ 1, 52 /* 11Mb -> 2Mb */ 1, 53 /* 6Mb -> 6Mb */ 4, 54 /* 9Mb -> 6Mb */ 4, 55 /* 12Mb -> 12Mb */ 6, 56 /* 18Mb -> 12Mb */ 6, 57 /* 24Mb -> 24Mb */ 8, 58 /* 36Mb -> 24Mb */ 8, 59 /* 48Mb -> 24Mb */ 8, 60 /* 54Mb -> 24Mb */ 8 }; 61 62 /*******************\ 63 * Helper functions * 64 \*******************/ 65 66 /** 67 * ath5k_hw_get_frame_duration - Get tx time of a frame 68 * 69 * @ah: The &struct ath5k_hw 70 * @len: Frame's length in bytes 71 * @rate: The @struct ieee80211_rate 72 * 73 * Calculate tx duration of a frame given it's rate and length 74 * It extends ieee80211_generic_frame_duration for non standard 75 * bwmodes. 76 */ 77 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 78 int len, struct ieee80211_rate *rate) 79 { 80 struct ath5k_softc *sc = ah->ah_sc; 81 int sifs, preamble, plcp_bits, sym_time; 82 int bitrate, bits, symbols, symbol_bits; 83 int dur; 84 85 /* Fallback */ 86 if (!ah->ah_bwmode) { 87 dur = ieee80211_generic_frame_duration(sc->hw, 88 NULL, len, rate); 89 return dur; 90 } 91 92 bitrate = rate->bitrate; 93 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; 94 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; 95 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; 96 97 switch (ah->ah_bwmode) { 98 case AR5K_BWMODE_40MHZ: 99 sifs = AR5K_INIT_SIFS_TURBO; 100 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; 101 break; 102 case AR5K_BWMODE_10MHZ: 103 sifs = AR5K_INIT_SIFS_HALF_RATE; 104 preamble *= 2; 105 sym_time *= 2; 106 break; 107 case AR5K_BWMODE_5MHZ: 108 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 109 preamble *= 4; 110 sym_time *= 4; 111 break; 112 default: 113 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 114 break; 115 } 116 117 bits = plcp_bits + (len << 3); 118 /* Bit rate is in 100Kbits */ 119 symbol_bits = bitrate * sym_time; 120 symbols = DIV_ROUND_UP(bits * 10, symbol_bits); 121 122 dur = sifs + preamble + (sym_time * symbols); 123 124 return dur; 125 } 126 127 /** 128 * ath5k_hw_get_default_slottime - Get the default slot time for current mode 129 * 130 * @ah: The &struct ath5k_hw 131 */ 132 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 133 { 134 struct ieee80211_channel *channel = ah->ah_current_channel; 135 unsigned int slot_time; 136 137 switch (ah->ah_bwmode) { 138 case AR5K_BWMODE_40MHZ: 139 slot_time = AR5K_INIT_SLOT_TIME_TURBO; 140 break; 141 case AR5K_BWMODE_10MHZ: 142 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; 143 break; 144 case AR5K_BWMODE_5MHZ: 145 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; 146 break; 147 case AR5K_BWMODE_DEFAULT: 148 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; 149 default: 150 if (channel->hw_value & CHANNEL_CCK) 151 slot_time = AR5K_INIT_SLOT_TIME_B; 152 break; 153 } 154 155 return slot_time; 156 } 157 158 /** 159 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode 160 * 161 * @ah: The &struct ath5k_hw 162 */ 163 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 164 { 165 struct ieee80211_channel *channel = ah->ah_current_channel; 166 unsigned int sifs; 167 168 switch (ah->ah_bwmode) { 169 case AR5K_BWMODE_40MHZ: 170 sifs = AR5K_INIT_SIFS_TURBO; 171 break; 172 case AR5K_BWMODE_10MHZ: 173 sifs = AR5K_INIT_SIFS_HALF_RATE; 174 break; 175 case AR5K_BWMODE_5MHZ: 176 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 177 break; 178 case AR5K_BWMODE_DEFAULT: 179 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 180 default: 181 if (channel->hw_value & CHANNEL_5GHZ) 182 sifs = AR5K_INIT_SIFS_DEFAULT_A; 183 break; 184 } 185 186 return sifs; 187 } 188 189 /** 190 * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics) 191 * 192 * @ah: The &struct ath5k_hw 193 * 194 * Reads MIB counters from PCU and updates sw statistics. Is called after a 195 * MIB interrupt, because one of these counters might have reached their maximum 196 * and triggered the MIB interrupt, to let us read and clear the counter. 197 * 198 * Is called in interrupt context! 199 */ 200 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 201 { 202 struct ath5k_statistics *stats = &ah->ah_sc->stats; 203 204 /* Read-And-Clear */ 205 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 206 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 207 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 208 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 209 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 210 } 211 212 213 /******************\ 214 * ACK/CTS Timeouts * 215 \******************/ 216 217 /** 218 * ath5k_hw_write_rate_duration - fill rate code to duration table 219 * 220 * @ah: the &struct ath5k_hw 221 * @mode: one of enum ath5k_driver_mode 222 * 223 * Write the rate code to duration table upon hw reset. This is a helper for 224 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 225 * the hardware, based on current mode, for each rate. The rates which are 226 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 227 * different rate code so we write their value twice (one for long preamble 228 * and one for short). 229 * 230 * Note: Band doesn't matter here, if we set the values for OFDM it works 231 * on both a and g modes. So all we have to do is set values for all g rates 232 * that include all OFDM and CCK rates. 233 * 234 */ 235 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 236 { 237 struct ath5k_softc *sc = ah->ah_sc; 238 struct ieee80211_rate *rate; 239 unsigned int i; 240 /* 802.11g covers both OFDM and CCK */ 241 u8 band = IEEE80211_BAND_2GHZ; 242 243 /* Write rate duration table */ 244 for (i = 0; i < sc->sbands[band].n_bitrates; i++) { 245 u32 reg; 246 u16 tx_time; 247 248 if (ah->ah_ack_bitrate_high) 249 rate = &sc->sbands[band].bitrates[ack_rates_high[i]]; 250 /* CCK -> 1Mb */ 251 else if (i < 4) 252 rate = &sc->sbands[band].bitrates[0]; 253 /* OFDM -> 6Mb */ 254 else 255 rate = &sc->sbands[band].bitrates[4]; 256 257 /* Set ACK timeout */ 258 reg = AR5K_RATE_DUR(rate->hw_value); 259 260 /* An ACK frame consists of 10 bytes. If you add the FCS, 261 * which ieee80211_generic_frame_duration() adds, 262 * its 14 bytes. Note we use the control rate and not the 263 * actual rate for this rate. See mac80211 tx.c 264 * ieee80211_duration() for a brief description of 265 * what rate we should choose to TX ACKs. */ 266 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate); 267 268 tx_time = le16_to_cpu(tx_time); 269 270 ath5k_hw_reg_write(ah, tx_time, reg); 271 272 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 273 continue; 274 275 /* 276 * We're not distinguishing short preamble here, 277 * This is true, all we'll get is a longer value here 278 * which is not necessarilly bad. We could use 279 * export ieee80211_frame_duration() but that needs to be 280 * fixed first to be properly used by mac802111 drivers: 281 * 282 * - remove erp stuff and let the routine figure ofdm 283 * erp rates 284 * - remove passing argument ieee80211_local as 285 * drivers don't have access to it 286 * - move drivers using ieee80211_generic_frame_duration() 287 * to this 288 */ 289 ath5k_hw_reg_write(ah, tx_time, 290 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 291 } 292 } 293 294 /** 295 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 296 * 297 * @ah: The &struct ath5k_hw 298 * @timeout: Timeout in usec 299 */ 300 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 301 { 302 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 303 <= timeout) 304 return -EINVAL; 305 306 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 307 ath5k_hw_htoclock(ah, timeout)); 308 309 return 0; 310 } 311 312 /** 313 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 314 * 315 * @ah: The &struct ath5k_hw 316 * @timeout: Timeout in usec 317 */ 318 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 319 { 320 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 321 <= timeout) 322 return -EINVAL; 323 324 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 325 ath5k_hw_htoclock(ah, timeout)); 326 327 return 0; 328 } 329 330 331 /*******************\ 332 * RX filter Control * 333 \*******************/ 334 335 /** 336 * ath5k_hw_set_lladdr - Set station id 337 * 338 * @ah: The &struct ath5k_hw 339 * @mac: The card's mac address 340 * 341 * Set station id on hw using the provided mac address 342 */ 343 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 344 { 345 struct ath_common *common = ath5k_hw_common(ah); 346 u32 low_id, high_id; 347 u32 pcu_reg; 348 349 /* Set new station ID */ 350 memcpy(common->macaddr, mac, ETH_ALEN); 351 352 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 353 354 low_id = get_unaligned_le32(mac); 355 high_id = get_unaligned_le16(mac + 4); 356 357 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 358 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 359 360 return 0; 361 } 362 363 /** 364 * ath5k_hw_set_bssid - Set current BSSID on hw 365 * 366 * @ah: The &struct ath5k_hw 367 * 368 * Sets the current BSSID and BSSID mask we have from the 369 * common struct into the hardware 370 */ 371 void ath5k_hw_set_bssid(struct ath5k_hw *ah) 372 { 373 struct ath_common *common = ath5k_hw_common(ah); 374 u16 tim_offset = 0; 375 376 /* 377 * Set BSSID mask on 5212 378 */ 379 if (ah->ah_version == AR5K_AR5212) 380 ath_hw_setbssidmask(common); 381 382 /* 383 * Set BSSID 384 */ 385 ath5k_hw_reg_write(ah, 386 get_unaligned_le32(common->curbssid), 387 AR5K_BSS_ID0); 388 ath5k_hw_reg_write(ah, 389 get_unaligned_le16(common->curbssid + 4) | 390 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 391 AR5K_BSS_ID1); 392 393 if (common->curaid == 0) { 394 ath5k_hw_disable_pspoll(ah); 395 return; 396 } 397 398 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 399 tim_offset ? tim_offset + 4 : 0); 400 401 ath5k_hw_enable_pspoll(ah, NULL, 0); 402 } 403 404 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 405 { 406 struct ath_common *common = ath5k_hw_common(ah); 407 408 /* Cache bssid mask so that we can restore it 409 * on reset */ 410 memcpy(common->bssidmask, mask, ETH_ALEN); 411 if (ah->ah_version == AR5K_AR5212) 412 ath_hw_setbssidmask(common); 413 } 414 415 /* 416 * Set multicast filter 417 */ 418 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 419 { 420 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 421 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 422 } 423 424 /** 425 * ath5k_hw_get_rx_filter - Get current rx filter 426 * 427 * @ah: The &struct ath5k_hw 428 * 429 * Returns the RX filter by reading rx filter and 430 * phy error filter registers. RX filter is used 431 * to set the allowed frame types that PCU will accept 432 * and pass to the driver. For a list of frame types 433 * check out reg.h. 434 */ 435 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 436 { 437 u32 data, filter = 0; 438 439 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 440 441 /*Radar detection for 5212*/ 442 if (ah->ah_version == AR5K_AR5212) { 443 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 444 445 if (data & AR5K_PHY_ERR_FIL_RADAR) 446 filter |= AR5K_RX_FILTER_RADARERR; 447 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 448 filter |= AR5K_RX_FILTER_PHYERR; 449 } 450 451 return filter; 452 } 453 454 /** 455 * ath5k_hw_set_rx_filter - Set rx filter 456 * 457 * @ah: The &struct ath5k_hw 458 * @filter: RX filter mask (see reg.h) 459 * 460 * Sets RX filter register and also handles PHY error filter 461 * register on 5212 and newer chips so that we have proper PHY 462 * error reporting. 463 */ 464 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 465 { 466 u32 data = 0; 467 468 /* Set PHY error filter register on 5212*/ 469 if (ah->ah_version == AR5K_AR5212) { 470 if (filter & AR5K_RX_FILTER_RADARERR) 471 data |= AR5K_PHY_ERR_FIL_RADAR; 472 if (filter & AR5K_RX_FILTER_PHYERR) 473 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 474 } 475 476 /* 477 * The AR5210 uses promiscous mode to detect radar activity 478 */ 479 if (ah->ah_version == AR5K_AR5210 && 480 (filter & AR5K_RX_FILTER_RADARERR)) { 481 filter &= ~AR5K_RX_FILTER_RADARERR; 482 filter |= AR5K_RX_FILTER_PROM; 483 } 484 485 /*Zero length DMA (phy error reporting) */ 486 if (data) 487 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 488 else 489 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 490 491 /*Write RX Filter register*/ 492 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 493 494 /*Write PHY error filter register on 5212*/ 495 if (ah->ah_version == AR5K_AR5212) 496 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 497 498 } 499 500 501 /****************\ 502 * Beacon control * 503 \****************/ 504 505 #define ATH5K_MAX_TSF_READ 10 506 507 /** 508 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 509 * 510 * @ah: The &struct ath5k_hw 511 * 512 * Returns the current TSF 513 */ 514 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 515 { 516 u32 tsf_lower, tsf_upper1, tsf_upper2; 517 int i; 518 unsigned long flags; 519 520 /* This code is time critical - we don't want to be interrupted here */ 521 local_irq_save(flags); 522 523 /* 524 * While reading TSF upper and then lower part, the clock is still 525 * counting (or jumping in case of IBSS merge) so we might get 526 * inconsistent values. To avoid this, we read the upper part again 527 * and check it has not been changed. We make the hypothesis that a 528 * maximum of 3 changes can happens in a row (we use 10 as a safe 529 * value). 530 * 531 * Impact on performance is pretty small, since in most cases, only 532 * 3 register reads are needed. 533 */ 534 535 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 536 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { 537 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 538 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 539 if (tsf_upper2 == tsf_upper1) 540 break; 541 tsf_upper1 = tsf_upper2; 542 } 543 544 local_irq_restore(flags); 545 546 WARN_ON( i == ATH5K_MAX_TSF_READ ); 547 548 return (((u64)tsf_upper1 << 32) | tsf_lower); 549 } 550 551 /** 552 * ath5k_hw_set_tsf64 - Set a new 64bit TSF 553 * 554 * @ah: The &struct ath5k_hw 555 * @tsf64: The new 64bit TSF 556 * 557 * Sets the new TSF 558 */ 559 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 560 { 561 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 562 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 563 } 564 565 /** 566 * ath5k_hw_reset_tsf - Force a TSF reset 567 * 568 * @ah: The &struct ath5k_hw 569 * 570 * Forces a TSF reset on PCU 571 */ 572 void ath5k_hw_reset_tsf(struct ath5k_hw *ah) 573 { 574 u32 val; 575 576 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 577 578 /* 579 * Each write to the RESET_TSF bit toggles a hardware internal 580 * signal to reset TSF, but if left high it will cause a TSF reset 581 * on the next chip reset as well. Thus we always write the value 582 * twice to clear the signal. 583 */ 584 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 585 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 586 } 587 588 /* 589 * Initialize beacon timers 590 */ 591 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 592 { 593 u32 timer1, timer2, timer3; 594 595 /* 596 * Set the additional timers by mode 597 */ 598 switch (ah->ah_sc->opmode) { 599 case NL80211_IFTYPE_MONITOR: 600 case NL80211_IFTYPE_STATION: 601 /* In STA mode timer1 is used as next wakeup 602 * timer and timer2 as next CFP duration start 603 * timer. Both in 1/8TUs. */ 604 /* TODO: PCF handling */ 605 if (ah->ah_version == AR5K_AR5210) { 606 timer1 = 0xffffffff; 607 timer2 = 0xffffffff; 608 } else { 609 timer1 = 0x0000ffff; 610 timer2 = 0x0007ffff; 611 } 612 /* Mark associated AP as PCF incapable for now */ 613 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 614 break; 615 case NL80211_IFTYPE_ADHOC: 616 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 617 default: 618 /* On non-STA modes timer1 is used as next DMA 619 * beacon alert (DBA) timer and timer2 as next 620 * software beacon alert. Both in 1/8TUs. */ 621 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 622 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 623 break; 624 } 625 626 /* Timer3 marks the end of our ATIM window 627 * a zero length window is not allowed because 628 * we 'll get no beacons */ 629 timer3 = next_beacon + 1; 630 631 /* 632 * Set the beacon register and enable all timers. 633 */ 634 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 635 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP || 636 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT) 637 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 638 639 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 640 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 641 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 642 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 643 644 /* Force a TSF reset if requested and enable beacons */ 645 if (interval & AR5K_BEACON_RESET_TSF) 646 ath5k_hw_reset_tsf(ah); 647 648 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 649 AR5K_BEACON_ENABLE), 650 AR5K_BEACON); 651 652 /* Flush any pending BMISS interrupts on ISR by 653 * performing a clear-on-write operation on PISR 654 * register for the BMISS bit (writing a bit on 655 * ISR togles a reset for that bit and leaves 656 * the rest bits intact) */ 657 if (ah->ah_version == AR5K_AR5210) 658 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 659 else 660 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 661 662 /* TODO: Set enchanced sleep registers on AR5212 663 * based on vif->bss_conf params, until then 664 * disable power save reporting.*/ 665 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 666 667 } 668 669 /** 670 * ath5k_check_timer_win - Check if timer B is timer A + window 671 * 672 * @a: timer a (before b) 673 * @b: timer b (after a) 674 * @window: difference between a and b 675 * @intval: timers are increased by this interval 676 * 677 * This helper function checks if timer B is timer A + window and covers 678 * cases where timer A or B might have already been updated or wrapped 679 * around (Timers are 16 bit). 680 * 681 * Returns true if O.K. 682 */ 683 static inline bool 684 ath5k_check_timer_win(int a, int b, int window, int intval) 685 { 686 /* 687 * 1.) usually B should be A + window 688 * 2.) A already updated, B not updated yet 689 * 3.) A already updated and has wrapped around 690 * 4.) B has wrapped around 691 */ 692 if ((b - a == window) || /* 1.) */ 693 (a - b == intval - window) || /* 2.) */ 694 ((a | 0x10000) - b == intval - window) || /* 3.) */ 695 ((b | 0x10000) - a == window)) /* 4.) */ 696 return true; /* O.K. */ 697 return false; 698 } 699 700 /** 701 * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct 702 * 703 * @ah: The &struct ath5k_hw 704 * @intval: beacon interval 705 * 706 * This is a workaround for IBSS mode: 707 * 708 * The need for this function arises from the fact that we have 4 separate 709 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 710 * next beacon target time (NBTT), and that the HW updates these timers 711 * seperately based on the current TSF value. The hardware increments each 712 * timer by the beacon interval, when the local TSF coverted to TU is equal 713 * to the value stored in the timer. 714 * 715 * The reception of a beacon with the same BSSID can update the local HW TSF 716 * at any time - this is something we can't avoid. If the TSF jumps to a 717 * time which is later than the time stored in a timer, this timer will not 718 * be updated until the TSF in TU wraps around at 16 bit (the size of the 719 * timers) and reaches the time which is stored in the timer. 720 * 721 * The problem is that these timers are closely related to TIMER0 (NBTT) and 722 * that they define a time "window". When the TSF jumps between two timers 723 * (e.g. ATIM and NBTT), the one in the past will be left behind (not 724 * updated), while the one in the future will be updated every beacon 725 * interval. This causes the window to get larger, until the TSF wraps 726 * around as described above and the timer which was left behind gets 727 * updated again. But - because the beacon interval is usually not an exact 728 * divisor of the size of the timers (16 bit), an unwanted "window" between 729 * these timers has developed! 730 * 731 * This is especially important with the ATIM window, because during 732 * the ATIM window only ATIM frames and no data frames are allowed to be 733 * sent, which creates transmission pauses after each beacon. This symptom 734 * has been described as "ramping ping" because ping times increase linearly 735 * for some time and then drop down again. A wrong window on the DMA beacon 736 * timer has the same effect, so we check for these two conditions. 737 * 738 * Returns true if O.K. 739 */ 740 bool 741 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) 742 { 743 unsigned int nbtt, atim, dma; 744 745 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); 746 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); 747 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 748 749 /* NOTE: SWBA is different. Having a wrong window there does not 750 * stop us from sending data and this condition is catched thru 751 * other means (SWBA interrupt) */ 752 753 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 754 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, 755 intval)) 756 return true; /* O.K. */ 757 return false; 758 } 759 760 /** 761 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class 762 * 763 * @ah: The &struct ath5k_hw 764 * @coverage_class: IEEE 802.11 coverage class number 765 * 766 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 767 */ 768 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 769 { 770 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 771 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 772 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 773 int cts_timeout = ack_timeout; 774 775 ath5k_hw_set_ifs_intervals(ah, slot_time); 776 ath5k_hw_set_ack_timeout(ah, ack_timeout); 777 ath5k_hw_set_cts_timeout(ah, cts_timeout); 778 779 ah->ah_coverage_class = coverage_class; 780 } 781 782 /***************************\ 783 * Init/Start/Stop functions * 784 \***************************/ 785 786 /** 787 * ath5k_hw_start_rx_pcu - Start RX engine 788 * 789 * @ah: The &struct ath5k_hw 790 * 791 * Starts RX engine on PCU so that hw can process RXed frames 792 * (ACK etc). 793 * 794 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 795 */ 796 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 797 { 798 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 799 } 800 801 /** 802 * at5k_hw_stop_rx_pcu - Stop RX engine 803 * 804 * @ah: The &struct ath5k_hw 805 * 806 * Stops RX engine on PCU 807 */ 808 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 809 { 810 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 811 } 812 813 /** 814 * ath5k_hw_set_opmode - Set PCU operating mode 815 * 816 * @ah: The &struct ath5k_hw 817 * @op_mode: &enum nl80211_iftype operating mode 818 * 819 * Configure PCU for the various operating modes (AP/STA etc) 820 */ 821 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 822 { 823 struct ath_common *common = ath5k_hw_common(ah); 824 u32 pcu_reg, beacon_reg, low_id, high_id; 825 826 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 827 828 /* Preserve rest settings */ 829 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 830 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 831 | AR5K_STA_ID1_KEYSRCH_MODE 832 | (ah->ah_version == AR5K_AR5210 ? 833 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 834 835 beacon_reg = 0; 836 837 switch (op_mode) { 838 case NL80211_IFTYPE_ADHOC: 839 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 840 beacon_reg |= AR5K_BCR_ADHOC; 841 if (ah->ah_version == AR5K_AR5210) 842 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 843 else 844 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 845 break; 846 847 case NL80211_IFTYPE_AP: 848 case NL80211_IFTYPE_MESH_POINT: 849 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 850 beacon_reg |= AR5K_BCR_AP; 851 if (ah->ah_version == AR5K_AR5210) 852 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 853 else 854 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 855 break; 856 857 case NL80211_IFTYPE_STATION: 858 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 859 | (ah->ah_version == AR5K_AR5210 ? 860 AR5K_STA_ID1_PWR_SV : 0); 861 case NL80211_IFTYPE_MONITOR: 862 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 863 | (ah->ah_version == AR5K_AR5210 ? 864 AR5K_STA_ID1_NO_PSPOLL : 0); 865 break; 866 867 default: 868 return -EINVAL; 869 } 870 871 /* 872 * Set PCU registers 873 */ 874 low_id = get_unaligned_le32(common->macaddr); 875 high_id = get_unaligned_le16(common->macaddr + 4); 876 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 877 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 878 879 /* 880 * Set Beacon Control Register on 5210 881 */ 882 if (ah->ah_version == AR5K_AR5210) 883 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 884 885 return 0; 886 } 887 888 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 889 u8 mode) 890 { 891 /* Set bssid and bssid mask */ 892 ath5k_hw_set_bssid(ah); 893 894 /* Set PCU config */ 895 ath5k_hw_set_opmode(ah, op_mode); 896 897 /* Write rate duration table only on AR5212 and if 898 * virtual interface has already been brought up 899 * XXX: rethink this after new mode changes to 900 * mac80211 are integrated */ 901 if (ah->ah_version == AR5K_AR5212 && 902 ah->ah_sc->nvifs) 903 ath5k_hw_write_rate_duration(ah); 904 905 /* Set RSSI/BRSSI thresholds 906 * 907 * Note: If we decide to set this value 908 * dynamicaly, have in mind that when AR5K_RSSI_THR 909 * register is read it might return 0x40 if we haven't 910 * wrote anything to it plus BMISS RSSI threshold is zeroed. 911 * So doing a save/restore procedure here isn't the right 912 * choice. Instead store it on ath5k_hw */ 913 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 914 AR5K_TUNE_BMISS_THRES << 915 AR5K_RSSI_THR_BMISS_S), 916 AR5K_RSSI_THR); 917 918 /* MIC QoS support */ 919 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 920 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 921 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 922 } 923 924 /* QoS NOACK Policy */ 925 if (ah->ah_version == AR5K_AR5212) { 926 ath5k_hw_reg_write(ah, 927 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 928 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 929 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 930 AR5K_QOS_NOACK); 931 } 932 933 /* Restore slot time and ACK timeouts */ 934 if (ah->ah_coverage_class > 0) 935 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 936 937 /* Set ACK bitrate mode (see ack_rates_high) */ 938 if (ah->ah_version == AR5K_AR5212) { 939 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 940 if (ah->ah_ack_bitrate_high) 941 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 942 else 943 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 944 } 945 return; 946 } 947