1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 #include "base.h" 33 34 /* 35 * AR5212+ can use higher rates for ack transmission 36 * based on current tx rate instead of the base rate. 37 * It does this to better utilize channel usage. 38 * This is a mapping between G rates (that cover both 39 * CCK and OFDM) and ack rates that we use when setting 40 * rate -> duration table. This mapping is hw-based so 41 * don't change anything. 42 * 43 * To enable this functionality we must set 44 * ah->ah_ack_bitrate_high to true else base rate is 45 * used (1Mb for CCK, 6Mb for OFDM). 46 */ 47 static const unsigned int ack_rates_high[] = 48 /* Tx -> ACK */ 49 /* 1Mb -> 1Mb */ { 0, 50 /* 2MB -> 2Mb */ 1, 51 /* 5.5Mb -> 2Mb */ 1, 52 /* 11Mb -> 2Mb */ 1, 53 /* 6Mb -> 6Mb */ 4, 54 /* 9Mb -> 6Mb */ 4, 55 /* 12Mb -> 12Mb */ 6, 56 /* 18Mb -> 12Mb */ 6, 57 /* 24Mb -> 24Mb */ 8, 58 /* 36Mb -> 24Mb */ 8, 59 /* 48Mb -> 24Mb */ 8, 60 /* 54Mb -> 24Mb */ 8 }; 61 62 /*******************\ 63 * Helper functions * 64 \*******************/ 65 66 /** 67 * ath5k_hw_get_frame_duration - Get tx time of a frame 68 * 69 * @ah: The &struct ath5k_hw 70 * @len: Frame's length in bytes 71 * @rate: The @struct ieee80211_rate 72 * 73 * Calculate tx duration of a frame given it's rate and length 74 * It extends ieee80211_generic_frame_duration for non standard 75 * bwmodes. 76 */ 77 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 78 int len, struct ieee80211_rate *rate, bool shortpre) 79 { 80 int sifs, preamble, plcp_bits, sym_time; 81 int bitrate, bits, symbols, symbol_bits; 82 int dur; 83 84 /* Fallback */ 85 if (!ah->ah_bwmode) { 86 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, 87 NULL, len, rate); 88 89 /* subtract difference between long and short preamble */ 90 dur = le16_to_cpu(raw_dur); 91 if (shortpre) 92 dur -= 96; 93 94 return dur; 95 } 96 97 bitrate = rate->bitrate; 98 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; 99 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; 100 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; 101 102 switch (ah->ah_bwmode) { 103 case AR5K_BWMODE_40MHZ: 104 sifs = AR5K_INIT_SIFS_TURBO; 105 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; 106 break; 107 case AR5K_BWMODE_10MHZ: 108 sifs = AR5K_INIT_SIFS_HALF_RATE; 109 preamble *= 2; 110 sym_time *= 2; 111 break; 112 case AR5K_BWMODE_5MHZ: 113 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 114 preamble *= 4; 115 sym_time *= 4; 116 break; 117 default: 118 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 119 break; 120 } 121 122 bits = plcp_bits + (len << 3); 123 /* Bit rate is in 100Kbits */ 124 symbol_bits = bitrate * sym_time; 125 symbols = DIV_ROUND_UP(bits * 10, symbol_bits); 126 127 dur = sifs + preamble + (sym_time * symbols); 128 129 return dur; 130 } 131 132 /** 133 * ath5k_hw_get_default_slottime - Get the default slot time for current mode 134 * 135 * @ah: The &struct ath5k_hw 136 */ 137 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 138 { 139 struct ieee80211_channel *channel = ah->ah_current_channel; 140 unsigned int slot_time; 141 142 switch (ah->ah_bwmode) { 143 case AR5K_BWMODE_40MHZ: 144 slot_time = AR5K_INIT_SLOT_TIME_TURBO; 145 break; 146 case AR5K_BWMODE_10MHZ: 147 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; 148 break; 149 case AR5K_BWMODE_5MHZ: 150 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; 151 break; 152 case AR5K_BWMODE_DEFAULT: 153 default: 154 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; 155 if ((channel->hw_value & CHANNEL_CCK) && !ah->ah_short_slot) 156 slot_time = AR5K_INIT_SLOT_TIME_B; 157 break; 158 } 159 160 return slot_time; 161 } 162 163 /** 164 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode 165 * 166 * @ah: The &struct ath5k_hw 167 */ 168 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 169 { 170 struct ieee80211_channel *channel = ah->ah_current_channel; 171 unsigned int sifs; 172 173 switch (ah->ah_bwmode) { 174 case AR5K_BWMODE_40MHZ: 175 sifs = AR5K_INIT_SIFS_TURBO; 176 break; 177 case AR5K_BWMODE_10MHZ: 178 sifs = AR5K_INIT_SIFS_HALF_RATE; 179 break; 180 case AR5K_BWMODE_5MHZ: 181 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 182 break; 183 case AR5K_BWMODE_DEFAULT: 184 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 185 default: 186 if (channel->hw_value & CHANNEL_5GHZ) 187 sifs = AR5K_INIT_SIFS_DEFAULT_A; 188 break; 189 } 190 191 return sifs; 192 } 193 194 /** 195 * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics) 196 * 197 * @ah: The &struct ath5k_hw 198 * 199 * Reads MIB counters from PCU and updates sw statistics. Is called after a 200 * MIB interrupt, because one of these counters might have reached their maximum 201 * and triggered the MIB interrupt, to let us read and clear the counter. 202 * 203 * Is called in interrupt context! 204 */ 205 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 206 { 207 struct ath5k_statistics *stats = &ah->stats; 208 209 /* Read-And-Clear */ 210 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 211 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 212 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 213 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 214 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 215 } 216 217 218 /******************\ 219 * ACK/CTS Timeouts * 220 \******************/ 221 222 /** 223 * ath5k_hw_write_rate_duration - fill rate code to duration table 224 * 225 * @ah: the &struct ath5k_hw 226 * @mode: one of enum ath5k_driver_mode 227 * 228 * Write the rate code to duration table upon hw reset. This is a helper for 229 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 230 * the hardware, based on current mode, for each rate. The rates which are 231 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 232 * different rate code so we write their value twice (one for long preamble 233 * and one for short). 234 * 235 * Note: Band doesn't matter here, if we set the values for OFDM it works 236 * on both a and g modes. So all we have to do is set values for all g rates 237 * that include all OFDM and CCK rates. 238 * 239 */ 240 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 241 { 242 struct ieee80211_rate *rate; 243 unsigned int i; 244 /* 802.11g covers both OFDM and CCK */ 245 u8 band = IEEE80211_BAND_2GHZ; 246 247 /* Write rate duration table */ 248 for (i = 0; i < ah->sbands[band].n_bitrates; i++) { 249 u32 reg; 250 u16 tx_time; 251 252 if (ah->ah_ack_bitrate_high) 253 rate = &ah->sbands[band].bitrates[ack_rates_high[i]]; 254 /* CCK -> 1Mb */ 255 else if (i < 4) 256 rate = &ah->sbands[band].bitrates[0]; 257 /* OFDM -> 6Mb */ 258 else 259 rate = &ah->sbands[band].bitrates[4]; 260 261 /* Set ACK timeout */ 262 reg = AR5K_RATE_DUR(rate->hw_value); 263 264 /* An ACK frame consists of 10 bytes. If you add the FCS, 265 * which ieee80211_generic_frame_duration() adds, 266 * its 14 bytes. Note we use the control rate and not the 267 * actual rate for this rate. See mac80211 tx.c 268 * ieee80211_duration() for a brief description of 269 * what rate we should choose to TX ACKs. */ 270 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false); 271 272 ath5k_hw_reg_write(ah, tx_time, reg); 273 274 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 275 continue; 276 277 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true); 278 ath5k_hw_reg_write(ah, tx_time, 279 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 280 } 281 } 282 283 /** 284 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 285 * 286 * @ah: The &struct ath5k_hw 287 * @timeout: Timeout in usec 288 */ 289 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 290 { 291 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 292 <= timeout) 293 return -EINVAL; 294 295 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 296 ath5k_hw_htoclock(ah, timeout)); 297 298 return 0; 299 } 300 301 /** 302 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 303 * 304 * @ah: The &struct ath5k_hw 305 * @timeout: Timeout in usec 306 */ 307 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 308 { 309 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 310 <= timeout) 311 return -EINVAL; 312 313 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 314 ath5k_hw_htoclock(ah, timeout)); 315 316 return 0; 317 } 318 319 320 /*******************\ 321 * RX filter Control * 322 \*******************/ 323 324 /** 325 * ath5k_hw_set_lladdr - Set station id 326 * 327 * @ah: The &struct ath5k_hw 328 * @mac: The card's mac address 329 * 330 * Set station id on hw using the provided mac address 331 */ 332 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 333 { 334 struct ath_common *common = ath5k_hw_common(ah); 335 u32 low_id, high_id; 336 u32 pcu_reg; 337 338 /* Set new station ID */ 339 memcpy(common->macaddr, mac, ETH_ALEN); 340 341 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 342 343 low_id = get_unaligned_le32(mac); 344 high_id = get_unaligned_le16(mac + 4); 345 346 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 347 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 348 349 return 0; 350 } 351 352 /** 353 * ath5k_hw_set_bssid - Set current BSSID on hw 354 * 355 * @ah: The &struct ath5k_hw 356 * 357 * Sets the current BSSID and BSSID mask we have from the 358 * common struct into the hardware 359 */ 360 void ath5k_hw_set_bssid(struct ath5k_hw *ah) 361 { 362 struct ath_common *common = ath5k_hw_common(ah); 363 u16 tim_offset = 0; 364 365 /* 366 * Set BSSID mask on 5212 367 */ 368 if (ah->ah_version == AR5K_AR5212) 369 ath_hw_setbssidmask(common); 370 371 /* 372 * Set BSSID 373 */ 374 ath5k_hw_reg_write(ah, 375 get_unaligned_le32(common->curbssid), 376 AR5K_BSS_ID0); 377 ath5k_hw_reg_write(ah, 378 get_unaligned_le16(common->curbssid + 4) | 379 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 380 AR5K_BSS_ID1); 381 382 if (common->curaid == 0) { 383 ath5k_hw_disable_pspoll(ah); 384 return; 385 } 386 387 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 388 tim_offset ? tim_offset + 4 : 0); 389 390 ath5k_hw_enable_pspoll(ah, NULL, 0); 391 } 392 393 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 394 { 395 struct ath_common *common = ath5k_hw_common(ah); 396 397 /* Cache bssid mask so that we can restore it 398 * on reset */ 399 memcpy(common->bssidmask, mask, ETH_ALEN); 400 if (ah->ah_version == AR5K_AR5212) 401 ath_hw_setbssidmask(common); 402 } 403 404 /* 405 * Set multicast filter 406 */ 407 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 408 { 409 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 410 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 411 } 412 413 /** 414 * ath5k_hw_get_rx_filter - Get current rx filter 415 * 416 * @ah: The &struct ath5k_hw 417 * 418 * Returns the RX filter by reading rx filter and 419 * phy error filter registers. RX filter is used 420 * to set the allowed frame types that PCU will accept 421 * and pass to the driver. For a list of frame types 422 * check out reg.h. 423 */ 424 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 425 { 426 u32 data, filter = 0; 427 428 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 429 430 /*Radar detection for 5212*/ 431 if (ah->ah_version == AR5K_AR5212) { 432 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 433 434 if (data & AR5K_PHY_ERR_FIL_RADAR) 435 filter |= AR5K_RX_FILTER_RADARERR; 436 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 437 filter |= AR5K_RX_FILTER_PHYERR; 438 } 439 440 return filter; 441 } 442 443 /** 444 * ath5k_hw_set_rx_filter - Set rx filter 445 * 446 * @ah: The &struct ath5k_hw 447 * @filter: RX filter mask (see reg.h) 448 * 449 * Sets RX filter register and also handles PHY error filter 450 * register on 5212 and newer chips so that we have proper PHY 451 * error reporting. 452 */ 453 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 454 { 455 u32 data = 0; 456 457 /* Set PHY error filter register on 5212*/ 458 if (ah->ah_version == AR5K_AR5212) { 459 if (filter & AR5K_RX_FILTER_RADARERR) 460 data |= AR5K_PHY_ERR_FIL_RADAR; 461 if (filter & AR5K_RX_FILTER_PHYERR) 462 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 463 } 464 465 /* 466 * The AR5210 uses promiscuous mode to detect radar activity 467 */ 468 if (ah->ah_version == AR5K_AR5210 && 469 (filter & AR5K_RX_FILTER_RADARERR)) { 470 filter &= ~AR5K_RX_FILTER_RADARERR; 471 filter |= AR5K_RX_FILTER_PROM; 472 } 473 474 /*Zero length DMA (phy error reporting) */ 475 if (data) 476 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 477 else 478 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 479 480 /*Write RX Filter register*/ 481 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 482 483 /*Write PHY error filter register on 5212*/ 484 if (ah->ah_version == AR5K_AR5212) 485 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 486 487 } 488 489 490 /****************\ 491 * Beacon control * 492 \****************/ 493 494 #define ATH5K_MAX_TSF_READ 10 495 496 /** 497 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 498 * 499 * @ah: The &struct ath5k_hw 500 * 501 * Returns the current TSF 502 */ 503 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 504 { 505 u32 tsf_lower, tsf_upper1, tsf_upper2; 506 int i; 507 unsigned long flags; 508 509 /* This code is time critical - we don't want to be interrupted here */ 510 local_irq_save(flags); 511 512 /* 513 * While reading TSF upper and then lower part, the clock is still 514 * counting (or jumping in case of IBSS merge) so we might get 515 * inconsistent values. To avoid this, we read the upper part again 516 * and check it has not been changed. We make the hypothesis that a 517 * maximum of 3 changes can happens in a row (we use 10 as a safe 518 * value). 519 * 520 * Impact on performance is pretty small, since in most cases, only 521 * 3 register reads are needed. 522 */ 523 524 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 525 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { 526 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 527 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 528 if (tsf_upper2 == tsf_upper1) 529 break; 530 tsf_upper1 = tsf_upper2; 531 } 532 533 local_irq_restore(flags); 534 535 WARN_ON(i == ATH5K_MAX_TSF_READ); 536 537 return ((u64)tsf_upper1 << 32) | tsf_lower; 538 } 539 540 /** 541 * ath5k_hw_set_tsf64 - Set a new 64bit TSF 542 * 543 * @ah: The &struct ath5k_hw 544 * @tsf64: The new 64bit TSF 545 * 546 * Sets the new TSF 547 */ 548 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 549 { 550 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 551 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 552 } 553 554 /** 555 * ath5k_hw_reset_tsf - Force a TSF reset 556 * 557 * @ah: The &struct ath5k_hw 558 * 559 * Forces a TSF reset on PCU 560 */ 561 void ath5k_hw_reset_tsf(struct ath5k_hw *ah) 562 { 563 u32 val; 564 565 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 566 567 /* 568 * Each write to the RESET_TSF bit toggles a hardware internal 569 * signal to reset TSF, but if left high it will cause a TSF reset 570 * on the next chip reset as well. Thus we always write the value 571 * twice to clear the signal. 572 */ 573 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 574 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 575 } 576 577 /* 578 * Initialize beacon timers 579 */ 580 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 581 { 582 u32 timer1, timer2, timer3; 583 584 /* 585 * Set the additional timers by mode 586 */ 587 switch (ah->opmode) { 588 case NL80211_IFTYPE_MONITOR: 589 case NL80211_IFTYPE_STATION: 590 /* In STA mode timer1 is used as next wakeup 591 * timer and timer2 as next CFP duration start 592 * timer. Both in 1/8TUs. */ 593 /* TODO: PCF handling */ 594 if (ah->ah_version == AR5K_AR5210) { 595 timer1 = 0xffffffff; 596 timer2 = 0xffffffff; 597 } else { 598 timer1 = 0x0000ffff; 599 timer2 = 0x0007ffff; 600 } 601 /* Mark associated AP as PCF incapable for now */ 602 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 603 break; 604 case NL80211_IFTYPE_ADHOC: 605 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 606 default: 607 /* On non-STA modes timer1 is used as next DMA 608 * beacon alert (DBA) timer and timer2 as next 609 * software beacon alert. Both in 1/8TUs. */ 610 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 611 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 612 break; 613 } 614 615 /* Timer3 marks the end of our ATIM window 616 * a zero length window is not allowed because 617 * we 'll get no beacons */ 618 timer3 = next_beacon + 1; 619 620 /* 621 * Set the beacon register and enable all timers. 622 */ 623 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 624 if (ah->opmode == NL80211_IFTYPE_AP || 625 ah->opmode == NL80211_IFTYPE_MESH_POINT) 626 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 627 628 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 629 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 630 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 631 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 632 633 /* Force a TSF reset if requested and enable beacons */ 634 if (interval & AR5K_BEACON_RESET_TSF) 635 ath5k_hw_reset_tsf(ah); 636 637 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 638 AR5K_BEACON_ENABLE), 639 AR5K_BEACON); 640 641 /* Flush any pending BMISS interrupts on ISR by 642 * performing a clear-on-write operation on PISR 643 * register for the BMISS bit (writing a bit on 644 * ISR toggles a reset for that bit and leaves 645 * the remaining bits intact) */ 646 if (ah->ah_version == AR5K_AR5210) 647 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 648 else 649 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 650 651 /* TODO: Set enhanced sleep registers on AR5212 652 * based on vif->bss_conf params, until then 653 * disable power save reporting.*/ 654 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 655 656 } 657 658 /** 659 * ath5k_check_timer_win - Check if timer B is timer A + window 660 * 661 * @a: timer a (before b) 662 * @b: timer b (after a) 663 * @window: difference between a and b 664 * @intval: timers are increased by this interval 665 * 666 * This helper function checks if timer B is timer A + window and covers 667 * cases where timer A or B might have already been updated or wrapped 668 * around (Timers are 16 bit). 669 * 670 * Returns true if O.K. 671 */ 672 static inline bool 673 ath5k_check_timer_win(int a, int b, int window, int intval) 674 { 675 /* 676 * 1.) usually B should be A + window 677 * 2.) A already updated, B not updated yet 678 * 3.) A already updated and has wrapped around 679 * 4.) B has wrapped around 680 */ 681 if ((b - a == window) || /* 1.) */ 682 (a - b == intval - window) || /* 2.) */ 683 ((a | 0x10000) - b == intval - window) || /* 3.) */ 684 ((b | 0x10000) - a == window)) /* 4.) */ 685 return true; /* O.K. */ 686 return false; 687 } 688 689 /** 690 * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct 691 * 692 * @ah: The &struct ath5k_hw 693 * @intval: beacon interval 694 * 695 * This is a workaround for IBSS mode: 696 * 697 * The need for this function arises from the fact that we have 4 separate 698 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 699 * next beacon target time (NBTT), and that the HW updates these timers 700 * separately based on the current TSF value. The hardware increments each 701 * timer by the beacon interval, when the local TSF converted to TU is equal 702 * to the value stored in the timer. 703 * 704 * The reception of a beacon with the same BSSID can update the local HW TSF 705 * at any time - this is something we can't avoid. If the TSF jumps to a 706 * time which is later than the time stored in a timer, this timer will not 707 * be updated until the TSF in TU wraps around at 16 bit (the size of the 708 * timers) and reaches the time which is stored in the timer. 709 * 710 * The problem is that these timers are closely related to TIMER0 (NBTT) and 711 * that they define a time "window". When the TSF jumps between two timers 712 * (e.g. ATIM and NBTT), the one in the past will be left behind (not 713 * updated), while the one in the future will be updated every beacon 714 * interval. This causes the window to get larger, until the TSF wraps 715 * around as described above and the timer which was left behind gets 716 * updated again. But - because the beacon interval is usually not an exact 717 * divisor of the size of the timers (16 bit), an unwanted "window" between 718 * these timers has developed! 719 * 720 * This is especially important with the ATIM window, because during 721 * the ATIM window only ATIM frames and no data frames are allowed to be 722 * sent, which creates transmission pauses after each beacon. This symptom 723 * has been described as "ramping ping" because ping times increase linearly 724 * for some time and then drop down again. A wrong window on the DMA beacon 725 * timer has the same effect, so we check for these two conditions. 726 * 727 * Returns true if O.K. 728 */ 729 bool 730 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) 731 { 732 unsigned int nbtt, atim, dma; 733 734 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); 735 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); 736 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 737 738 /* NOTE: SWBA is different. Having a wrong window there does not 739 * stop us from sending data and this condition is caught by 740 * other means (SWBA interrupt) */ 741 742 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 743 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, 744 intval)) 745 return true; /* O.K. */ 746 return false; 747 } 748 749 /** 750 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class 751 * 752 * @ah: The &struct ath5k_hw 753 * @coverage_class: IEEE 802.11 coverage class number 754 * 755 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 756 */ 757 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 758 { 759 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 760 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 761 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 762 int cts_timeout = ack_timeout; 763 764 ath5k_hw_set_ifs_intervals(ah, slot_time); 765 ath5k_hw_set_ack_timeout(ah, ack_timeout); 766 ath5k_hw_set_cts_timeout(ah, cts_timeout); 767 768 ah->ah_coverage_class = coverage_class; 769 } 770 771 /***************************\ 772 * Init/Start/Stop functions * 773 \***************************/ 774 775 /** 776 * ath5k_hw_start_rx_pcu - Start RX engine 777 * 778 * @ah: The &struct ath5k_hw 779 * 780 * Starts RX engine on PCU so that hw can process RXed frames 781 * (ACK etc). 782 * 783 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 784 */ 785 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 786 { 787 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 788 } 789 790 /** 791 * at5k_hw_stop_rx_pcu - Stop RX engine 792 * 793 * @ah: The &struct ath5k_hw 794 * 795 * Stops RX engine on PCU 796 */ 797 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 798 { 799 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 800 } 801 802 /** 803 * ath5k_hw_set_opmode - Set PCU operating mode 804 * 805 * @ah: The &struct ath5k_hw 806 * @op_mode: &enum nl80211_iftype operating mode 807 * 808 * Configure PCU for the various operating modes (AP/STA etc) 809 */ 810 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 811 { 812 struct ath_common *common = ath5k_hw_common(ah); 813 u32 pcu_reg, beacon_reg, low_id, high_id; 814 815 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 816 817 /* Preserve rest settings */ 818 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 819 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 820 | AR5K_STA_ID1_KEYSRCH_MODE 821 | (ah->ah_version == AR5K_AR5210 ? 822 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 823 824 beacon_reg = 0; 825 826 switch (op_mode) { 827 case NL80211_IFTYPE_ADHOC: 828 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 829 beacon_reg |= AR5K_BCR_ADHOC; 830 if (ah->ah_version == AR5K_AR5210) 831 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 832 else 833 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 834 break; 835 836 case NL80211_IFTYPE_AP: 837 case NL80211_IFTYPE_MESH_POINT: 838 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 839 beacon_reg |= AR5K_BCR_AP; 840 if (ah->ah_version == AR5K_AR5210) 841 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 842 else 843 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 844 break; 845 846 case NL80211_IFTYPE_STATION: 847 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 848 | (ah->ah_version == AR5K_AR5210 ? 849 AR5K_STA_ID1_PWR_SV : 0); 850 case NL80211_IFTYPE_MONITOR: 851 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 852 | (ah->ah_version == AR5K_AR5210 ? 853 AR5K_STA_ID1_NO_PSPOLL : 0); 854 break; 855 856 default: 857 return -EINVAL; 858 } 859 860 /* 861 * Set PCU registers 862 */ 863 low_id = get_unaligned_le32(common->macaddr); 864 high_id = get_unaligned_le16(common->macaddr + 4); 865 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 866 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 867 868 /* 869 * Set Beacon Control Register on 5210 870 */ 871 if (ah->ah_version == AR5K_AR5210) 872 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 873 874 return 0; 875 } 876 877 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 878 u8 mode) 879 { 880 /* Set bssid and bssid mask */ 881 ath5k_hw_set_bssid(ah); 882 883 /* Set PCU config */ 884 ath5k_hw_set_opmode(ah, op_mode); 885 886 /* Write rate duration table only on AR5212 and if 887 * virtual interface has already been brought up 888 * XXX: rethink this after new mode changes to 889 * mac80211 are integrated */ 890 if (ah->ah_version == AR5K_AR5212 && 891 ah->nvifs) 892 ath5k_hw_write_rate_duration(ah); 893 894 /* Set RSSI/BRSSI thresholds 895 * 896 * Note: If we decide to set this value 897 * dynamically, have in mind that when AR5K_RSSI_THR 898 * register is read it might return 0x40 if we haven't 899 * wrote anything to it plus BMISS RSSI threshold is zeroed. 900 * So doing a save/restore procedure here isn't the right 901 * choice. Instead store it on ath5k_hw */ 902 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 903 AR5K_TUNE_BMISS_THRES << 904 AR5K_RSSI_THR_BMISS_S), 905 AR5K_RSSI_THR); 906 907 /* MIC QoS support */ 908 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 909 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 910 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 911 } 912 913 /* QoS NOACK Policy */ 914 if (ah->ah_version == AR5K_AR5212) { 915 ath5k_hw_reg_write(ah, 916 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 917 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 918 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 919 AR5K_QOS_NOACK); 920 } 921 922 /* Restore slot time and ACK timeouts */ 923 if (ah->ah_coverage_class > 0) 924 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 925 926 /* Set ACK bitrate mode (see ack_rates_high) */ 927 if (ah->ah_version == AR5K_AR5212) { 928 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 929 if (ah->ah_ack_bitrate_high) 930 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 931 else 932 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 933 } 934 return; 935 } 936