1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 #include "base.h" 33 34 /*******************\ 35 * Generic functions * 36 \*******************/ 37 38 /** 39 * ath5k_hw_set_opmode - Set PCU operating mode 40 * 41 * @ah: The &struct ath5k_hw 42 * 43 * Initialize PCU for the various operating modes (AP/STA etc) 44 * 45 * NOTE: ah->ah_op_mode must be set before calling this. 46 */ 47 int ath5k_hw_set_opmode(struct ath5k_hw *ah) 48 { 49 struct ath_common *common = ath5k_hw_common(ah); 50 u32 pcu_reg, beacon_reg, low_id, high_id; 51 52 53 /* Preserve rest settings */ 54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 56 | AR5K_STA_ID1_KEYSRCH_MODE 57 | (ah->ah_version == AR5K_AR5210 ? 58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 59 60 beacon_reg = 0; 61 62 ATH5K_TRACE(ah->ah_sc); 63 64 switch (ah->ah_op_mode) { 65 case NL80211_IFTYPE_ADHOC: 66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 67 beacon_reg |= AR5K_BCR_ADHOC; 68 if (ah->ah_version == AR5K_AR5210) 69 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 70 else 71 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 72 break; 73 74 case NL80211_IFTYPE_AP: 75 case NL80211_IFTYPE_MESH_POINT: 76 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 77 beacon_reg |= AR5K_BCR_AP; 78 if (ah->ah_version == AR5K_AR5210) 79 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 80 else 81 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 82 break; 83 84 case NL80211_IFTYPE_STATION: 85 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 86 | (ah->ah_version == AR5K_AR5210 ? 87 AR5K_STA_ID1_PWR_SV : 0); 88 case NL80211_IFTYPE_MONITOR: 89 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 90 | (ah->ah_version == AR5K_AR5210 ? 91 AR5K_STA_ID1_NO_PSPOLL : 0); 92 break; 93 94 default: 95 return -EINVAL; 96 } 97 98 /* 99 * Set PCU registers 100 */ 101 low_id = get_unaligned_le32(common->macaddr); 102 high_id = get_unaligned_le16(common->macaddr + 4); 103 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 104 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 105 106 /* 107 * Set Beacon Control Register on 5210 108 */ 109 if (ah->ah_version == AR5K_AR5210) 110 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 111 112 return 0; 113 } 114 115 /** 116 * ath5k_hw_update - Update mib counters (mac layer statistics) 117 * 118 * @ah: The &struct ath5k_hw 119 * @stats: The &struct ieee80211_low_level_stats we use to track 120 * statistics on the driver 121 * 122 * Reads MIB counters from PCU and updates sw statistics. Must be 123 * called after a MIB interrupt. 124 */ 125 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, 126 struct ieee80211_low_level_stats *stats) 127 { 128 ATH5K_TRACE(ah->ah_sc); 129 130 /* Read-And-Clear */ 131 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 132 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 133 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 134 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 135 136 /* XXX: Should we use this to track beacon count ? 137 * -we read it anyway to clear the register */ 138 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 139 140 /* Reset profile count registers on 5212*/ 141 if (ah->ah_version == AR5K_AR5212) { 142 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX); 143 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX); 144 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR); 145 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE); 146 } 147 148 /* TODO: Handle ANI stats */ 149 } 150 151 /** 152 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs 153 * 154 * @ah: The &struct ath5k_hw 155 * @high: Flag to determine if we want to use high transmition rate 156 * for ACKs or not 157 * 158 * If high flag is set, we tell hw to use a set of control rates based on 159 * the current transmition rate (check out control_rates array inside reset.c). 160 * If not hw just uses the lowest rate available for the current modulation 161 * scheme being used (1Mbit for CCK and 6Mbits for OFDM). 162 */ 163 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high) 164 { 165 if (ah->ah_version != AR5K_AR5212) 166 return; 167 else { 168 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 169 if (high) 170 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 171 else 172 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 173 } 174 } 175 176 177 /******************\ 178 * ACK/CTS Timeouts * 179 \******************/ 180 181 /** 182 * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec 183 * 184 * @ah: The &struct ath5k_hw 185 */ 186 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah) 187 { 188 ATH5K_TRACE(ah->ah_sc); 189 190 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, 191 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo); 192 } 193 194 /** 195 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 196 * 197 * @ah: The &struct ath5k_hw 198 * @timeout: Timeout in usec 199 */ 200 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 201 { 202 ATH5K_TRACE(ah->ah_sc); 203 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), 204 ah->ah_turbo) <= timeout) 205 return -EINVAL; 206 207 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 208 ath5k_hw_htoclock(timeout, ah->ah_turbo)); 209 210 return 0; 211 } 212 213 /** 214 * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec 215 * 216 * @ah: The &struct ath5k_hw 217 */ 218 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah) 219 { 220 ATH5K_TRACE(ah->ah_sc); 221 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, 222 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo); 223 } 224 225 /** 226 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 227 * 228 * @ah: The &struct ath5k_hw 229 * @timeout: Timeout in usec 230 */ 231 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 232 { 233 ATH5K_TRACE(ah->ah_sc); 234 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), 235 ah->ah_turbo) <= timeout) 236 return -EINVAL; 237 238 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 239 ath5k_hw_htoclock(timeout, ah->ah_turbo)); 240 241 return 0; 242 } 243 244 /** 245 * ath5k_hw_set_lladdr - Set station id 246 * 247 * @ah: The &struct ath5k_hw 248 * @mac: The card's mac address 249 * 250 * Set station id on hw using the provided mac address 251 */ 252 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 253 { 254 struct ath_common *common = ath5k_hw_common(ah); 255 u32 low_id, high_id; 256 u32 pcu_reg; 257 258 ATH5K_TRACE(ah->ah_sc); 259 /* Set new station ID */ 260 memcpy(common->macaddr, mac, ETH_ALEN); 261 262 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 263 264 low_id = get_unaligned_le32(mac); 265 high_id = get_unaligned_le16(mac + 4); 266 267 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 268 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 269 270 return 0; 271 } 272 273 /** 274 * ath5k_hw_set_associd - Set BSSID for association 275 * 276 * @ah: The &struct ath5k_hw 277 * @bssid: BSSID 278 * @assoc_id: Assoc id 279 * 280 * Sets the BSSID which trigers the "SME Join" operation 281 */ 282 void ath5k_hw_set_associd(struct ath5k_hw *ah) 283 { 284 struct ath_common *common = ath5k_hw_common(ah); 285 u16 tim_offset = 0; 286 287 /* 288 * Set simple BSSID mask on 5212 289 */ 290 if (ah->ah_version == AR5K_AR5212) 291 ath_hw_setbssidmask(common); 292 293 /* 294 * Set BSSID which triggers the "SME Join" operation 295 */ 296 ath5k_hw_reg_write(ah, 297 get_unaligned_le32(common->curbssid), 298 AR5K_BSS_ID0); 299 ath5k_hw_reg_write(ah, 300 get_unaligned_le16(common->curbssid + 4) | 301 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 302 AR5K_BSS_ID1); 303 304 if (common->curaid == 0) { 305 ath5k_hw_disable_pspoll(ah); 306 return; 307 } 308 309 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 310 tim_offset ? tim_offset + 4 : 0); 311 312 ath5k_hw_enable_pspoll(ah, NULL, 0); 313 } 314 315 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 316 { 317 struct ath_common *common = ath5k_hw_common(ah); 318 ATH5K_TRACE(ah->ah_sc); 319 320 /* Cache bssid mask so that we can restore it 321 * on reset */ 322 memcpy(common->bssidmask, mask, ETH_ALEN); 323 if (ah->ah_version == AR5K_AR5212) 324 ath_hw_setbssidmask(common); 325 } 326 327 /************\ 328 * RX Control * 329 \************/ 330 331 /** 332 * ath5k_hw_start_rx_pcu - Start RX engine 333 * 334 * @ah: The &struct ath5k_hw 335 * 336 * Starts RX engine on PCU so that hw can process RXed frames 337 * (ACK etc). 338 * 339 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 340 * TODO: Init ANI here 341 */ 342 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 343 { 344 ATH5K_TRACE(ah->ah_sc); 345 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 346 } 347 348 /** 349 * at5k_hw_stop_rx_pcu - Stop RX engine 350 * 351 * @ah: The &struct ath5k_hw 352 * 353 * Stops RX engine on PCU 354 * 355 * TODO: Detach ANI here 356 */ 357 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 358 { 359 ATH5K_TRACE(ah->ah_sc); 360 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 361 } 362 363 /* 364 * Set multicast filter 365 */ 366 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 367 { 368 ATH5K_TRACE(ah->ah_sc); 369 /* Set the multicat filter */ 370 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 371 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 372 } 373 374 /* 375 * Set multicast filter by index 376 */ 377 int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index) 378 { 379 380 ATH5K_TRACE(ah->ah_sc); 381 if (index >= 64) 382 return -EINVAL; 383 else if (index >= 32) 384 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1, 385 (1 << (index - 32))); 386 else 387 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); 388 389 return 0; 390 } 391 392 /* 393 * Clear Multicast filter by index 394 */ 395 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index) 396 { 397 398 ATH5K_TRACE(ah->ah_sc); 399 if (index >= 64) 400 return -EINVAL; 401 else if (index >= 32) 402 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1, 403 (1 << (index - 32))); 404 else 405 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); 406 407 return 0; 408 } 409 410 /** 411 * ath5k_hw_get_rx_filter - Get current rx filter 412 * 413 * @ah: The &struct ath5k_hw 414 * 415 * Returns the RX filter by reading rx filter and 416 * phy error filter registers. RX filter is used 417 * to set the allowed frame types that PCU will accept 418 * and pass to the driver. For a list of frame types 419 * check out reg.h. 420 */ 421 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 422 { 423 u32 data, filter = 0; 424 425 ATH5K_TRACE(ah->ah_sc); 426 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 427 428 /*Radar detection for 5212*/ 429 if (ah->ah_version == AR5K_AR5212) { 430 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 431 432 if (data & AR5K_PHY_ERR_FIL_RADAR) 433 filter |= AR5K_RX_FILTER_RADARERR; 434 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 435 filter |= AR5K_RX_FILTER_PHYERR; 436 } 437 438 return filter; 439 } 440 441 /** 442 * ath5k_hw_set_rx_filter - Set rx filter 443 * 444 * @ah: The &struct ath5k_hw 445 * @filter: RX filter mask (see reg.h) 446 * 447 * Sets RX filter register and also handles PHY error filter 448 * register on 5212 and newer chips so that we have proper PHY 449 * error reporting. 450 */ 451 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 452 { 453 u32 data = 0; 454 455 ATH5K_TRACE(ah->ah_sc); 456 457 /* Set PHY error filter register on 5212*/ 458 if (ah->ah_version == AR5K_AR5212) { 459 if (filter & AR5K_RX_FILTER_RADARERR) 460 data |= AR5K_PHY_ERR_FIL_RADAR; 461 if (filter & AR5K_RX_FILTER_PHYERR) 462 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 463 } 464 465 /* 466 * The AR5210 uses promiscous mode to detect radar activity 467 */ 468 if (ah->ah_version == AR5K_AR5210 && 469 (filter & AR5K_RX_FILTER_RADARERR)) { 470 filter &= ~AR5K_RX_FILTER_RADARERR; 471 filter |= AR5K_RX_FILTER_PROM; 472 } 473 474 /*Zero length DMA (phy error reporting) */ 475 if (data) 476 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 477 else 478 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 479 480 /*Write RX Filter register*/ 481 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 482 483 /*Write PHY error filter register on 5212*/ 484 if (ah->ah_version == AR5K_AR5212) 485 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 486 487 } 488 489 490 /****************\ 491 * Beacon control * 492 \****************/ 493 494 /** 495 * ath5k_hw_get_tsf32 - Get a 32bit TSF 496 * 497 * @ah: The &struct ath5k_hw 498 * 499 * Returns lower 32 bits of current TSF 500 */ 501 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah) 502 { 503 ATH5K_TRACE(ah->ah_sc); 504 return ath5k_hw_reg_read(ah, AR5K_TSF_L32); 505 } 506 507 /** 508 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 509 * 510 * @ah: The &struct ath5k_hw 511 * 512 * Returns the current TSF 513 */ 514 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 515 { 516 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 517 ATH5K_TRACE(ah->ah_sc); 518 519 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32); 520 } 521 522 /** 523 * ath5k_hw_set_tsf64 - Set a new 64bit TSF 524 * 525 * @ah: The &struct ath5k_hw 526 * @tsf64: The new 64bit TSF 527 * 528 * Sets the new TSF 529 */ 530 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 531 { 532 ATH5K_TRACE(ah->ah_sc); 533 534 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 535 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 536 } 537 538 /** 539 * ath5k_hw_reset_tsf - Force a TSF reset 540 * 541 * @ah: The &struct ath5k_hw 542 * 543 * Forces a TSF reset on PCU 544 */ 545 void ath5k_hw_reset_tsf(struct ath5k_hw *ah) 546 { 547 u32 val; 548 549 ATH5K_TRACE(ah->ah_sc); 550 551 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 552 553 /* 554 * Each write to the RESET_TSF bit toggles a hardware internal 555 * signal to reset TSF, but if left high it will cause a TSF reset 556 * on the next chip reset as well. Thus we always write the value 557 * twice to clear the signal. 558 */ 559 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 560 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 561 } 562 563 /* 564 * Initialize beacon timers 565 */ 566 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 567 { 568 u32 timer1, timer2, timer3; 569 570 ATH5K_TRACE(ah->ah_sc); 571 /* 572 * Set the additional timers by mode 573 */ 574 switch (ah->ah_op_mode) { 575 case NL80211_IFTYPE_MONITOR: 576 case NL80211_IFTYPE_STATION: 577 /* In STA mode timer1 is used as next wakeup 578 * timer and timer2 as next CFP duration start 579 * timer. Both in 1/8TUs. */ 580 /* TODO: PCF handling */ 581 if (ah->ah_version == AR5K_AR5210) { 582 timer1 = 0xffffffff; 583 timer2 = 0xffffffff; 584 } else { 585 timer1 = 0x0000ffff; 586 timer2 = 0x0007ffff; 587 } 588 /* Mark associated AP as PCF incapable for now */ 589 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 590 break; 591 case NL80211_IFTYPE_ADHOC: 592 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 593 default: 594 /* On non-STA modes timer1 is used as next DMA 595 * beacon alert (DBA) timer and timer2 as next 596 * software beacon alert. Both in 1/8TUs. */ 597 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 598 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 599 break; 600 } 601 602 /* Timer3 marks the end of our ATIM window 603 * a zero length window is not allowed because 604 * we 'll get no beacons */ 605 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1); 606 607 /* 608 * Set the beacon register and enable all timers. 609 */ 610 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 611 if (ah->ah_op_mode == NL80211_IFTYPE_AP || 612 ah->ah_op_mode == NL80211_IFTYPE_MESH_POINT) 613 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 614 615 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 616 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 617 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 618 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 619 620 /* Force a TSF reset if requested and enable beacons */ 621 if (interval & AR5K_BEACON_RESET_TSF) 622 ath5k_hw_reset_tsf(ah); 623 624 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 625 AR5K_BEACON_ENABLE), 626 AR5K_BEACON); 627 628 /* Flush any pending BMISS interrupts on ISR by 629 * performing a clear-on-write operation on PISR 630 * register for the BMISS bit (writing a bit on 631 * ISR togles a reset for that bit and leaves 632 * the rest bits intact) */ 633 if (ah->ah_version == AR5K_AR5210) 634 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 635 else 636 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 637 638 /* TODO: Set enchanced sleep registers on AR5212 639 * based on vif->bss_conf params, until then 640 * disable power save reporting.*/ 641 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 642 643 } 644 645 #if 0 646 /* 647 * Set beacon timers 648 */ 649 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, 650 const struct ath5k_beacon_state *state) 651 { 652 u32 cfp_period, next_cfp, dtim, interval, next_beacon; 653 654 /* 655 * TODO: should be changed through *state 656 * review struct ath5k_beacon_state struct 657 * 658 * XXX: These are used for cfp period bellow, are they 659 * ok ? Is it O.K. for tsf here to be 0 or should we use 660 * get_tsf ? 661 */ 662 u32 dtim_count = 0; /* XXX */ 663 u32 cfp_count = 0; /* XXX */ 664 u32 tsf = 0; /* XXX */ 665 666 ATH5K_TRACE(ah->ah_sc); 667 /* Return on an invalid beacon state */ 668 if (state->bs_interval < 1) 669 return -EINVAL; 670 671 interval = state->bs_interval; 672 dtim = state->bs_dtim_period; 673 674 /* 675 * PCF support? 676 */ 677 if (state->bs_cfp_period > 0) { 678 /* 679 * Enable PCF mode and set the CFP 680 * (Contention Free Period) and timer registers 681 */ 682 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 683 state->bs_interval; 684 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 685 state->bs_interval; 686 687 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, 688 AR5K_STA_ID1_DEFAULT_ANTENNA | 689 AR5K_STA_ID1_PCF); 690 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD); 691 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration, 692 AR5K_CFP_DUR); 693 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period : 694 next_cfp)) << 3, AR5K_TIMER2); 695 } else { 696 /* Disable PCF mode */ 697 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, 698 AR5K_STA_ID1_DEFAULT_ANTENNA | 699 AR5K_STA_ID1_PCF); 700 } 701 702 /* 703 * Enable the beacon timer register 704 */ 705 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0); 706 707 /* 708 * Start the beacon timers 709 */ 710 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) & 711 ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | 712 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 713 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 714 AR5K_BEACON_PERIOD), AR5K_BEACON); 715 716 /* 717 * Write new beacon miss threshold, if it appears to be valid 718 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max 719 * and return if its not in range. We can test this by reading value and 720 * setting value to a largest value and seeing which values register. 721 */ 722 723 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, 724 state->bs_bmiss_threshold); 725 726 /* 727 * Set sleep control register 728 * XXX: Didn't find this in 5210 code but since this register 729 * exists also in ar5k's 5210 headers i leave it as common code. 730 */ 731 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, 732 (state->bs_sleep_duration - 3) << 3); 733 734 /* 735 * Set enhanced sleep registers on 5212 736 */ 737 if (ah->ah_version == AR5K_AR5212) { 738 if (state->bs_sleep_duration > state->bs_interval && 739 roundup(state->bs_sleep_duration, interval) == 740 state->bs_sleep_duration) 741 interval = state->bs_sleep_duration; 742 743 if (state->bs_sleep_duration > dtim && (dtim == 0 || 744 roundup(state->bs_sleep_duration, dtim) == 745 state->bs_sleep_duration)) 746 dtim = state->bs_sleep_duration; 747 748 if (interval > dtim) 749 return -EINVAL; 750 751 next_beacon = interval == dtim ? state->bs_next_dtim : 752 state->bs_next_beacon; 753 754 ath5k_hw_reg_write(ah, 755 AR5K_REG_SM((state->bs_next_dtim - 3) << 3, 756 AR5K_SLEEP0_NEXT_DTIM) | 757 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | 758 AR5K_SLEEP0_ENH_SLEEP_EN | 759 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); 760 761 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3, 762 AR5K_SLEEP1_NEXT_TIM) | 763 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); 764 765 ath5k_hw_reg_write(ah, 766 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | 767 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); 768 } 769 770 return 0; 771 } 772 773 /* 774 * Reset beacon timers 775 */ 776 void ath5k_hw_reset_beacon(struct ath5k_hw *ah) 777 { 778 ATH5K_TRACE(ah->ah_sc); 779 /* 780 * Disable beacon timer 781 */ 782 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 783 784 /* 785 * Disable some beacon register values 786 */ 787 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, 788 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); 789 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON); 790 } 791 792 /* 793 * Wait for beacon queue to finish 794 */ 795 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr) 796 { 797 unsigned int i; 798 int ret; 799 800 ATH5K_TRACE(ah->ah_sc); 801 802 /* 5210 doesn't have QCU*/ 803 if (ah->ah_version == AR5K_AR5210) { 804 /* 805 * Wait for beaconn queue to finish by checking 806 * Control Register and Beacon Status Register. 807 */ 808 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) { 809 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F) 810 || 811 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F)) 812 break; 813 udelay(10); 814 } 815 816 /* Timeout... */ 817 if (i <= 0) { 818 /* 819 * Re-schedule the beacon queue 820 */ 821 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1); 822 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, 823 AR5K_BCR); 824 825 return -EIO; 826 } 827 ret = 0; 828 } else { 829 /*5211/5212*/ 830 ret = ath5k_hw_register_timeout(ah, 831 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), 832 AR5K_QCU_STS_FRMPENDCNT, 0, false); 833 834 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) 835 return -EIO; 836 } 837 838 return ret; 839 } 840 #endif 841 842 843 /*********************\ 844 * Key table functions * 845 \*********************/ 846 847 /* 848 * Reset a key entry on the table 849 */ 850 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry) 851 { 852 unsigned int i, type; 853 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; 854 855 ATH5K_TRACE(ah->ah_sc); 856 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); 857 858 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry)); 859 860 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) 861 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); 862 863 /* Reset associated MIC entry if TKIP 864 * is enabled located at offset (entry + 64) */ 865 if (type == AR5K_KEYTABLE_TYPE_TKIP) { 866 AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE); 867 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++) 868 ath5k_hw_reg_write(ah, 0, 869 AR5K_KEYTABLE_OFF(micentry, i)); 870 } 871 872 /* 873 * Set NULL encryption on AR5212+ 874 * 875 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5) 876 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007 877 * 878 * Note2: Windows driver (ndiswrapper) sets this to 879 * 0x00000714 instead of 0x00000007 880 */ 881 if (ah->ah_version >= AR5K_AR5211) { 882 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 883 AR5K_KEYTABLE_TYPE(entry)); 884 885 if (type == AR5K_KEYTABLE_TYPE_TKIP) { 886 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 887 AR5K_KEYTABLE_TYPE(micentry)); 888 } 889 } 890 891 return 0; 892 } 893 894 /* 895 * Check if a table entry is valid 896 */ 897 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry) 898 { 899 ATH5K_TRACE(ah->ah_sc); 900 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); 901 902 /* Check the validation flag at the end of the entry */ 903 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) & 904 AR5K_KEYTABLE_VALID; 905 } 906 907 static 908 int ath5k_keycache_type(const struct ieee80211_key_conf *key) 909 { 910 switch (key->alg) { 911 case ALG_TKIP: 912 return AR5K_KEYTABLE_TYPE_TKIP; 913 case ALG_CCMP: 914 return AR5K_KEYTABLE_TYPE_CCM; 915 case ALG_WEP: 916 if (key->keylen == WLAN_KEY_LEN_WEP40) 917 return AR5K_KEYTABLE_TYPE_40; 918 else if (key->keylen == WLAN_KEY_LEN_WEP104) 919 return AR5K_KEYTABLE_TYPE_104; 920 return -EINVAL; 921 default: 922 return -EINVAL; 923 } 924 return -EINVAL; 925 } 926 927 /* 928 * Set a key entry on the table 929 */ 930 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, 931 const struct ieee80211_key_conf *key, const u8 *mac) 932 { 933 unsigned int i; 934 int keylen; 935 __le32 key_v[5] = {}; 936 __le32 key0 = 0, key1 = 0; 937 __le32 *rxmic, *txmic; 938 int keytype; 939 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; 940 bool is_tkip; 941 const u8 *key_ptr; 942 943 ATH5K_TRACE(ah->ah_sc); 944 945 is_tkip = (key->alg == ALG_TKIP); 946 947 /* 948 * key->keylen comes in from mac80211 in bytes. 949 * TKIP is 128 bit + 128 bit mic 950 */ 951 keylen = (is_tkip) ? (128 / 8) : key->keylen; 952 953 if (entry > AR5K_KEYTABLE_SIZE || 954 (is_tkip && micentry > AR5K_KEYTABLE_SIZE)) 955 return -EOPNOTSUPP; 956 957 if (unlikely(keylen > 16)) 958 return -EOPNOTSUPP; 959 960 keytype = ath5k_keycache_type(key); 961 if (keytype < 0) 962 return keytype; 963 964 /* 965 * each key block is 6 bytes wide, written as pairs of 966 * alternating 32 and 16 bit le values. 967 */ 968 key_ptr = key->key; 969 for (i = 0; keylen >= 6; keylen -= 6) { 970 memcpy(&key_v[i], key_ptr, 6); 971 i += 2; 972 key_ptr += 6; 973 } 974 if (keylen) 975 memcpy(&key_v[i], key_ptr, keylen); 976 977 /* intentionally corrupt key until mic is installed */ 978 if (is_tkip) { 979 key0 = key_v[0] = ~key_v[0]; 980 key1 = key_v[1] = ~key_v[1]; 981 } 982 983 for (i = 0; i < ARRAY_SIZE(key_v); i++) 984 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), 985 AR5K_KEYTABLE_OFF(entry, i)); 986 987 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry)); 988 989 if (is_tkip) { 990 /* Install rx/tx MIC */ 991 rxmic = (__le32 *) &key->key[16]; 992 txmic = (__le32 *) &key->key[24]; 993 994 if (ah->ah_combined_mic) { 995 key_v[0] = rxmic[0]; 996 key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16); 997 key_v[2] = rxmic[1]; 998 key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff); 999 key_v[4] = txmic[1]; 1000 } else { 1001 key_v[0] = rxmic[0]; 1002 key_v[1] = 0; 1003 key_v[2] = rxmic[1]; 1004 key_v[3] = 0; 1005 key_v[4] = 0; 1006 } 1007 for (i = 0; i < ARRAY_SIZE(key_v); i++) 1008 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), 1009 AR5K_KEYTABLE_OFF(micentry, i)); 1010 1011 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 1012 AR5K_KEYTABLE_TYPE(micentry)); 1013 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry)); 1014 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry)); 1015 1016 /* restore first 2 words of key */ 1017 ath5k_hw_reg_write(ah, le32_to_cpu(~key0), 1018 AR5K_KEYTABLE_OFF(entry, 0)); 1019 ath5k_hw_reg_write(ah, le32_to_cpu(~key1), 1020 AR5K_KEYTABLE_OFF(entry, 1)); 1021 } 1022 1023 return ath5k_hw_set_key_lladdr(ah, entry, mac); 1024 } 1025 1026 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac) 1027 { 1028 u32 low_id, high_id; 1029 1030 ATH5K_TRACE(ah->ah_sc); 1031 /* Invalid entry (key table overflow) */ 1032 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); 1033 1034 /* 1035 * MAC may be NULL if it's a broadcast key. In this case no need to 1036 * to compute get_unaligned_le32 and get_unaligned_le16 as we 1037 * already know it. 1038 */ 1039 if (!mac) { 1040 low_id = 0xffffffff; 1041 high_id = 0xffff | AR5K_KEYTABLE_VALID; 1042 } else { 1043 low_id = get_unaligned_le32(mac); 1044 high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID; 1045 } 1046 1047 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry)); 1048 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry)); 1049 1050 return 0; 1051 } 1052 1053