1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 #include "base.h" 33 34 /* 35 * AR5212+ can use higher rates for ack transmition 36 * based on current tx rate instead of the base rate. 37 * It does this to better utilize channel usage. 38 * This is a mapping between G rates (that cover both 39 * CCK and OFDM) and ack rates that we use when setting 40 * rate -> duration table. This mapping is hw-based so 41 * don't change anything. 42 * 43 * To enable this functionality we must set 44 * ah->ah_ack_bitrate_high to true else base rate is 45 * used (1Mb for CCK, 6Mb for OFDM). 46 */ 47 static const unsigned int ack_rates_high[] = 48 /* Tx -> ACK */ 49 /* 1Mb -> 1Mb */ { 0, 50 /* 2MB -> 2Mb */ 1, 51 /* 5.5Mb -> 2Mb */ 1, 52 /* 11Mb -> 2Mb */ 1, 53 /* 6Mb -> 6Mb */ 4, 54 /* 9Mb -> 6Mb */ 4, 55 /* 12Mb -> 12Mb */ 6, 56 /* 18Mb -> 12Mb */ 6, 57 /* 24Mb -> 24Mb */ 8, 58 /* 36Mb -> 24Mb */ 8, 59 /* 48Mb -> 24Mb */ 8, 60 /* 54Mb -> 24Mb */ 8 }; 61 62 /*******************\ 63 * Helper functions * 64 \*******************/ 65 66 /** 67 * ath5k_hw_get_frame_duration - Get tx time of a frame 68 * 69 * @ah: The &struct ath5k_hw 70 * @len: Frame's length in bytes 71 * @rate: The @struct ieee80211_rate 72 * 73 * Calculate tx duration of a frame given it's rate and length 74 * It extends ieee80211_generic_frame_duration for non standard 75 * bwmodes. 76 */ 77 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 78 int len, struct ieee80211_rate *rate) 79 { 80 struct ath5k_softc *sc = ah->ah_sc; 81 int sifs, preamble, plcp_bits, sym_time; 82 int bitrate, bits, symbols, symbol_bits; 83 int dur; 84 85 /* Fallback */ 86 if (!ah->ah_bwmode) { 87 dur = ieee80211_generic_frame_duration(sc->hw, 88 NULL, len, rate); 89 return le16_to_cpu(dur); 90 } 91 92 bitrate = rate->bitrate; 93 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; 94 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; 95 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; 96 97 switch (ah->ah_bwmode) { 98 case AR5K_BWMODE_40MHZ: 99 sifs = AR5K_INIT_SIFS_TURBO; 100 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; 101 break; 102 case AR5K_BWMODE_10MHZ: 103 sifs = AR5K_INIT_SIFS_HALF_RATE; 104 preamble *= 2; 105 sym_time *= 2; 106 break; 107 case AR5K_BWMODE_5MHZ: 108 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 109 preamble *= 4; 110 sym_time *= 4; 111 break; 112 default: 113 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 114 break; 115 } 116 117 bits = plcp_bits + (len << 3); 118 /* Bit rate is in 100Kbits */ 119 symbol_bits = bitrate * sym_time; 120 symbols = DIV_ROUND_UP(bits * 10, symbol_bits); 121 122 dur = sifs + preamble + (sym_time * symbols); 123 124 return dur; 125 } 126 127 /** 128 * ath5k_hw_get_default_slottime - Get the default slot time for current mode 129 * 130 * @ah: The &struct ath5k_hw 131 */ 132 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 133 { 134 struct ieee80211_channel *channel = ah->ah_current_channel; 135 unsigned int slot_time; 136 137 switch (ah->ah_bwmode) { 138 case AR5K_BWMODE_40MHZ: 139 slot_time = AR5K_INIT_SLOT_TIME_TURBO; 140 break; 141 case AR5K_BWMODE_10MHZ: 142 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; 143 break; 144 case AR5K_BWMODE_5MHZ: 145 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; 146 break; 147 case AR5K_BWMODE_DEFAULT: 148 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; 149 default: 150 if (channel->hw_value & CHANNEL_CCK) 151 slot_time = AR5K_INIT_SLOT_TIME_B; 152 break; 153 } 154 155 return slot_time; 156 } 157 158 /** 159 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode 160 * 161 * @ah: The &struct ath5k_hw 162 */ 163 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 164 { 165 struct ieee80211_channel *channel = ah->ah_current_channel; 166 unsigned int sifs; 167 168 switch (ah->ah_bwmode) { 169 case AR5K_BWMODE_40MHZ: 170 sifs = AR5K_INIT_SIFS_TURBO; 171 break; 172 case AR5K_BWMODE_10MHZ: 173 sifs = AR5K_INIT_SIFS_HALF_RATE; 174 break; 175 case AR5K_BWMODE_5MHZ: 176 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 177 break; 178 case AR5K_BWMODE_DEFAULT: 179 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 180 default: 181 if (channel->hw_value & CHANNEL_5GHZ) 182 sifs = AR5K_INIT_SIFS_DEFAULT_A; 183 break; 184 } 185 186 return sifs; 187 } 188 189 /** 190 * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics) 191 * 192 * @ah: The &struct ath5k_hw 193 * 194 * Reads MIB counters from PCU and updates sw statistics. Is called after a 195 * MIB interrupt, because one of these counters might have reached their maximum 196 * and triggered the MIB interrupt, to let us read and clear the counter. 197 * 198 * Is called in interrupt context! 199 */ 200 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 201 { 202 struct ath5k_statistics *stats = &ah->ah_sc->stats; 203 204 /* Read-And-Clear */ 205 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 206 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 207 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 208 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 209 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 210 } 211 212 213 /******************\ 214 * ACK/CTS Timeouts * 215 \******************/ 216 217 /** 218 * ath5k_hw_write_rate_duration - fill rate code to duration table 219 * 220 * @ah: the &struct ath5k_hw 221 * @mode: one of enum ath5k_driver_mode 222 * 223 * Write the rate code to duration table upon hw reset. This is a helper for 224 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 225 * the hardware, based on current mode, for each rate. The rates which are 226 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 227 * different rate code so we write their value twice (one for long preamble 228 * and one for short). 229 * 230 * Note: Band doesn't matter here, if we set the values for OFDM it works 231 * on both a and g modes. So all we have to do is set values for all g rates 232 * that include all OFDM and CCK rates. 233 * 234 */ 235 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 236 { 237 struct ath5k_softc *sc = ah->ah_sc; 238 struct ieee80211_rate *rate; 239 unsigned int i; 240 /* 802.11g covers both OFDM and CCK */ 241 u8 band = IEEE80211_BAND_2GHZ; 242 243 /* Write rate duration table */ 244 for (i = 0; i < sc->sbands[band].n_bitrates; i++) { 245 u32 reg; 246 u16 tx_time; 247 248 if (ah->ah_ack_bitrate_high) 249 rate = &sc->sbands[band].bitrates[ack_rates_high[i]]; 250 /* CCK -> 1Mb */ 251 else if (i < 4) 252 rate = &sc->sbands[band].bitrates[0]; 253 /* OFDM -> 6Mb */ 254 else 255 rate = &sc->sbands[band].bitrates[4]; 256 257 /* Set ACK timeout */ 258 reg = AR5K_RATE_DUR(rate->hw_value); 259 260 /* An ACK frame consists of 10 bytes. If you add the FCS, 261 * which ieee80211_generic_frame_duration() adds, 262 * its 14 bytes. Note we use the control rate and not the 263 * actual rate for this rate. See mac80211 tx.c 264 * ieee80211_duration() for a brief description of 265 * what rate we should choose to TX ACKs. */ 266 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate); 267 268 ath5k_hw_reg_write(ah, tx_time, reg); 269 270 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 271 continue; 272 273 /* 274 * We're not distinguishing short preamble here, 275 * This is true, all we'll get is a longer value here 276 * which is not necessarilly bad. We could use 277 * export ieee80211_frame_duration() but that needs to be 278 * fixed first to be properly used by mac802111 drivers: 279 * 280 * - remove erp stuff and let the routine figure ofdm 281 * erp rates 282 * - remove passing argument ieee80211_local as 283 * drivers don't have access to it 284 * - move drivers using ieee80211_generic_frame_duration() 285 * to this 286 */ 287 ath5k_hw_reg_write(ah, tx_time, 288 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 289 } 290 } 291 292 /** 293 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 294 * 295 * @ah: The &struct ath5k_hw 296 * @timeout: Timeout in usec 297 */ 298 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 299 { 300 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 301 <= timeout) 302 return -EINVAL; 303 304 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 305 ath5k_hw_htoclock(ah, timeout)); 306 307 return 0; 308 } 309 310 /** 311 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 312 * 313 * @ah: The &struct ath5k_hw 314 * @timeout: Timeout in usec 315 */ 316 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 317 { 318 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 319 <= timeout) 320 return -EINVAL; 321 322 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 323 ath5k_hw_htoclock(ah, timeout)); 324 325 return 0; 326 } 327 328 329 /*******************\ 330 * RX filter Control * 331 \*******************/ 332 333 /** 334 * ath5k_hw_set_lladdr - Set station id 335 * 336 * @ah: The &struct ath5k_hw 337 * @mac: The card's mac address 338 * 339 * Set station id on hw using the provided mac address 340 */ 341 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 342 { 343 struct ath_common *common = ath5k_hw_common(ah); 344 u32 low_id, high_id; 345 u32 pcu_reg; 346 347 /* Set new station ID */ 348 memcpy(common->macaddr, mac, ETH_ALEN); 349 350 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 351 352 low_id = get_unaligned_le32(mac); 353 high_id = get_unaligned_le16(mac + 4); 354 355 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 356 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 357 358 return 0; 359 } 360 361 /** 362 * ath5k_hw_set_bssid - Set current BSSID on hw 363 * 364 * @ah: The &struct ath5k_hw 365 * 366 * Sets the current BSSID and BSSID mask we have from the 367 * common struct into the hardware 368 */ 369 void ath5k_hw_set_bssid(struct ath5k_hw *ah) 370 { 371 struct ath_common *common = ath5k_hw_common(ah); 372 u16 tim_offset = 0; 373 374 /* 375 * Set BSSID mask on 5212 376 */ 377 if (ah->ah_version == AR5K_AR5212) 378 ath_hw_setbssidmask(common); 379 380 /* 381 * Set BSSID 382 */ 383 ath5k_hw_reg_write(ah, 384 get_unaligned_le32(common->curbssid), 385 AR5K_BSS_ID0); 386 ath5k_hw_reg_write(ah, 387 get_unaligned_le16(common->curbssid + 4) | 388 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 389 AR5K_BSS_ID1); 390 391 if (common->curaid == 0) { 392 ath5k_hw_disable_pspoll(ah); 393 return; 394 } 395 396 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 397 tim_offset ? tim_offset + 4 : 0); 398 399 ath5k_hw_enable_pspoll(ah, NULL, 0); 400 } 401 402 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 403 { 404 struct ath_common *common = ath5k_hw_common(ah); 405 406 /* Cache bssid mask so that we can restore it 407 * on reset */ 408 memcpy(common->bssidmask, mask, ETH_ALEN); 409 if (ah->ah_version == AR5K_AR5212) 410 ath_hw_setbssidmask(common); 411 } 412 413 /* 414 * Set multicast filter 415 */ 416 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 417 { 418 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 419 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 420 } 421 422 /** 423 * ath5k_hw_get_rx_filter - Get current rx filter 424 * 425 * @ah: The &struct ath5k_hw 426 * 427 * Returns the RX filter by reading rx filter and 428 * phy error filter registers. RX filter is used 429 * to set the allowed frame types that PCU will accept 430 * and pass to the driver. For a list of frame types 431 * check out reg.h. 432 */ 433 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 434 { 435 u32 data, filter = 0; 436 437 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 438 439 /*Radar detection for 5212*/ 440 if (ah->ah_version == AR5K_AR5212) { 441 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 442 443 if (data & AR5K_PHY_ERR_FIL_RADAR) 444 filter |= AR5K_RX_FILTER_RADARERR; 445 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 446 filter |= AR5K_RX_FILTER_PHYERR; 447 } 448 449 return filter; 450 } 451 452 /** 453 * ath5k_hw_set_rx_filter - Set rx filter 454 * 455 * @ah: The &struct ath5k_hw 456 * @filter: RX filter mask (see reg.h) 457 * 458 * Sets RX filter register and also handles PHY error filter 459 * register on 5212 and newer chips so that we have proper PHY 460 * error reporting. 461 */ 462 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 463 { 464 u32 data = 0; 465 466 /* Set PHY error filter register on 5212*/ 467 if (ah->ah_version == AR5K_AR5212) { 468 if (filter & AR5K_RX_FILTER_RADARERR) 469 data |= AR5K_PHY_ERR_FIL_RADAR; 470 if (filter & AR5K_RX_FILTER_PHYERR) 471 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 472 } 473 474 /* 475 * The AR5210 uses promiscous mode to detect radar activity 476 */ 477 if (ah->ah_version == AR5K_AR5210 && 478 (filter & AR5K_RX_FILTER_RADARERR)) { 479 filter &= ~AR5K_RX_FILTER_RADARERR; 480 filter |= AR5K_RX_FILTER_PROM; 481 } 482 483 /*Zero length DMA (phy error reporting) */ 484 if (data) 485 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 486 else 487 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 488 489 /*Write RX Filter register*/ 490 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 491 492 /*Write PHY error filter register on 5212*/ 493 if (ah->ah_version == AR5K_AR5212) 494 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 495 496 } 497 498 499 /****************\ 500 * Beacon control * 501 \****************/ 502 503 #define ATH5K_MAX_TSF_READ 10 504 505 /** 506 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 507 * 508 * @ah: The &struct ath5k_hw 509 * 510 * Returns the current TSF 511 */ 512 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 513 { 514 u32 tsf_lower, tsf_upper1, tsf_upper2; 515 int i; 516 unsigned long flags; 517 518 /* This code is time critical - we don't want to be interrupted here */ 519 local_irq_save(flags); 520 521 /* 522 * While reading TSF upper and then lower part, the clock is still 523 * counting (or jumping in case of IBSS merge) so we might get 524 * inconsistent values. To avoid this, we read the upper part again 525 * and check it has not been changed. We make the hypothesis that a 526 * maximum of 3 changes can happens in a row (we use 10 as a safe 527 * value). 528 * 529 * Impact on performance is pretty small, since in most cases, only 530 * 3 register reads are needed. 531 */ 532 533 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 534 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { 535 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 536 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 537 if (tsf_upper2 == tsf_upper1) 538 break; 539 tsf_upper1 = tsf_upper2; 540 } 541 542 local_irq_restore(flags); 543 544 WARN_ON( i == ATH5K_MAX_TSF_READ ); 545 546 return (((u64)tsf_upper1 << 32) | tsf_lower); 547 } 548 549 /** 550 * ath5k_hw_set_tsf64 - Set a new 64bit TSF 551 * 552 * @ah: The &struct ath5k_hw 553 * @tsf64: The new 64bit TSF 554 * 555 * Sets the new TSF 556 */ 557 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 558 { 559 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 560 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 561 } 562 563 /** 564 * ath5k_hw_reset_tsf - Force a TSF reset 565 * 566 * @ah: The &struct ath5k_hw 567 * 568 * Forces a TSF reset on PCU 569 */ 570 void ath5k_hw_reset_tsf(struct ath5k_hw *ah) 571 { 572 u32 val; 573 574 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 575 576 /* 577 * Each write to the RESET_TSF bit toggles a hardware internal 578 * signal to reset TSF, but if left high it will cause a TSF reset 579 * on the next chip reset as well. Thus we always write the value 580 * twice to clear the signal. 581 */ 582 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 583 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 584 } 585 586 /* 587 * Initialize beacon timers 588 */ 589 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 590 { 591 u32 timer1, timer2, timer3; 592 593 /* 594 * Set the additional timers by mode 595 */ 596 switch (ah->ah_sc->opmode) { 597 case NL80211_IFTYPE_MONITOR: 598 case NL80211_IFTYPE_STATION: 599 /* In STA mode timer1 is used as next wakeup 600 * timer and timer2 as next CFP duration start 601 * timer. Both in 1/8TUs. */ 602 /* TODO: PCF handling */ 603 if (ah->ah_version == AR5K_AR5210) { 604 timer1 = 0xffffffff; 605 timer2 = 0xffffffff; 606 } else { 607 timer1 = 0x0000ffff; 608 timer2 = 0x0007ffff; 609 } 610 /* Mark associated AP as PCF incapable for now */ 611 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 612 break; 613 case NL80211_IFTYPE_ADHOC: 614 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 615 default: 616 /* On non-STA modes timer1 is used as next DMA 617 * beacon alert (DBA) timer and timer2 as next 618 * software beacon alert. Both in 1/8TUs. */ 619 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 620 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 621 break; 622 } 623 624 /* Timer3 marks the end of our ATIM window 625 * a zero length window is not allowed because 626 * we 'll get no beacons */ 627 timer3 = next_beacon + 1; 628 629 /* 630 * Set the beacon register and enable all timers. 631 */ 632 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 633 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP || 634 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT) 635 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 636 637 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 638 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 639 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 640 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 641 642 /* Force a TSF reset if requested and enable beacons */ 643 if (interval & AR5K_BEACON_RESET_TSF) 644 ath5k_hw_reset_tsf(ah); 645 646 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 647 AR5K_BEACON_ENABLE), 648 AR5K_BEACON); 649 650 /* Flush any pending BMISS interrupts on ISR by 651 * performing a clear-on-write operation on PISR 652 * register for the BMISS bit (writing a bit on 653 * ISR togles a reset for that bit and leaves 654 * the rest bits intact) */ 655 if (ah->ah_version == AR5K_AR5210) 656 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 657 else 658 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 659 660 /* TODO: Set enchanced sleep registers on AR5212 661 * based on vif->bss_conf params, until then 662 * disable power save reporting.*/ 663 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 664 665 } 666 667 /** 668 * ath5k_check_timer_win - Check if timer B is timer A + window 669 * 670 * @a: timer a (before b) 671 * @b: timer b (after a) 672 * @window: difference between a and b 673 * @intval: timers are increased by this interval 674 * 675 * This helper function checks if timer B is timer A + window and covers 676 * cases where timer A or B might have already been updated or wrapped 677 * around (Timers are 16 bit). 678 * 679 * Returns true if O.K. 680 */ 681 static inline bool 682 ath5k_check_timer_win(int a, int b, int window, int intval) 683 { 684 /* 685 * 1.) usually B should be A + window 686 * 2.) A already updated, B not updated yet 687 * 3.) A already updated and has wrapped around 688 * 4.) B has wrapped around 689 */ 690 if ((b - a == window) || /* 1.) */ 691 (a - b == intval - window) || /* 2.) */ 692 ((a | 0x10000) - b == intval - window) || /* 3.) */ 693 ((b | 0x10000) - a == window)) /* 4.) */ 694 return true; /* O.K. */ 695 return false; 696 } 697 698 /** 699 * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct 700 * 701 * @ah: The &struct ath5k_hw 702 * @intval: beacon interval 703 * 704 * This is a workaround for IBSS mode: 705 * 706 * The need for this function arises from the fact that we have 4 separate 707 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 708 * next beacon target time (NBTT), and that the HW updates these timers 709 * seperately based on the current TSF value. The hardware increments each 710 * timer by the beacon interval, when the local TSF coverted to TU is equal 711 * to the value stored in the timer. 712 * 713 * The reception of a beacon with the same BSSID can update the local HW TSF 714 * at any time - this is something we can't avoid. If the TSF jumps to a 715 * time which is later than the time stored in a timer, this timer will not 716 * be updated until the TSF in TU wraps around at 16 bit (the size of the 717 * timers) and reaches the time which is stored in the timer. 718 * 719 * The problem is that these timers are closely related to TIMER0 (NBTT) and 720 * that they define a time "window". When the TSF jumps between two timers 721 * (e.g. ATIM and NBTT), the one in the past will be left behind (not 722 * updated), while the one in the future will be updated every beacon 723 * interval. This causes the window to get larger, until the TSF wraps 724 * around as described above and the timer which was left behind gets 725 * updated again. But - because the beacon interval is usually not an exact 726 * divisor of the size of the timers (16 bit), an unwanted "window" between 727 * these timers has developed! 728 * 729 * This is especially important with the ATIM window, because during 730 * the ATIM window only ATIM frames and no data frames are allowed to be 731 * sent, which creates transmission pauses after each beacon. This symptom 732 * has been described as "ramping ping" because ping times increase linearly 733 * for some time and then drop down again. A wrong window on the DMA beacon 734 * timer has the same effect, so we check for these two conditions. 735 * 736 * Returns true if O.K. 737 */ 738 bool 739 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) 740 { 741 unsigned int nbtt, atim, dma; 742 743 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); 744 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); 745 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 746 747 /* NOTE: SWBA is different. Having a wrong window there does not 748 * stop us from sending data and this condition is catched thru 749 * other means (SWBA interrupt) */ 750 751 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 752 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, 753 intval)) 754 return true; /* O.K. */ 755 return false; 756 } 757 758 /** 759 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class 760 * 761 * @ah: The &struct ath5k_hw 762 * @coverage_class: IEEE 802.11 coverage class number 763 * 764 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 765 */ 766 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 767 { 768 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 769 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 770 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 771 int cts_timeout = ack_timeout; 772 773 ath5k_hw_set_ifs_intervals(ah, slot_time); 774 ath5k_hw_set_ack_timeout(ah, ack_timeout); 775 ath5k_hw_set_cts_timeout(ah, cts_timeout); 776 777 ah->ah_coverage_class = coverage_class; 778 } 779 780 /***************************\ 781 * Init/Start/Stop functions * 782 \***************************/ 783 784 /** 785 * ath5k_hw_start_rx_pcu - Start RX engine 786 * 787 * @ah: The &struct ath5k_hw 788 * 789 * Starts RX engine on PCU so that hw can process RXed frames 790 * (ACK etc). 791 * 792 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 793 */ 794 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 795 { 796 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 797 } 798 799 /** 800 * at5k_hw_stop_rx_pcu - Stop RX engine 801 * 802 * @ah: The &struct ath5k_hw 803 * 804 * Stops RX engine on PCU 805 */ 806 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 807 { 808 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 809 } 810 811 /** 812 * ath5k_hw_set_opmode - Set PCU operating mode 813 * 814 * @ah: The &struct ath5k_hw 815 * @op_mode: &enum nl80211_iftype operating mode 816 * 817 * Configure PCU for the various operating modes (AP/STA etc) 818 */ 819 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 820 { 821 struct ath_common *common = ath5k_hw_common(ah); 822 u32 pcu_reg, beacon_reg, low_id, high_id; 823 824 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 825 826 /* Preserve rest settings */ 827 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 828 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 829 | AR5K_STA_ID1_KEYSRCH_MODE 830 | (ah->ah_version == AR5K_AR5210 ? 831 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 832 833 beacon_reg = 0; 834 835 switch (op_mode) { 836 case NL80211_IFTYPE_ADHOC: 837 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 838 beacon_reg |= AR5K_BCR_ADHOC; 839 if (ah->ah_version == AR5K_AR5210) 840 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 841 else 842 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 843 break; 844 845 case NL80211_IFTYPE_AP: 846 case NL80211_IFTYPE_MESH_POINT: 847 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 848 beacon_reg |= AR5K_BCR_AP; 849 if (ah->ah_version == AR5K_AR5210) 850 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 851 else 852 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 853 break; 854 855 case NL80211_IFTYPE_STATION: 856 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 857 | (ah->ah_version == AR5K_AR5210 ? 858 AR5K_STA_ID1_PWR_SV : 0); 859 case NL80211_IFTYPE_MONITOR: 860 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 861 | (ah->ah_version == AR5K_AR5210 ? 862 AR5K_STA_ID1_NO_PSPOLL : 0); 863 break; 864 865 default: 866 return -EINVAL; 867 } 868 869 /* 870 * Set PCU registers 871 */ 872 low_id = get_unaligned_le32(common->macaddr); 873 high_id = get_unaligned_le16(common->macaddr + 4); 874 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 875 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 876 877 /* 878 * Set Beacon Control Register on 5210 879 */ 880 if (ah->ah_version == AR5K_AR5210) 881 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 882 883 return 0; 884 } 885 886 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 887 u8 mode) 888 { 889 /* Set bssid and bssid mask */ 890 ath5k_hw_set_bssid(ah); 891 892 /* Set PCU config */ 893 ath5k_hw_set_opmode(ah, op_mode); 894 895 /* Write rate duration table only on AR5212 and if 896 * virtual interface has already been brought up 897 * XXX: rethink this after new mode changes to 898 * mac80211 are integrated */ 899 if (ah->ah_version == AR5K_AR5212 && 900 ah->ah_sc->nvifs) 901 ath5k_hw_write_rate_duration(ah); 902 903 /* Set RSSI/BRSSI thresholds 904 * 905 * Note: If we decide to set this value 906 * dynamicaly, have in mind that when AR5K_RSSI_THR 907 * register is read it might return 0x40 if we haven't 908 * wrote anything to it plus BMISS RSSI threshold is zeroed. 909 * So doing a save/restore procedure here isn't the right 910 * choice. Instead store it on ath5k_hw */ 911 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 912 AR5K_TUNE_BMISS_THRES << 913 AR5K_RSSI_THR_BMISS_S), 914 AR5K_RSSI_THR); 915 916 /* MIC QoS support */ 917 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 918 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 919 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 920 } 921 922 /* QoS NOACK Policy */ 923 if (ah->ah_version == AR5K_AR5212) { 924 ath5k_hw_reg_write(ah, 925 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 926 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 927 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 928 AR5K_QOS_NOACK); 929 } 930 931 /* Restore slot time and ACK timeouts */ 932 if (ah->ah_coverage_class > 0) 933 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 934 935 /* Set ACK bitrate mode (see ack_rates_high) */ 936 if (ah->ah_version == AR5K_AR5212) { 937 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 938 if (ah->ah_ack_bitrate_high) 939 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 940 else 941 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 942 } 943 return; 944 } 945