1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include <linux/pci-aspm.h> 20 #include "../ath.h" 21 #include "ath5k.h" 22 #include "debug.h" 23 #include "base.h" 24 #include "reg.h" 25 26 /* Known PCI ids */ 27 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = { 28 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 29 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 30 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 31 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 32 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 33 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 34 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 35 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 36 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 37 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 38 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 39 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 40 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 41 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 42 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 43 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 44 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 45 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 46 { 0 } 47 }; 48 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 49 50 /* return bus cachesize in 4B word units */ 51 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) 52 { 53 struct ath5k_softc *sc = (struct ath5k_softc *) common->priv; 54 u8 u8tmp; 55 56 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); 57 *csz = (int)u8tmp; 58 59 /* 60 * This check was put in to avoid "unplesant" consequences if 61 * the bootrom has not fully initialized all PCI devices. 62 * Sometimes the cache line size register is not set 63 */ 64 65 if (*csz == 0) 66 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ 67 } 68 69 /* 70 * Read from eeprom 71 */ 72 bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) 73 { 74 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; 75 u32 status, timeout; 76 77 /* 78 * Initialize EEPROM access 79 */ 80 if (ah->ah_version == AR5K_AR5210) { 81 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); 82 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); 83 } else { 84 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); 85 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, 86 AR5K_EEPROM_CMD_READ); 87 } 88 89 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { 90 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); 91 if (status & AR5K_EEPROM_STAT_RDDONE) { 92 if (status & AR5K_EEPROM_STAT_RDERR) 93 return -EIO; 94 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & 95 0xffff); 96 return 0; 97 } 98 udelay(15); 99 } 100 101 return -ETIMEDOUT; 102 } 103 104 int ath5k_hw_read_srev(struct ath5k_hw *ah) 105 { 106 ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV); 107 return 0; 108 } 109 110 /* Common ath_bus_opts structure */ 111 static const struct ath_bus_ops ath_pci_bus_ops = { 112 .ath_bus_type = ATH_PCI, 113 .read_cachesize = ath5k_pci_read_cachesize, 114 .eeprom_read = ath5k_pci_eeprom_read, 115 }; 116 117 /********************\ 118 * PCI Initialization * 119 \********************/ 120 121 static int __devinit 122 ath5k_pci_probe(struct pci_dev *pdev, 123 const struct pci_device_id *id) 124 { 125 void __iomem *mem; 126 struct ath5k_softc *sc; 127 struct ieee80211_hw *hw; 128 int ret; 129 u8 csz; 130 131 /* 132 * L0s needs to be disabled on all ath5k cards. 133 * 134 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled 135 * by default in the future in 2.6.36) this will also mean both L1 and 136 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do 137 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices 138 * though but cannot currently undue the effect of a blacklist, for 139 * details you can read pcie_aspm_sanity_check() and see how it adjusts 140 * the device link capability. 141 * 142 * It may be possible in the future to implement some PCI API to allow 143 * drivers to override blacklists for pre 1.1 PCIe but for now it is 144 * best to accept that both L0s and L1 will be disabled completely for 145 * distributions shipping with CONFIG_PCIEASPM rather than having this 146 * issue present. Motivation for adding this new API will be to help 147 * with power consumption for some of these devices. 148 */ 149 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); 150 151 ret = pci_enable_device(pdev); 152 if (ret) { 153 dev_err(&pdev->dev, "can't enable device\n"); 154 goto err; 155 } 156 157 /* XXX 32-bit addressing only */ 158 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 159 if (ret) { 160 dev_err(&pdev->dev, "32-bit DMA not available\n"); 161 goto err_dis; 162 } 163 164 /* 165 * Cache line size is used to size and align various 166 * structures used to communicate with the hardware. 167 */ 168 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 169 if (csz == 0) { 170 /* 171 * Linux 2.4.18 (at least) writes the cache line size 172 * register as a 16-bit wide register which is wrong. 173 * We must have this setup properly for rx buffer 174 * DMA to work so force a reasonable value here if it 175 * comes up zero. 176 */ 177 csz = L1_CACHE_BYTES >> 2; 178 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 179 } 180 /* 181 * The default setting of latency timer yields poor results, 182 * set it to the value used by other systems. It may be worth 183 * tweaking this setting more. 184 */ 185 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 186 187 /* Enable bus mastering */ 188 pci_set_master(pdev); 189 190 /* 191 * Disable the RETRY_TIMEOUT register (0x41) to keep 192 * PCI Tx retries from interfering with C3 CPU state. 193 */ 194 pci_write_config_byte(pdev, 0x41, 0); 195 196 ret = pci_request_region(pdev, 0, "ath5k"); 197 if (ret) { 198 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 199 goto err_dis; 200 } 201 202 mem = pci_iomap(pdev, 0, 0); 203 if (!mem) { 204 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 205 ret = -EIO; 206 goto err_reg; 207 } 208 209 /* 210 * Allocate hw (mac80211 main struct) 211 * and hw->priv (driver private data) 212 */ 213 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 214 if (hw == NULL) { 215 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 216 ret = -ENOMEM; 217 goto err_map; 218 } 219 220 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 221 222 sc = hw->priv; 223 sc->hw = hw; 224 sc->pdev = pdev; 225 sc->dev = &pdev->dev; 226 sc->irq = pdev->irq; 227 sc->devid = id->device; 228 sc->iobase = mem; /* So we can unmap it on detach */ 229 230 /* Initialize */ 231 ret = ath5k_init_softc(sc, &ath_pci_bus_ops); 232 if (ret) 233 goto err_free; 234 235 /* Set private data */ 236 pci_set_drvdata(pdev, hw); 237 238 return 0; 239 err_free: 240 ieee80211_free_hw(hw); 241 err_map: 242 pci_iounmap(pdev, mem); 243 err_reg: 244 pci_release_region(pdev, 0); 245 err_dis: 246 pci_disable_device(pdev); 247 err: 248 return ret; 249 } 250 251 static void __devexit 252 ath5k_pci_remove(struct pci_dev *pdev) 253 { 254 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 255 struct ath5k_softc *sc = hw->priv; 256 257 ath5k_deinit_softc(sc); 258 pci_iounmap(pdev, sc->iobase); 259 pci_release_region(pdev, 0); 260 pci_disable_device(pdev); 261 ieee80211_free_hw(hw); 262 } 263 264 #ifdef CONFIG_PM_SLEEP 265 static int ath5k_pci_suspend(struct device *dev) 266 { 267 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev)); 268 269 ath5k_led_off(sc); 270 return 0; 271 } 272 273 static int ath5k_pci_resume(struct device *dev) 274 { 275 struct pci_dev *pdev = to_pci_dev(dev); 276 struct ath5k_softc *sc = pci_get_drvdata(pdev); 277 278 /* 279 * Suspend/Resume resets the PCI configuration space, so we have to 280 * re-disable the RETRY_TIMEOUT register (0x41) to keep 281 * PCI Tx retries from interfering with C3 CPU state 282 */ 283 pci_write_config_byte(pdev, 0x41, 0); 284 285 ath5k_led_enable(sc); 286 return 0; 287 } 288 289 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 290 #define ATH5K_PM_OPS (&ath5k_pm_ops) 291 #else 292 #define ATH5K_PM_OPS NULL 293 #endif /* CONFIG_PM_SLEEP */ 294 295 static struct pci_driver ath5k_pci_driver = { 296 .name = KBUILD_MODNAME, 297 .id_table = ath5k_pci_id_table, 298 .probe = ath5k_pci_probe, 299 .remove = __devexit_p(ath5k_pci_remove), 300 .driver.pm = ATH5K_PM_OPS, 301 }; 302 303 /* 304 * Module init/exit functions 305 */ 306 static int __init 307 init_ath5k_pci(void) 308 { 309 int ret; 310 311 ret = pci_register_driver(&ath5k_pci_driver); 312 if (ret) { 313 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 314 return ret; 315 } 316 317 return 0; 318 } 319 320 static void __exit 321 exit_ath5k_pci(void) 322 { 323 pci_unregister_driver(&ath5k_pci_driver); 324 } 325 326 module_init(init_ath5k_pci); 327 module_exit(exit_ath5k_pci); 328