1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include <linux/pci-aspm.h> 20 #include <linux/etherdevice.h> 21 #include "../ath.h" 22 #include "ath5k.h" 23 #include "debug.h" 24 #include "base.h" 25 #include "reg.h" 26 27 /* Known PCI ids */ 28 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = { 29 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 30 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 31 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 32 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 33 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 34 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 35 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 36 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 37 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */ 38 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */ 39 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */ 40 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */ 41 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */ 42 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */ 43 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 44 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 45 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 46 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 47 { 0 } 48 }; 49 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 50 51 /* return bus cachesize in 4B word units */ 52 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) 53 { 54 struct ath5k_hw *ah = (struct ath5k_hw *) common->priv; 55 u8 u8tmp; 56 57 pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); 58 *csz = (int)u8tmp; 59 60 /* 61 * This check was put in to avoid "unpleasant" consequences if 62 * the bootrom has not fully initialized all PCI devices. 63 * Sometimes the cache line size register is not set 64 */ 65 66 if (*csz == 0) 67 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ 68 } 69 70 /* 71 * Read from eeprom 72 */ 73 static bool 74 ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) 75 { 76 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; 77 u32 status, timeout; 78 79 /* 80 * Initialize EEPROM access 81 */ 82 if (ah->ah_version == AR5K_AR5210) { 83 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); 84 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); 85 } else { 86 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); 87 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, 88 AR5K_EEPROM_CMD_READ); 89 } 90 91 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { 92 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); 93 if (status & AR5K_EEPROM_STAT_RDDONE) { 94 if (status & AR5K_EEPROM_STAT_RDERR) 95 return false; 96 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & 97 0xffff); 98 return true; 99 } 100 udelay(15); 101 } 102 103 return false; 104 } 105 106 int ath5k_hw_read_srev(struct ath5k_hw *ah) 107 { 108 ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV); 109 return 0; 110 } 111 112 /* 113 * Read the MAC address from eeprom or platform_data 114 */ 115 static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) 116 { 117 u8 mac_d[ETH_ALEN] = {}; 118 u32 total, offset; 119 u16 data; 120 int octet; 121 122 AR5K_EEPROM_READ(0x20, data); 123 124 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { 125 AR5K_EEPROM_READ(offset, data); 126 127 total += data; 128 mac_d[octet + 1] = data & 0xff; 129 mac_d[octet] = data >> 8; 130 octet += 2; 131 } 132 133 if (!total || total == 3 * 0xffff) 134 return -EINVAL; 135 136 memcpy(mac, mac_d, ETH_ALEN); 137 138 return 0; 139 } 140 141 142 /* Common ath_bus_opts structure */ 143 static const struct ath_bus_ops ath_pci_bus_ops = { 144 .ath_bus_type = ATH_PCI, 145 .read_cachesize = ath5k_pci_read_cachesize, 146 .eeprom_read = ath5k_pci_eeprom_read, 147 .eeprom_read_mac = ath5k_pci_eeprom_read_mac, 148 }; 149 150 /********************\ 151 * PCI Initialization * 152 \********************/ 153 154 static int __devinit 155 ath5k_pci_probe(struct pci_dev *pdev, 156 const struct pci_device_id *id) 157 { 158 void __iomem *mem; 159 struct ath5k_hw *ah; 160 struct ieee80211_hw *hw; 161 int ret; 162 u8 csz; 163 164 /* 165 * L0s needs to be disabled on all ath5k cards. 166 * 167 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled 168 * by default in the future in 2.6.36) this will also mean both L1 and 169 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do 170 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices 171 * though but cannot currently undue the effect of a blacklist, for 172 * details you can read pcie_aspm_sanity_check() and see how it adjusts 173 * the device link capability. 174 * 175 * It may be possible in the future to implement some PCI API to allow 176 * drivers to override blacklists for pre 1.1 PCIe but for now it is 177 * best to accept that both L0s and L1 will be disabled completely for 178 * distributions shipping with CONFIG_PCIEASPM rather than having this 179 * issue present. Motivation for adding this new API will be to help 180 * with power consumption for some of these devices. 181 */ 182 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); 183 184 ret = pci_enable_device(pdev); 185 if (ret) { 186 dev_err(&pdev->dev, "can't enable device\n"); 187 goto err; 188 } 189 190 /* XXX 32-bit addressing only */ 191 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 192 if (ret) { 193 dev_err(&pdev->dev, "32-bit DMA not available\n"); 194 goto err_dis; 195 } 196 197 /* 198 * Cache line size is used to size and align various 199 * structures used to communicate with the hardware. 200 */ 201 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 202 if (csz == 0) { 203 /* 204 * Linux 2.4.18 (at least) writes the cache line size 205 * register as a 16-bit wide register which is wrong. 206 * We must have this setup properly for rx buffer 207 * DMA to work so force a reasonable value here if it 208 * comes up zero. 209 */ 210 csz = L1_CACHE_BYTES >> 2; 211 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 212 } 213 /* 214 * The default setting of latency timer yields poor results, 215 * set it to the value used by other systems. It may be worth 216 * tweaking this setting more. 217 */ 218 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 219 220 /* Enable bus mastering */ 221 pci_set_master(pdev); 222 223 /* 224 * Disable the RETRY_TIMEOUT register (0x41) to keep 225 * PCI Tx retries from interfering with C3 CPU state. 226 */ 227 pci_write_config_byte(pdev, 0x41, 0); 228 229 ret = pci_request_region(pdev, 0, "ath5k"); 230 if (ret) { 231 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 232 goto err_dis; 233 } 234 235 mem = pci_iomap(pdev, 0, 0); 236 if (!mem) { 237 dev_err(&pdev->dev, "cannot remap PCI memory region\n"); 238 ret = -EIO; 239 goto err_reg; 240 } 241 242 /* 243 * Allocate hw (mac80211 main struct) 244 * and hw->priv (driver private data) 245 */ 246 hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops); 247 if (hw == NULL) { 248 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 249 ret = -ENOMEM; 250 goto err_map; 251 } 252 253 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 254 255 ah = hw->priv; 256 ah->hw = hw; 257 ah->pdev = pdev; 258 ah->dev = &pdev->dev; 259 ah->irq = pdev->irq; 260 ah->devid = id->device; 261 ah->iobase = mem; /* So we can unmap it on detach */ 262 263 /* Initialize */ 264 ret = ath5k_init_softc(ah, &ath_pci_bus_ops); 265 if (ret) 266 goto err_free; 267 268 /* Set private data */ 269 pci_set_drvdata(pdev, hw); 270 271 return 0; 272 err_free: 273 ieee80211_free_hw(hw); 274 err_map: 275 pci_iounmap(pdev, mem); 276 err_reg: 277 pci_release_region(pdev, 0); 278 err_dis: 279 pci_disable_device(pdev); 280 err: 281 return ret; 282 } 283 284 static void __devexit 285 ath5k_pci_remove(struct pci_dev *pdev) 286 { 287 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 288 struct ath5k_hw *ah = hw->priv; 289 290 ath5k_deinit_softc(ah); 291 pci_iounmap(pdev, ah->iobase); 292 pci_release_region(pdev, 0); 293 pci_disable_device(pdev); 294 ieee80211_free_hw(hw); 295 } 296 297 #ifdef CONFIG_PM_SLEEP 298 static int ath5k_pci_suspend(struct device *dev) 299 { 300 struct pci_dev *pdev = to_pci_dev(dev); 301 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 302 struct ath5k_hw *ah = hw->priv; 303 304 ath5k_led_off(ah); 305 return 0; 306 } 307 308 static int ath5k_pci_resume(struct device *dev) 309 { 310 struct pci_dev *pdev = to_pci_dev(dev); 311 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 312 struct ath5k_hw *ah = hw->priv; 313 314 /* 315 * Suspend/Resume resets the PCI configuration space, so we have to 316 * re-disable the RETRY_TIMEOUT register (0x41) to keep 317 * PCI Tx retries from interfering with C3 CPU state 318 */ 319 pci_write_config_byte(pdev, 0x41, 0); 320 321 ath5k_led_enable(ah); 322 return 0; 323 } 324 325 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 326 #define ATH5K_PM_OPS (&ath5k_pm_ops) 327 #else 328 #define ATH5K_PM_OPS NULL 329 #endif /* CONFIG_PM_SLEEP */ 330 331 static struct pci_driver ath5k_pci_driver = { 332 .name = KBUILD_MODNAME, 333 .id_table = ath5k_pci_id_table, 334 .probe = ath5k_pci_probe, 335 .remove = __devexit_p(ath5k_pci_remove), 336 .driver.pm = ATH5K_PM_OPS, 337 }; 338 339 /* 340 * Module init/exit functions 341 */ 342 static int __init 343 init_ath5k_pci(void) 344 { 345 int ret; 346 347 ret = pci_register_driver(&ath5k_pci_driver); 348 if (ret) { 349 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static void __exit 357 exit_ath5k_pci(void) 358 { 359 pci_unregister_driver(&ath5k_pci_driver); 360 } 361 362 module_init(init_ath5k_pci); 363 module_exit(exit_ath5k_pci); 364