1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/nl80211.h> 20 #include <linux/pci.h> 21 #include <linux/etherdevice.h> 22 #include <linux/module.h> 23 #include "../ath.h" 24 #include "ath5k.h" 25 #include "debug.h" 26 #include "base.h" 27 #include "reg.h" 28 29 /* Known PCI ids */ 30 static const struct pci_device_id ath5k_pci_id_table[] = { 31 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 32 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 33 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 34 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 35 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 36 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 37 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 38 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 39 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */ 40 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */ 41 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */ 42 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */ 43 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */ 44 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */ 45 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 46 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 47 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 48 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 49 { PCI_VDEVICE(ATHEROS, 0xff16) }, /* Gigaset SX76[23] AR241[34]A */ 50 { PCI_VDEVICE(ATHEROS, 0xff1a) }, /* Arcadyan ARV45XX AR2417 */ 51 { PCI_VDEVICE(ATHEROS, 0xff1b) }, /* AR5BXB63 */ 52 { 0 } 53 }; 54 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 55 56 /* return bus cachesize in 4B word units */ 57 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) 58 { 59 struct ath5k_hw *ah = (struct ath5k_hw *) common->priv; 60 u8 u8tmp; 61 62 pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); 63 *csz = (int)u8tmp; 64 65 /* 66 * This check was put in to avoid "unpleasant" consequences if 67 * the bootrom has not fully initialized all PCI devices. 68 * Sometimes the cache line size register is not set 69 */ 70 71 if (*csz == 0) 72 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ 73 } 74 75 /* 76 * Read from eeprom 77 */ 78 static bool 79 ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) 80 { 81 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; 82 u32 status, timeout; 83 84 /* 85 * Initialize EEPROM access 86 */ 87 if (ah->ah_version == AR5K_AR5210) { 88 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); 89 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); 90 } else { 91 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); 92 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, 93 AR5K_EEPROM_CMD_READ); 94 } 95 96 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { 97 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); 98 if (status & AR5K_EEPROM_STAT_RDDONE) { 99 if (status & AR5K_EEPROM_STAT_RDERR) 100 return false; 101 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & 102 0xffff); 103 return true; 104 } 105 usleep_range(15, 20); 106 } 107 108 return false; 109 } 110 111 int ath5k_hw_read_srev(struct ath5k_hw *ah) 112 { 113 ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV); 114 return 0; 115 } 116 117 /* 118 * Read the MAC address from eeprom or platform_data 119 */ 120 static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) 121 { 122 u8 mac_d[ETH_ALEN] = {}; 123 u32 total, offset; 124 u16 data; 125 int octet; 126 127 AR5K_EEPROM_READ(0x20, data); 128 129 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { 130 AR5K_EEPROM_READ(offset, data); 131 132 total += data; 133 mac_d[octet + 1] = data & 0xff; 134 mac_d[octet] = data >> 8; 135 octet += 2; 136 } 137 138 if (!total || total == 3 * 0xffff) 139 return -EINVAL; 140 141 memcpy(mac, mac_d, ETH_ALEN); 142 143 return 0; 144 } 145 146 147 /* Common ath_bus_opts structure */ 148 static const struct ath_bus_ops ath_pci_bus_ops = { 149 .ath_bus_type = ATH_PCI, 150 .read_cachesize = ath5k_pci_read_cachesize, 151 .eeprom_read = ath5k_pci_eeprom_read, 152 .eeprom_read_mac = ath5k_pci_eeprom_read_mac, 153 }; 154 155 /********************\ 156 * PCI Initialization * 157 \********************/ 158 159 static int 160 ath5k_pci_probe(struct pci_dev *pdev, 161 const struct pci_device_id *id) 162 { 163 void __iomem *mem; 164 struct ath5k_hw *ah; 165 struct ieee80211_hw *hw; 166 int ret; 167 u8 csz; 168 169 /* 170 * L0s needs to be disabled on all ath5k cards. 171 * 172 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled 173 * by default in the future in 2.6.36) this will also mean both L1 and 174 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do 175 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices 176 * though but cannot currently undue the effect of a blacklist, for 177 * details you can read pcie_aspm_sanity_check() and see how it adjusts 178 * the device link capability. 179 * 180 * It may be possible in the future to implement some PCI API to allow 181 * drivers to override blacklists for pre 1.1 PCIe but for now it is 182 * best to accept that both L0s and L1 will be disabled completely for 183 * distributions shipping with CONFIG_PCIEASPM rather than having this 184 * issue present. Motivation for adding this new API will be to help 185 * with power consumption for some of these devices. 186 */ 187 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); 188 189 ret = pci_enable_device(pdev); 190 if (ret) { 191 dev_err(&pdev->dev, "can't enable device\n"); 192 goto err; 193 } 194 195 /* XXX 32-bit addressing only */ 196 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 197 if (ret) { 198 dev_err(&pdev->dev, "32-bit DMA not available\n"); 199 goto err_dis; 200 } 201 202 /* 203 * Cache line size is used to size and align various 204 * structures used to communicate with the hardware. 205 */ 206 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 207 if (csz == 0) { 208 /* 209 * Linux 2.4.18 (at least) writes the cache line size 210 * register as a 16-bit wide register which is wrong. 211 * We must have this setup properly for rx buffer 212 * DMA to work so force a reasonable value here if it 213 * comes up zero. 214 */ 215 csz = L1_CACHE_BYTES >> 2; 216 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 217 } 218 /* 219 * The default setting of latency timer yields poor results, 220 * set it to the value used by other systems. It may be worth 221 * tweaking this setting more. 222 */ 223 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 224 225 /* Enable bus mastering */ 226 pci_set_master(pdev); 227 228 /* 229 * Disable the RETRY_TIMEOUT register (0x41) to keep 230 * PCI Tx retries from interfering with C3 CPU state. 231 */ 232 pci_write_config_byte(pdev, 0x41, 0); 233 234 ret = pci_request_region(pdev, 0, "ath5k"); 235 if (ret) { 236 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 237 goto err_dis; 238 } 239 240 mem = pci_iomap(pdev, 0, 0); 241 if (!mem) { 242 dev_err(&pdev->dev, "cannot remap PCI memory region\n"); 243 ret = -EIO; 244 goto err_reg; 245 } 246 247 /* 248 * Allocate hw (mac80211 main struct) 249 * and hw->priv (driver private data) 250 */ 251 hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops); 252 if (hw == NULL) { 253 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 254 ret = -ENOMEM; 255 goto err_map; 256 } 257 258 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 259 260 ah = hw->priv; 261 ah->hw = hw; 262 ah->pdev = pdev; 263 ah->dev = &pdev->dev; 264 ah->irq = pdev->irq; 265 ah->devid = id->device; 266 ah->iobase = mem; /* So we can unmap it on detach */ 267 268 /* Initialize */ 269 ret = ath5k_init_ah(ah, &ath_pci_bus_ops); 270 if (ret) 271 goto err_free; 272 273 /* Set private data */ 274 pci_set_drvdata(pdev, hw); 275 276 return 0; 277 err_free: 278 ieee80211_free_hw(hw); 279 err_map: 280 pci_iounmap(pdev, mem); 281 err_reg: 282 pci_release_region(pdev, 0); 283 err_dis: 284 pci_disable_device(pdev); 285 err: 286 return ret; 287 } 288 289 static void 290 ath5k_pci_remove(struct pci_dev *pdev) 291 { 292 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 293 struct ath5k_hw *ah = hw->priv; 294 295 ath5k_deinit_ah(ah); 296 pci_iounmap(pdev, ah->iobase); 297 pci_release_region(pdev, 0); 298 pci_disable_device(pdev); 299 ieee80211_free_hw(hw); 300 } 301 302 #ifdef CONFIG_PM_SLEEP 303 static int ath5k_pci_suspend(struct device *dev) 304 { 305 struct ieee80211_hw *hw = dev_get_drvdata(dev); 306 struct ath5k_hw *ah = hw->priv; 307 308 ath5k_led_off(ah); 309 return 0; 310 } 311 312 static int ath5k_pci_resume(struct device *dev) 313 { 314 struct pci_dev *pdev = to_pci_dev(dev); 315 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 316 struct ath5k_hw *ah = hw->priv; 317 318 /* 319 * Suspend/Resume resets the PCI configuration space, so we have to 320 * re-disable the RETRY_TIMEOUT register (0x41) to keep 321 * PCI Tx retries from interfering with C3 CPU state 322 */ 323 pci_write_config_byte(pdev, 0x41, 0); 324 325 ath5k_led_enable(ah); 326 return 0; 327 } 328 329 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 330 #define ATH5K_PM_OPS (&ath5k_pm_ops) 331 #else 332 #define ATH5K_PM_OPS NULL 333 #endif /* CONFIG_PM_SLEEP */ 334 335 static struct pci_driver ath5k_pci_driver = { 336 .name = KBUILD_MODNAME, 337 .id_table = ath5k_pci_id_table, 338 .probe = ath5k_pci_probe, 339 .remove = ath5k_pci_remove, 340 .driver.pm = ATH5K_PM_OPS, 341 }; 342 343 module_pci_driver(ath5k_pci_driver); 344