1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include <linux/pci-aspm.h> 20 #include <linux/etherdevice.h> 21 #include <linux/module.h> 22 #include "../ath.h" 23 #include "ath5k.h" 24 #include "debug.h" 25 #include "base.h" 26 #include "reg.h" 27 28 /* Known PCI ids */ 29 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = { 30 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 31 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 32 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 33 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 34 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 35 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 36 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 37 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 38 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */ 39 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */ 40 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */ 41 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */ 42 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */ 43 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */ 44 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 45 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 46 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 47 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 48 { 0 } 49 }; 50 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 51 52 /* return bus cachesize in 4B word units */ 53 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) 54 { 55 struct ath5k_hw *ah = (struct ath5k_hw *) common->priv; 56 u8 u8tmp; 57 58 pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); 59 *csz = (int)u8tmp; 60 61 /* 62 * This check was put in to avoid "unpleasant" consequences if 63 * the bootrom has not fully initialized all PCI devices. 64 * Sometimes the cache line size register is not set 65 */ 66 67 if (*csz == 0) 68 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ 69 } 70 71 /* 72 * Read from eeprom 73 */ 74 static bool 75 ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) 76 { 77 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; 78 u32 status, timeout; 79 80 /* 81 * Initialize EEPROM access 82 */ 83 if (ah->ah_version == AR5K_AR5210) { 84 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); 85 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); 86 } else { 87 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); 88 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, 89 AR5K_EEPROM_CMD_READ); 90 } 91 92 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { 93 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); 94 if (status & AR5K_EEPROM_STAT_RDDONE) { 95 if (status & AR5K_EEPROM_STAT_RDERR) 96 return false; 97 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & 98 0xffff); 99 return true; 100 } 101 usleep_range(15, 20); 102 } 103 104 return false; 105 } 106 107 int ath5k_hw_read_srev(struct ath5k_hw *ah) 108 { 109 ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV); 110 return 0; 111 } 112 113 /* 114 * Read the MAC address from eeprom or platform_data 115 */ 116 static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) 117 { 118 u8 mac_d[ETH_ALEN] = {}; 119 u32 total, offset; 120 u16 data; 121 int octet; 122 123 AR5K_EEPROM_READ(0x20, data); 124 125 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { 126 AR5K_EEPROM_READ(offset, data); 127 128 total += data; 129 mac_d[octet + 1] = data & 0xff; 130 mac_d[octet] = data >> 8; 131 octet += 2; 132 } 133 134 if (!total || total == 3 * 0xffff) 135 return -EINVAL; 136 137 memcpy(mac, mac_d, ETH_ALEN); 138 139 return 0; 140 } 141 142 143 /* Common ath_bus_opts structure */ 144 static const struct ath_bus_ops ath_pci_bus_ops = { 145 .ath_bus_type = ATH_PCI, 146 .read_cachesize = ath5k_pci_read_cachesize, 147 .eeprom_read = ath5k_pci_eeprom_read, 148 .eeprom_read_mac = ath5k_pci_eeprom_read_mac, 149 }; 150 151 /********************\ 152 * PCI Initialization * 153 \********************/ 154 155 static int __devinit 156 ath5k_pci_probe(struct pci_dev *pdev, 157 const struct pci_device_id *id) 158 { 159 void __iomem *mem; 160 struct ath5k_hw *ah; 161 struct ieee80211_hw *hw; 162 int ret; 163 u8 csz; 164 165 /* 166 * L0s needs to be disabled on all ath5k cards. 167 * 168 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled 169 * by default in the future in 2.6.36) this will also mean both L1 and 170 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do 171 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices 172 * though but cannot currently undue the effect of a blacklist, for 173 * details you can read pcie_aspm_sanity_check() and see how it adjusts 174 * the device link capability. 175 * 176 * It may be possible in the future to implement some PCI API to allow 177 * drivers to override blacklists for pre 1.1 PCIe but for now it is 178 * best to accept that both L0s and L1 will be disabled completely for 179 * distributions shipping with CONFIG_PCIEASPM rather than having this 180 * issue present. Motivation for adding this new API will be to help 181 * with power consumption for some of these devices. 182 */ 183 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); 184 185 ret = pci_enable_device(pdev); 186 if (ret) { 187 dev_err(&pdev->dev, "can't enable device\n"); 188 goto err; 189 } 190 191 /* XXX 32-bit addressing only */ 192 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 193 if (ret) { 194 dev_err(&pdev->dev, "32-bit DMA not available\n"); 195 goto err_dis; 196 } 197 198 /* 199 * Cache line size is used to size and align various 200 * structures used to communicate with the hardware. 201 */ 202 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 203 if (csz == 0) { 204 /* 205 * Linux 2.4.18 (at least) writes the cache line size 206 * register as a 16-bit wide register which is wrong. 207 * We must have this setup properly for rx buffer 208 * DMA to work so force a reasonable value here if it 209 * comes up zero. 210 */ 211 csz = L1_CACHE_BYTES >> 2; 212 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 213 } 214 /* 215 * The default setting of latency timer yields poor results, 216 * set it to the value used by other systems. It may be worth 217 * tweaking this setting more. 218 */ 219 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 220 221 /* Enable bus mastering */ 222 pci_set_master(pdev); 223 224 /* 225 * Disable the RETRY_TIMEOUT register (0x41) to keep 226 * PCI Tx retries from interfering with C3 CPU state. 227 */ 228 pci_write_config_byte(pdev, 0x41, 0); 229 230 ret = pci_request_region(pdev, 0, "ath5k"); 231 if (ret) { 232 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 233 goto err_dis; 234 } 235 236 mem = pci_iomap(pdev, 0, 0); 237 if (!mem) { 238 dev_err(&pdev->dev, "cannot remap PCI memory region\n"); 239 ret = -EIO; 240 goto err_reg; 241 } 242 243 /* 244 * Allocate hw (mac80211 main struct) 245 * and hw->priv (driver private data) 246 */ 247 hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops); 248 if (hw == NULL) { 249 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 250 ret = -ENOMEM; 251 goto err_map; 252 } 253 254 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 255 256 ah = hw->priv; 257 ah->hw = hw; 258 ah->pdev = pdev; 259 ah->dev = &pdev->dev; 260 ah->irq = pdev->irq; 261 ah->devid = id->device; 262 ah->iobase = mem; /* So we can unmap it on detach */ 263 264 /* Initialize */ 265 ret = ath5k_init_ah(ah, &ath_pci_bus_ops); 266 if (ret) 267 goto err_free; 268 269 /* Set private data */ 270 pci_set_drvdata(pdev, hw); 271 272 return 0; 273 err_free: 274 ieee80211_free_hw(hw); 275 err_map: 276 pci_iounmap(pdev, mem); 277 err_reg: 278 pci_release_region(pdev, 0); 279 err_dis: 280 pci_disable_device(pdev); 281 err: 282 return ret; 283 } 284 285 static void __devexit 286 ath5k_pci_remove(struct pci_dev *pdev) 287 { 288 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 289 struct ath5k_hw *ah = hw->priv; 290 291 ath5k_deinit_ah(ah); 292 pci_iounmap(pdev, ah->iobase); 293 pci_release_region(pdev, 0); 294 pci_disable_device(pdev); 295 ieee80211_free_hw(hw); 296 } 297 298 #ifdef CONFIG_PM_SLEEP 299 static int ath5k_pci_suspend(struct device *dev) 300 { 301 struct pci_dev *pdev = to_pci_dev(dev); 302 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 303 struct ath5k_hw *ah = hw->priv; 304 305 ath5k_led_off(ah); 306 return 0; 307 } 308 309 static int ath5k_pci_resume(struct device *dev) 310 { 311 struct pci_dev *pdev = to_pci_dev(dev); 312 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 313 struct ath5k_hw *ah = hw->priv; 314 315 /* 316 * Suspend/Resume resets the PCI configuration space, so we have to 317 * re-disable the RETRY_TIMEOUT register (0x41) to keep 318 * PCI Tx retries from interfering with C3 CPU state 319 */ 320 pci_write_config_byte(pdev, 0x41, 0); 321 322 ath5k_led_enable(ah); 323 return 0; 324 } 325 326 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 327 #define ATH5K_PM_OPS (&ath5k_pm_ops) 328 #else 329 #define ATH5K_PM_OPS NULL 330 #endif /* CONFIG_PM_SLEEP */ 331 332 static struct pci_driver ath5k_pci_driver = { 333 .name = KBUILD_MODNAME, 334 .id_table = ath5k_pci_id_table, 335 .probe = ath5k_pci_probe, 336 .remove = __devexit_p(ath5k_pci_remove), 337 .driver.pm = ATH5K_PM_OPS, 338 }; 339 340 /* 341 * Module init/exit functions 342 */ 343 static int __init 344 init_ath5k_pci(void) 345 { 346 int ret; 347 348 ret = pci_register_driver(&ath5k_pci_driver); 349 if (ret) { 350 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 351 return ret; 352 } 353 354 return 0; 355 } 356 357 static void __exit 358 exit_ath5k_pci(void) 359 { 360 pci_unregister_driver(&ath5k_pci_driver); 361 } 362 363 module_init(init_ath5k_pci); 364 module_exit(exit_ath5k_pci); 365