1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 /* 20 * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) 21 */ 22 #define AR5K_EEPROM_PCIE_OFFSET 0x02 /* Contains offset to PCI-E infos */ 23 #define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40 /* PCIE_OFFSET points here when 24 * SERDES infos are present */ 25 #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ 26 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ 27 #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ 28 #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ 29 #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ 30 31 #define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */ 32 33 #define AR5K_EEPROM_RFKILL 0x0f 34 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c 35 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 36 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 37 #define AR5K_EEPROM_RFKILL_POLARITY_S 1 38 39 #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ 40 #define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */ 41 #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ 42 #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) 43 #define AR5K_EEPROM_INFO_CKSUM 0xffff 44 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) 45 46 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ 47 #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ 48 #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ 49 #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ 50 #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ 51 #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */ 52 #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ 53 #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ 54 #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ 55 #define AR5K_EEPROM_VERSION_4_3 0x4003 /* power calibration changes */ 56 #define AR5K_EEPROM_VERSION_4_4 0x4004 57 #define AR5K_EEPROM_VERSION_4_5 0x4005 58 #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ 59 #define AR5K_EEPROM_VERSION_4_7 0x3007 /* 4007 ? */ 60 #define AR5K_EEPROM_VERSION_4_9 0x4009 /* EAR futureproofing */ 61 #define AR5K_EEPROM_VERSION_5_0 0x5000 /* Has 2413 PDADC calibration etc */ 62 #define AR5K_EEPROM_VERSION_5_1 0x5001 /* Has capability values */ 63 #define AR5K_EEPROM_VERSION_5_3 0x5003 /* Has spur mitigation tables */ 64 65 #define AR5K_EEPROM_MODE_11A 0 66 #define AR5K_EEPROM_MODE_11B 1 67 #define AR5K_EEPROM_MODE_11G 2 68 69 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ 70 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) 71 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) 72 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) 73 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ 74 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ 75 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) 76 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ 77 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ 78 79 /* Newer EEPROMs are using a different offset */ 80 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ 81 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) 82 83 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) 84 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((s8)(((_v) >> 8) & 0xff)) 85 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((s8)((_v) & 0xff)) 86 87 /* Misc values available since EEPROM 4.0 */ 88 #define AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4) 89 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) 90 #define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1) 91 #define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1) 92 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) 93 94 #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) 95 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) 96 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) 97 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1) 98 99 #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) 100 #define AR5K_EEPROM_EEP_FILE_VERSION(_v) (((_v) >> 8) & 0xff) 101 #define AR5K_EEPROM_EAR_FILE_VERSION(_v) ((_v) & 0xff) 102 103 #define AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7) 104 #define AR5K_EEPROM_ART_BUILD_NUM(_v) (((_v) >> 10) & 0x3f) 105 #define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff) 106 107 #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) 108 #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff) 109 #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) 110 #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) 111 112 #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) 113 #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) 114 #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) 115 #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) 116 #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) 117 #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) 118 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) 119 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) 120 121 #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) 122 #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) 123 #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) 124 #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) 125 #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) 126 #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) 127 #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) 128 #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) 129 130 /* calibration settings */ 131 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) 132 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) 133 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) 134 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */ 135 #define AR5K_EEPROM_GROUPS_START(_v) AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */ 136 #define AR5K_EEPROM_GROUP1_OFFSET 0x0 137 #define AR5K_EEPROM_GROUP2_OFFSET 0x5 138 #define AR5K_EEPROM_GROUP3_OFFSET 0x37 139 #define AR5K_EEPROM_GROUP4_OFFSET 0x46 140 #define AR5K_EEPROM_GROUP5_OFFSET 0x55 141 #define AR5K_EEPROM_GROUP6_OFFSET 0x65 142 #define AR5K_EEPROM_GROUP7_OFFSET 0x69 143 #define AR5K_EEPROM_GROUP8_OFFSET 0x6f 144 145 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ 146 AR5K_EEPROM_GROUP5_OFFSET, 0x0000) 147 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ 148 AR5K_EEPROM_GROUP6_OFFSET, 0x0010) 149 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ 150 AR5K_EEPROM_GROUP7_OFFSET, 0x0014) 151 152 /* [3.1 - 3.3] */ 153 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec 154 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed 155 156 #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */ 157 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ 158 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ 159 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ 160 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 161 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ 162 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 163 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */ 164 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 165 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ 166 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 167 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ 168 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 169 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ 170 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 171 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ 172 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 173 174 /* Some EEPROM defines */ 175 #define AR5K_EEPROM_EEP_SCALE 100 176 #define AR5K_EEPROM_EEP_DELTA 10 177 #define AR5K_EEPROM_N_MODES 3 178 #define AR5K_EEPROM_N_5GHZ_CHAN 10 179 #define AR5K_EEPROM_N_2GHZ_CHAN 3 180 #define AR5K_EEPROM_N_2GHZ_CHAN_2413 4 181 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4 182 #define AR5K_EEPROM_MAX_CHAN 10 183 #define AR5K_EEPROM_N_PWR_POINTS_5111 11 184 #define AR5K_EEPROM_N_PCDAC 11 185 #define AR5K_EEPROM_N_PHASE_CAL 5 186 #define AR5K_EEPROM_N_TEST_FREQ 8 187 #define AR5K_EEPROM_N_EDGES 8 188 #define AR5K_EEPROM_N_INTERCEPTS 11 189 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) 190 #define AR5K_EEPROM_PCDAC_M 0x3f 191 #define AR5K_EEPROM_PCDAC_START 1 192 #define AR5K_EEPROM_PCDAC_STOP 63 193 #define AR5K_EEPROM_PCDAC_STEP 1 194 #define AR5K_EEPROM_NON_EDGE_M 0x40 195 #define AR5K_EEPROM_CHANNEL_POWER 8 196 #define AR5K_EEPROM_N_OBDB 4 197 #define AR5K_EEPROM_OBDB_DIS 0xffff 198 #define AR5K_EEPROM_CHANNEL_DIS 0xff 199 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) 200 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) 201 #define AR5K_EEPROM_MAX_CTLS 32 202 #define AR5K_EEPROM_N_PD_CURVES 4 203 #define AR5K_EEPROM_N_XPD0_POINTS 4 204 #define AR5K_EEPROM_N_XPD3_POINTS 3 205 #define AR5K_EEPROM_N_PD_GAINS 4 206 #define AR5K_EEPROM_N_PD_POINTS 5 207 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 208 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 209 #define AR5K_EEPROM_POWER_M 0x3f 210 #define AR5K_EEPROM_POWER_MIN 0 211 #define AR5K_EEPROM_POWER_MAX 3150 212 #define AR5K_EEPROM_POWER_STEP 50 213 #define AR5K_EEPROM_POWER_TABLE_SIZE 64 214 #define AR5K_EEPROM_N_POWER_LOC_11B 4 215 #define AR5K_EEPROM_N_POWER_LOC_11G 6 216 #define AR5K_EEPROM_I_GAIN 10 217 #define AR5K_EEPROM_CCK_OFDM_DELTA 15 218 #define AR5K_EEPROM_N_IQ_CAL 2 219 /* 5GHz/2GHz */ 220 enum ath5k_eeprom_freq_bands{ 221 AR5K_EEPROM_BAND_5GHZ = 0, 222 AR5K_EEPROM_BAND_2GHZ = 1, 223 AR5K_EEPROM_N_FREQ_BANDS, 224 }; 225 /* Spur chans per freq band */ 226 #define AR5K_EEPROM_N_SPUR_CHANS 5 227 /* fbin value for chan 2464 x2 */ 228 #define AR5K_EEPROM_5413_SPUR_CHAN_1 1640 229 /* fbin value for chan 2420 x2 */ 230 #define AR5K_EEPROM_5413_SPUR_CHAN_2 1200 231 #define AR5K_EEPROM_SPUR_CHAN_MASK 0x3FFF 232 #define AR5K_EEPROM_NO_SPUR 0x8000 233 #define AR5K_SPUR_CHAN_WIDTH 87 234 #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz 3125 235 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz 6250 236 237 #define AR5K_EEPROM_READ(_o, _v) do { \ 238 ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \ 239 if (ret) \ 240 return ret; \ 241 } while (0) 242 243 #define AR5K_EEPROM_READ_HDR(_o, _v) \ 244 AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \ 245 246 enum ath5k_ant_table { 247 AR5K_ANT_CTL = 0, /* Idle switch table settings */ 248 AR5K_ANT_SWTABLE_A = 1, /* Switch table for antenna A */ 249 AR5K_ANT_SWTABLE_B = 2, /* Switch table for antenna B */ 250 AR5K_ANT_MAX, 251 }; 252 253 enum ath5k_ctl_mode { 254 AR5K_CTL_11A = 0, 255 AR5K_CTL_11B = 1, 256 AR5K_CTL_11G = 2, 257 AR5K_CTL_TURBO = 3, 258 AR5K_CTL_TURBOG = 4, 259 AR5K_CTL_2GHT20 = 5, 260 AR5K_CTL_5GHT20 = 6, 261 AR5K_CTL_2GHT40 = 7, 262 AR5K_CTL_5GHT40 = 8, 263 AR5K_CTL_MODE_M = 15, 264 }; 265 266 /* Default CTL ids for the 3 main reg domains. 267 * Atheros only uses these by default but vendors 268 * can have up to 32 different CTLs for different 269 * scenarios. Note that theese values are ORed with 270 * the mode id (above) so we can have up to 24 CTL 271 * datasets out of these 3 main regdomains. That leaves 272 * 8 ids that can be used by vendors and since 0x20 is 273 * missing from HAL sources i guess this is the set of 274 * custom CTLs vendors can use. */ 275 #define AR5K_CTL_FCC 0x10 276 #define AR5K_CTL_CUSTOM 0x20 277 #define AR5K_CTL_ETSI 0x30 278 #define AR5K_CTL_MKK 0x40 279 280 /* Indicates a CTL with only mode set and 281 * no reg domain mapping, such CTLs are used 282 * for world roaming domains or simply when 283 * a reg domain is not set */ 284 #define AR5K_CTL_NO_REGDOMAIN 0xf0 285 286 /* Indicates an empty (invalid) CTL */ 287 #define AR5K_CTL_NO_CTL 0xff 288 289 /* Per channel calibration data, used for power table setup */ 290 struct ath5k_chan_pcal_info_rf5111 { 291 /* Power levels in half dbm units 292 * for one power curve. */ 293 u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111]; 294 /* PCDAC table steps 295 * for the above values */ 296 u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111]; 297 /* Starting PCDAC step */ 298 u8 pcdac_min; 299 /* Final PCDAC step */ 300 u8 pcdac_max; 301 }; 302 303 struct ath5k_chan_pcal_info_rf5112 { 304 /* Power levels in quarter dBm units 305 * for lower (0) and higher (3) 306 * level curves in 0.25dB units */ 307 s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS]; 308 s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS]; 309 /* PCDAC table steps 310 * for the above values */ 311 u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS]; 312 u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS]; 313 }; 314 315 struct ath5k_chan_pcal_info_rf2413 { 316 /* Starting pwr/pddac values */ 317 s8 pwr_i[AR5K_EEPROM_N_PD_GAINS]; 318 u8 pddac_i[AR5K_EEPROM_N_PD_GAINS]; 319 /* (pwr,pddac) points 320 * power levels in 0.5dB units */ 321 s8 pwr[AR5K_EEPROM_N_PD_GAINS] 322 [AR5K_EEPROM_N_PD_POINTS]; 323 u8 pddac[AR5K_EEPROM_N_PD_GAINS] 324 [AR5K_EEPROM_N_PD_POINTS]; 325 }; 326 327 enum ath5k_powertable_type { 328 AR5K_PWRTABLE_PWR_TO_PCDAC = 0, 329 AR5K_PWRTABLE_LINEAR_PCDAC = 1, 330 AR5K_PWRTABLE_PWR_TO_PDADC = 2, 331 }; 332 333 struct ath5k_pdgain_info { 334 u8 pd_points; 335 u8 *pd_step; 336 /* Power values are in 337 * 0.25dB units */ 338 s16 *pd_pwr; 339 }; 340 341 struct ath5k_chan_pcal_info { 342 /* Frequency */ 343 u16 freq; 344 /* Tx power boundaries */ 345 s16 max_pwr; 346 s16 min_pwr; 347 union { 348 struct ath5k_chan_pcal_info_rf5111 rf5111_info; 349 struct ath5k_chan_pcal_info_rf5112 rf5112_info; 350 struct ath5k_chan_pcal_info_rf2413 rf2413_info; 351 }; 352 /* Raw values used by phy code 353 * Curves are stored in order from lower 354 * gain to higher gain (max txpower -> min txpower) */ 355 struct ath5k_pdgain_info *pd_curves; 356 }; 357 358 /* Per rate calibration data for each mode, 359 * used for rate power table setup. 360 * Note: Values in 0.5dB units */ 361 struct ath5k_rate_pcal_info { 362 u16 freq; /* Frequency */ 363 /* Power level for 6-24Mbit/s rates or 364 * 1Mb rate */ 365 u16 target_power_6to24; 366 /* Power level for 36Mbit rate or 367 * 2Mb rate */ 368 u16 target_power_36; 369 /* Power level for 48Mbit rate or 370 * 5.5Mbit rate */ 371 u16 target_power_48; 372 /* Power level for 54Mbit rate or 373 * 11Mbit rate */ 374 u16 target_power_54; 375 }; 376 377 /* Power edges for conformance test limits */ 378 struct ath5k_edge_power { 379 u16 freq; 380 u16 edge; /* in half dBm */ 381 bool flag; 382 }; 383 384 /* EEPROM calibration data */ 385 struct ath5k_eeprom_info { 386 387 /* Header information */ 388 u16 ee_magic; 389 u16 ee_protect; 390 u16 ee_regdomain; 391 u16 ee_version; 392 u16 ee_header; 393 u16 ee_ant_gain; 394 u8 ee_rfkill_pin; 395 bool ee_rfkill_pol; 396 bool ee_is_hb63; 397 bool ee_serdes; 398 u16 ee_misc0; 399 u16 ee_misc1; 400 u16 ee_misc2; 401 u16 ee_misc3; 402 u16 ee_misc4; 403 u16 ee_misc5; 404 u16 ee_misc6; 405 u16 ee_cck_ofdm_gain_delta; 406 u16 ee_cck_ofdm_power_delta; 407 u16 ee_scaled_cck_delta; 408 409 /* RF Calibration settings (reset, rfregs) */ 410 u16 ee_i_cal[AR5K_EEPROM_N_MODES]; 411 u16 ee_q_cal[AR5K_EEPROM_N_MODES]; 412 u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; 413 u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; 414 u16 ee_xr_power[AR5K_EEPROM_N_MODES]; 415 u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; 416 u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES]; 417 u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; 418 u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; 419 u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; 420 u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; 421 u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; 422 u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; 423 u16 ee_thr_62[AR5K_EEPROM_N_MODES]; 424 u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; 425 u16 ee_xpd[AR5K_EEPROM_N_MODES]; 426 u16 ee_x_gain[AR5K_EEPROM_N_MODES]; 427 u16 ee_i_gain[AR5K_EEPROM_N_MODES]; 428 u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; 429 u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES]; 430 u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES]; 431 u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES]; 432 433 /* Power calibration data */ 434 u16 ee_false_detect[AR5K_EEPROM_N_MODES]; 435 436 /* Number of pd gain curves per mode */ 437 u8 ee_pd_gains[AR5K_EEPROM_N_MODES]; 438 /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */ 439 u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS]; 440 441 u8 ee_n_piers[AR5K_EEPROM_N_MODES]; 442 struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN]; 443 struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 444 struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 445 446 /* Per rate target power levels */ 447 u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES]; 448 struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN]; 449 struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 450 struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 451 452 /* Conformance test limits (Unused) */ 453 u8 ee_ctls; 454 u8 ee_ctl[AR5K_EEPROM_MAX_CTLS]; 455 struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS]; 456 457 /* Noise Floor Calibration settings */ 458 s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; 459 s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]; 460 s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]; 461 s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES]; 462 s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES]; 463 s8 ee_pd_gain_overlap; 464 465 /* Spur mitigation data (fbin values for spur channels) */ 466 u16 ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS]; 467 468 /* Antenna raw switch tables */ 469 u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 470 }; 471 472