1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 /* 20 * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) 21 */ 22 #define AR5K_EEPROM_PCIE_OFFSET 0x02 /* Contains offset to PCI-E infos */ 23 #define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40 /* PCIE_OFFSET points here when 24 * SERDES infos are present */ 25 #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ 26 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ 27 #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ 28 #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ 29 #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ 30 31 #define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */ 32 33 #define AR5K_EEPROM_RFKILL 0x0f 34 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c 35 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 36 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 37 #define AR5K_EEPROM_RFKILL_POLARITY_S 1 38 39 #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ 40 41 /* FLASH(EEPROM) Defines for AR531X chips */ 42 #define AR5K_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */ 43 #define AR5K_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */ 44 #define AR5K_EEPROM_SIZE_UPPER_MASK 0xfff0 45 #define AR5K_EEPROM_SIZE_UPPER_SHIFT 4 46 #define AR5K_EEPROM_SIZE_ENDLOC_SHIFT 12 47 48 #define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */ 49 #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ 50 #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) 51 #define AR5K_EEPROM_INFO_CKSUM 0xffff 52 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) 53 54 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ 55 #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ 56 #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ 57 #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ 58 #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ 59 #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */ 60 #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ 61 #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ 62 #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ 63 #define AR5K_EEPROM_VERSION_4_3 0x4003 /* power calibration changes */ 64 #define AR5K_EEPROM_VERSION_4_4 0x4004 65 #define AR5K_EEPROM_VERSION_4_5 0x4005 66 #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ 67 #define AR5K_EEPROM_VERSION_4_7 0x3007 /* 4007 ? */ 68 #define AR5K_EEPROM_VERSION_4_9 0x4009 /* EAR futureproofing */ 69 #define AR5K_EEPROM_VERSION_5_0 0x5000 /* Has 2413 PDADC calibration etc */ 70 #define AR5K_EEPROM_VERSION_5_1 0x5001 /* Has capability values */ 71 #define AR5K_EEPROM_VERSION_5_3 0x5003 /* Has spur mitigation tables */ 72 73 #define AR5K_EEPROM_MODE_11A 0 74 #define AR5K_EEPROM_MODE_11B 1 75 #define AR5K_EEPROM_MODE_11G 2 76 77 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ 78 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) 79 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) 80 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) 81 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ 82 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ 83 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) 84 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ 85 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ 86 87 /* Newer EEPROMs are using a different offset */ 88 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ 89 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) 90 91 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) 92 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((s8)(((_v) >> 8) & 0xff)) 93 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((s8)((_v) & 0xff)) 94 95 /* Misc values available since EEPROM 4.0 */ 96 #define AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4) 97 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) 98 #define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1) 99 #define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1) 100 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) 101 102 #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) 103 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) 104 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) 105 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1) 106 107 #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) 108 #define AR5K_EEPROM_EEP_FILE_VERSION(_v) (((_v) >> 8) & 0xff) 109 #define AR5K_EEPROM_EAR_FILE_VERSION(_v) ((_v) & 0xff) 110 111 #define AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7) 112 #define AR5K_EEPROM_ART_BUILD_NUM(_v) (((_v) >> 10) & 0x3f) 113 #define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff) 114 115 #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) 116 #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff) 117 #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) 118 #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) 119 120 #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) 121 #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) 122 #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) 123 #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) 124 #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) 125 #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) 126 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) 127 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) 128 129 #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) 130 #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) 131 #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) 132 #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) 133 #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) 134 #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) 135 #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) 136 #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) 137 138 /* calibration settings */ 139 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) 140 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) 141 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) 142 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */ 143 #define AR5K_EEPROM_GROUPS_START(_v) AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */ 144 #define AR5K_EEPROM_GROUP1_OFFSET 0x0 145 #define AR5K_EEPROM_GROUP2_OFFSET 0x5 146 #define AR5K_EEPROM_GROUP3_OFFSET 0x37 147 #define AR5K_EEPROM_GROUP4_OFFSET 0x46 148 #define AR5K_EEPROM_GROUP5_OFFSET 0x55 149 #define AR5K_EEPROM_GROUP6_OFFSET 0x65 150 #define AR5K_EEPROM_GROUP7_OFFSET 0x69 151 #define AR5K_EEPROM_GROUP8_OFFSET 0x6f 152 153 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ 154 AR5K_EEPROM_GROUP5_OFFSET, 0x0000) 155 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ 156 AR5K_EEPROM_GROUP6_OFFSET, 0x0010) 157 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ 158 AR5K_EEPROM_GROUP7_OFFSET, 0x0014) 159 160 /* [3.1 - 3.3] */ 161 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec 162 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed 163 164 #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */ 165 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ 166 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ 167 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ 168 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 169 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ 170 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 171 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */ 172 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 173 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ 174 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 175 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ 176 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 177 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ 178 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 179 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ 180 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 181 182 /* Some EEPROM defines */ 183 #define AR5K_EEPROM_EEP_SCALE 100 184 #define AR5K_EEPROM_EEP_DELTA 10 185 #define AR5K_EEPROM_N_MODES 3 186 #define AR5K_EEPROM_N_5GHZ_CHAN 10 187 #define AR5K_EEPROM_N_2GHZ_CHAN 3 188 #define AR5K_EEPROM_N_2GHZ_CHAN_2413 4 189 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4 190 #define AR5K_EEPROM_MAX_CHAN 10 191 #define AR5K_EEPROM_N_PWR_POINTS_5111 11 192 #define AR5K_EEPROM_N_PCDAC 11 193 #define AR5K_EEPROM_N_PHASE_CAL 5 194 #define AR5K_EEPROM_N_TEST_FREQ 8 195 #define AR5K_EEPROM_N_EDGES 8 196 #define AR5K_EEPROM_N_INTERCEPTS 11 197 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) 198 #define AR5K_EEPROM_PCDAC_M 0x3f 199 #define AR5K_EEPROM_PCDAC_START 1 200 #define AR5K_EEPROM_PCDAC_STOP 63 201 #define AR5K_EEPROM_PCDAC_STEP 1 202 #define AR5K_EEPROM_NON_EDGE_M 0x40 203 #define AR5K_EEPROM_CHANNEL_POWER 8 204 #define AR5K_EEPROM_N_OBDB 4 205 #define AR5K_EEPROM_OBDB_DIS 0xffff 206 #define AR5K_EEPROM_CHANNEL_DIS 0xff 207 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) 208 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) 209 #define AR5K_EEPROM_MAX_CTLS 32 210 #define AR5K_EEPROM_N_PD_CURVES 4 211 #define AR5K_EEPROM_N_XPD0_POINTS 4 212 #define AR5K_EEPROM_N_XPD3_POINTS 3 213 #define AR5K_EEPROM_N_PD_GAINS 4 214 #define AR5K_EEPROM_N_PD_POINTS 5 215 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 216 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 217 #define AR5K_EEPROM_POWER_M 0x3f 218 #define AR5K_EEPROM_POWER_MIN 0 219 #define AR5K_EEPROM_POWER_MAX 3150 220 #define AR5K_EEPROM_POWER_STEP 50 221 #define AR5K_EEPROM_POWER_TABLE_SIZE 64 222 #define AR5K_EEPROM_N_POWER_LOC_11B 4 223 #define AR5K_EEPROM_N_POWER_LOC_11G 6 224 #define AR5K_EEPROM_I_GAIN 10 225 #define AR5K_EEPROM_CCK_OFDM_DELTA 15 226 #define AR5K_EEPROM_N_IQ_CAL 2 227 /* 5GHz/2GHz */ 228 enum ath5k_eeprom_freq_bands{ 229 AR5K_EEPROM_BAND_5GHZ = 0, 230 AR5K_EEPROM_BAND_2GHZ = 1, 231 AR5K_EEPROM_N_FREQ_BANDS, 232 }; 233 /* Spur chans per freq band */ 234 #define AR5K_EEPROM_N_SPUR_CHANS 5 235 /* fbin value for chan 2464 x2 */ 236 #define AR5K_EEPROM_5413_SPUR_CHAN_1 1640 237 /* fbin value for chan 2420 x2 */ 238 #define AR5K_EEPROM_5413_SPUR_CHAN_2 1200 239 #define AR5K_EEPROM_SPUR_CHAN_MASK 0x3FFF 240 #define AR5K_EEPROM_NO_SPUR 0x8000 241 #define AR5K_SPUR_CHAN_WIDTH 87 242 #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz 3125 243 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz 6250 244 245 #define AR5K_EEPROM_READ(_o, _v) do { \ 246 ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \ 247 if (ret) \ 248 return ret; \ 249 } while (0) 250 251 #define AR5K_EEPROM_READ_HDR(_o, _v) \ 252 AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \ 253 254 enum ath5k_ant_table { 255 AR5K_ANT_CTL = 0, /* Idle switch table settings */ 256 AR5K_ANT_SWTABLE_A = 1, /* Switch table for antenna A */ 257 AR5K_ANT_SWTABLE_B = 2, /* Switch table for antenna B */ 258 AR5K_ANT_MAX, 259 }; 260 261 enum ath5k_ctl_mode { 262 AR5K_CTL_11A = 0, 263 AR5K_CTL_11B = 1, 264 AR5K_CTL_11G = 2, 265 AR5K_CTL_TURBO = 3, 266 AR5K_CTL_TURBOG = 4, 267 AR5K_CTL_2GHT20 = 5, 268 AR5K_CTL_5GHT20 = 6, 269 AR5K_CTL_2GHT40 = 7, 270 AR5K_CTL_5GHT40 = 8, 271 AR5K_CTL_MODE_M = 15, 272 }; 273 274 /* Default CTL ids for the 3 main reg domains. 275 * Atheros only uses these by default but vendors 276 * can have up to 32 different CTLs for different 277 * scenarios. Note that theese values are ORed with 278 * the mode id (above) so we can have up to 24 CTL 279 * datasets out of these 3 main regdomains. That leaves 280 * 8 ids that can be used by vendors and since 0x20 is 281 * missing from HAL sources i guess this is the set of 282 * custom CTLs vendors can use. */ 283 #define AR5K_CTL_FCC 0x10 284 #define AR5K_CTL_CUSTOM 0x20 285 #define AR5K_CTL_ETSI 0x30 286 #define AR5K_CTL_MKK 0x40 287 288 /* Indicates a CTL with only mode set and 289 * no reg domain mapping, such CTLs are used 290 * for world roaming domains or simply when 291 * a reg domain is not set */ 292 #define AR5K_CTL_NO_REGDOMAIN 0xf0 293 294 /* Indicates an empty (invalid) CTL */ 295 #define AR5K_CTL_NO_CTL 0xff 296 297 /* Per channel calibration data, used for power table setup */ 298 struct ath5k_chan_pcal_info_rf5111 { 299 /* Power levels in half dbm units 300 * for one power curve. */ 301 u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111]; 302 /* PCDAC table steps 303 * for the above values */ 304 u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111]; 305 /* Starting PCDAC step */ 306 u8 pcdac_min; 307 /* Final PCDAC step */ 308 u8 pcdac_max; 309 }; 310 311 struct ath5k_chan_pcal_info_rf5112 { 312 /* Power levels in quarter dBm units 313 * for lower (0) and higher (3) 314 * level curves in 0.25dB units */ 315 s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS]; 316 s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS]; 317 /* PCDAC table steps 318 * for the above values */ 319 u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS]; 320 u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS]; 321 }; 322 323 struct ath5k_chan_pcal_info_rf2413 { 324 /* Starting pwr/pddac values */ 325 s8 pwr_i[AR5K_EEPROM_N_PD_GAINS]; 326 u8 pddac_i[AR5K_EEPROM_N_PD_GAINS]; 327 /* (pwr,pddac) points 328 * power levels in 0.5dB units */ 329 s8 pwr[AR5K_EEPROM_N_PD_GAINS] 330 [AR5K_EEPROM_N_PD_POINTS]; 331 u8 pddac[AR5K_EEPROM_N_PD_GAINS] 332 [AR5K_EEPROM_N_PD_POINTS]; 333 }; 334 335 enum ath5k_powertable_type { 336 AR5K_PWRTABLE_PWR_TO_PCDAC = 0, 337 AR5K_PWRTABLE_LINEAR_PCDAC = 1, 338 AR5K_PWRTABLE_PWR_TO_PDADC = 2, 339 }; 340 341 struct ath5k_pdgain_info { 342 u8 pd_points; 343 u8 *pd_step; 344 /* Power values are in 345 * 0.25dB units */ 346 s16 *pd_pwr; 347 }; 348 349 struct ath5k_chan_pcal_info { 350 /* Frequency */ 351 u16 freq; 352 /* Tx power boundaries */ 353 s16 max_pwr; 354 s16 min_pwr; 355 union { 356 struct ath5k_chan_pcal_info_rf5111 rf5111_info; 357 struct ath5k_chan_pcal_info_rf5112 rf5112_info; 358 struct ath5k_chan_pcal_info_rf2413 rf2413_info; 359 }; 360 /* Raw values used by phy code 361 * Curves are stored in order from lower 362 * gain to higher gain (max txpower -> min txpower) */ 363 struct ath5k_pdgain_info *pd_curves; 364 }; 365 366 /* Per rate calibration data for each mode, 367 * used for rate power table setup. 368 * Note: Values in 0.5dB units */ 369 struct ath5k_rate_pcal_info { 370 u16 freq; /* Frequency */ 371 /* Power level for 6-24Mbit/s rates or 372 * 1Mb rate */ 373 u16 target_power_6to24; 374 /* Power level for 36Mbit rate or 375 * 2Mb rate */ 376 u16 target_power_36; 377 /* Power level for 48Mbit rate or 378 * 5.5Mbit rate */ 379 u16 target_power_48; 380 /* Power level for 54Mbit rate or 381 * 11Mbit rate */ 382 u16 target_power_54; 383 }; 384 385 /* Power edges for conformance test limits */ 386 struct ath5k_edge_power { 387 u16 freq; 388 u16 edge; /* in half dBm */ 389 bool flag; 390 }; 391 392 /* EEPROM calibration data */ 393 struct ath5k_eeprom_info { 394 395 /* Header information */ 396 u16 ee_magic; 397 u16 ee_protect; 398 u16 ee_regdomain; 399 u16 ee_version; 400 u16 ee_header; 401 u16 ee_ant_gain; 402 u8 ee_rfkill_pin; 403 bool ee_rfkill_pol; 404 bool ee_is_hb63; 405 bool ee_serdes; 406 u16 ee_misc0; 407 u16 ee_misc1; 408 u16 ee_misc2; 409 u16 ee_misc3; 410 u16 ee_misc4; 411 u16 ee_misc5; 412 u16 ee_misc6; 413 u16 ee_cck_ofdm_gain_delta; 414 u16 ee_cck_ofdm_power_delta; 415 u16 ee_scaled_cck_delta; 416 417 /* RF Calibration settings (reset, rfregs) */ 418 u16 ee_i_cal[AR5K_EEPROM_N_MODES]; 419 u16 ee_q_cal[AR5K_EEPROM_N_MODES]; 420 u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; 421 u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; 422 u16 ee_xr_power[AR5K_EEPROM_N_MODES]; 423 u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; 424 u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES]; 425 u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; 426 u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; 427 u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; 428 u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; 429 u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; 430 u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; 431 u16 ee_thr_62[AR5K_EEPROM_N_MODES]; 432 u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; 433 u16 ee_xpd[AR5K_EEPROM_N_MODES]; 434 u16 ee_x_gain[AR5K_EEPROM_N_MODES]; 435 u16 ee_i_gain[AR5K_EEPROM_N_MODES]; 436 u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; 437 u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES]; 438 u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES]; 439 u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES]; 440 441 /* Power calibration data */ 442 u16 ee_false_detect[AR5K_EEPROM_N_MODES]; 443 444 /* Number of pd gain curves per mode */ 445 u8 ee_pd_gains[AR5K_EEPROM_N_MODES]; 446 /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */ 447 u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS]; 448 449 u8 ee_n_piers[AR5K_EEPROM_N_MODES]; 450 struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN]; 451 struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 452 struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 453 454 /* Per rate target power levels */ 455 u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES]; 456 struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN]; 457 struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 458 struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; 459 460 /* Conformance test limits (Unused) */ 461 u8 ee_ctls; 462 u8 ee_ctl[AR5K_EEPROM_MAX_CTLS]; 463 struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS]; 464 465 /* Noise Floor Calibration settings */ 466 s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; 467 s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]; 468 s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]; 469 s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES]; 470 s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES]; 471 s8 ee_pd_gain_overlap; 472 473 /* Spur mitigation data (fbin values for spur channels) */ 474 u16 ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS]; 475 476 /* Antenna raw switch tables */ 477 u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 478 }; 479 480