1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/pci.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 54 #include <net/ieee80211_radiotap.h> 55 56 #include <asm/unaligned.h> 57 58 #include "base.h" 59 #include "reg.h" 60 #include "debug.h" 61 62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */ 63 static int modparam_nohwcrypt; 64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 66 67 static int modparam_all_channels; 68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 70 71 72 /******************\ 73 * Internal defines * 74 \******************/ 75 76 /* Module info */ 77 MODULE_AUTHOR("Jiri Slaby"); 78 MODULE_AUTHOR("Nick Kossifidis"); 79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 81 MODULE_LICENSE("Dual BSD/GPL"); 82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)"); 83 84 85 /* Known PCI ids */ 86 static const struct pci_device_id ath5k_pci_id_table[] = { 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 105 { 0 } 106 }; 107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 108 109 /* Known SREVs */ 110 static const struct ath5k_srev_name srev_names[] = { 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 147 }; 148 149 static const struct ieee80211_rate ath5k_rates[] = { 150 { .bitrate = 10, 151 .hw_value = ATH5K_RATE_CODE_1M, }, 152 { .bitrate = 20, 153 .hw_value = ATH5K_RATE_CODE_2M, 154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 155 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 156 { .bitrate = 55, 157 .hw_value = ATH5K_RATE_CODE_5_5M, 158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 159 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 160 { .bitrate = 110, 161 .hw_value = ATH5K_RATE_CODE_11M, 162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 163 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 164 { .bitrate = 60, 165 .hw_value = ATH5K_RATE_CODE_6M, 166 .flags = 0 }, 167 { .bitrate = 90, 168 .hw_value = ATH5K_RATE_CODE_9M, 169 .flags = 0 }, 170 { .bitrate = 120, 171 .hw_value = ATH5K_RATE_CODE_12M, 172 .flags = 0 }, 173 { .bitrate = 180, 174 .hw_value = ATH5K_RATE_CODE_18M, 175 .flags = 0 }, 176 { .bitrate = 240, 177 .hw_value = ATH5K_RATE_CODE_24M, 178 .flags = 0 }, 179 { .bitrate = 360, 180 .hw_value = ATH5K_RATE_CODE_36M, 181 .flags = 0 }, 182 { .bitrate = 480, 183 .hw_value = ATH5K_RATE_CODE_48M, 184 .flags = 0 }, 185 { .bitrate = 540, 186 .hw_value = ATH5K_RATE_CODE_54M, 187 .flags = 0 }, 188 /* XR missing */ 189 }; 190 191 /* 192 * Prototypes - PCI stack related functions 193 */ 194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev, 195 const struct pci_device_id *id); 196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev); 197 #ifdef CONFIG_PM 198 static int ath5k_pci_suspend(struct pci_dev *pdev, 199 pm_message_t state); 200 static int ath5k_pci_resume(struct pci_dev *pdev); 201 #else 202 #define ath5k_pci_suspend NULL 203 #define ath5k_pci_resume NULL 204 #endif /* CONFIG_PM */ 205 206 static struct pci_driver ath5k_pci_driver = { 207 .name = KBUILD_MODNAME, 208 .id_table = ath5k_pci_id_table, 209 .probe = ath5k_pci_probe, 210 .remove = __devexit_p(ath5k_pci_remove), 211 .suspend = ath5k_pci_suspend, 212 .resume = ath5k_pci_resume, 213 }; 214 215 216 217 /* 218 * Prototypes - MAC 802.11 stack related functions 219 */ 220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 222 struct ath5k_txq *txq); 223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan); 224 static int ath5k_reset_wake(struct ath5k_softc *sc); 225 static int ath5k_start(struct ieee80211_hw *hw); 226 static void ath5k_stop(struct ieee80211_hw *hw); 227 static int ath5k_add_interface(struct ieee80211_hw *hw, 228 struct ieee80211_if_init_conf *conf); 229 static void ath5k_remove_interface(struct ieee80211_hw *hw, 230 struct ieee80211_if_init_conf *conf); 231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed); 232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 233 int mc_count, struct dev_addr_list *mc_list); 234 static void ath5k_configure_filter(struct ieee80211_hw *hw, 235 unsigned int changed_flags, 236 unsigned int *new_flags, 237 u64 multicast); 238 static int ath5k_set_key(struct ieee80211_hw *hw, 239 enum set_key_cmd cmd, 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 241 struct ieee80211_key_conf *key); 242 static int ath5k_get_stats(struct ieee80211_hw *hw, 243 struct ieee80211_low_level_stats *stats); 244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw, 245 struct ieee80211_tx_queue_stats *stats); 246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw); 247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf); 248 static void ath5k_reset_tsf(struct ieee80211_hw *hw); 249 static int ath5k_beacon_update(struct ieee80211_hw *hw, 250 struct ieee80211_vif *vif); 251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 252 struct ieee80211_vif *vif, 253 struct ieee80211_bss_conf *bss_conf, 254 u32 changes); 255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw); 256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw); 257 258 static const struct ieee80211_ops ath5k_hw_ops = { 259 .tx = ath5k_tx, 260 .start = ath5k_start, 261 .stop = ath5k_stop, 262 .add_interface = ath5k_add_interface, 263 .remove_interface = ath5k_remove_interface, 264 .config = ath5k_config, 265 .prepare_multicast = ath5k_prepare_multicast, 266 .configure_filter = ath5k_configure_filter, 267 .set_key = ath5k_set_key, 268 .get_stats = ath5k_get_stats, 269 .conf_tx = NULL, 270 .get_tx_stats = ath5k_get_tx_stats, 271 .get_tsf = ath5k_get_tsf, 272 .set_tsf = ath5k_set_tsf, 273 .reset_tsf = ath5k_reset_tsf, 274 .bss_info_changed = ath5k_bss_info_changed, 275 .sw_scan_start = ath5k_sw_scan_start, 276 .sw_scan_complete = ath5k_sw_scan_complete, 277 }; 278 279 /* 280 * Prototypes - Internal functions 281 */ 282 /* Attach detach */ 283 static int ath5k_attach(struct pci_dev *pdev, 284 struct ieee80211_hw *hw); 285 static void ath5k_detach(struct pci_dev *pdev, 286 struct ieee80211_hw *hw); 287 /* Channel/mode setup */ 288 static inline short ath5k_ieee2mhz(short chan); 289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, 290 struct ieee80211_channel *channels, 291 unsigned int mode, 292 unsigned int max); 293 static int ath5k_setup_bands(struct ieee80211_hw *hw); 294 static int ath5k_chan_set(struct ath5k_softc *sc, 295 struct ieee80211_channel *chan); 296 static void ath5k_setcurmode(struct ath5k_softc *sc, 297 unsigned int mode); 298 static void ath5k_mode_setup(struct ath5k_softc *sc); 299 300 /* Descriptor setup */ 301 static int ath5k_desc_alloc(struct ath5k_softc *sc, 302 struct pci_dev *pdev); 303 static void ath5k_desc_free(struct ath5k_softc *sc, 304 struct pci_dev *pdev); 305 /* Buffers setup */ 306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc, 307 struct ath5k_buf *bf); 308 static int ath5k_txbuf_setup(struct ath5k_softc *sc, 309 struct ath5k_buf *bf, 310 struct ath5k_txq *txq); 311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 312 struct ath5k_buf *bf) 313 { 314 BUG_ON(!bf); 315 if (!bf->skb) 316 return; 317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, 318 PCI_DMA_TODEVICE); 319 dev_kfree_skb_any(bf->skb); 320 bf->skb = NULL; 321 } 322 323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc, 324 struct ath5k_buf *bf) 325 { 326 BUG_ON(!bf); 327 if (!bf->skb) 328 return; 329 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, 330 PCI_DMA_FROMDEVICE); 331 dev_kfree_skb_any(bf->skb); 332 bf->skb = NULL; 333 } 334 335 336 /* Queues setup */ 337 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, 338 int qtype, int subtype); 339 static int ath5k_beaconq_setup(struct ath5k_hw *ah); 340 static int ath5k_beaconq_config(struct ath5k_softc *sc); 341 static void ath5k_txq_drainq(struct ath5k_softc *sc, 342 struct ath5k_txq *txq); 343 static void ath5k_txq_cleanup(struct ath5k_softc *sc); 344 static void ath5k_txq_release(struct ath5k_softc *sc); 345 /* Rx handling */ 346 static int ath5k_rx_start(struct ath5k_softc *sc); 347 static void ath5k_rx_stop(struct ath5k_softc *sc); 348 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, 349 struct ath5k_desc *ds, 350 struct sk_buff *skb, 351 struct ath5k_rx_status *rs); 352 static void ath5k_tasklet_rx(unsigned long data); 353 /* Tx handling */ 354 static void ath5k_tx_processq(struct ath5k_softc *sc, 355 struct ath5k_txq *txq); 356 static void ath5k_tasklet_tx(unsigned long data); 357 /* Beacon handling */ 358 static int ath5k_beacon_setup(struct ath5k_softc *sc, 359 struct ath5k_buf *bf); 360 static void ath5k_beacon_send(struct ath5k_softc *sc); 361 static void ath5k_beacon_config(struct ath5k_softc *sc); 362 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 363 static void ath5k_tasklet_beacon(unsigned long data); 364 365 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 366 { 367 u64 tsf = ath5k_hw_get_tsf64(ah); 368 369 if ((tsf & 0x7fff) < rstamp) 370 tsf -= 0x8000; 371 372 return (tsf & ~0x7fff) | rstamp; 373 } 374 375 /* Interrupt handling */ 376 static int ath5k_init(struct ath5k_softc *sc); 377 static int ath5k_stop_locked(struct ath5k_softc *sc); 378 static int ath5k_stop_hw(struct ath5k_softc *sc); 379 static irqreturn_t ath5k_intr(int irq, void *dev_id); 380 static void ath5k_tasklet_reset(unsigned long data); 381 382 static void ath5k_tasklet_calibrate(unsigned long data); 383 384 /* 385 * Module init/exit functions 386 */ 387 static int __init 388 init_ath5k_pci(void) 389 { 390 int ret; 391 392 ath5k_debug_init(); 393 394 ret = pci_register_driver(&ath5k_pci_driver); 395 if (ret) { 396 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static void __exit 404 exit_ath5k_pci(void) 405 { 406 pci_unregister_driver(&ath5k_pci_driver); 407 408 ath5k_debug_finish(); 409 } 410 411 module_init(init_ath5k_pci); 412 module_exit(exit_ath5k_pci); 413 414 415 /********************\ 416 * PCI Initialization * 417 \********************/ 418 419 static const char * 420 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 421 { 422 const char *name = "xxxxx"; 423 unsigned int i; 424 425 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 426 if (srev_names[i].sr_type != type) 427 continue; 428 429 if ((val & 0xf0) == srev_names[i].sr_val) 430 name = srev_names[i].sr_name; 431 432 if ((val & 0xff) == srev_names[i].sr_val) { 433 name = srev_names[i].sr_name; 434 break; 435 } 436 } 437 438 return name; 439 } 440 441 static int __devinit 442 ath5k_pci_probe(struct pci_dev *pdev, 443 const struct pci_device_id *id) 444 { 445 void __iomem *mem; 446 struct ath5k_softc *sc; 447 struct ieee80211_hw *hw; 448 int ret; 449 u8 csz; 450 451 ret = pci_enable_device(pdev); 452 if (ret) { 453 dev_err(&pdev->dev, "can't enable device\n"); 454 goto err; 455 } 456 457 /* XXX 32-bit addressing only */ 458 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 459 if (ret) { 460 dev_err(&pdev->dev, "32-bit DMA not available\n"); 461 goto err_dis; 462 } 463 464 /* 465 * Cache line size is used to size and align various 466 * structures used to communicate with the hardware. 467 */ 468 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 469 if (csz == 0) { 470 /* 471 * Linux 2.4.18 (at least) writes the cache line size 472 * register as a 16-bit wide register which is wrong. 473 * We must have this setup properly for rx buffer 474 * DMA to work so force a reasonable value here if it 475 * comes up zero. 476 */ 477 csz = L1_CACHE_BYTES >> 2; 478 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 479 } 480 /* 481 * The default setting of latency timer yields poor results, 482 * set it to the value used by other systems. It may be worth 483 * tweaking this setting more. 484 */ 485 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 486 487 /* Enable bus mastering */ 488 pci_set_master(pdev); 489 490 /* 491 * Disable the RETRY_TIMEOUT register (0x41) to keep 492 * PCI Tx retries from interfering with C3 CPU state. 493 */ 494 pci_write_config_byte(pdev, 0x41, 0); 495 496 ret = pci_request_region(pdev, 0, "ath5k"); 497 if (ret) { 498 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 499 goto err_dis; 500 } 501 502 mem = pci_iomap(pdev, 0, 0); 503 if (!mem) { 504 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 505 ret = -EIO; 506 goto err_reg; 507 } 508 509 /* 510 * Allocate hw (mac80211 main struct) 511 * and hw->priv (driver private data) 512 */ 513 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 514 if (hw == NULL) { 515 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 516 ret = -ENOMEM; 517 goto err_map; 518 } 519 520 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 521 522 /* Initialize driver private data */ 523 SET_IEEE80211_DEV(hw, &pdev->dev); 524 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 526 IEEE80211_HW_SIGNAL_DBM | 527 IEEE80211_HW_NOISE_DBM; 528 529 hw->wiphy->interface_modes = 530 BIT(NL80211_IFTYPE_AP) | 531 BIT(NL80211_IFTYPE_STATION) | 532 BIT(NL80211_IFTYPE_ADHOC) | 533 BIT(NL80211_IFTYPE_MESH_POINT); 534 535 hw->extra_tx_headroom = 2; 536 hw->channel_change_time = 5000; 537 sc = hw->priv; 538 sc->hw = hw; 539 sc->pdev = pdev; 540 541 ath5k_debug_init_device(sc); 542 543 /* 544 * Mark the device as detached to avoid processing 545 * interrupts until setup is complete. 546 */ 547 __set_bit(ATH_STAT_INVALID, sc->status); 548 549 sc->iobase = mem; /* So we can unmap it on detach */ 550 sc->common.cachelsz = csz << 2; /* convert to bytes */ 551 sc->opmode = NL80211_IFTYPE_STATION; 552 sc->bintval = 1000; 553 mutex_init(&sc->lock); 554 spin_lock_init(&sc->rxbuflock); 555 spin_lock_init(&sc->txbuflock); 556 spin_lock_init(&sc->block); 557 558 /* Set private data */ 559 pci_set_drvdata(pdev, hw); 560 561 /* Setup interrupt handler */ 562 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 563 if (ret) { 564 ATH5K_ERR(sc, "request_irq failed\n"); 565 goto err_free; 566 } 567 568 /* Initialize device */ 569 sc->ah = ath5k_hw_attach(sc); 570 if (IS_ERR(sc->ah)) { 571 ret = PTR_ERR(sc->ah); 572 goto err_irq; 573 } 574 575 /* set up multi-rate retry capabilities */ 576 if (sc->ah->ah_version == AR5K_AR5212) { 577 hw->max_rates = 4; 578 hw->max_rate_tries = 11; 579 } 580 581 /* Finish private driver data initialization */ 582 ret = ath5k_attach(pdev, hw); 583 if (ret) 584 goto err_ah; 585 586 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 587 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 588 sc->ah->ah_mac_srev, 589 sc->ah->ah_phy_revision); 590 591 if (!sc->ah->ah_single_chip) { 592 /* Single chip radio (!RF5111) */ 593 if (sc->ah->ah_radio_5ghz_revision && 594 !sc->ah->ah_radio_2ghz_revision) { 595 /* No 5GHz support -> report 2GHz radio */ 596 if (!test_bit(AR5K_MODE_11A, 597 sc->ah->ah_capabilities.cap_mode)) { 598 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 599 ath5k_chip_name(AR5K_VERSION_RAD, 600 sc->ah->ah_radio_5ghz_revision), 601 sc->ah->ah_radio_5ghz_revision); 602 /* No 2GHz support (5110 and some 603 * 5Ghz only cards) -> report 5Ghz radio */ 604 } else if (!test_bit(AR5K_MODE_11B, 605 sc->ah->ah_capabilities.cap_mode)) { 606 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 607 ath5k_chip_name(AR5K_VERSION_RAD, 608 sc->ah->ah_radio_5ghz_revision), 609 sc->ah->ah_radio_5ghz_revision); 610 /* Multiband radio */ 611 } else { 612 ATH5K_INFO(sc, "RF%s multiband radio found" 613 " (0x%x)\n", 614 ath5k_chip_name(AR5K_VERSION_RAD, 615 sc->ah->ah_radio_5ghz_revision), 616 sc->ah->ah_radio_5ghz_revision); 617 } 618 } 619 /* Multi chip radio (RF5111 - RF2111) -> 620 * report both 2GHz/5GHz radios */ 621 else if (sc->ah->ah_radio_5ghz_revision && 622 sc->ah->ah_radio_2ghz_revision){ 623 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 624 ath5k_chip_name(AR5K_VERSION_RAD, 625 sc->ah->ah_radio_5ghz_revision), 626 sc->ah->ah_radio_5ghz_revision); 627 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 628 ath5k_chip_name(AR5K_VERSION_RAD, 629 sc->ah->ah_radio_2ghz_revision), 630 sc->ah->ah_radio_2ghz_revision); 631 } 632 } 633 634 635 /* ready to process interrupts */ 636 __clear_bit(ATH_STAT_INVALID, sc->status); 637 638 return 0; 639 err_ah: 640 ath5k_hw_detach(sc->ah); 641 err_irq: 642 free_irq(pdev->irq, sc); 643 err_free: 644 ieee80211_free_hw(hw); 645 err_map: 646 pci_iounmap(pdev, mem); 647 err_reg: 648 pci_release_region(pdev, 0); 649 err_dis: 650 pci_disable_device(pdev); 651 err: 652 return ret; 653 } 654 655 static void __devexit 656 ath5k_pci_remove(struct pci_dev *pdev) 657 { 658 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 659 struct ath5k_softc *sc = hw->priv; 660 661 ath5k_debug_finish_device(sc); 662 ath5k_detach(pdev, hw); 663 ath5k_hw_detach(sc->ah); 664 free_irq(pdev->irq, sc); 665 pci_iounmap(pdev, sc->iobase); 666 pci_release_region(pdev, 0); 667 pci_disable_device(pdev); 668 ieee80211_free_hw(hw); 669 } 670 671 #ifdef CONFIG_PM 672 static int 673 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state) 674 { 675 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 676 struct ath5k_softc *sc = hw->priv; 677 678 ath5k_led_off(sc); 679 680 pci_save_state(pdev); 681 pci_disable_device(pdev); 682 pci_set_power_state(pdev, PCI_D3hot); 683 684 return 0; 685 } 686 687 static int 688 ath5k_pci_resume(struct pci_dev *pdev) 689 { 690 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 691 struct ath5k_softc *sc = hw->priv; 692 int err; 693 694 pci_restore_state(pdev); 695 696 err = pci_enable_device(pdev); 697 if (err) 698 return err; 699 700 /* 701 * Suspend/Resume resets the PCI configuration space, so we have to 702 * re-disable the RETRY_TIMEOUT register (0x41) to keep 703 * PCI Tx retries from interfering with C3 CPU state 704 */ 705 pci_write_config_byte(pdev, 0x41, 0); 706 707 ath5k_led_enable(sc); 708 return 0; 709 } 710 #endif /* CONFIG_PM */ 711 712 713 /***********************\ 714 * Driver Initialization * 715 \***********************/ 716 717 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 718 { 719 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 720 struct ath5k_softc *sc = hw->priv; 721 struct ath_regulatory *regulatory = &sc->common.regulatory; 722 723 return ath_reg_notifier_apply(wiphy, request, regulatory); 724 } 725 726 static int 727 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) 728 { 729 struct ath5k_softc *sc = hw->priv; 730 struct ath5k_hw *ah = sc->ah; 731 struct ath_regulatory *regulatory = &sc->common.regulatory; 732 u8 mac[ETH_ALEN] = {}; 733 int ret; 734 735 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); 736 737 /* 738 * Check if the MAC has multi-rate retry support. 739 * We do this by trying to setup a fake extended 740 * descriptor. MAC's that don't have support will 741 * return false w/o doing anything. MAC's that do 742 * support it will return true w/o doing anything. 743 */ 744 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 745 if (ret < 0) 746 goto err; 747 if (ret > 0) 748 __set_bit(ATH_STAT_MRRETRY, sc->status); 749 750 /* 751 * Collect the channel list. The 802.11 layer 752 * is resposible for filtering this list based 753 * on settings like the phy mode and regulatory 754 * domain restrictions. 755 */ 756 ret = ath5k_setup_bands(hw); 757 if (ret) { 758 ATH5K_ERR(sc, "can't get channels\n"); 759 goto err; 760 } 761 762 /* NB: setup here so ath5k_rate_update is happy */ 763 if (test_bit(AR5K_MODE_11A, ah->ah_modes)) 764 ath5k_setcurmode(sc, AR5K_MODE_11A); 765 else 766 ath5k_setcurmode(sc, AR5K_MODE_11B); 767 768 /* 769 * Allocate tx+rx descriptors and populate the lists. 770 */ 771 ret = ath5k_desc_alloc(sc, pdev); 772 if (ret) { 773 ATH5K_ERR(sc, "can't allocate descriptors\n"); 774 goto err; 775 } 776 777 /* 778 * Allocate hardware transmit queues: one queue for 779 * beacon frames and one data queue for each QoS 780 * priority. Note that hw functions handle reseting 781 * these queues at the needed time. 782 */ 783 ret = ath5k_beaconq_setup(ah); 784 if (ret < 0) { 785 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 786 goto err_desc; 787 } 788 sc->bhalq = ret; 789 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 790 if (IS_ERR(sc->cabq)) { 791 ATH5K_ERR(sc, "can't setup cab queue\n"); 792 ret = PTR_ERR(sc->cabq); 793 goto err_bhal; 794 } 795 796 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 797 if (IS_ERR(sc->txq)) { 798 ATH5K_ERR(sc, "can't setup xmit queue\n"); 799 ret = PTR_ERR(sc->txq); 800 goto err_queues; 801 } 802 803 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 804 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 805 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); 806 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 807 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 808 809 ret = ath5k_eeprom_read_mac(ah, mac); 810 if (ret) { 811 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n", 812 sc->pdev->device); 813 goto err_queues; 814 } 815 816 SET_IEEE80211_PERM_ADDR(hw, mac); 817 /* All MAC address bits matter for ACKs */ 818 memset(sc->bssidmask, 0xff, ETH_ALEN); 819 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 820 821 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 822 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 823 if (ret) { 824 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 825 goto err_queues; 826 } 827 828 ret = ieee80211_register_hw(hw); 829 if (ret) { 830 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 831 goto err_queues; 832 } 833 834 if (!ath_is_world_regd(regulatory)) 835 regulatory_hint(hw->wiphy, regulatory->alpha2); 836 837 ath5k_init_leds(sc); 838 839 return 0; 840 err_queues: 841 ath5k_txq_release(sc); 842 err_bhal: 843 ath5k_hw_release_tx_queue(ah, sc->bhalq); 844 err_desc: 845 ath5k_desc_free(sc, pdev); 846 err: 847 return ret; 848 } 849 850 static void 851 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) 852 { 853 struct ath5k_softc *sc = hw->priv; 854 855 /* 856 * NB: the order of these is important: 857 * o call the 802.11 layer before detaching ath5k_hw to 858 * insure callbacks into the driver to delete global 859 * key cache entries can be handled 860 * o reclaim the tx queue data structures after calling 861 * the 802.11 layer as we'll get called back to reclaim 862 * node state and potentially want to use them 863 * o to cleanup the tx queues the hal is called, so detach 864 * it last 865 * XXX: ??? detach ath5k_hw ??? 866 * Other than that, it's straightforward... 867 */ 868 ieee80211_unregister_hw(hw); 869 ath5k_desc_free(sc, pdev); 870 ath5k_txq_release(sc); 871 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 872 ath5k_unregister_leds(sc); 873 874 /* 875 * NB: can't reclaim these until after ieee80211_ifdetach 876 * returns because we'll get called back to reclaim node 877 * state and potentially want to use them. 878 */ 879 } 880 881 882 883 884 /********************\ 885 * Channel/mode setup * 886 \********************/ 887 888 /* 889 * Convert IEEE channel number to MHz frequency. 890 */ 891 static inline short 892 ath5k_ieee2mhz(short chan) 893 { 894 if (chan <= 14 || chan >= 27) 895 return ieee80211chan2mhz(chan); 896 else 897 return 2212 + chan * 20; 898 } 899 900 /* 901 * Returns true for the channel numbers used without all_channels modparam. 902 */ 903 static bool ath5k_is_standard_channel(short chan) 904 { 905 return ((chan <= 14) || 906 /* UNII 1,2 */ 907 ((chan & 3) == 0 && chan >= 36 && chan <= 64) || 908 /* midband */ 909 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 910 /* UNII-3 */ 911 ((chan & 3) == 1 && chan >= 149 && chan <= 165)); 912 } 913 914 static unsigned int 915 ath5k_copy_channels(struct ath5k_hw *ah, 916 struct ieee80211_channel *channels, 917 unsigned int mode, 918 unsigned int max) 919 { 920 unsigned int i, count, size, chfreq, freq, ch; 921 922 if (!test_bit(mode, ah->ah_modes)) 923 return 0; 924 925 switch (mode) { 926 case AR5K_MODE_11A: 927 case AR5K_MODE_11A_TURBO: 928 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 929 size = 220 ; 930 chfreq = CHANNEL_5GHZ; 931 break; 932 case AR5K_MODE_11B: 933 case AR5K_MODE_11G: 934 case AR5K_MODE_11G_TURBO: 935 size = 26; 936 chfreq = CHANNEL_2GHZ; 937 break; 938 default: 939 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 940 return 0; 941 } 942 943 for (i = 0, count = 0; i < size && max > 0; i++) { 944 ch = i + 1 ; 945 freq = ath5k_ieee2mhz(ch); 946 947 /* Check if channel is supported by the chipset */ 948 if (!ath5k_channel_ok(ah, freq, chfreq)) 949 continue; 950 951 if (!modparam_all_channels && !ath5k_is_standard_channel(ch)) 952 continue; 953 954 /* Write channel info and increment counter */ 955 channels[count].center_freq = freq; 956 channels[count].band = (chfreq == CHANNEL_2GHZ) ? 957 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 958 switch (mode) { 959 case AR5K_MODE_11A: 960 case AR5K_MODE_11G: 961 channels[count].hw_value = chfreq | CHANNEL_OFDM; 962 break; 963 case AR5K_MODE_11A_TURBO: 964 case AR5K_MODE_11G_TURBO: 965 channels[count].hw_value = chfreq | 966 CHANNEL_OFDM | CHANNEL_TURBO; 967 break; 968 case AR5K_MODE_11B: 969 channels[count].hw_value = CHANNEL_B; 970 } 971 972 count++; 973 max--; 974 } 975 976 return count; 977 } 978 979 static void 980 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 981 { 982 u8 i; 983 984 for (i = 0; i < AR5K_MAX_RATES; i++) 985 sc->rate_idx[b->band][i] = -1; 986 987 for (i = 0; i < b->n_bitrates; i++) { 988 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 989 if (b->bitrates[i].hw_value_short) 990 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 991 } 992 } 993 994 static int 995 ath5k_setup_bands(struct ieee80211_hw *hw) 996 { 997 struct ath5k_softc *sc = hw->priv; 998 struct ath5k_hw *ah = sc->ah; 999 struct ieee80211_supported_band *sband; 1000 int max_c, count_c = 0; 1001 int i; 1002 1003 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 1004 max_c = ARRAY_SIZE(sc->channels); 1005 1006 /* 2GHz band */ 1007 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1008 sband->band = IEEE80211_BAND_2GHZ; 1009 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 1010 1011 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 1012 /* G mode */ 1013 memcpy(sband->bitrates, &ath5k_rates[0], 1014 sizeof(struct ieee80211_rate) * 12); 1015 sband->n_bitrates = 12; 1016 1017 sband->channels = sc->channels; 1018 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1019 AR5K_MODE_11G, max_c); 1020 1021 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1022 count_c = sband->n_channels; 1023 max_c -= count_c; 1024 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 1025 /* B mode */ 1026 memcpy(sband->bitrates, &ath5k_rates[0], 1027 sizeof(struct ieee80211_rate) * 4); 1028 sband->n_bitrates = 4; 1029 1030 /* 5211 only supports B rates and uses 4bit rate codes 1031 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 1032 * fix them up here: 1033 */ 1034 if (ah->ah_version == AR5K_AR5211) { 1035 for (i = 0; i < 4; i++) { 1036 sband->bitrates[i].hw_value = 1037 sband->bitrates[i].hw_value & 0xF; 1038 sband->bitrates[i].hw_value_short = 1039 sband->bitrates[i].hw_value_short & 0xF; 1040 } 1041 } 1042 1043 sband->channels = sc->channels; 1044 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1045 AR5K_MODE_11B, max_c); 1046 1047 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1048 count_c = sband->n_channels; 1049 max_c -= count_c; 1050 } 1051 ath5k_setup_rate_idx(sc, sband); 1052 1053 /* 5GHz band, A mode */ 1054 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 1055 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1056 sband->band = IEEE80211_BAND_5GHZ; 1057 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 1058 1059 memcpy(sband->bitrates, &ath5k_rates[4], 1060 sizeof(struct ieee80211_rate) * 8); 1061 sband->n_bitrates = 8; 1062 1063 sband->channels = &sc->channels[count_c]; 1064 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1065 AR5K_MODE_11A, max_c); 1066 1067 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 1068 } 1069 ath5k_setup_rate_idx(sc, sband); 1070 1071 ath5k_debug_dump_bands(sc); 1072 1073 return 0; 1074 } 1075 1076 /* 1077 * Set/change channels. We always reset the chip. 1078 * To accomplish this we must first cleanup any pending DMA, 1079 * then restart stuff after a la ath5k_init. 1080 * 1081 * Called with sc->lock. 1082 */ 1083 static int 1084 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 1085 { 1086 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", 1087 sc->curchan->center_freq, chan->center_freq); 1088 1089 /* 1090 * To switch channels clear any pending DMA operations; 1091 * wait long enough for the RX fifo to drain, reset the 1092 * hardware at the new frequency, and then re-enable 1093 * the relevant bits of the h/w. 1094 */ 1095 return ath5k_reset(sc, chan); 1096 } 1097 1098 static void 1099 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) 1100 { 1101 sc->curmode = mode; 1102 1103 if (mode == AR5K_MODE_11A) { 1104 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1105 } else { 1106 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1107 } 1108 } 1109 1110 static void 1111 ath5k_mode_setup(struct ath5k_softc *sc) 1112 { 1113 struct ath5k_hw *ah = sc->ah; 1114 u32 rfilt; 1115 1116 ah->ah_op_mode = sc->opmode; 1117 1118 /* configure rx filter */ 1119 rfilt = sc->filter_flags; 1120 ath5k_hw_set_rx_filter(ah, rfilt); 1121 1122 if (ath5k_hw_hasbssidmask(ah)) 1123 ath5k_hw_set_bssid_mask(ah, sc->bssidmask); 1124 1125 /* configure operational mode */ 1126 ath5k_hw_set_opmode(ah); 1127 1128 ath5k_hw_set_mcast_filter(ah, 0, 0); 1129 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 1130 } 1131 1132 static inline int 1133 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 1134 { 1135 int rix; 1136 1137 /* return base rate on errors */ 1138 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 1139 "hw_rix out of bounds: %x\n", hw_rix)) 1140 return 0; 1141 1142 rix = sc->rate_idx[sc->curband->band][hw_rix]; 1143 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 1144 rix = 0; 1145 1146 return rix; 1147 } 1148 1149 /***************\ 1150 * Buffers setup * 1151 \***************/ 1152 1153 static 1154 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 1155 { 1156 struct sk_buff *skb; 1157 1158 /* 1159 * Allocate buffer with headroom_needed space for the 1160 * fake physical layer header at the start. 1161 */ 1162 skb = ath_rxbuf_alloc(&sc->common, 1163 sc->rxbufsize + sc->common.cachelsz - 1, 1164 GFP_ATOMIC); 1165 1166 if (!skb) { 1167 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 1168 sc->rxbufsize + sc->common.cachelsz - 1); 1169 return NULL; 1170 } 1171 1172 *skb_addr = pci_map_single(sc->pdev, 1173 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); 1174 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) { 1175 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 1176 dev_kfree_skb(skb); 1177 return NULL; 1178 } 1179 return skb; 1180 } 1181 1182 static int 1183 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1184 { 1185 struct ath5k_hw *ah = sc->ah; 1186 struct sk_buff *skb = bf->skb; 1187 struct ath5k_desc *ds; 1188 1189 if (!skb) { 1190 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 1191 if (!skb) 1192 return -ENOMEM; 1193 bf->skb = skb; 1194 } 1195 1196 /* 1197 * Setup descriptors. For receive we always terminate 1198 * the descriptor list with a self-linked entry so we'll 1199 * not get overrun under high load (as can happen with a 1200 * 5212 when ANI processing enables PHY error frames). 1201 * 1202 * To insure the last descriptor is self-linked we create 1203 * each descriptor as self-linked and add it to the end. As 1204 * each additional descriptor is added the previous self-linked 1205 * entry is ``fixed'' naturally. This should be safe even 1206 * if DMA is happening. When processing RX interrupts we 1207 * never remove/process the last, self-linked, entry on the 1208 * descriptor list. This insures the hardware always has 1209 * someplace to write a new frame. 1210 */ 1211 ds = bf->desc; 1212 ds->ds_link = bf->daddr; /* link to self */ 1213 ds->ds_data = bf->skbaddr; 1214 ah->ah_setup_rx_desc(ah, ds, 1215 skb_tailroom(skb), /* buffer size */ 1216 0); 1217 1218 if (sc->rxlink != NULL) 1219 *sc->rxlink = bf->daddr; 1220 sc->rxlink = &ds->ds_link; 1221 return 0; 1222 } 1223 1224 static int 1225 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1226 struct ath5k_txq *txq) 1227 { 1228 struct ath5k_hw *ah = sc->ah; 1229 struct ath5k_desc *ds = bf->desc; 1230 struct sk_buff *skb = bf->skb; 1231 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1232 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 1233 struct ieee80211_rate *rate; 1234 unsigned int mrr_rate[3], mrr_tries[3]; 1235 int i, ret; 1236 u16 hw_rate; 1237 u16 cts_rate = 0; 1238 u16 duration = 0; 1239 u8 rc_flags; 1240 1241 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 1242 1243 /* XXX endianness */ 1244 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 1245 PCI_DMA_TODEVICE); 1246 1247 rate = ieee80211_get_tx_rate(sc->hw, info); 1248 1249 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1250 flags |= AR5K_TXDESC_NOACK; 1251 1252 rc_flags = info->control.rates[0].flags; 1253 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 1254 rate->hw_value_short : rate->hw_value; 1255 1256 pktlen = skb->len; 1257 1258 /* FIXME: If we are in g mode and rate is a CCK rate 1259 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1260 * from tx power (value is in dB units already) */ 1261 if (info->control.hw_key) { 1262 keyidx = info->control.hw_key->hw_key_idx; 1263 pktlen += info->control.hw_key->icv_len; 1264 } 1265 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1266 flags |= AR5K_TXDESC_RTSENA; 1267 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1268 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 1269 sc->vif, pktlen, info)); 1270 } 1271 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1272 flags |= AR5K_TXDESC_CTSENA; 1273 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1274 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 1275 sc->vif, pktlen, info)); 1276 } 1277 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1278 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, 1279 (sc->power_level * 2), 1280 hw_rate, 1281 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 1282 cts_rate, duration); 1283 if (ret) 1284 goto err_unmap; 1285 1286 memset(mrr_rate, 0, sizeof(mrr_rate)); 1287 memset(mrr_tries, 0, sizeof(mrr_tries)); 1288 for (i = 0; i < 3; i++) { 1289 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 1290 if (!rate) 1291 break; 1292 1293 mrr_rate[i] = rate->hw_value; 1294 mrr_tries[i] = info->control.rates[i + 1].count; 1295 } 1296 1297 ah->ah_setup_mrr_tx_desc(ah, ds, 1298 mrr_rate[0], mrr_tries[0], 1299 mrr_rate[1], mrr_tries[1], 1300 mrr_rate[2], mrr_tries[2]); 1301 1302 ds->ds_link = 0; 1303 ds->ds_data = bf->skbaddr; 1304 1305 spin_lock_bh(&txq->lock); 1306 list_add_tail(&bf->list, &txq->q); 1307 sc->tx_stats[txq->qnum].len++; 1308 if (txq->link == NULL) /* is this first packet? */ 1309 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 1310 else /* no, so only link it */ 1311 *txq->link = bf->daddr; 1312 1313 txq->link = &ds->ds_link; 1314 ath5k_hw_start_tx_dma(ah, txq->qnum); 1315 mmiowb(); 1316 spin_unlock_bh(&txq->lock); 1317 1318 return 0; 1319 err_unmap: 1320 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 1321 return ret; 1322 } 1323 1324 /*******************\ 1325 * Descriptors setup * 1326 \*******************/ 1327 1328 static int 1329 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) 1330 { 1331 struct ath5k_desc *ds; 1332 struct ath5k_buf *bf; 1333 dma_addr_t da; 1334 unsigned int i; 1335 int ret; 1336 1337 /* allocate descriptors */ 1338 sc->desc_len = sizeof(struct ath5k_desc) * 1339 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 1340 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); 1341 if (sc->desc == NULL) { 1342 ATH5K_ERR(sc, "can't allocate descriptors\n"); 1343 ret = -ENOMEM; 1344 goto err; 1345 } 1346 ds = sc->desc; 1347 da = sc->desc_daddr; 1348 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 1349 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 1350 1351 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 1352 sizeof(struct ath5k_buf), GFP_KERNEL); 1353 if (bf == NULL) { 1354 ATH5K_ERR(sc, "can't allocate bufptr\n"); 1355 ret = -ENOMEM; 1356 goto err_free; 1357 } 1358 sc->bufptr = bf; 1359 1360 INIT_LIST_HEAD(&sc->rxbuf); 1361 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 1362 bf->desc = ds; 1363 bf->daddr = da; 1364 list_add_tail(&bf->list, &sc->rxbuf); 1365 } 1366 1367 INIT_LIST_HEAD(&sc->txbuf); 1368 sc->txbuf_len = ATH_TXBUF; 1369 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 1370 da += sizeof(*ds)) { 1371 bf->desc = ds; 1372 bf->daddr = da; 1373 list_add_tail(&bf->list, &sc->txbuf); 1374 } 1375 1376 /* beacon buffer */ 1377 bf->desc = ds; 1378 bf->daddr = da; 1379 sc->bbuf = bf; 1380 1381 return 0; 1382 err_free: 1383 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1384 err: 1385 sc->desc = NULL; 1386 return ret; 1387 } 1388 1389 static void 1390 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) 1391 { 1392 struct ath5k_buf *bf; 1393 1394 ath5k_txbuf_free(sc, sc->bbuf); 1395 list_for_each_entry(bf, &sc->txbuf, list) 1396 ath5k_txbuf_free(sc, bf); 1397 list_for_each_entry(bf, &sc->rxbuf, list) 1398 ath5k_rxbuf_free(sc, bf); 1399 1400 /* Free memory associated with all descriptors */ 1401 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1402 1403 kfree(sc->bufptr); 1404 sc->bufptr = NULL; 1405 } 1406 1407 1408 1409 1410 1411 /**************\ 1412 * Queues setup * 1413 \**************/ 1414 1415 static struct ath5k_txq * 1416 ath5k_txq_setup(struct ath5k_softc *sc, 1417 int qtype, int subtype) 1418 { 1419 struct ath5k_hw *ah = sc->ah; 1420 struct ath5k_txq *txq; 1421 struct ath5k_txq_info qi = { 1422 .tqi_subtype = subtype, 1423 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1424 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1425 .tqi_cw_max = AR5K_TXQ_USEDEFAULT 1426 }; 1427 int qnum; 1428 1429 /* 1430 * Enable interrupts only for EOL and DESC conditions. 1431 * We mark tx descriptors to receive a DESC interrupt 1432 * when a tx queue gets deep; otherwise waiting for the 1433 * EOL to reap descriptors. Note that this is done to 1434 * reduce interrupt load and this only defers reaping 1435 * descriptors, never transmitting frames. Aside from 1436 * reducing interrupts this also permits more concurrency. 1437 * The only potential downside is if the tx queue backs 1438 * up in which case the top half of the kernel may backup 1439 * due to a lack of tx descriptors. 1440 */ 1441 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1442 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1443 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1444 if (qnum < 0) { 1445 /* 1446 * NB: don't print a message, this happens 1447 * normally on parts with too few tx queues 1448 */ 1449 return ERR_PTR(qnum); 1450 } 1451 if (qnum >= ARRAY_SIZE(sc->txqs)) { 1452 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 1453 qnum, ARRAY_SIZE(sc->txqs)); 1454 ath5k_hw_release_tx_queue(ah, qnum); 1455 return ERR_PTR(-EINVAL); 1456 } 1457 txq = &sc->txqs[qnum]; 1458 if (!txq->setup) { 1459 txq->qnum = qnum; 1460 txq->link = NULL; 1461 INIT_LIST_HEAD(&txq->q); 1462 spin_lock_init(&txq->lock); 1463 txq->setup = true; 1464 } 1465 return &sc->txqs[qnum]; 1466 } 1467 1468 static int 1469 ath5k_beaconq_setup(struct ath5k_hw *ah) 1470 { 1471 struct ath5k_txq_info qi = { 1472 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1473 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1474 .tqi_cw_max = AR5K_TXQ_USEDEFAULT, 1475 /* NB: for dynamic turbo, don't enable any other interrupts */ 1476 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1477 }; 1478 1479 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1480 } 1481 1482 static int 1483 ath5k_beaconq_config(struct ath5k_softc *sc) 1484 { 1485 struct ath5k_hw *ah = sc->ah; 1486 struct ath5k_txq_info qi; 1487 int ret; 1488 1489 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 1490 if (ret) 1491 return ret; 1492 if (sc->opmode == NL80211_IFTYPE_AP || 1493 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1494 /* 1495 * Always burst out beacon and CAB traffic 1496 * (aifs = cwmin = cwmax = 0) 1497 */ 1498 qi.tqi_aifs = 0; 1499 qi.tqi_cw_min = 0; 1500 qi.tqi_cw_max = 0; 1501 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 1502 /* 1503 * Adhoc mode; backoff between 0 and (2 * cw_min). 1504 */ 1505 qi.tqi_aifs = 0; 1506 qi.tqi_cw_min = 0; 1507 qi.tqi_cw_max = 2 * ah->ah_cw_min; 1508 } 1509 1510 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1511 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1512 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1513 1514 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1515 if (ret) { 1516 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1517 "hardware queue!\n", __func__); 1518 return ret; 1519 } 1520 1521 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; 1522 } 1523 1524 static void 1525 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1526 { 1527 struct ath5k_buf *bf, *bf0; 1528 1529 /* 1530 * NB: this assumes output has been stopped and 1531 * we do not need to block ath5k_tx_tasklet 1532 */ 1533 spin_lock_bh(&txq->lock); 1534 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1535 ath5k_debug_printtxbuf(sc, bf); 1536 1537 ath5k_txbuf_free(sc, bf); 1538 1539 spin_lock_bh(&sc->txbuflock); 1540 sc->tx_stats[txq->qnum].len--; 1541 list_move_tail(&bf->list, &sc->txbuf); 1542 sc->txbuf_len++; 1543 spin_unlock_bh(&sc->txbuflock); 1544 } 1545 txq->link = NULL; 1546 spin_unlock_bh(&txq->lock); 1547 } 1548 1549 /* 1550 * Drain the transmit queues and reclaim resources. 1551 */ 1552 static void 1553 ath5k_txq_cleanup(struct ath5k_softc *sc) 1554 { 1555 struct ath5k_hw *ah = sc->ah; 1556 unsigned int i; 1557 1558 /* XXX return value */ 1559 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { 1560 /* don't touch the hardware if marked invalid */ 1561 ath5k_hw_stop_tx_dma(ah, sc->bhalq); 1562 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", 1563 ath5k_hw_get_txdp(ah, sc->bhalq)); 1564 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1565 if (sc->txqs[i].setup) { 1566 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); 1567 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " 1568 "link %p\n", 1569 sc->txqs[i].qnum, 1570 ath5k_hw_get_txdp(ah, 1571 sc->txqs[i].qnum), 1572 sc->txqs[i].link); 1573 } 1574 } 1575 ieee80211_wake_queues(sc->hw); /* XXX move to callers */ 1576 1577 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1578 if (sc->txqs[i].setup) 1579 ath5k_txq_drainq(sc, &sc->txqs[i]); 1580 } 1581 1582 static void 1583 ath5k_txq_release(struct ath5k_softc *sc) 1584 { 1585 struct ath5k_txq *txq = sc->txqs; 1586 unsigned int i; 1587 1588 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1589 if (txq->setup) { 1590 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1591 txq->setup = false; 1592 } 1593 } 1594 1595 1596 1597 1598 /*************\ 1599 * RX Handling * 1600 \*************/ 1601 1602 /* 1603 * Enable the receive h/w following a reset. 1604 */ 1605 static int 1606 ath5k_rx_start(struct ath5k_softc *sc) 1607 { 1608 struct ath5k_hw *ah = sc->ah; 1609 struct ath5k_buf *bf; 1610 int ret; 1611 1612 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->common.cachelsz); 1613 1614 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n", 1615 sc->common.cachelsz, sc->rxbufsize); 1616 1617 spin_lock_bh(&sc->rxbuflock); 1618 sc->rxlink = NULL; 1619 list_for_each_entry(bf, &sc->rxbuf, list) { 1620 ret = ath5k_rxbuf_setup(sc, bf); 1621 if (ret != 0) { 1622 spin_unlock_bh(&sc->rxbuflock); 1623 goto err; 1624 } 1625 } 1626 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1627 ath5k_hw_set_rxdp(ah, bf->daddr); 1628 spin_unlock_bh(&sc->rxbuflock); 1629 1630 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1631 ath5k_mode_setup(sc); /* set filters, etc. */ 1632 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1633 1634 return 0; 1635 err: 1636 return ret; 1637 } 1638 1639 /* 1640 * Disable the receive h/w in preparation for a reset. 1641 */ 1642 static void 1643 ath5k_rx_stop(struct ath5k_softc *sc) 1644 { 1645 struct ath5k_hw *ah = sc->ah; 1646 1647 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1648 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1649 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ 1650 1651 ath5k_debug_printrxbuffs(sc, ah); 1652 1653 sc->rxlink = NULL; /* just in case */ 1654 } 1655 1656 static unsigned int 1657 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, 1658 struct sk_buff *skb, struct ath5k_rx_status *rs) 1659 { 1660 struct ieee80211_hdr *hdr = (void *)skb->data; 1661 unsigned int keyix, hlen; 1662 1663 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1664 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1665 return RX_FLAG_DECRYPTED; 1666 1667 /* Apparently when a default key is used to decrypt the packet 1668 the hw does not set the index used to decrypt. In such cases 1669 get the index from the packet. */ 1670 hlen = ieee80211_hdrlen(hdr->frame_control); 1671 if (ieee80211_has_protected(hdr->frame_control) && 1672 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1673 skb->len >= hlen + 4) { 1674 keyix = skb->data[hlen + 3] >> 6; 1675 1676 if (test_bit(keyix, sc->keymap)) 1677 return RX_FLAG_DECRYPTED; 1678 } 1679 1680 return 0; 1681 } 1682 1683 1684 static void 1685 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1686 struct ieee80211_rx_status *rxs) 1687 { 1688 u64 tsf, bc_tstamp; 1689 u32 hw_tu; 1690 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1691 1692 if (ieee80211_is_beacon(mgmt->frame_control) && 1693 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1694 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) { 1695 /* 1696 * Received an IBSS beacon with the same BSSID. Hardware *must* 1697 * have updated the local TSF. We have to work around various 1698 * hardware bugs, though... 1699 */ 1700 tsf = ath5k_hw_get_tsf64(sc->ah); 1701 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1702 hw_tu = TSF_TO_TU(tsf); 1703 1704 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1705 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1706 (unsigned long long)bc_tstamp, 1707 (unsigned long long)rxs->mactime, 1708 (unsigned long long)(rxs->mactime - bc_tstamp), 1709 (unsigned long long)tsf); 1710 1711 /* 1712 * Sometimes the HW will give us a wrong tstamp in the rx 1713 * status, causing the timestamp extension to go wrong. 1714 * (This seems to happen especially with beacon frames bigger 1715 * than 78 byte (incl. FCS)) 1716 * But we know that the receive timestamp must be later than the 1717 * timestamp of the beacon since HW must have synced to that. 1718 * 1719 * NOTE: here we assume mactime to be after the frame was 1720 * received, not like mac80211 which defines it at the start. 1721 */ 1722 if (bc_tstamp > rxs->mactime) { 1723 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1724 "fixing mactime from %llx to %llx\n", 1725 (unsigned long long)rxs->mactime, 1726 (unsigned long long)tsf); 1727 rxs->mactime = tsf; 1728 } 1729 1730 /* 1731 * Local TSF might have moved higher than our beacon timers, 1732 * in that case we have to update them to continue sending 1733 * beacons. This also takes care of synchronizing beacon sending 1734 * times with other stations. 1735 */ 1736 if (hw_tu >= sc->nexttbtt) 1737 ath5k_beacon_update_timers(sc, bc_tstamp); 1738 } 1739 } 1740 1741 static void 1742 ath5k_tasklet_rx(unsigned long data) 1743 { 1744 struct ieee80211_rx_status *rxs; 1745 struct ath5k_rx_status rs = {}; 1746 struct sk_buff *skb, *next_skb; 1747 dma_addr_t next_skb_addr; 1748 struct ath5k_softc *sc = (void *)data; 1749 struct ath5k_buf *bf; 1750 struct ath5k_desc *ds; 1751 int ret; 1752 int hdrlen; 1753 int padsize; 1754 int rx_flag; 1755 1756 spin_lock(&sc->rxbuflock); 1757 if (list_empty(&sc->rxbuf)) { 1758 ATH5K_WARN(sc, "empty rx buf pool\n"); 1759 goto unlock; 1760 } 1761 do { 1762 rx_flag = 0; 1763 1764 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1765 BUG_ON(bf->skb == NULL); 1766 skb = bf->skb; 1767 ds = bf->desc; 1768 1769 /* bail if HW is still using self-linked descriptor */ 1770 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1771 break; 1772 1773 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1774 if (unlikely(ret == -EINPROGRESS)) 1775 break; 1776 else if (unlikely(ret)) { 1777 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1778 spin_unlock(&sc->rxbuflock); 1779 return; 1780 } 1781 1782 if (unlikely(rs.rs_more)) { 1783 ATH5K_WARN(sc, "unsupported jumbo\n"); 1784 goto next; 1785 } 1786 1787 if (unlikely(rs.rs_status)) { 1788 if (rs.rs_status & AR5K_RXERR_PHY) 1789 goto next; 1790 if (rs.rs_status & AR5K_RXERR_DECRYPT) { 1791 /* 1792 * Decrypt error. If the error occurred 1793 * because there was no hardware key, then 1794 * let the frame through so the upper layers 1795 * can process it. This is necessary for 5210 1796 * parts which have no way to setup a ``clear'' 1797 * key cache entry. 1798 * 1799 * XXX do key cache faulting 1800 */ 1801 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && 1802 !(rs.rs_status & AR5K_RXERR_CRC)) 1803 goto accept; 1804 } 1805 if (rs.rs_status & AR5K_RXERR_MIC) { 1806 rx_flag |= RX_FLAG_MMIC_ERROR; 1807 goto accept; 1808 } 1809 1810 /* let crypto-error packets fall through in MNTR */ 1811 if ((rs.rs_status & 1812 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || 1813 sc->opmode != NL80211_IFTYPE_MONITOR) 1814 goto next; 1815 } 1816 accept: 1817 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1818 1819 /* 1820 * If we can't replace bf->skb with a new skb under memory 1821 * pressure, just skip this packet 1822 */ 1823 if (!next_skb) 1824 goto next; 1825 1826 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, 1827 PCI_DMA_FROMDEVICE); 1828 skb_put(skb, rs.rs_datalen); 1829 1830 /* The MAC header is padded to have 32-bit boundary if the 1831 * packet payload is non-zero. The general calculation for 1832 * padsize would take into account odd header lengths: 1833 * padsize = (4 - hdrlen % 4) % 4; However, since only 1834 * even-length headers are used, padding can only be 0 or 2 1835 * bytes and we can optimize this a bit. In addition, we must 1836 * not try to remove padding from short control frames that do 1837 * not have payload. */ 1838 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1839 padsize = ath5k_pad_size(hdrlen); 1840 if (padsize) { 1841 memmove(skb->data + padsize, skb->data, hdrlen); 1842 skb_pull(skb, padsize); 1843 } 1844 rxs = IEEE80211_SKB_RXCB(skb); 1845 1846 /* 1847 * always extend the mac timestamp, since this information is 1848 * also needed for proper IBSS merging. 1849 * 1850 * XXX: it might be too late to do it here, since rs_tstamp is 1851 * 15bit only. that means TSF extension has to be done within 1852 * 32768usec (about 32ms). it might be necessary to move this to 1853 * the interrupt handler, like it is done in madwifi. 1854 * 1855 * Unfortunately we don't know when the hardware takes the rx 1856 * timestamp (beginning of phy frame, data frame, end of rx?). 1857 * The only thing we know is that it is hardware specific... 1858 * On AR5213 it seems the rx timestamp is at the end of the 1859 * frame, but i'm not sure. 1860 * 1861 * NOTE: mac80211 defines mactime at the beginning of the first 1862 * data symbol. Since we don't have any time references it's 1863 * impossible to comply to that. This affects IBSS merge only 1864 * right now, so it's not too bad... 1865 */ 1866 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp); 1867 rxs->flag = rx_flag | RX_FLAG_TSFT; 1868 1869 rxs->freq = sc->curchan->center_freq; 1870 rxs->band = sc->curband->band; 1871 1872 rxs->noise = sc->ah->ah_noise_floor; 1873 rxs->signal = rxs->noise + rs.rs_rssi; 1874 1875 /* An rssi of 35 indicates you should be able use 1876 * 54 Mbps reliably. A more elaborate scheme can be used 1877 * here but it requires a map of SNR/throughput for each 1878 * possible mode used */ 1879 rxs->qual = rs.rs_rssi * 100 / 35; 1880 1881 /* rssi can be more than 35 though, anything above that 1882 * should be considered at 100% */ 1883 if (rxs->qual > 100) 1884 rxs->qual = 100; 1885 1886 rxs->antenna = rs.rs_antenna; 1887 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 1888 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); 1889 1890 if (rxs->rate_idx >= 0 && rs.rs_rate == 1891 sc->curband->bitrates[rxs->rate_idx].hw_value_short) 1892 rxs->flag |= RX_FLAG_SHORTPRE; 1893 1894 ath5k_debug_dump_skb(sc, skb, "RX ", 0); 1895 1896 /* check beacons in IBSS mode */ 1897 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1898 ath5k_check_ibss_tsf(sc, skb, rxs); 1899 1900 ieee80211_rx(sc->hw, skb); 1901 1902 bf->skb = next_skb; 1903 bf->skbaddr = next_skb_addr; 1904 next: 1905 list_move_tail(&bf->list, &sc->rxbuf); 1906 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1907 unlock: 1908 spin_unlock(&sc->rxbuflock); 1909 } 1910 1911 1912 1913 1914 /*************\ 1915 * TX Handling * 1916 \*************/ 1917 1918 static void 1919 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1920 { 1921 struct ath5k_tx_status ts = {}; 1922 struct ath5k_buf *bf, *bf0; 1923 struct ath5k_desc *ds; 1924 struct sk_buff *skb; 1925 struct ieee80211_tx_info *info; 1926 int i, ret; 1927 1928 spin_lock(&txq->lock); 1929 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1930 ds = bf->desc; 1931 1932 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1933 if (unlikely(ret == -EINPROGRESS)) 1934 break; 1935 else if (unlikely(ret)) { 1936 ATH5K_ERR(sc, "error %d while processing queue %u\n", 1937 ret, txq->qnum); 1938 break; 1939 } 1940 1941 skb = bf->skb; 1942 info = IEEE80211_SKB_CB(skb); 1943 bf->skb = NULL; 1944 1945 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, 1946 PCI_DMA_TODEVICE); 1947 1948 ieee80211_tx_info_clear_status(info); 1949 for (i = 0; i < 4; i++) { 1950 struct ieee80211_tx_rate *r = 1951 &info->status.rates[i]; 1952 1953 if (ts.ts_rate[i]) { 1954 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]); 1955 r->count = ts.ts_retry[i]; 1956 } else { 1957 r->idx = -1; 1958 r->count = 0; 1959 } 1960 } 1961 1962 /* count the successful attempt as well */ 1963 info->status.rates[ts.ts_final_idx].count++; 1964 1965 if (unlikely(ts.ts_status)) { 1966 sc->ll_stats.dot11ACKFailureCount++; 1967 if (ts.ts_status & AR5K_TXERR_FILT) 1968 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1969 } else { 1970 info->flags |= IEEE80211_TX_STAT_ACK; 1971 info->status.ack_signal = ts.ts_rssi; 1972 } 1973 1974 ieee80211_tx_status(sc->hw, skb); 1975 sc->tx_stats[txq->qnum].count++; 1976 1977 spin_lock(&sc->txbuflock); 1978 sc->tx_stats[txq->qnum].len--; 1979 list_move_tail(&bf->list, &sc->txbuf); 1980 sc->txbuf_len++; 1981 spin_unlock(&sc->txbuflock); 1982 } 1983 if (likely(list_empty(&txq->q))) 1984 txq->link = NULL; 1985 spin_unlock(&txq->lock); 1986 if (sc->txbuf_len > ATH_TXBUF / 5) 1987 ieee80211_wake_queues(sc->hw); 1988 } 1989 1990 static void 1991 ath5k_tasklet_tx(unsigned long data) 1992 { 1993 int i; 1994 struct ath5k_softc *sc = (void *)data; 1995 1996 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 1997 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1998 ath5k_tx_processq(sc, &sc->txqs[i]); 1999 } 2000 2001 2002 /*****************\ 2003 * Beacon handling * 2004 \*****************/ 2005 2006 /* 2007 * Setup the beacon frame for transmit. 2008 */ 2009 static int 2010 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 2011 { 2012 struct sk_buff *skb = bf->skb; 2013 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2014 struct ath5k_hw *ah = sc->ah; 2015 struct ath5k_desc *ds; 2016 int ret = 0; 2017 u8 antenna; 2018 u32 flags; 2019 2020 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 2021 PCI_DMA_TODEVICE); 2022 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 2023 "skbaddr %llx\n", skb, skb->data, skb->len, 2024 (unsigned long long)bf->skbaddr); 2025 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) { 2026 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 2027 return -EIO; 2028 } 2029 2030 ds = bf->desc; 2031 antenna = ah->ah_tx_ant; 2032 2033 flags = AR5K_TXDESC_NOACK; 2034 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 2035 ds->ds_link = bf->daddr; /* self-linked */ 2036 flags |= AR5K_TXDESC_VEOL; 2037 } else 2038 ds->ds_link = 0; 2039 2040 /* 2041 * If we use multiple antennas on AP and use 2042 * the Sectored AP scenario, switch antenna every 2043 * 4 beacons to make sure everybody hears our AP. 2044 * When a client tries to associate, hw will keep 2045 * track of the tx antenna to be used for this client 2046 * automaticaly, based on ACKed packets. 2047 * 2048 * Note: AP still listens and transmits RTS on the 2049 * default antenna which is supposed to be an omni. 2050 * 2051 * Note2: On sectored scenarios it's possible to have 2052 * multiple antennas (1omni -the default- and 14 sectors) 2053 * so if we choose to actually support this mode we need 2054 * to allow user to set how many antennas we have and tweak 2055 * the code below to send beacons on all of them. 2056 */ 2057 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 2058 antenna = sc->bsent & 4 ? 2 : 1; 2059 2060 2061 /* FIXME: If we are in g mode and rate is a CCK rate 2062 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 2063 * from tx power (value is in dB units already) */ 2064 ds->ds_data = bf->skbaddr; 2065 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 2066 ieee80211_get_hdrlen_from_skb(skb), 2067 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 2068 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 2069 1, AR5K_TXKEYIX_INVALID, 2070 antenna, flags, 0, 0); 2071 if (ret) 2072 goto err_unmap; 2073 2074 return 0; 2075 err_unmap: 2076 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 2077 return ret; 2078 } 2079 2080 /* 2081 * Transmit a beacon frame at SWBA. Dynamic updates to the 2082 * frame contents are done as needed and the slot time is 2083 * also adjusted based on current state. 2084 * 2085 * This is called from software irq context (beacontq or restq 2086 * tasklets) or user context from ath5k_beacon_config. 2087 */ 2088 static void 2089 ath5k_beacon_send(struct ath5k_softc *sc) 2090 { 2091 struct ath5k_buf *bf = sc->bbuf; 2092 struct ath5k_hw *ah = sc->ah; 2093 struct sk_buff *skb; 2094 2095 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 2096 2097 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 2098 sc->opmode == NL80211_IFTYPE_MONITOR)) { 2099 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 2100 return; 2101 } 2102 /* 2103 * Check if the previous beacon has gone out. If 2104 * not don't don't try to post another, skip this 2105 * period and wait for the next. Missed beacons 2106 * indicate a problem and should not occur. If we 2107 * miss too many consecutive beacons reset the device. 2108 */ 2109 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 2110 sc->bmisscount++; 2111 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2112 "missed %u consecutive beacons\n", sc->bmisscount); 2113 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 2114 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2115 "stuck beacon time (%u missed)\n", 2116 sc->bmisscount); 2117 tasklet_schedule(&sc->restq); 2118 } 2119 return; 2120 } 2121 if (unlikely(sc->bmisscount != 0)) { 2122 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2123 "resume beacon xmit after %u misses\n", 2124 sc->bmisscount); 2125 sc->bmisscount = 0; 2126 } 2127 2128 /* 2129 * Stop any current dma and put the new frame on the queue. 2130 * This should never fail since we check above that no frames 2131 * are still pending on the queue. 2132 */ 2133 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { 2134 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 2135 /* NB: hw still stops DMA, so proceed */ 2136 } 2137 2138 /* refresh the beacon for AP mode */ 2139 if (sc->opmode == NL80211_IFTYPE_AP) 2140 ath5k_beacon_update(sc->hw, sc->vif); 2141 2142 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 2143 ath5k_hw_start_tx_dma(ah, sc->bhalq); 2144 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2145 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 2146 2147 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2148 while (skb) { 2149 ath5k_tx_queue(sc->hw, skb, sc->cabq); 2150 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2151 } 2152 2153 sc->bsent++; 2154 } 2155 2156 2157 /** 2158 * ath5k_beacon_update_timers - update beacon timers 2159 * 2160 * @sc: struct ath5k_softc pointer we are operating on 2161 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2162 * beacon timer update based on the current HW TSF. 2163 * 2164 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2165 * of a received beacon or the current local hardware TSF and write it to the 2166 * beacon timer registers. 2167 * 2168 * This is called in a variety of situations, e.g. when a beacon is received, 2169 * when a TSF update has been detected, but also when an new IBSS is created or 2170 * when we otherwise know we have to update the timers, but we keep it in this 2171 * function to have it all together in one place. 2172 */ 2173 static void 2174 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 2175 { 2176 struct ath5k_hw *ah = sc->ah; 2177 u32 nexttbtt, intval, hw_tu, bc_tu; 2178 u64 hw_tsf; 2179 2180 intval = sc->bintval & AR5K_BEACON_PERIOD; 2181 if (WARN_ON(!intval)) 2182 return; 2183 2184 /* beacon TSF converted to TU */ 2185 bc_tu = TSF_TO_TU(bc_tsf); 2186 2187 /* current TSF converted to TU */ 2188 hw_tsf = ath5k_hw_get_tsf64(ah); 2189 hw_tu = TSF_TO_TU(hw_tsf); 2190 2191 #define FUDGE 3 2192 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */ 2193 if (bc_tsf == -1) { 2194 /* 2195 * no beacons received, called internally. 2196 * just need to refresh timers based on HW TSF. 2197 */ 2198 nexttbtt = roundup(hw_tu + FUDGE, intval); 2199 } else if (bc_tsf == 0) { 2200 /* 2201 * no beacon received, probably called by ath5k_reset_tsf(). 2202 * reset TSF to start with 0. 2203 */ 2204 nexttbtt = intval; 2205 intval |= AR5K_BEACON_RESET_TSF; 2206 } else if (bc_tsf > hw_tsf) { 2207 /* 2208 * beacon received, SW merge happend but HW TSF not yet updated. 2209 * not possible to reconfigure timers yet, but next time we 2210 * receive a beacon with the same BSSID, the hardware will 2211 * automatically update the TSF and then we need to reconfigure 2212 * the timers. 2213 */ 2214 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2215 "need to wait for HW TSF sync\n"); 2216 return; 2217 } else { 2218 /* 2219 * most important case for beacon synchronization between STA. 2220 * 2221 * beacon received and HW TSF has been already updated by HW. 2222 * update next TBTT based on the TSF of the beacon, but make 2223 * sure it is ahead of our local TSF timer. 2224 */ 2225 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2226 } 2227 #undef FUDGE 2228 2229 sc->nexttbtt = nexttbtt; 2230 2231 intval |= AR5K_BEACON_ENA; 2232 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2233 2234 /* 2235 * debugging output last in order to preserve the time critical aspect 2236 * of this function 2237 */ 2238 if (bc_tsf == -1) 2239 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2240 "reconfigured timers based on HW TSF\n"); 2241 else if (bc_tsf == 0) 2242 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2243 "reset HW TSF and timers\n"); 2244 else 2245 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2246 "updated timers based on beacon TSF\n"); 2247 2248 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2249 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2250 (unsigned long long) bc_tsf, 2251 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2252 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2253 intval & AR5K_BEACON_PERIOD, 2254 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2255 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2256 } 2257 2258 2259 /** 2260 * ath5k_beacon_config - Configure the beacon queues and interrupts 2261 * 2262 * @sc: struct ath5k_softc pointer we are operating on 2263 * 2264 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2265 * interrupts to detect TSF updates only. 2266 */ 2267 static void 2268 ath5k_beacon_config(struct ath5k_softc *sc) 2269 { 2270 struct ath5k_hw *ah = sc->ah; 2271 unsigned long flags; 2272 2273 spin_lock_irqsave(&sc->block, flags); 2274 sc->bmisscount = 0; 2275 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2276 2277 if (sc->enable_beacon) { 2278 /* 2279 * In IBSS mode we use a self-linked tx descriptor and let the 2280 * hardware send the beacons automatically. We have to load it 2281 * only once here. 2282 * We use the SWBA interrupt only to keep track of the beacon 2283 * timers in order to detect automatic TSF updates. 2284 */ 2285 ath5k_beaconq_config(sc); 2286 2287 sc->imask |= AR5K_INT_SWBA; 2288 2289 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2290 if (ath5k_hw_hasveol(ah)) 2291 ath5k_beacon_send(sc); 2292 } else 2293 ath5k_beacon_update_timers(sc, -1); 2294 } else { 2295 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq); 2296 } 2297 2298 ath5k_hw_set_imr(ah, sc->imask); 2299 mmiowb(); 2300 spin_unlock_irqrestore(&sc->block, flags); 2301 } 2302 2303 static void ath5k_tasklet_beacon(unsigned long data) 2304 { 2305 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2306 2307 /* 2308 * Software beacon alert--time to send a beacon. 2309 * 2310 * In IBSS mode we use this interrupt just to 2311 * keep track of the next TBTT (target beacon 2312 * transmission time) in order to detect wether 2313 * automatic TSF updates happened. 2314 */ 2315 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2316 /* XXX: only if VEOL suppported */ 2317 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2318 sc->nexttbtt += sc->bintval; 2319 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2320 "SWBA nexttbtt: %x hw_tu: %x " 2321 "TSF: %llx\n", 2322 sc->nexttbtt, 2323 TSF_TO_TU(tsf), 2324 (unsigned long long) tsf); 2325 } else { 2326 spin_lock(&sc->block); 2327 ath5k_beacon_send(sc); 2328 spin_unlock(&sc->block); 2329 } 2330 } 2331 2332 2333 /********************\ 2334 * Interrupt handling * 2335 \********************/ 2336 2337 static int 2338 ath5k_init(struct ath5k_softc *sc) 2339 { 2340 struct ath5k_hw *ah = sc->ah; 2341 int ret, i; 2342 2343 mutex_lock(&sc->lock); 2344 2345 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2346 2347 /* 2348 * Stop anything previously setup. This is safe 2349 * no matter this is the first time through or not. 2350 */ 2351 ath5k_stop_locked(sc); 2352 2353 /* 2354 * The basic interface to setting the hardware in a good 2355 * state is ``reset''. On return the hardware is known to 2356 * be powered up and with interrupts disabled. This must 2357 * be followed by initialization of the appropriate bits 2358 * and then setup of the interrupt mask. 2359 */ 2360 sc->curchan = sc->hw->conf.channel; 2361 sc->curband = &sc->sbands[sc->curchan->band]; 2362 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2363 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2364 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI; 2365 ret = ath5k_reset(sc, NULL); 2366 if (ret) 2367 goto done; 2368 2369 ath5k_rfkill_hw_start(ah); 2370 2371 /* 2372 * Reset the key cache since some parts do not reset the 2373 * contents on initial power up or resume from suspend. 2374 */ 2375 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) 2376 ath5k_hw_reset_key(ah, i); 2377 2378 /* Set ack to be sent at low bit-rates */ 2379 ath5k_hw_set_ack_bitrate_high(ah, false); 2380 2381 /* Set PHY calibration inteval */ 2382 ah->ah_cal_intval = ath5k_calinterval; 2383 2384 ret = 0; 2385 done: 2386 mmiowb(); 2387 mutex_unlock(&sc->lock); 2388 return ret; 2389 } 2390 2391 static int 2392 ath5k_stop_locked(struct ath5k_softc *sc) 2393 { 2394 struct ath5k_hw *ah = sc->ah; 2395 2396 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2397 test_bit(ATH_STAT_INVALID, sc->status)); 2398 2399 /* 2400 * Shutdown the hardware and driver: 2401 * stop output from above 2402 * disable interrupts 2403 * turn off timers 2404 * turn off the radio 2405 * clear transmit machinery 2406 * clear receive machinery 2407 * drain and release tx queues 2408 * reclaim beacon resources 2409 * power down hardware 2410 * 2411 * Note that some of this work is not possible if the 2412 * hardware is gone (invalid). 2413 */ 2414 ieee80211_stop_queues(sc->hw); 2415 2416 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2417 ath5k_led_off(sc); 2418 ath5k_hw_set_imr(ah, 0); 2419 synchronize_irq(sc->pdev->irq); 2420 } 2421 ath5k_txq_cleanup(sc); 2422 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2423 ath5k_rx_stop(sc); 2424 ath5k_hw_phy_disable(ah); 2425 } else 2426 sc->rxlink = NULL; 2427 2428 return 0; 2429 } 2430 2431 /* 2432 * Stop the device, grabbing the top-level lock to protect 2433 * against concurrent entry through ath5k_init (which can happen 2434 * if another thread does a system call and the thread doing the 2435 * stop is preempted). 2436 */ 2437 static int 2438 ath5k_stop_hw(struct ath5k_softc *sc) 2439 { 2440 int ret; 2441 2442 mutex_lock(&sc->lock); 2443 ret = ath5k_stop_locked(sc); 2444 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2445 /* 2446 * Don't set the card in full sleep mode! 2447 * 2448 * a) When the device is in this state it must be carefully 2449 * woken up or references to registers in the PCI clock 2450 * domain may freeze the bus (and system). This varies 2451 * by chip and is mostly an issue with newer parts 2452 * (madwifi sources mentioned srev >= 0x78) that go to 2453 * sleep more quickly. 2454 * 2455 * b) On older chips full sleep results a weird behaviour 2456 * during wakeup. I tested various cards with srev < 0x78 2457 * and they don't wake up after module reload, a second 2458 * module reload is needed to bring the card up again. 2459 * 2460 * Until we figure out what's going on don't enable 2461 * full chip reset on any chip (this is what Legacy HAL 2462 * and Sam's HAL do anyway). Instead Perform a full reset 2463 * on the device (same as initial state after attach) and 2464 * leave it idle (keep MAC/BB on warm reset) */ 2465 ret = ath5k_hw_on_hold(sc->ah); 2466 2467 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2468 "putting device to sleep\n"); 2469 } 2470 ath5k_txbuf_free(sc, sc->bbuf); 2471 2472 mmiowb(); 2473 mutex_unlock(&sc->lock); 2474 2475 tasklet_kill(&sc->rxtq); 2476 tasklet_kill(&sc->txtq); 2477 tasklet_kill(&sc->restq); 2478 tasklet_kill(&sc->calib); 2479 tasklet_kill(&sc->beacontq); 2480 2481 ath5k_rfkill_hw_stop(sc->ah); 2482 2483 return ret; 2484 } 2485 2486 static irqreturn_t 2487 ath5k_intr(int irq, void *dev_id) 2488 { 2489 struct ath5k_softc *sc = dev_id; 2490 struct ath5k_hw *ah = sc->ah; 2491 enum ath5k_int status; 2492 unsigned int counter = 1000; 2493 2494 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2495 !ath5k_hw_is_intr_pending(ah))) 2496 return IRQ_NONE; 2497 2498 do { 2499 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2500 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2501 status, sc->imask); 2502 if (unlikely(status & AR5K_INT_FATAL)) { 2503 /* 2504 * Fatal errors are unrecoverable. 2505 * Typically these are caused by DMA errors. 2506 */ 2507 tasklet_schedule(&sc->restq); 2508 } else if (unlikely(status & AR5K_INT_RXORN)) { 2509 tasklet_schedule(&sc->restq); 2510 } else { 2511 if (status & AR5K_INT_SWBA) { 2512 tasklet_hi_schedule(&sc->beacontq); 2513 } 2514 if (status & AR5K_INT_RXEOL) { 2515 /* 2516 * NB: the hardware should re-read the link when 2517 * RXE bit is written, but it doesn't work at 2518 * least on older hardware revs. 2519 */ 2520 sc->rxlink = NULL; 2521 } 2522 if (status & AR5K_INT_TXURN) { 2523 /* bump tx trigger level */ 2524 ath5k_hw_update_tx_triglevel(ah, true); 2525 } 2526 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2527 tasklet_schedule(&sc->rxtq); 2528 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2529 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2530 tasklet_schedule(&sc->txtq); 2531 if (status & AR5K_INT_BMISS) { 2532 /* TODO */ 2533 } 2534 if (status & AR5K_INT_SWI) { 2535 tasklet_schedule(&sc->calib); 2536 } 2537 if (status & AR5K_INT_MIB) { 2538 /* 2539 * These stats are also used for ANI i think 2540 * so how about updating them more often ? 2541 */ 2542 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 2543 } 2544 if (status & AR5K_INT_GPIO) 2545 tasklet_schedule(&sc->rf_kill.toggleq); 2546 2547 } 2548 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2549 2550 if (unlikely(!counter)) 2551 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2552 2553 ath5k_hw_calibration_poll(ah); 2554 2555 return IRQ_HANDLED; 2556 } 2557 2558 static void 2559 ath5k_tasklet_reset(unsigned long data) 2560 { 2561 struct ath5k_softc *sc = (void *)data; 2562 2563 ath5k_reset_wake(sc); 2564 } 2565 2566 /* 2567 * Periodically recalibrate the PHY to account 2568 * for temperature/environment changes. 2569 */ 2570 static void 2571 ath5k_tasklet_calibrate(unsigned long data) 2572 { 2573 struct ath5k_softc *sc = (void *)data; 2574 struct ath5k_hw *ah = sc->ah; 2575 2576 /* Only full calibration for now */ 2577 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION) 2578 return; 2579 2580 /* Stop queues so that calibration 2581 * doesn't interfere with tx */ 2582 ieee80211_stop_queues(sc->hw); 2583 2584 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2585 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2586 sc->curchan->hw_value); 2587 2588 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2589 /* 2590 * Rfgain is out of bounds, reset the chip 2591 * to load new gain values. 2592 */ 2593 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2594 ath5k_reset_wake(sc); 2595 } 2596 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2597 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2598 ieee80211_frequency_to_channel( 2599 sc->curchan->center_freq)); 2600 2601 ah->ah_swi_mask = 0; 2602 2603 /* Wake queues */ 2604 ieee80211_wake_queues(sc->hw); 2605 2606 } 2607 2608 2609 /********************\ 2610 * Mac80211 functions * 2611 \********************/ 2612 2613 static int 2614 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2615 { 2616 struct ath5k_softc *sc = hw->priv; 2617 2618 return ath5k_tx_queue(hw, skb, sc->txq); 2619 } 2620 2621 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 2622 struct ath5k_txq *txq) 2623 { 2624 struct ath5k_softc *sc = hw->priv; 2625 struct ath5k_buf *bf; 2626 unsigned long flags; 2627 int hdrlen; 2628 int padsize; 2629 2630 ath5k_debug_dump_skb(sc, skb, "TX ", 1); 2631 2632 if (sc->opmode == NL80211_IFTYPE_MONITOR) 2633 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n"); 2634 2635 /* 2636 * the hardware expects the header padded to 4 byte boundaries 2637 * if this is not the case we add the padding after the header 2638 */ 2639 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 2640 padsize = ath5k_pad_size(hdrlen); 2641 if (padsize) { 2642 2643 if (skb_headroom(skb) < padsize) { 2644 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough" 2645 " headroom to pad %d\n", hdrlen, padsize); 2646 goto drop_packet; 2647 } 2648 skb_push(skb, padsize); 2649 memmove(skb->data, skb->data+padsize, hdrlen); 2650 } 2651 2652 spin_lock_irqsave(&sc->txbuflock, flags); 2653 if (list_empty(&sc->txbuf)) { 2654 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 2655 spin_unlock_irqrestore(&sc->txbuflock, flags); 2656 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 2657 goto drop_packet; 2658 } 2659 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 2660 list_del(&bf->list); 2661 sc->txbuf_len--; 2662 if (list_empty(&sc->txbuf)) 2663 ieee80211_stop_queues(hw); 2664 spin_unlock_irqrestore(&sc->txbuflock, flags); 2665 2666 bf->skb = skb; 2667 2668 if (ath5k_txbuf_setup(sc, bf, txq)) { 2669 bf->skb = NULL; 2670 spin_lock_irqsave(&sc->txbuflock, flags); 2671 list_add_tail(&bf->list, &sc->txbuf); 2672 sc->txbuf_len++; 2673 spin_unlock_irqrestore(&sc->txbuflock, flags); 2674 goto drop_packet; 2675 } 2676 return NETDEV_TX_OK; 2677 2678 drop_packet: 2679 dev_kfree_skb_any(skb); 2680 return NETDEV_TX_OK; 2681 } 2682 2683 /* 2684 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2685 * and change to the given channel. 2686 */ 2687 static int 2688 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan) 2689 { 2690 struct ath5k_hw *ah = sc->ah; 2691 int ret; 2692 2693 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2694 2695 if (chan) { 2696 ath5k_hw_set_imr(ah, 0); 2697 ath5k_txq_cleanup(sc); 2698 ath5k_rx_stop(sc); 2699 2700 sc->curchan = chan; 2701 sc->curband = &sc->sbands[chan->band]; 2702 } 2703 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL); 2704 if (ret) { 2705 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2706 goto err; 2707 } 2708 2709 ret = ath5k_rx_start(sc); 2710 if (ret) { 2711 ATH5K_ERR(sc, "can't start recv logic\n"); 2712 goto err; 2713 } 2714 2715 /* 2716 * Change channels and update the h/w rate map if we're switching; 2717 * e.g. 11a to 11b/g. 2718 * 2719 * We may be doing a reset in response to an ioctl that changes the 2720 * channel so update any state that might change as a result. 2721 * 2722 * XXX needed? 2723 */ 2724 /* ath5k_chan_change(sc, c); */ 2725 2726 ath5k_beacon_config(sc); 2727 /* intrs are enabled by ath5k_beacon_config */ 2728 2729 return 0; 2730 err: 2731 return ret; 2732 } 2733 2734 static int 2735 ath5k_reset_wake(struct ath5k_softc *sc) 2736 { 2737 int ret; 2738 2739 ret = ath5k_reset(sc, sc->curchan); 2740 if (!ret) 2741 ieee80211_wake_queues(sc->hw); 2742 2743 return ret; 2744 } 2745 2746 static int ath5k_start(struct ieee80211_hw *hw) 2747 { 2748 return ath5k_init(hw->priv); 2749 } 2750 2751 static void ath5k_stop(struct ieee80211_hw *hw) 2752 { 2753 ath5k_stop_hw(hw->priv); 2754 } 2755 2756 static int ath5k_add_interface(struct ieee80211_hw *hw, 2757 struct ieee80211_if_init_conf *conf) 2758 { 2759 struct ath5k_softc *sc = hw->priv; 2760 int ret; 2761 2762 mutex_lock(&sc->lock); 2763 if (sc->vif) { 2764 ret = 0; 2765 goto end; 2766 } 2767 2768 sc->vif = conf->vif; 2769 2770 switch (conf->type) { 2771 case NL80211_IFTYPE_AP: 2772 case NL80211_IFTYPE_STATION: 2773 case NL80211_IFTYPE_ADHOC: 2774 case NL80211_IFTYPE_MESH_POINT: 2775 case NL80211_IFTYPE_MONITOR: 2776 sc->opmode = conf->type; 2777 break; 2778 default: 2779 ret = -EOPNOTSUPP; 2780 goto end; 2781 } 2782 2783 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr); 2784 ath5k_mode_setup(sc); 2785 2786 ret = 0; 2787 end: 2788 mutex_unlock(&sc->lock); 2789 return ret; 2790 } 2791 2792 static void 2793 ath5k_remove_interface(struct ieee80211_hw *hw, 2794 struct ieee80211_if_init_conf *conf) 2795 { 2796 struct ath5k_softc *sc = hw->priv; 2797 u8 mac[ETH_ALEN] = {}; 2798 2799 mutex_lock(&sc->lock); 2800 if (sc->vif != conf->vif) 2801 goto end; 2802 2803 ath5k_hw_set_lladdr(sc->ah, mac); 2804 sc->vif = NULL; 2805 end: 2806 mutex_unlock(&sc->lock); 2807 } 2808 2809 /* 2810 * TODO: Phy disable/diversity etc 2811 */ 2812 static int 2813 ath5k_config(struct ieee80211_hw *hw, u32 changed) 2814 { 2815 struct ath5k_softc *sc = hw->priv; 2816 struct ath5k_hw *ah = sc->ah; 2817 struct ieee80211_conf *conf = &hw->conf; 2818 int ret = 0; 2819 2820 mutex_lock(&sc->lock); 2821 2822 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 2823 ret = ath5k_chan_set(sc, conf->channel); 2824 if (ret < 0) 2825 goto unlock; 2826 } 2827 2828 if ((changed & IEEE80211_CONF_CHANGE_POWER) && 2829 (sc->power_level != conf->power_level)) { 2830 sc->power_level = conf->power_level; 2831 2832 /* Half dB steps */ 2833 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); 2834 } 2835 2836 /* TODO: 2837 * 1) Move this on config_interface and handle each case 2838 * separately eg. when we have only one STA vif, use 2839 * AR5K_ANTMODE_SINGLE_AP 2840 * 2841 * 2) Allow the user to change antenna mode eg. when only 2842 * one antenna is present 2843 * 2844 * 3) Allow the user to set default/tx antenna when possible 2845 * 2846 * 4) Default mode should handle 90% of the cases, together 2847 * with fixed a/b and single AP modes we should be able to 2848 * handle 99%. Sectored modes are extreme cases and i still 2849 * haven't found a usage for them. If we decide to support them, 2850 * then we must allow the user to set how many tx antennas we 2851 * have available 2852 */ 2853 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT); 2854 2855 unlock: 2856 mutex_unlock(&sc->lock); 2857 return ret; 2858 } 2859 2860 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 2861 int mc_count, struct dev_addr_list *mclist) 2862 { 2863 u32 mfilt[2], val; 2864 int i; 2865 u8 pos; 2866 2867 mfilt[0] = 0; 2868 mfilt[1] = 1; 2869 2870 for (i = 0; i < mc_count; i++) { 2871 if (!mclist) 2872 break; 2873 /* calculate XOR of eight 6-bit values */ 2874 val = get_unaligned_le32(mclist->dmi_addr + 0); 2875 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2876 val = get_unaligned_le32(mclist->dmi_addr + 3); 2877 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2878 pos &= 0x3f; 2879 mfilt[pos / 32] |= (1 << (pos % 32)); 2880 /* XXX: we might be able to just do this instead, 2881 * but not sure, needs testing, if we do use this we'd 2882 * neet to inform below to not reset the mcast */ 2883 /* ath5k_hw_set_mcast_filterindex(ah, 2884 * mclist->dmi_addr[5]); */ 2885 mclist = mclist->next; 2886 } 2887 2888 return ((u64)(mfilt[1]) << 32) | mfilt[0]; 2889 } 2890 2891 #define SUPPORTED_FIF_FLAGS \ 2892 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ 2893 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ 2894 FIF_BCN_PRBRESP_PROMISC 2895 /* 2896 * o always accept unicast, broadcast, and multicast traffic 2897 * o multicast traffic for all BSSIDs will be enabled if mac80211 2898 * says it should be 2899 * o maintain current state of phy ofdm or phy cck error reception. 2900 * If the hardware detects any of these type of errors then 2901 * ath5k_hw_get_rx_filter() will pass to us the respective 2902 * hardware filters to be able to receive these type of frames. 2903 * o probe request frames are accepted only when operating in 2904 * hostap, adhoc, or monitor modes 2905 * o enable promiscuous mode according to the interface state 2906 * o accept beacons: 2907 * - when operating in adhoc mode so the 802.11 layer creates 2908 * node table entries for peers, 2909 * - when operating in station mode for collecting rssi data when 2910 * the station is otherwise quiet, or 2911 * - when scanning 2912 */ 2913 static void ath5k_configure_filter(struct ieee80211_hw *hw, 2914 unsigned int changed_flags, 2915 unsigned int *new_flags, 2916 u64 multicast) 2917 { 2918 struct ath5k_softc *sc = hw->priv; 2919 struct ath5k_hw *ah = sc->ah; 2920 u32 mfilt[2], rfilt; 2921 2922 mutex_lock(&sc->lock); 2923 2924 mfilt[0] = multicast; 2925 mfilt[1] = multicast >> 32; 2926 2927 /* Only deal with supported flags */ 2928 changed_flags &= SUPPORTED_FIF_FLAGS; 2929 *new_flags &= SUPPORTED_FIF_FLAGS; 2930 2931 /* If HW detects any phy or radar errors, leave those filters on. 2932 * Also, always enable Unicast, Broadcasts and Multicast 2933 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ 2934 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | 2935 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | 2936 AR5K_RX_FILTER_MCAST); 2937 2938 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { 2939 if (*new_flags & FIF_PROMISC_IN_BSS) { 2940 rfilt |= AR5K_RX_FILTER_PROM; 2941 __set_bit(ATH_STAT_PROMISC, sc->status); 2942 } else { 2943 __clear_bit(ATH_STAT_PROMISC, sc->status); 2944 } 2945 } 2946 2947 /* Note, AR5K_RX_FILTER_MCAST is already enabled */ 2948 if (*new_flags & FIF_ALLMULTI) { 2949 mfilt[0] = ~0; 2950 mfilt[1] = ~0; 2951 } 2952 2953 /* This is the best we can do */ 2954 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) 2955 rfilt |= AR5K_RX_FILTER_PHYERR; 2956 2957 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons 2958 * and probes for any BSSID, this needs testing */ 2959 if (*new_flags & FIF_BCN_PRBRESP_PROMISC) 2960 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ; 2961 2962 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not 2963 * set we should only pass on control frames for this 2964 * station. This needs testing. I believe right now this 2965 * enables *all* control frames, which is OK.. but 2966 * but we should see if we can improve on granularity */ 2967 if (*new_flags & FIF_CONTROL) 2968 rfilt |= AR5K_RX_FILTER_CONTROL; 2969 2970 /* Additional settings per mode -- this is per ath5k */ 2971 2972 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ 2973 2974 switch (sc->opmode) { 2975 case NL80211_IFTYPE_MESH_POINT: 2976 case NL80211_IFTYPE_MONITOR: 2977 rfilt |= AR5K_RX_FILTER_CONTROL | 2978 AR5K_RX_FILTER_BEACON | 2979 AR5K_RX_FILTER_PROBEREQ | 2980 AR5K_RX_FILTER_PROM; 2981 break; 2982 case NL80211_IFTYPE_AP: 2983 case NL80211_IFTYPE_ADHOC: 2984 rfilt |= AR5K_RX_FILTER_PROBEREQ | 2985 AR5K_RX_FILTER_BEACON; 2986 break; 2987 case NL80211_IFTYPE_STATION: 2988 if (sc->assoc) 2989 rfilt |= AR5K_RX_FILTER_BEACON; 2990 default: 2991 break; 2992 } 2993 2994 /* Set filters */ 2995 ath5k_hw_set_rx_filter(ah, rfilt); 2996 2997 /* Set multicast bits */ 2998 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); 2999 /* Set the cached hw filter flags, this will alter actually 3000 * be set in HW */ 3001 sc->filter_flags = rfilt; 3002 3003 mutex_unlock(&sc->lock); 3004 } 3005 3006 static int 3007 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3008 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3009 struct ieee80211_key_conf *key) 3010 { 3011 struct ath5k_softc *sc = hw->priv; 3012 int ret = 0; 3013 3014 if (modparam_nohwcrypt) 3015 return -EOPNOTSUPP; 3016 3017 if (sc->opmode == NL80211_IFTYPE_AP) 3018 return -EOPNOTSUPP; 3019 3020 switch (key->alg) { 3021 case ALG_WEP: 3022 case ALG_TKIP: 3023 break; 3024 case ALG_CCMP: 3025 if (sc->ah->ah_aes_support) 3026 break; 3027 3028 return -EOPNOTSUPP; 3029 default: 3030 WARN_ON(1); 3031 return -EINVAL; 3032 } 3033 3034 mutex_lock(&sc->lock); 3035 3036 switch (cmd) { 3037 case SET_KEY: 3038 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, 3039 sta ? sta->addr : NULL); 3040 if (ret) { 3041 ATH5K_ERR(sc, "can't set the key\n"); 3042 goto unlock; 3043 } 3044 __set_bit(key->keyidx, sc->keymap); 3045 key->hw_key_idx = key->keyidx; 3046 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV | 3047 IEEE80211_KEY_FLAG_GENERATE_MMIC); 3048 break; 3049 case DISABLE_KEY: 3050 ath5k_hw_reset_key(sc->ah, key->keyidx); 3051 __clear_bit(key->keyidx, sc->keymap); 3052 break; 3053 default: 3054 ret = -EINVAL; 3055 goto unlock; 3056 } 3057 3058 unlock: 3059 mmiowb(); 3060 mutex_unlock(&sc->lock); 3061 return ret; 3062 } 3063 3064 static int 3065 ath5k_get_stats(struct ieee80211_hw *hw, 3066 struct ieee80211_low_level_stats *stats) 3067 { 3068 struct ath5k_softc *sc = hw->priv; 3069 struct ath5k_hw *ah = sc->ah; 3070 3071 /* Force update */ 3072 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 3073 3074 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); 3075 3076 return 0; 3077 } 3078 3079 static int 3080 ath5k_get_tx_stats(struct ieee80211_hw *hw, 3081 struct ieee80211_tx_queue_stats *stats) 3082 { 3083 struct ath5k_softc *sc = hw->priv; 3084 3085 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); 3086 3087 return 0; 3088 } 3089 3090 static u64 3091 ath5k_get_tsf(struct ieee80211_hw *hw) 3092 { 3093 struct ath5k_softc *sc = hw->priv; 3094 3095 return ath5k_hw_get_tsf64(sc->ah); 3096 } 3097 3098 static void 3099 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3100 { 3101 struct ath5k_softc *sc = hw->priv; 3102 3103 ath5k_hw_set_tsf64(sc->ah, tsf); 3104 } 3105 3106 static void 3107 ath5k_reset_tsf(struct ieee80211_hw *hw) 3108 { 3109 struct ath5k_softc *sc = hw->priv; 3110 3111 /* 3112 * in IBSS mode we need to update the beacon timers too. 3113 * this will also reset the TSF if we call it with 0 3114 */ 3115 if (sc->opmode == NL80211_IFTYPE_ADHOC) 3116 ath5k_beacon_update_timers(sc, 0); 3117 else 3118 ath5k_hw_reset_tsf(sc->ah); 3119 } 3120 3121 /* 3122 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 3123 * this is called only once at config_bss time, for AP we do it every 3124 * SWBA interrupt so that the TIM will reflect buffered frames. 3125 * 3126 * Called with the beacon lock. 3127 */ 3128 static int 3129 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3130 { 3131 int ret; 3132 struct ath5k_softc *sc = hw->priv; 3133 struct sk_buff *skb; 3134 3135 if (WARN_ON(!vif)) { 3136 ret = -EINVAL; 3137 goto out; 3138 } 3139 3140 skb = ieee80211_beacon_get(hw, vif); 3141 3142 if (!skb) { 3143 ret = -ENOMEM; 3144 goto out; 3145 } 3146 3147 ath5k_debug_dump_skb(sc, skb, "BC ", 1); 3148 3149 ath5k_txbuf_free(sc, sc->bbuf); 3150 sc->bbuf->skb = skb; 3151 ret = ath5k_beacon_setup(sc, sc->bbuf); 3152 if (ret) 3153 sc->bbuf->skb = NULL; 3154 out: 3155 return ret; 3156 } 3157 3158 static void 3159 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3160 { 3161 struct ath5k_softc *sc = hw->priv; 3162 struct ath5k_hw *ah = sc->ah; 3163 u32 rfilt; 3164 rfilt = ath5k_hw_get_rx_filter(ah); 3165 if (enable) 3166 rfilt |= AR5K_RX_FILTER_BEACON; 3167 else 3168 rfilt &= ~AR5K_RX_FILTER_BEACON; 3169 ath5k_hw_set_rx_filter(ah, rfilt); 3170 sc->filter_flags = rfilt; 3171 } 3172 3173 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 3174 struct ieee80211_vif *vif, 3175 struct ieee80211_bss_conf *bss_conf, 3176 u32 changes) 3177 { 3178 struct ath5k_softc *sc = hw->priv; 3179 struct ath5k_hw *ah = sc->ah; 3180 unsigned long flags; 3181 3182 mutex_lock(&sc->lock); 3183 if (WARN_ON(sc->vif != vif)) 3184 goto unlock; 3185 3186 if (changes & BSS_CHANGED_BSSID) { 3187 /* Cache for later use during resets */ 3188 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN); 3189 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have 3190 * a clean way of letting us retrieve this yet. */ 3191 ath5k_hw_set_associd(ah, ah->ah_bssid, 0); 3192 mmiowb(); 3193 } 3194 3195 if (changes & BSS_CHANGED_BEACON_INT) 3196 sc->bintval = bss_conf->beacon_int; 3197 3198 if (changes & BSS_CHANGED_ASSOC) { 3199 sc->assoc = bss_conf->assoc; 3200 if (sc->opmode == NL80211_IFTYPE_STATION) 3201 set_beacon_filter(hw, sc->assoc); 3202 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3203 AR5K_LED_ASSOC : AR5K_LED_INIT); 3204 } 3205 3206 if (changes & BSS_CHANGED_BEACON) { 3207 spin_lock_irqsave(&sc->block, flags); 3208 ath5k_beacon_update(hw, vif); 3209 spin_unlock_irqrestore(&sc->block, flags); 3210 } 3211 3212 if (changes & BSS_CHANGED_BEACON_ENABLED) 3213 sc->enable_beacon = bss_conf->enable_beacon; 3214 3215 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | 3216 BSS_CHANGED_BEACON_INT)) 3217 ath5k_beacon_config(sc); 3218 3219 unlock: 3220 mutex_unlock(&sc->lock); 3221 } 3222 3223 static void ath5k_sw_scan_start(struct ieee80211_hw *hw) 3224 { 3225 struct ath5k_softc *sc = hw->priv; 3226 if (!sc->assoc) 3227 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); 3228 } 3229 3230 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw) 3231 { 3232 struct ath5k_softc *sc = hw->priv; 3233 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3234 AR5K_LED_ASSOC : AR5K_LED_INIT); 3235 } 3236