1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 44 45 #include <linux/module.h> 46 #include <linux/delay.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/hardirq.h> 49 #include <linux/if.h> 50 #include <linux/io.h> 51 #include <linux/netdevice.h> 52 #include <linux/cache.h> 53 #include <linux/ethtool.h> 54 #include <linux/uaccess.h> 55 #include <linux/slab.h> 56 #include <linux/etherdevice.h> 57 #include <linux/nl80211.h> 58 59 #include <net/ieee80211_radiotap.h> 60 61 #include <asm/unaligned.h> 62 63 #include <net/mac80211.h> 64 #include "base.h" 65 #include "reg.h" 66 #include "debug.h" 67 #include "ani.h" 68 #include "ath5k.h" 69 #include "../regd.h" 70 71 #define CREATE_TRACE_POINTS 72 #include "trace.h" 73 74 bool ath5k_modparam_nohwcrypt; 75 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 77 78 static bool modparam_fastchanswitch; 79 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 80 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 81 82 static bool ath5k_modparam_no_hw_rfkill_switch; 83 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, 84 bool, S_IRUGO); 85 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); 86 87 88 /* Module info */ 89 MODULE_AUTHOR("Jiri Slaby"); 90 MODULE_AUTHOR("Nick Kossifidis"); 91 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 92 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 93 MODULE_LICENSE("Dual BSD/GPL"); 94 95 static int ath5k_init(struct ieee80211_hw *hw); 96 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 97 bool skip_pcu); 98 99 /* Known SREVs */ 100 static const struct ath5k_srev_name srev_names[] = { 101 #ifdef CONFIG_ATHEROS_AR231X 102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 104 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 109 #else 110 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 111 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 112 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 113 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 114 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 115 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 116 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 117 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 118 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 119 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 120 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 121 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 122 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 123 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 124 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 125 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 126 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 127 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 128 #endif 129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 142 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 143 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 144 #ifdef CONFIG_ATHEROS_AR231X 145 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 146 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 147 #endif 148 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 149 }; 150 151 static const struct ieee80211_rate ath5k_rates[] = { 152 { .bitrate = 10, 153 .hw_value = ATH5K_RATE_CODE_1M, }, 154 { .bitrate = 20, 155 .hw_value = ATH5K_RATE_CODE_2M, 156 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 157 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 158 { .bitrate = 55, 159 .hw_value = ATH5K_RATE_CODE_5_5M, 160 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 161 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 162 { .bitrate = 110, 163 .hw_value = ATH5K_RATE_CODE_11M, 164 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 165 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 166 { .bitrate = 60, 167 .hw_value = ATH5K_RATE_CODE_6M, 168 .flags = 0 }, 169 { .bitrate = 90, 170 .hw_value = ATH5K_RATE_CODE_9M, 171 .flags = 0 }, 172 { .bitrate = 120, 173 .hw_value = ATH5K_RATE_CODE_12M, 174 .flags = 0 }, 175 { .bitrate = 180, 176 .hw_value = ATH5K_RATE_CODE_18M, 177 .flags = 0 }, 178 { .bitrate = 240, 179 .hw_value = ATH5K_RATE_CODE_24M, 180 .flags = 0 }, 181 { .bitrate = 360, 182 .hw_value = ATH5K_RATE_CODE_36M, 183 .flags = 0 }, 184 { .bitrate = 480, 185 .hw_value = ATH5K_RATE_CODE_48M, 186 .flags = 0 }, 187 { .bitrate = 540, 188 .hw_value = ATH5K_RATE_CODE_54M, 189 .flags = 0 }, 190 }; 191 192 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 193 { 194 u64 tsf = ath5k_hw_get_tsf64(ah); 195 196 if ((tsf & 0x7fff) < rstamp) 197 tsf -= 0x8000; 198 199 return (tsf & ~0x7fff) | rstamp; 200 } 201 202 const char * 203 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 204 { 205 const char *name = "xxxxx"; 206 unsigned int i; 207 208 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 209 if (srev_names[i].sr_type != type) 210 continue; 211 212 if ((val & 0xf0) == srev_names[i].sr_val) 213 name = srev_names[i].sr_name; 214 215 if ((val & 0xff) == srev_names[i].sr_val) { 216 name = srev_names[i].sr_name; 217 break; 218 } 219 } 220 221 return name; 222 } 223 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 224 { 225 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 226 return ath5k_hw_reg_read(ah, reg_offset); 227 } 228 229 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 230 { 231 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 232 ath5k_hw_reg_write(ah, val, reg_offset); 233 } 234 235 static const struct ath_ops ath5k_common_ops = { 236 .read = ath5k_ioread32, 237 .write = ath5k_iowrite32, 238 }; 239 240 /***********************\ 241 * Driver Initialization * 242 \***********************/ 243 244 static void ath5k_reg_notifier(struct wiphy *wiphy, 245 struct regulatory_request *request) 246 { 247 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 248 struct ath5k_hw *ah = hw->priv; 249 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 250 251 ath_reg_notifier_apply(wiphy, request, regulatory); 252 } 253 254 /********************\ 255 * Channel/mode setup * 256 \********************/ 257 258 /* 259 * Returns true for the channel numbers used. 260 */ 261 #ifdef CONFIG_ATH5K_TEST_CHANNELS 262 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 263 { 264 return true; 265 } 266 267 #else 268 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 269 { 270 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 271 return true; 272 273 return /* UNII 1,2 */ 274 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 275 /* midband */ 276 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 277 /* UNII-3 */ 278 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 279 /* 802.11j 5.030-5.080 GHz (20MHz) */ 280 (chan == 8 || chan == 12 || chan == 16) || 281 /* 802.11j 4.9GHz (20MHz) */ 282 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 283 } 284 #endif 285 286 static unsigned int 287 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 288 unsigned int mode, unsigned int max) 289 { 290 unsigned int count, size, freq, ch; 291 enum ieee80211_band band; 292 293 switch (mode) { 294 case AR5K_MODE_11A: 295 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 296 size = 220; 297 band = IEEE80211_BAND_5GHZ; 298 break; 299 case AR5K_MODE_11B: 300 case AR5K_MODE_11G: 301 size = 26; 302 band = IEEE80211_BAND_2GHZ; 303 break; 304 default: 305 ATH5K_WARN(ah, "bad mode, not copying channels\n"); 306 return 0; 307 } 308 309 count = 0; 310 for (ch = 1; ch <= size && count < max; ch++) { 311 freq = ieee80211_channel_to_frequency(ch, band); 312 313 if (freq == 0) /* mapping failed - not a standard channel */ 314 continue; 315 316 /* Write channel info, needed for ath5k_channel_ok() */ 317 channels[count].center_freq = freq; 318 channels[count].band = band; 319 channels[count].hw_value = mode; 320 321 /* Check if channel is supported by the chipset */ 322 if (!ath5k_channel_ok(ah, &channels[count])) 323 continue; 324 325 if (!ath5k_is_standard_channel(ch, band)) 326 continue; 327 328 count++; 329 } 330 331 return count; 332 } 333 334 static void 335 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) 336 { 337 u8 i; 338 339 for (i = 0; i < AR5K_MAX_RATES; i++) 340 ah->rate_idx[b->band][i] = -1; 341 342 for (i = 0; i < b->n_bitrates; i++) { 343 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; 344 if (b->bitrates[i].hw_value_short) 345 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 346 } 347 } 348 349 static int 350 ath5k_setup_bands(struct ieee80211_hw *hw) 351 { 352 struct ath5k_hw *ah = hw->priv; 353 struct ieee80211_supported_band *sband; 354 int max_c, count_c = 0; 355 int i; 356 357 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS); 358 max_c = ARRAY_SIZE(ah->channels); 359 360 /* 2GHz band */ 361 sband = &ah->sbands[IEEE80211_BAND_2GHZ]; 362 sband->band = IEEE80211_BAND_2GHZ; 363 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0]; 364 365 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { 366 /* G mode */ 367 memcpy(sband->bitrates, &ath5k_rates[0], 368 sizeof(struct ieee80211_rate) * 12); 369 sband->n_bitrates = 12; 370 371 sband->channels = ah->channels; 372 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 373 AR5K_MODE_11G, max_c); 374 375 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 376 count_c = sband->n_channels; 377 max_c -= count_c; 378 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { 379 /* B mode */ 380 memcpy(sband->bitrates, &ath5k_rates[0], 381 sizeof(struct ieee80211_rate) * 4); 382 sband->n_bitrates = 4; 383 384 /* 5211 only supports B rates and uses 4bit rate codes 385 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 386 * fix them up here: 387 */ 388 if (ah->ah_version == AR5K_AR5211) { 389 for (i = 0; i < 4; i++) { 390 sband->bitrates[i].hw_value = 391 sband->bitrates[i].hw_value & 0xF; 392 sband->bitrates[i].hw_value_short = 393 sband->bitrates[i].hw_value_short & 0xF; 394 } 395 } 396 397 sband->channels = ah->channels; 398 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 399 AR5K_MODE_11B, max_c); 400 401 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 402 count_c = sband->n_channels; 403 max_c -= count_c; 404 } 405 ath5k_setup_rate_idx(ah, sband); 406 407 /* 5GHz band, A mode */ 408 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 409 sband = &ah->sbands[IEEE80211_BAND_5GHZ]; 410 sband->band = IEEE80211_BAND_5GHZ; 411 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0]; 412 413 memcpy(sband->bitrates, &ath5k_rates[4], 414 sizeof(struct ieee80211_rate) * 8); 415 sband->n_bitrates = 8; 416 417 sband->channels = &ah->channels[count_c]; 418 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 419 AR5K_MODE_11A, max_c); 420 421 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 422 } 423 ath5k_setup_rate_idx(ah, sband); 424 425 ath5k_debug_dump_bands(ah); 426 427 return 0; 428 } 429 430 /* 431 * Set/change channels. We always reset the chip. 432 * To accomplish this we must first cleanup any pending DMA, 433 * then restart stuff after a la ath5k_init. 434 * 435 * Called with ah->lock. 436 */ 437 int 438 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan) 439 { 440 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 441 "channel set, resetting (%u -> %u MHz)\n", 442 ah->curchan->center_freq, chan->center_freq); 443 444 /* 445 * To switch channels clear any pending DMA operations; 446 * wait long enough for the RX fifo to drain, reset the 447 * hardware at the new frequency, and then re-enable 448 * the relevant bits of the h/w. 449 */ 450 return ath5k_reset(ah, chan, true); 451 } 452 453 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 454 { 455 struct ath5k_vif_iter_data *iter_data = data; 456 int i; 457 struct ath5k_vif *avf = (void *)vif->drv_priv; 458 459 if (iter_data->hw_macaddr) 460 for (i = 0; i < ETH_ALEN; i++) 461 iter_data->mask[i] &= 462 ~(iter_data->hw_macaddr[i] ^ mac[i]); 463 464 if (!iter_data->found_active) { 465 iter_data->found_active = true; 466 memcpy(iter_data->active_mac, mac, ETH_ALEN); 467 } 468 469 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 470 if (ether_addr_equal(iter_data->hw_macaddr, mac)) 471 iter_data->need_set_hw_addr = false; 472 473 if (!iter_data->any_assoc) { 474 if (avf->assoc) 475 iter_data->any_assoc = true; 476 } 477 478 /* Calculate combined mode - when APs are active, operate in AP mode. 479 * Otherwise use the mode of the new interface. This can currently 480 * only deal with combinations of APs and STAs. Only one ad-hoc 481 * interfaces is allowed. 482 */ 483 if (avf->opmode == NL80211_IFTYPE_AP) 484 iter_data->opmode = NL80211_IFTYPE_AP; 485 else { 486 if (avf->opmode == NL80211_IFTYPE_STATION) 487 iter_data->n_stas++; 488 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 489 iter_data->opmode = avf->opmode; 490 } 491 } 492 493 void 494 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, 495 struct ieee80211_vif *vif) 496 { 497 struct ath_common *common = ath5k_hw_common(ah); 498 struct ath5k_vif_iter_data iter_data; 499 u32 rfilt; 500 501 /* 502 * Use the hardware MAC address as reference, the hardware uses it 503 * together with the BSSID mask when matching addresses. 504 */ 505 iter_data.hw_macaddr = common->macaddr; 506 memset(&iter_data.mask, 0xff, ETH_ALEN); 507 iter_data.found_active = false; 508 iter_data.need_set_hw_addr = true; 509 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 510 iter_data.n_stas = 0; 511 512 if (vif) 513 ath5k_vif_iter(&iter_data, vif->addr, vif); 514 515 /* Get list of all active MAC addresses */ 516 ieee80211_iterate_active_interfaces_atomic( 517 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 518 ath5k_vif_iter, &iter_data); 519 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); 520 521 ah->opmode = iter_data.opmode; 522 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) 523 /* Nothing active, default to station mode */ 524 ah->opmode = NL80211_IFTYPE_STATION; 525 526 ath5k_hw_set_opmode(ah, ah->opmode); 527 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 528 ah->opmode, ath_opmode_to_string(ah->opmode)); 529 530 if (iter_data.need_set_hw_addr && iter_data.found_active) 531 ath5k_hw_set_lladdr(ah, iter_data.active_mac); 532 533 if (ath5k_hw_hasbssidmask(ah)) 534 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); 535 536 /* Set up RX Filter */ 537 if (iter_data.n_stas > 1) { 538 /* If you have multiple STA interfaces connected to 539 * different APs, ARPs are not received (most of the time?) 540 * Enabling PROMISC appears to fix that problem. 541 */ 542 ah->filter_flags |= AR5K_RX_FILTER_PROM; 543 } 544 545 rfilt = ah->filter_flags; 546 ath5k_hw_set_rx_filter(ah, rfilt); 547 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 548 } 549 550 static inline int 551 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) 552 { 553 int rix; 554 555 /* return base rate on errors */ 556 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 557 "hw_rix out of bounds: %x\n", hw_rix)) 558 return 0; 559 560 rix = ah->rate_idx[ah->curchan->band][hw_rix]; 561 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 562 rix = 0; 563 564 return rix; 565 } 566 567 /***************\ 568 * Buffers setup * 569 \***************/ 570 571 static 572 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) 573 { 574 struct ath_common *common = ath5k_hw_common(ah); 575 struct sk_buff *skb; 576 577 /* 578 * Allocate buffer with headroom_needed space for the 579 * fake physical layer header at the start. 580 */ 581 skb = ath_rxbuf_alloc(common, 582 common->rx_bufsize, 583 GFP_ATOMIC); 584 585 if (!skb) { 586 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", 587 common->rx_bufsize); 588 return NULL; 589 } 590 591 *skb_addr = dma_map_single(ah->dev, 592 skb->data, common->rx_bufsize, 593 DMA_FROM_DEVICE); 594 595 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { 596 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); 597 dev_kfree_skb(skb); 598 return NULL; 599 } 600 return skb; 601 } 602 603 static int 604 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 605 { 606 struct sk_buff *skb = bf->skb; 607 struct ath5k_desc *ds; 608 int ret; 609 610 if (!skb) { 611 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); 612 if (!skb) 613 return -ENOMEM; 614 bf->skb = skb; 615 } 616 617 /* 618 * Setup descriptors. For receive we always terminate 619 * the descriptor list with a self-linked entry so we'll 620 * not get overrun under high load (as can happen with a 621 * 5212 when ANI processing enables PHY error frames). 622 * 623 * To ensure the last descriptor is self-linked we create 624 * each descriptor as self-linked and add it to the end. As 625 * each additional descriptor is added the previous self-linked 626 * entry is "fixed" naturally. This should be safe even 627 * if DMA is happening. When processing RX interrupts we 628 * never remove/process the last, self-linked, entry on the 629 * descriptor list. This ensures the hardware always has 630 * someplace to write a new frame. 631 */ 632 ds = bf->desc; 633 ds->ds_link = bf->daddr; /* link to self */ 634 ds->ds_data = bf->skbaddr; 635 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 636 if (ret) { 637 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); 638 return ret; 639 } 640 641 if (ah->rxlink != NULL) 642 *ah->rxlink = bf->daddr; 643 ah->rxlink = &ds->ds_link; 644 return 0; 645 } 646 647 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 648 { 649 struct ieee80211_hdr *hdr; 650 enum ath5k_pkt_type htype; 651 __le16 fc; 652 653 hdr = (struct ieee80211_hdr *)skb->data; 654 fc = hdr->frame_control; 655 656 if (ieee80211_is_beacon(fc)) 657 htype = AR5K_PKT_TYPE_BEACON; 658 else if (ieee80211_is_probe_resp(fc)) 659 htype = AR5K_PKT_TYPE_PROBE_RESP; 660 else if (ieee80211_is_atim(fc)) 661 htype = AR5K_PKT_TYPE_ATIM; 662 else if (ieee80211_is_pspoll(fc)) 663 htype = AR5K_PKT_TYPE_PSPOLL; 664 else 665 htype = AR5K_PKT_TYPE_NORMAL; 666 667 return htype; 668 } 669 670 static struct ieee80211_rate * 671 ath5k_get_rate(const struct ieee80211_hw *hw, 672 const struct ieee80211_tx_info *info, 673 struct ath5k_buf *bf, int idx) 674 { 675 /* 676 * convert a ieee80211_tx_rate RC-table entry to 677 * the respective ieee80211_rate struct 678 */ 679 if (bf->rates[idx].idx < 0) { 680 return NULL; 681 } 682 683 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ]; 684 } 685 686 static u16 687 ath5k_get_rate_hw_value(const struct ieee80211_hw *hw, 688 const struct ieee80211_tx_info *info, 689 struct ath5k_buf *bf, int idx) 690 { 691 struct ieee80211_rate *rate; 692 u16 hw_rate; 693 u8 rc_flags; 694 695 rate = ath5k_get_rate(hw, info, bf, idx); 696 if (!rate) 697 return 0; 698 699 rc_flags = bf->rates[idx].flags; 700 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 701 rate->hw_value_short : rate->hw_value; 702 703 return hw_rate; 704 } 705 706 static int 707 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, 708 struct ath5k_txq *txq, int padsize, 709 struct ieee80211_tx_control *control) 710 { 711 struct ath5k_desc *ds = bf->desc; 712 struct sk_buff *skb = bf->skb; 713 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 714 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 715 struct ieee80211_rate *rate; 716 unsigned int mrr_rate[3], mrr_tries[3]; 717 int i, ret; 718 u16 hw_rate; 719 u16 cts_rate = 0; 720 u16 duration = 0; 721 u8 rc_flags; 722 723 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 724 725 /* XXX endianness */ 726 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 727 DMA_TO_DEVICE); 728 729 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates, 730 ARRAY_SIZE(bf->rates)); 731 732 rate = ath5k_get_rate(ah->hw, info, bf, 0); 733 734 if (!rate) { 735 ret = -EINVAL; 736 goto err_unmap; 737 } 738 739 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 740 flags |= AR5K_TXDESC_NOACK; 741 742 rc_flags = info->control.rates[0].flags; 743 744 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); 745 746 pktlen = skb->len; 747 748 /* FIXME: If we are in g mode and rate is a CCK rate 749 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 750 * from tx power (value is in dB units already) */ 751 if (info->control.hw_key) { 752 keyidx = info->control.hw_key->hw_key_idx; 753 pktlen += info->control.hw_key->icv_len; 754 } 755 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 756 flags |= AR5K_TXDESC_RTSENA; 757 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 758 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, 759 info->control.vif, pktlen, info)); 760 } 761 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 762 flags |= AR5K_TXDESC_CTSENA; 763 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 764 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, 765 info->control.vif, pktlen, info)); 766 } 767 768 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 769 ieee80211_get_hdrlen_from_skb(skb), padsize, 770 get_hw_packet_type(skb), 771 (ah->ah_txpower.txp_requested * 2), 772 hw_rate, 773 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, 774 cts_rate, duration); 775 if (ret) 776 goto err_unmap; 777 778 /* Set up MRR descriptor */ 779 if (ah->ah_capabilities.cap_has_mrr_support) { 780 memset(mrr_rate, 0, sizeof(mrr_rate)); 781 memset(mrr_tries, 0, sizeof(mrr_tries)); 782 783 for (i = 0; i < 3; i++) { 784 785 rate = ath5k_get_rate(ah->hw, info, bf, i); 786 if (!rate) 787 break; 788 789 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); 790 mrr_tries[i] = bf->rates[i].count; 791 } 792 793 ath5k_hw_setup_mrr_tx_desc(ah, ds, 794 mrr_rate[0], mrr_tries[0], 795 mrr_rate[1], mrr_tries[1], 796 mrr_rate[2], mrr_tries[2]); 797 } 798 799 ds->ds_link = 0; 800 ds->ds_data = bf->skbaddr; 801 802 spin_lock_bh(&txq->lock); 803 list_add_tail(&bf->list, &txq->q); 804 txq->txq_len++; 805 if (txq->link == NULL) /* is this first packet? */ 806 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 807 else /* no, so only link it */ 808 *txq->link = bf->daddr; 809 810 txq->link = &ds->ds_link; 811 ath5k_hw_start_tx_dma(ah, txq->qnum); 812 mmiowb(); 813 spin_unlock_bh(&txq->lock); 814 815 return 0; 816 err_unmap: 817 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 818 return ret; 819 } 820 821 /*******************\ 822 * Descriptors setup * 823 \*******************/ 824 825 static int 826 ath5k_desc_alloc(struct ath5k_hw *ah) 827 { 828 struct ath5k_desc *ds; 829 struct ath5k_buf *bf; 830 dma_addr_t da; 831 unsigned int i; 832 int ret; 833 834 /* allocate descriptors */ 835 ah->desc_len = sizeof(struct ath5k_desc) * 836 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 837 838 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, 839 &ah->desc_daddr, GFP_KERNEL); 840 if (ah->desc == NULL) { 841 ATH5K_ERR(ah, "can't allocate descriptors\n"); 842 ret = -ENOMEM; 843 goto err; 844 } 845 ds = ah->desc; 846 da = ah->desc_daddr; 847 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 848 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); 849 850 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 851 sizeof(struct ath5k_buf), GFP_KERNEL); 852 if (bf == NULL) { 853 ATH5K_ERR(ah, "can't allocate bufptr\n"); 854 ret = -ENOMEM; 855 goto err_free; 856 } 857 ah->bufptr = bf; 858 859 INIT_LIST_HEAD(&ah->rxbuf); 860 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 861 bf->desc = ds; 862 bf->daddr = da; 863 list_add_tail(&bf->list, &ah->rxbuf); 864 } 865 866 INIT_LIST_HEAD(&ah->txbuf); 867 ah->txbuf_len = ATH_TXBUF; 868 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 869 bf->desc = ds; 870 bf->daddr = da; 871 list_add_tail(&bf->list, &ah->txbuf); 872 } 873 874 /* beacon buffers */ 875 INIT_LIST_HEAD(&ah->bcbuf); 876 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 877 bf->desc = ds; 878 bf->daddr = da; 879 list_add_tail(&bf->list, &ah->bcbuf); 880 } 881 882 return 0; 883 err_free: 884 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 885 err: 886 ah->desc = NULL; 887 return ret; 888 } 889 890 void 891 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 892 { 893 BUG_ON(!bf); 894 if (!bf->skb) 895 return; 896 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, 897 DMA_TO_DEVICE); 898 ieee80211_free_txskb(ah->hw, bf->skb); 899 bf->skb = NULL; 900 bf->skbaddr = 0; 901 bf->desc->ds_data = 0; 902 } 903 904 void 905 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 906 { 907 struct ath_common *common = ath5k_hw_common(ah); 908 909 BUG_ON(!bf); 910 if (!bf->skb) 911 return; 912 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, 913 DMA_FROM_DEVICE); 914 dev_kfree_skb_any(bf->skb); 915 bf->skb = NULL; 916 bf->skbaddr = 0; 917 bf->desc->ds_data = 0; 918 } 919 920 static void 921 ath5k_desc_free(struct ath5k_hw *ah) 922 { 923 struct ath5k_buf *bf; 924 925 list_for_each_entry(bf, &ah->txbuf, list) 926 ath5k_txbuf_free_skb(ah, bf); 927 list_for_each_entry(bf, &ah->rxbuf, list) 928 ath5k_rxbuf_free_skb(ah, bf); 929 list_for_each_entry(bf, &ah->bcbuf, list) 930 ath5k_txbuf_free_skb(ah, bf); 931 932 /* Free memory associated with all descriptors */ 933 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 934 ah->desc = NULL; 935 ah->desc_daddr = 0; 936 937 kfree(ah->bufptr); 938 ah->bufptr = NULL; 939 } 940 941 942 /**************\ 943 * Queues setup * 944 \**************/ 945 946 static struct ath5k_txq * 947 ath5k_txq_setup(struct ath5k_hw *ah, 948 int qtype, int subtype) 949 { 950 struct ath5k_txq *txq; 951 struct ath5k_txq_info qi = { 952 .tqi_subtype = subtype, 953 /* XXX: default values not correct for B and XR channels, 954 * but who cares? */ 955 .tqi_aifs = AR5K_TUNE_AIFS, 956 .tqi_cw_min = AR5K_TUNE_CWMIN, 957 .tqi_cw_max = AR5K_TUNE_CWMAX 958 }; 959 int qnum; 960 961 /* 962 * Enable interrupts only for EOL and DESC conditions. 963 * We mark tx descriptors to receive a DESC interrupt 964 * when a tx queue gets deep; otherwise we wait for the 965 * EOL to reap descriptors. Note that this is done to 966 * reduce interrupt load and this only defers reaping 967 * descriptors, never transmitting frames. Aside from 968 * reducing interrupts this also permits more concurrency. 969 * The only potential downside is if the tx queue backs 970 * up in which case the top half of the kernel may backup 971 * due to a lack of tx descriptors. 972 */ 973 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 974 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 975 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 976 if (qnum < 0) { 977 /* 978 * NB: don't print a message, this happens 979 * normally on parts with too few tx queues 980 */ 981 return ERR_PTR(qnum); 982 } 983 txq = &ah->txqs[qnum]; 984 if (!txq->setup) { 985 txq->qnum = qnum; 986 txq->link = NULL; 987 INIT_LIST_HEAD(&txq->q); 988 spin_lock_init(&txq->lock); 989 txq->setup = true; 990 txq->txq_len = 0; 991 txq->txq_max = ATH5K_TXQ_LEN_MAX; 992 txq->txq_poll_mark = false; 993 txq->txq_stuck = 0; 994 } 995 return &ah->txqs[qnum]; 996 } 997 998 static int 999 ath5k_beaconq_setup(struct ath5k_hw *ah) 1000 { 1001 struct ath5k_txq_info qi = { 1002 /* XXX: default values not correct for B and XR channels, 1003 * but who cares? */ 1004 .tqi_aifs = AR5K_TUNE_AIFS, 1005 .tqi_cw_min = AR5K_TUNE_CWMIN, 1006 .tqi_cw_max = AR5K_TUNE_CWMAX, 1007 /* NB: for dynamic turbo, don't enable any other interrupts */ 1008 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1009 }; 1010 1011 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1012 } 1013 1014 static int 1015 ath5k_beaconq_config(struct ath5k_hw *ah) 1016 { 1017 struct ath5k_txq_info qi; 1018 int ret; 1019 1020 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); 1021 if (ret) 1022 goto err; 1023 1024 if (ah->opmode == NL80211_IFTYPE_AP || 1025 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1026 /* 1027 * Always burst out beacon and CAB traffic 1028 * (aifs = cwmin = cwmax = 0) 1029 */ 1030 qi.tqi_aifs = 0; 1031 qi.tqi_cw_min = 0; 1032 qi.tqi_cw_max = 0; 1033 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { 1034 /* 1035 * Adhoc mode; backoff between 0 and (2 * cw_min). 1036 */ 1037 qi.tqi_aifs = 0; 1038 qi.tqi_cw_min = 0; 1039 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 1040 } 1041 1042 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1043 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1044 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1045 1046 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); 1047 if (ret) { 1048 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " 1049 "hardware queue!\n", __func__); 1050 goto err; 1051 } 1052 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ 1053 if (ret) 1054 goto err; 1055 1056 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1057 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1058 if (ret) 1059 goto err; 1060 1061 qi.tqi_ready_time = (ah->bintval * 80) / 100; 1062 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1063 if (ret) 1064 goto err; 1065 1066 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1067 err: 1068 return ret; 1069 } 1070 1071 /** 1072 * ath5k_drain_tx_buffs - Empty tx buffers 1073 * 1074 * @ah The &struct ath5k_hw 1075 * 1076 * Empty tx buffers from all queues in preparation 1077 * of a reset or during shutdown. 1078 * 1079 * NB: this assumes output has been stopped and 1080 * we do not need to block ath5k_tx_tasklet 1081 */ 1082 static void 1083 ath5k_drain_tx_buffs(struct ath5k_hw *ah) 1084 { 1085 struct ath5k_txq *txq; 1086 struct ath5k_buf *bf, *bf0; 1087 int i; 1088 1089 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 1090 if (ah->txqs[i].setup) { 1091 txq = &ah->txqs[i]; 1092 spin_lock_bh(&txq->lock); 1093 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1094 ath5k_debug_printtxbuf(ah, bf); 1095 1096 ath5k_txbuf_free_skb(ah, bf); 1097 1098 spin_lock(&ah->txbuflock); 1099 list_move_tail(&bf->list, &ah->txbuf); 1100 ah->txbuf_len++; 1101 txq->txq_len--; 1102 spin_unlock(&ah->txbuflock); 1103 } 1104 txq->link = NULL; 1105 txq->txq_poll_mark = false; 1106 spin_unlock_bh(&txq->lock); 1107 } 1108 } 1109 } 1110 1111 static void 1112 ath5k_txq_release(struct ath5k_hw *ah) 1113 { 1114 struct ath5k_txq *txq = ah->txqs; 1115 unsigned int i; 1116 1117 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) 1118 if (txq->setup) { 1119 ath5k_hw_release_tx_queue(ah, txq->qnum); 1120 txq->setup = false; 1121 } 1122 } 1123 1124 1125 /*************\ 1126 * RX Handling * 1127 \*************/ 1128 1129 /* 1130 * Enable the receive h/w following a reset. 1131 */ 1132 static int 1133 ath5k_rx_start(struct ath5k_hw *ah) 1134 { 1135 struct ath_common *common = ath5k_hw_common(ah); 1136 struct ath5k_buf *bf; 1137 int ret; 1138 1139 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1140 1141 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1142 common->cachelsz, common->rx_bufsize); 1143 1144 spin_lock_bh(&ah->rxbuflock); 1145 ah->rxlink = NULL; 1146 list_for_each_entry(bf, &ah->rxbuf, list) { 1147 ret = ath5k_rxbuf_setup(ah, bf); 1148 if (ret != 0) { 1149 spin_unlock_bh(&ah->rxbuflock); 1150 goto err; 1151 } 1152 } 1153 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1154 ath5k_hw_set_rxdp(ah, bf->daddr); 1155 spin_unlock_bh(&ah->rxbuflock); 1156 1157 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1158 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ 1159 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1160 1161 return 0; 1162 err: 1163 return ret; 1164 } 1165 1166 /* 1167 * Disable the receive logic on PCU (DRU) 1168 * In preparation for a shutdown. 1169 * 1170 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1171 * does. 1172 */ 1173 static void 1174 ath5k_rx_stop(struct ath5k_hw *ah) 1175 { 1176 1177 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1178 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1179 1180 ath5k_debug_printrxbuffs(ah); 1181 } 1182 1183 static unsigned int 1184 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, 1185 struct ath5k_rx_status *rs) 1186 { 1187 struct ath_common *common = ath5k_hw_common(ah); 1188 struct ieee80211_hdr *hdr = (void *)skb->data; 1189 unsigned int keyix, hlen; 1190 1191 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1192 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1193 return RX_FLAG_DECRYPTED; 1194 1195 /* Apparently when a default key is used to decrypt the packet 1196 the hw does not set the index used to decrypt. In such cases 1197 get the index from the packet. */ 1198 hlen = ieee80211_hdrlen(hdr->frame_control); 1199 if (ieee80211_has_protected(hdr->frame_control) && 1200 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1201 skb->len >= hlen + 4) { 1202 keyix = skb->data[hlen + 3] >> 6; 1203 1204 if (test_bit(keyix, common->keymap)) 1205 return RX_FLAG_DECRYPTED; 1206 } 1207 1208 return 0; 1209 } 1210 1211 1212 static void 1213 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, 1214 struct ieee80211_rx_status *rxs) 1215 { 1216 struct ath_common *common = ath5k_hw_common(ah); 1217 u64 tsf, bc_tstamp; 1218 u32 hw_tu; 1219 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1220 1221 if (ieee80211_is_beacon(mgmt->frame_control) && 1222 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1223 ether_addr_equal(mgmt->bssid, common->curbssid)) { 1224 /* 1225 * Received an IBSS beacon with the same BSSID. Hardware *must* 1226 * have updated the local TSF. We have to work around various 1227 * hardware bugs, though... 1228 */ 1229 tsf = ath5k_hw_get_tsf64(ah); 1230 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1231 hw_tu = TSF_TO_TU(tsf); 1232 1233 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1234 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1235 (unsigned long long)bc_tstamp, 1236 (unsigned long long)rxs->mactime, 1237 (unsigned long long)(rxs->mactime - bc_tstamp), 1238 (unsigned long long)tsf); 1239 1240 /* 1241 * Sometimes the HW will give us a wrong tstamp in the rx 1242 * status, causing the timestamp extension to go wrong. 1243 * (This seems to happen especially with beacon frames bigger 1244 * than 78 byte (incl. FCS)) 1245 * But we know that the receive timestamp must be later than the 1246 * timestamp of the beacon since HW must have synced to that. 1247 * 1248 * NOTE: here we assume mactime to be after the frame was 1249 * received, not like mac80211 which defines it at the start. 1250 */ 1251 if (bc_tstamp > rxs->mactime) { 1252 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1253 "fixing mactime from %llx to %llx\n", 1254 (unsigned long long)rxs->mactime, 1255 (unsigned long long)tsf); 1256 rxs->mactime = tsf; 1257 } 1258 1259 /* 1260 * Local TSF might have moved higher than our beacon timers, 1261 * in that case we have to update them to continue sending 1262 * beacons. This also takes care of synchronizing beacon sending 1263 * times with other stations. 1264 */ 1265 if (hw_tu >= ah->nexttbtt) 1266 ath5k_beacon_update_timers(ah, bc_tstamp); 1267 1268 /* Check if the beacon timers are still correct, because a TSF 1269 * update might have created a window between them - for a 1270 * longer description see the comment of this function: */ 1271 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { 1272 ath5k_beacon_update_timers(ah, bc_tstamp); 1273 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1274 "fixed beacon timers after beacon receive\n"); 1275 } 1276 } 1277 } 1278 1279 static void 1280 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi) 1281 { 1282 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1283 struct ath_common *common = ath5k_hw_common(ah); 1284 1285 /* only beacons from our BSSID */ 1286 if (!ieee80211_is_beacon(mgmt->frame_control) || 1287 !ether_addr_equal(mgmt->bssid, common->curbssid)) 1288 return; 1289 1290 ewma_add(&ah->ah_beacon_rssi_avg, rssi); 1291 1292 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1293 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1294 } 1295 1296 /* 1297 * Compute padding position. skb must contain an IEEE 802.11 frame 1298 */ 1299 static int ath5k_common_padpos(struct sk_buff *skb) 1300 { 1301 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1302 __le16 frame_control = hdr->frame_control; 1303 int padpos = 24; 1304 1305 if (ieee80211_has_a4(frame_control)) 1306 padpos += ETH_ALEN; 1307 1308 if (ieee80211_is_data_qos(frame_control)) 1309 padpos += IEEE80211_QOS_CTL_LEN; 1310 1311 return padpos; 1312 } 1313 1314 /* 1315 * This function expects an 802.11 frame and returns the number of 1316 * bytes added, or -1 if we don't have enough header room. 1317 */ 1318 static int ath5k_add_padding(struct sk_buff *skb) 1319 { 1320 int padpos = ath5k_common_padpos(skb); 1321 int padsize = padpos & 3; 1322 1323 if (padsize && skb->len > padpos) { 1324 1325 if (skb_headroom(skb) < padsize) 1326 return -1; 1327 1328 skb_push(skb, padsize); 1329 memmove(skb->data, skb->data + padsize, padpos); 1330 return padsize; 1331 } 1332 1333 return 0; 1334 } 1335 1336 /* 1337 * The MAC header is padded to have 32-bit boundary if the 1338 * packet payload is non-zero. The general calculation for 1339 * padsize would take into account odd header lengths: 1340 * padsize = 4 - (hdrlen & 3); however, since only 1341 * even-length headers are used, padding can only be 0 or 2 1342 * bytes and we can optimize this a bit. We must not try to 1343 * remove padding from short control frames that do not have a 1344 * payload. 1345 * 1346 * This function expects an 802.11 frame and returns the number of 1347 * bytes removed. 1348 */ 1349 static int ath5k_remove_padding(struct sk_buff *skb) 1350 { 1351 int padpos = ath5k_common_padpos(skb); 1352 int padsize = padpos & 3; 1353 1354 if (padsize && skb->len >= padpos + padsize) { 1355 memmove(skb->data + padsize, skb->data, padpos); 1356 skb_pull(skb, padsize); 1357 return padsize; 1358 } 1359 1360 return 0; 1361 } 1362 1363 static void 1364 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, 1365 struct ath5k_rx_status *rs) 1366 { 1367 struct ieee80211_rx_status *rxs; 1368 1369 ath5k_remove_padding(skb); 1370 1371 rxs = IEEE80211_SKB_RXCB(skb); 1372 1373 rxs->flag = 0; 1374 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1375 rxs->flag |= RX_FLAG_MMIC_ERROR; 1376 1377 /* 1378 * always extend the mac timestamp, since this information is 1379 * also needed for proper IBSS merging. 1380 * 1381 * XXX: it might be too late to do it here, since rs_tstamp is 1382 * 15bit only. that means TSF extension has to be done within 1383 * 32768usec (about 32ms). it might be necessary to move this to 1384 * the interrupt handler, like it is done in madwifi. 1385 */ 1386 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); 1387 rxs->flag |= RX_FLAG_MACTIME_END; 1388 1389 rxs->freq = ah->curchan->center_freq; 1390 rxs->band = ah->curchan->band; 1391 1392 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; 1393 1394 rxs->antenna = rs->rs_antenna; 1395 1396 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1397 ah->stats.antenna_rx[rs->rs_antenna]++; 1398 else 1399 ah->stats.antenna_rx[0]++; /* invalid */ 1400 1401 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); 1402 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); 1403 1404 if (rxs->rate_idx >= 0 && rs->rs_rate == 1405 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1406 rxs->flag |= RX_FLAG_SHORTPRE; 1407 1408 trace_ath5k_rx(ah, skb); 1409 1410 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi); 1411 1412 /* check beacons in IBSS mode */ 1413 if (ah->opmode == NL80211_IFTYPE_ADHOC) 1414 ath5k_check_ibss_tsf(ah, skb, rxs); 1415 1416 ieee80211_rx(ah->hw, skb); 1417 } 1418 1419 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1420 * 1421 * Check if we want to further process this frame or not. Also update 1422 * statistics. Return true if we want this frame, false if not. 1423 */ 1424 static bool 1425 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) 1426 { 1427 ah->stats.rx_all_count++; 1428 ah->stats.rx_bytes_count += rs->rs_datalen; 1429 1430 if (unlikely(rs->rs_status)) { 1431 if (rs->rs_status & AR5K_RXERR_CRC) 1432 ah->stats.rxerr_crc++; 1433 if (rs->rs_status & AR5K_RXERR_FIFO) 1434 ah->stats.rxerr_fifo++; 1435 if (rs->rs_status & AR5K_RXERR_PHY) { 1436 ah->stats.rxerr_phy++; 1437 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1438 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; 1439 return false; 1440 } 1441 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1442 /* 1443 * Decrypt error. If the error occurred 1444 * because there was no hardware key, then 1445 * let the frame through so the upper layers 1446 * can process it. This is necessary for 5210 1447 * parts which have no way to setup a ``clear'' 1448 * key cache entry. 1449 * 1450 * XXX do key cache faulting 1451 */ 1452 ah->stats.rxerr_decrypt++; 1453 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1454 !(rs->rs_status & AR5K_RXERR_CRC)) 1455 return true; 1456 } 1457 if (rs->rs_status & AR5K_RXERR_MIC) { 1458 ah->stats.rxerr_mic++; 1459 return true; 1460 } 1461 1462 /* reject any frames with non-crypto errors */ 1463 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1464 return false; 1465 } 1466 1467 if (unlikely(rs->rs_more)) { 1468 ah->stats.rxerr_jumbo++; 1469 return false; 1470 } 1471 return true; 1472 } 1473 1474 static void 1475 ath5k_set_current_imask(struct ath5k_hw *ah) 1476 { 1477 enum ath5k_int imask; 1478 unsigned long flags; 1479 1480 spin_lock_irqsave(&ah->irqlock, flags); 1481 imask = ah->imask; 1482 if (ah->rx_pending) 1483 imask &= ~AR5K_INT_RX_ALL; 1484 if (ah->tx_pending) 1485 imask &= ~AR5K_INT_TX_ALL; 1486 ath5k_hw_set_imr(ah, imask); 1487 spin_unlock_irqrestore(&ah->irqlock, flags); 1488 } 1489 1490 static void 1491 ath5k_tasklet_rx(unsigned long data) 1492 { 1493 struct ath5k_rx_status rs = {}; 1494 struct sk_buff *skb, *next_skb; 1495 dma_addr_t next_skb_addr; 1496 struct ath5k_hw *ah = (void *)data; 1497 struct ath_common *common = ath5k_hw_common(ah); 1498 struct ath5k_buf *bf; 1499 struct ath5k_desc *ds; 1500 int ret; 1501 1502 spin_lock(&ah->rxbuflock); 1503 if (list_empty(&ah->rxbuf)) { 1504 ATH5K_WARN(ah, "empty rx buf pool\n"); 1505 goto unlock; 1506 } 1507 do { 1508 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1509 BUG_ON(bf->skb == NULL); 1510 skb = bf->skb; 1511 ds = bf->desc; 1512 1513 /* bail if HW is still using self-linked descriptor */ 1514 if (ath5k_hw_get_rxdp(ah) == bf->daddr) 1515 break; 1516 1517 ret = ah->ah_proc_rx_desc(ah, ds, &rs); 1518 if (unlikely(ret == -EINPROGRESS)) 1519 break; 1520 else if (unlikely(ret)) { 1521 ATH5K_ERR(ah, "error in processing rx descriptor\n"); 1522 ah->stats.rxerr_proc++; 1523 break; 1524 } 1525 1526 if (ath5k_receive_frame_ok(ah, &rs)) { 1527 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); 1528 1529 /* 1530 * If we can't replace bf->skb with a new skb under 1531 * memory pressure, just skip this packet 1532 */ 1533 if (!next_skb) 1534 goto next; 1535 1536 dma_unmap_single(ah->dev, bf->skbaddr, 1537 common->rx_bufsize, 1538 DMA_FROM_DEVICE); 1539 1540 skb_put(skb, rs.rs_datalen); 1541 1542 ath5k_receive_frame(ah, skb, &rs); 1543 1544 bf->skb = next_skb; 1545 bf->skbaddr = next_skb_addr; 1546 } 1547 next: 1548 list_move_tail(&bf->list, &ah->rxbuf); 1549 } while (ath5k_rxbuf_setup(ah, bf) == 0); 1550 unlock: 1551 spin_unlock(&ah->rxbuflock); 1552 ah->rx_pending = false; 1553 ath5k_set_current_imask(ah); 1554 } 1555 1556 1557 /*************\ 1558 * TX Handling * 1559 \*************/ 1560 1561 void 1562 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1563 struct ath5k_txq *txq, struct ieee80211_tx_control *control) 1564 { 1565 struct ath5k_hw *ah = hw->priv; 1566 struct ath5k_buf *bf; 1567 unsigned long flags; 1568 int padsize; 1569 1570 trace_ath5k_tx(ah, skb, txq); 1571 1572 /* 1573 * The hardware expects the header padded to 4 byte boundaries. 1574 * If this is not the case, we add the padding after the header. 1575 */ 1576 padsize = ath5k_add_padding(skb); 1577 if (padsize < 0) { 1578 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" 1579 " headroom to pad"); 1580 goto drop_packet; 1581 } 1582 1583 if (txq->txq_len >= txq->txq_max && 1584 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1585 ieee80211_stop_queue(hw, txq->qnum); 1586 1587 spin_lock_irqsave(&ah->txbuflock, flags); 1588 if (list_empty(&ah->txbuf)) { 1589 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); 1590 spin_unlock_irqrestore(&ah->txbuflock, flags); 1591 ieee80211_stop_queues(hw); 1592 goto drop_packet; 1593 } 1594 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); 1595 list_del(&bf->list); 1596 ah->txbuf_len--; 1597 if (list_empty(&ah->txbuf)) 1598 ieee80211_stop_queues(hw); 1599 spin_unlock_irqrestore(&ah->txbuflock, flags); 1600 1601 bf->skb = skb; 1602 1603 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { 1604 bf->skb = NULL; 1605 spin_lock_irqsave(&ah->txbuflock, flags); 1606 list_add_tail(&bf->list, &ah->txbuf); 1607 ah->txbuf_len++; 1608 spin_unlock_irqrestore(&ah->txbuflock, flags); 1609 goto drop_packet; 1610 } 1611 return; 1612 1613 drop_packet: 1614 ieee80211_free_txskb(hw, skb); 1615 } 1616 1617 static void 1618 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, 1619 struct ath5k_txq *txq, struct ath5k_tx_status *ts, 1620 struct ath5k_buf *bf) 1621 { 1622 struct ieee80211_tx_info *info; 1623 u8 tries[3]; 1624 int i; 1625 int size = 0; 1626 1627 ah->stats.tx_all_count++; 1628 ah->stats.tx_bytes_count += skb->len; 1629 info = IEEE80211_SKB_CB(skb); 1630 1631 tries[0] = info->status.rates[0].count; 1632 tries[1] = info->status.rates[1].count; 1633 tries[2] = info->status.rates[2].count; 1634 1635 ieee80211_tx_info_clear_status(info); 1636 1637 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates)); 1638 memcpy(info->status.rates, bf->rates, size); 1639 1640 for (i = 0; i < ts->ts_final_idx; i++) { 1641 struct ieee80211_tx_rate *r = 1642 &info->status.rates[i]; 1643 1644 r->count = tries[i]; 1645 } 1646 1647 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1648 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1649 1650 if (unlikely(ts->ts_status)) { 1651 ah->stats.ack_fail++; 1652 if (ts->ts_status & AR5K_TXERR_FILT) { 1653 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1654 ah->stats.txerr_filt++; 1655 } 1656 if (ts->ts_status & AR5K_TXERR_XRETRY) 1657 ah->stats.txerr_retry++; 1658 if (ts->ts_status & AR5K_TXERR_FIFO) 1659 ah->stats.txerr_fifo++; 1660 } else { 1661 info->flags |= IEEE80211_TX_STAT_ACK; 1662 info->status.ack_signal = ts->ts_rssi; 1663 1664 /* count the successful attempt as well */ 1665 info->status.rates[ts->ts_final_idx].count++; 1666 } 1667 1668 /* 1669 * Remove MAC header padding before giving the frame 1670 * back to mac80211. 1671 */ 1672 ath5k_remove_padding(skb); 1673 1674 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1675 ah->stats.antenna_tx[ts->ts_antenna]++; 1676 else 1677 ah->stats.antenna_tx[0]++; /* invalid */ 1678 1679 trace_ath5k_tx_complete(ah, skb, txq, ts); 1680 ieee80211_tx_status(ah->hw, skb); 1681 } 1682 1683 static void 1684 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) 1685 { 1686 struct ath5k_tx_status ts = {}; 1687 struct ath5k_buf *bf, *bf0; 1688 struct ath5k_desc *ds; 1689 struct sk_buff *skb; 1690 int ret; 1691 1692 spin_lock(&txq->lock); 1693 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1694 1695 txq->txq_poll_mark = false; 1696 1697 /* skb might already have been processed last time. */ 1698 if (bf->skb != NULL) { 1699 ds = bf->desc; 1700 1701 ret = ah->ah_proc_tx_desc(ah, ds, &ts); 1702 if (unlikely(ret == -EINPROGRESS)) 1703 break; 1704 else if (unlikely(ret)) { 1705 ATH5K_ERR(ah, 1706 "error %d while processing " 1707 "queue %u\n", ret, txq->qnum); 1708 break; 1709 } 1710 1711 skb = bf->skb; 1712 bf->skb = NULL; 1713 1714 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, 1715 DMA_TO_DEVICE); 1716 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); 1717 } 1718 1719 /* 1720 * It's possible that the hardware can say the buffer is 1721 * completed when it hasn't yet loaded the ds_link from 1722 * host memory and moved on. 1723 * Always keep the last descriptor to avoid HW races... 1724 */ 1725 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { 1726 spin_lock(&ah->txbuflock); 1727 list_move_tail(&bf->list, &ah->txbuf); 1728 ah->txbuf_len++; 1729 txq->txq_len--; 1730 spin_unlock(&ah->txbuflock); 1731 } 1732 } 1733 spin_unlock(&txq->lock); 1734 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1735 ieee80211_wake_queue(ah->hw, txq->qnum); 1736 } 1737 1738 static void 1739 ath5k_tasklet_tx(unsigned long data) 1740 { 1741 int i; 1742 struct ath5k_hw *ah = (void *)data; 1743 1744 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1745 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) 1746 ath5k_tx_processq(ah, &ah->txqs[i]); 1747 1748 ah->tx_pending = false; 1749 ath5k_set_current_imask(ah); 1750 } 1751 1752 1753 /*****************\ 1754 * Beacon handling * 1755 \*****************/ 1756 1757 /* 1758 * Setup the beacon frame for transmit. 1759 */ 1760 static int 1761 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 1762 { 1763 struct sk_buff *skb = bf->skb; 1764 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1765 struct ath5k_desc *ds; 1766 int ret = 0; 1767 u8 antenna; 1768 u32 flags; 1769 const int padsize = 0; 1770 1771 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 1772 DMA_TO_DEVICE); 1773 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1774 "skbaddr %llx\n", skb, skb->data, skb->len, 1775 (unsigned long long)bf->skbaddr); 1776 1777 if (dma_mapping_error(ah->dev, bf->skbaddr)) { 1778 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); 1779 dev_kfree_skb_any(skb); 1780 bf->skb = NULL; 1781 return -EIO; 1782 } 1783 1784 ds = bf->desc; 1785 antenna = ah->ah_tx_ant; 1786 1787 flags = AR5K_TXDESC_NOACK; 1788 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1789 ds->ds_link = bf->daddr; /* self-linked */ 1790 flags |= AR5K_TXDESC_VEOL; 1791 } else 1792 ds->ds_link = 0; 1793 1794 /* 1795 * If we use multiple antennas on AP and use 1796 * the Sectored AP scenario, switch antenna every 1797 * 4 beacons to make sure everybody hears our AP. 1798 * When a client tries to associate, hw will keep 1799 * track of the tx antenna to be used for this client 1800 * automatically, based on ACKed packets. 1801 * 1802 * Note: AP still listens and transmits RTS on the 1803 * default antenna which is supposed to be an omni. 1804 * 1805 * Note2: On sectored scenarios it's possible to have 1806 * multiple antennas (1 omni -- the default -- and 14 1807 * sectors), so if we choose to actually support this 1808 * mode, we need to allow the user to set how many antennas 1809 * we have and tweak the code below to send beacons 1810 * on all of them. 1811 */ 1812 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1813 antenna = ah->bsent & 4 ? 2 : 1; 1814 1815 1816 /* FIXME: If we are in g mode and rate is a CCK rate 1817 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1818 * from tx power (value is in dB units already) */ 1819 ds->ds_data = bf->skbaddr; 1820 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1821 ieee80211_get_hdrlen_from_skb(skb), padsize, 1822 AR5K_PKT_TYPE_BEACON, 1823 (ah->ah_txpower.txp_requested * 2), 1824 ieee80211_get_tx_rate(ah->hw, info)->hw_value, 1825 1, AR5K_TXKEYIX_INVALID, 1826 antenna, flags, 0, 0); 1827 if (ret) 1828 goto err_unmap; 1829 1830 return 0; 1831 err_unmap: 1832 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1833 return ret; 1834 } 1835 1836 /* 1837 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1838 * this is called only once at config_bss time, for AP we do it every 1839 * SWBA interrupt so that the TIM will reflect buffered frames. 1840 * 1841 * Called with the beacon lock. 1842 */ 1843 int 1844 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1845 { 1846 int ret; 1847 struct ath5k_hw *ah = hw->priv; 1848 struct ath5k_vif *avf; 1849 struct sk_buff *skb; 1850 1851 if (WARN_ON(!vif)) { 1852 ret = -EINVAL; 1853 goto out; 1854 } 1855 1856 skb = ieee80211_beacon_get(hw, vif); 1857 1858 if (!skb) { 1859 ret = -ENOMEM; 1860 goto out; 1861 } 1862 1863 avf = (void *)vif->drv_priv; 1864 ath5k_txbuf_free_skb(ah, avf->bbuf); 1865 avf->bbuf->skb = skb; 1866 ret = ath5k_beacon_setup(ah, avf->bbuf); 1867 out: 1868 return ret; 1869 } 1870 1871 /* 1872 * Transmit a beacon frame at SWBA. Dynamic updates to the 1873 * frame contents are done as needed and the slot time is 1874 * also adjusted based on current state. 1875 * 1876 * This is called from software irq context (beacontq tasklets) 1877 * or user context from ath5k_beacon_config. 1878 */ 1879 static void 1880 ath5k_beacon_send(struct ath5k_hw *ah) 1881 { 1882 struct ieee80211_vif *vif; 1883 struct ath5k_vif *avf; 1884 struct ath5k_buf *bf; 1885 struct sk_buff *skb; 1886 int err; 1887 1888 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1889 1890 /* 1891 * Check if the previous beacon has gone out. If 1892 * not, don't don't try to post another: skip this 1893 * period and wait for the next. Missed beacons 1894 * indicate a problem and should not occur. If we 1895 * miss too many consecutive beacons reset the device. 1896 */ 1897 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { 1898 ah->bmisscount++; 1899 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1900 "missed %u consecutive beacons\n", ah->bmisscount); 1901 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ 1902 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1903 "stuck beacon time (%u missed)\n", 1904 ah->bmisscount); 1905 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 1906 "stuck beacon, resetting\n"); 1907 ieee80211_queue_work(ah->hw, &ah->reset_work); 1908 } 1909 return; 1910 } 1911 if (unlikely(ah->bmisscount != 0)) { 1912 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1913 "resume beacon xmit after %u misses\n", 1914 ah->bmisscount); 1915 ah->bmisscount = 0; 1916 } 1917 1918 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + 1919 ah->num_mesh_vifs > 1) || 1920 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1921 u64 tsf = ath5k_hw_get_tsf64(ah); 1922 u32 tsftu = TSF_TO_TU(tsf); 1923 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; 1924 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; 1925 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1926 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1927 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); 1928 } else /* only one interface */ 1929 vif = ah->bslot[0]; 1930 1931 if (!vif) 1932 return; 1933 1934 avf = (void *)vif->drv_priv; 1935 bf = avf->bbuf; 1936 1937 /* 1938 * Stop any current dma and put the new frame on the queue. 1939 * This should never fail since we check above that no frames 1940 * are still pending on the queue. 1941 */ 1942 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { 1943 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); 1944 /* NB: hw still stops DMA, so proceed */ 1945 } 1946 1947 /* refresh the beacon for AP or MESH mode */ 1948 if (ah->opmode == NL80211_IFTYPE_AP || 1949 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1950 err = ath5k_beacon_update(ah->hw, vif); 1951 if (err) 1952 return; 1953 } 1954 1955 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || 1956 ah->opmode == NL80211_IFTYPE_MONITOR)) { 1957 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); 1958 return; 1959 } 1960 1961 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); 1962 1963 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); 1964 ath5k_hw_start_tx_dma(ah, ah->bhalq); 1965 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1966 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); 1967 1968 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1969 while (skb) { 1970 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); 1971 1972 if (ah->cabq->txq_len >= ah->cabq->txq_max) 1973 break; 1974 1975 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1976 } 1977 1978 ah->bsent++; 1979 } 1980 1981 /** 1982 * ath5k_beacon_update_timers - update beacon timers 1983 * 1984 * @ah: struct ath5k_hw pointer we are operating on 1985 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1986 * beacon timer update based on the current HW TSF. 1987 * 1988 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 1989 * of a received beacon or the current local hardware TSF and write it to the 1990 * beacon timer registers. 1991 * 1992 * This is called in a variety of situations, e.g. when a beacon is received, 1993 * when a TSF update has been detected, but also when an new IBSS is created or 1994 * when we otherwise know we have to update the timers, but we keep it in this 1995 * function to have it all together in one place. 1996 */ 1997 void 1998 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) 1999 { 2000 u32 nexttbtt, intval, hw_tu, bc_tu; 2001 u64 hw_tsf; 2002 2003 intval = ah->bintval & AR5K_BEACON_PERIOD; 2004 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs 2005 + ah->num_mesh_vifs > 1) { 2006 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 2007 if (intval < 15) 2008 ATH5K_WARN(ah, "intval %u is too low, min 15\n", 2009 intval); 2010 } 2011 if (WARN_ON(!intval)) 2012 return; 2013 2014 /* beacon TSF converted to TU */ 2015 bc_tu = TSF_TO_TU(bc_tsf); 2016 2017 /* current TSF converted to TU */ 2018 hw_tsf = ath5k_hw_get_tsf64(ah); 2019 hw_tu = TSF_TO_TU(hw_tsf); 2020 2021 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 2022 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 2023 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 2024 * configuration we need to make sure it is bigger than that. */ 2025 2026 if (bc_tsf == -1) { 2027 /* 2028 * no beacons received, called internally. 2029 * just need to refresh timers based on HW TSF. 2030 */ 2031 nexttbtt = roundup(hw_tu + FUDGE, intval); 2032 } else if (bc_tsf == 0) { 2033 /* 2034 * no beacon received, probably called by ath5k_reset_tsf(). 2035 * reset TSF to start with 0. 2036 */ 2037 nexttbtt = intval; 2038 intval |= AR5K_BEACON_RESET_TSF; 2039 } else if (bc_tsf > hw_tsf) { 2040 /* 2041 * beacon received, SW merge happened but HW TSF not yet updated. 2042 * not possible to reconfigure timers yet, but next time we 2043 * receive a beacon with the same BSSID, the hardware will 2044 * automatically update the TSF and then we need to reconfigure 2045 * the timers. 2046 */ 2047 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2048 "need to wait for HW TSF sync\n"); 2049 return; 2050 } else { 2051 /* 2052 * most important case for beacon synchronization between STA. 2053 * 2054 * beacon received and HW TSF has been already updated by HW. 2055 * update next TBTT based on the TSF of the beacon, but make 2056 * sure it is ahead of our local TSF timer. 2057 */ 2058 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2059 } 2060 #undef FUDGE 2061 2062 ah->nexttbtt = nexttbtt; 2063 2064 intval |= AR5K_BEACON_ENA; 2065 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); 2066 2067 /* 2068 * debugging output last in order to preserve the time critical aspect 2069 * of this function 2070 */ 2071 if (bc_tsf == -1) 2072 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2073 "reconfigured timers based on HW TSF\n"); 2074 else if (bc_tsf == 0) 2075 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2076 "reset HW TSF and timers\n"); 2077 else 2078 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2079 "updated timers based on beacon TSF\n"); 2080 2081 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2082 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2083 (unsigned long long) bc_tsf, 2084 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2085 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2086 intval & AR5K_BEACON_PERIOD, 2087 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2088 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2089 } 2090 2091 /** 2092 * ath5k_beacon_config - Configure the beacon queues and interrupts 2093 * 2094 * @ah: struct ath5k_hw pointer we are operating on 2095 * 2096 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2097 * interrupts to detect TSF updates only. 2098 */ 2099 void 2100 ath5k_beacon_config(struct ath5k_hw *ah) 2101 { 2102 spin_lock_bh(&ah->block); 2103 ah->bmisscount = 0; 2104 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2105 2106 if (ah->enable_beacon) { 2107 /* 2108 * In IBSS mode we use a self-linked tx descriptor and let the 2109 * hardware send the beacons automatically. We have to load it 2110 * only once here. 2111 * We use the SWBA interrupt only to keep track of the beacon 2112 * timers in order to detect automatic TSF updates. 2113 */ 2114 ath5k_beaconq_config(ah); 2115 2116 ah->imask |= AR5K_INT_SWBA; 2117 2118 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2119 if (ath5k_hw_hasveol(ah)) 2120 ath5k_beacon_send(ah); 2121 } else 2122 ath5k_beacon_update_timers(ah, -1); 2123 } else { 2124 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); 2125 } 2126 2127 ath5k_hw_set_imr(ah, ah->imask); 2128 mmiowb(); 2129 spin_unlock_bh(&ah->block); 2130 } 2131 2132 static void ath5k_tasklet_beacon(unsigned long data) 2133 { 2134 struct ath5k_hw *ah = (struct ath5k_hw *) data; 2135 2136 /* 2137 * Software beacon alert--time to send a beacon. 2138 * 2139 * In IBSS mode we use this interrupt just to 2140 * keep track of the next TBTT (target beacon 2141 * transmission time) in order to detect whether 2142 * automatic TSF updates happened. 2143 */ 2144 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2145 /* XXX: only if VEOL supported */ 2146 u64 tsf = ath5k_hw_get_tsf64(ah); 2147 ah->nexttbtt += ah->bintval; 2148 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2149 "SWBA nexttbtt: %x hw_tu: %x " 2150 "TSF: %llx\n", 2151 ah->nexttbtt, 2152 TSF_TO_TU(tsf), 2153 (unsigned long long) tsf); 2154 } else { 2155 spin_lock(&ah->block); 2156 ath5k_beacon_send(ah); 2157 spin_unlock(&ah->block); 2158 } 2159 } 2160 2161 2162 /********************\ 2163 * Interrupt handling * 2164 \********************/ 2165 2166 static void 2167 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2168 { 2169 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2170 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2171 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2172 2173 /* Run ANI only when calibration is not active */ 2174 2175 ah->ah_cal_next_ani = jiffies + 2176 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2177 tasklet_schedule(&ah->ani_tasklet); 2178 2179 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && 2180 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2181 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2182 2183 /* Run calibration only when another calibration 2184 * is not running. 2185 * 2186 * Note: This is for both full/short calibration, 2187 * if it's time for a full one, ath5k_calibrate_work will deal 2188 * with it. */ 2189 2190 ah->ah_cal_next_short = jiffies + 2191 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2192 ieee80211_queue_work(ah->hw, &ah->calib_work); 2193 } 2194 /* we could use SWI to generate enough interrupts to meet our 2195 * calibration interval requirements, if necessary: 2196 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2197 } 2198 2199 static void 2200 ath5k_schedule_rx(struct ath5k_hw *ah) 2201 { 2202 ah->rx_pending = true; 2203 tasklet_schedule(&ah->rxtq); 2204 } 2205 2206 static void 2207 ath5k_schedule_tx(struct ath5k_hw *ah) 2208 { 2209 ah->tx_pending = true; 2210 tasklet_schedule(&ah->txtq); 2211 } 2212 2213 static irqreturn_t 2214 ath5k_intr(int irq, void *dev_id) 2215 { 2216 struct ath5k_hw *ah = dev_id; 2217 enum ath5k_int status; 2218 unsigned int counter = 1000; 2219 2220 2221 /* 2222 * If hw is not ready (or detached) and we get an 2223 * interrupt, or if we have no interrupts pending 2224 * (that means it's not for us) skip it. 2225 * 2226 * NOTE: Group 0/1 PCI interface registers are not 2227 * supported on WiSOCs, so we can't check for pending 2228 * interrupts (ISR belongs to another register group 2229 * so we are ok). 2230 */ 2231 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || 2232 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2233 !ath5k_hw_is_intr_pending(ah)))) 2234 return IRQ_NONE; 2235 2236 /** Main loop **/ 2237 do { 2238 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2239 2240 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2241 status, ah->imask); 2242 2243 /* 2244 * Fatal hw error -> Log and reset 2245 * 2246 * Fatal errors are unrecoverable so we have to 2247 * reset the card. These errors include bus and 2248 * dma errors. 2249 */ 2250 if (unlikely(status & AR5K_INT_FATAL)) { 2251 2252 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2253 "fatal int, resetting\n"); 2254 ieee80211_queue_work(ah->hw, &ah->reset_work); 2255 2256 /* 2257 * RX Overrun -> Count and reset if needed 2258 * 2259 * Receive buffers are full. Either the bus is busy or 2260 * the CPU is not fast enough to process all received 2261 * frames. 2262 */ 2263 } else if (unlikely(status & AR5K_INT_RXORN)) { 2264 2265 /* 2266 * Older chipsets need a reset to come out of this 2267 * condition, but we treat it as RX for newer chips. 2268 * We don't know exactly which versions need a reset 2269 * this guess is copied from the HAL. 2270 */ 2271 ah->stats.rxorn_intr++; 2272 2273 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2274 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2275 "rx overrun, resetting\n"); 2276 ieee80211_queue_work(ah->hw, &ah->reset_work); 2277 } else 2278 ath5k_schedule_rx(ah); 2279 2280 } else { 2281 2282 /* Software Beacon Alert -> Schedule beacon tasklet */ 2283 if (status & AR5K_INT_SWBA) 2284 tasklet_hi_schedule(&ah->beacontq); 2285 2286 /* 2287 * No more RX descriptors -> Just count 2288 * 2289 * NB: the hardware should re-read the link when 2290 * RXE bit is written, but it doesn't work at 2291 * least on older hardware revs. 2292 */ 2293 if (status & AR5K_INT_RXEOL) 2294 ah->stats.rxeol_intr++; 2295 2296 2297 /* TX Underrun -> Bump tx trigger level */ 2298 if (status & AR5K_INT_TXURN) 2299 ath5k_hw_update_tx_triglevel(ah, true); 2300 2301 /* RX -> Schedule rx tasklet */ 2302 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2303 ath5k_schedule_rx(ah); 2304 2305 /* TX -> Schedule tx tasklet */ 2306 if (status & (AR5K_INT_TXOK 2307 | AR5K_INT_TXDESC 2308 | AR5K_INT_TXERR 2309 | AR5K_INT_TXEOL)) 2310 ath5k_schedule_tx(ah); 2311 2312 /* Missed beacon -> TODO 2313 if (status & AR5K_INT_BMISS) 2314 */ 2315 2316 /* MIB event -> Update counters and notify ANI */ 2317 if (status & AR5K_INT_MIB) { 2318 ah->stats.mib_intr++; 2319 ath5k_hw_update_mib_counters(ah); 2320 ath5k_ani_mib_intr(ah); 2321 } 2322 2323 /* GPIO -> Notify RFKill layer */ 2324 if (status & AR5K_INT_GPIO) 2325 tasklet_schedule(&ah->rf_kill.toggleq); 2326 2327 } 2328 2329 if (ath5k_get_bus_type(ah) == ATH_AHB) 2330 break; 2331 2332 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2333 2334 /* 2335 * Until we handle rx/tx interrupts mask them on IMR 2336 * 2337 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets 2338 * and unset after we 've handled the interrupts. 2339 */ 2340 if (ah->rx_pending || ah->tx_pending) 2341 ath5k_set_current_imask(ah); 2342 2343 if (unlikely(!counter)) 2344 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); 2345 2346 /* Fire up calibration poll */ 2347 ath5k_intr_calibration_poll(ah); 2348 2349 return IRQ_HANDLED; 2350 } 2351 2352 /* 2353 * Periodically recalibrate the PHY to account 2354 * for temperature/environment changes. 2355 */ 2356 static void 2357 ath5k_calibrate_work(struct work_struct *work) 2358 { 2359 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2360 calib_work); 2361 2362 /* Should we run a full calibration ? */ 2363 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2364 2365 ah->ah_cal_next_full = jiffies + 2366 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2367 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2368 2369 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 2370 "running full calibration\n"); 2371 2372 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2373 /* 2374 * Rfgain is out of bounds, reset the chip 2375 * to load new gain values. 2376 */ 2377 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2378 "got new rfgain, resetting\n"); 2379 ieee80211_queue_work(ah->hw, &ah->reset_work); 2380 } 2381 } else 2382 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; 2383 2384 2385 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2386 ieee80211_frequency_to_channel(ah->curchan->center_freq), 2387 ah->curchan->hw_value); 2388 2389 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) 2390 ATH5K_ERR(ah, "calibration of channel %u failed\n", 2391 ieee80211_frequency_to_channel( 2392 ah->curchan->center_freq)); 2393 2394 /* Clear calibration flags */ 2395 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) 2396 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2397 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) 2398 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; 2399 } 2400 2401 2402 static void 2403 ath5k_tasklet_ani(unsigned long data) 2404 { 2405 struct ath5k_hw *ah = (void *)data; 2406 2407 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2408 ath5k_ani_calibration(ah); 2409 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2410 } 2411 2412 2413 static void 2414 ath5k_tx_complete_poll_work(struct work_struct *work) 2415 { 2416 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2417 tx_complete_work.work); 2418 struct ath5k_txq *txq; 2419 int i; 2420 bool needreset = false; 2421 2422 if (!test_bit(ATH_STAT_STARTED, ah->status)) 2423 return; 2424 2425 mutex_lock(&ah->lock); 2426 2427 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 2428 if (ah->txqs[i].setup) { 2429 txq = &ah->txqs[i]; 2430 spin_lock_bh(&txq->lock); 2431 if (txq->txq_len > 1) { 2432 if (txq->txq_poll_mark) { 2433 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, 2434 "TX queue stuck %d\n", 2435 txq->qnum); 2436 needreset = true; 2437 txq->txq_stuck++; 2438 spin_unlock_bh(&txq->lock); 2439 break; 2440 } else { 2441 txq->txq_poll_mark = true; 2442 } 2443 } 2444 spin_unlock_bh(&txq->lock); 2445 } 2446 } 2447 2448 if (needreset) { 2449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2450 "TX queues stuck, resetting\n"); 2451 ath5k_reset(ah, NULL, true); 2452 } 2453 2454 mutex_unlock(&ah->lock); 2455 2456 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2457 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2458 } 2459 2460 2461 /*************************\ 2462 * Initialization routines * 2463 \*************************/ 2464 2465 static const struct ieee80211_iface_limit if_limits[] = { 2466 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 2467 { .max = 4, .types = 2468 #ifdef CONFIG_MAC80211_MESH 2469 BIT(NL80211_IFTYPE_MESH_POINT) | 2470 #endif 2471 BIT(NL80211_IFTYPE_AP) }, 2472 }; 2473 2474 static const struct ieee80211_iface_combination if_comb = { 2475 .limits = if_limits, 2476 .n_limits = ARRAY_SIZE(if_limits), 2477 .max_interfaces = 2048, 2478 .num_different_channels = 1, 2479 }; 2480 2481 int 2482 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) 2483 { 2484 struct ieee80211_hw *hw = ah->hw; 2485 struct ath_common *common; 2486 int ret; 2487 int csz; 2488 2489 /* Initialize driver private data */ 2490 SET_IEEE80211_DEV(hw, ah->dev); 2491 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2492 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2493 IEEE80211_HW_SIGNAL_DBM | 2494 IEEE80211_HW_MFP_CAPABLE | 2495 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 2496 IEEE80211_HW_SUPPORTS_RC_TABLE; 2497 2498 hw->wiphy->interface_modes = 2499 BIT(NL80211_IFTYPE_AP) | 2500 BIT(NL80211_IFTYPE_STATION) | 2501 BIT(NL80211_IFTYPE_ADHOC) | 2502 BIT(NL80211_IFTYPE_MESH_POINT); 2503 2504 hw->wiphy->iface_combinations = &if_comb; 2505 hw->wiphy->n_iface_combinations = 1; 2506 2507 /* SW support for IBSS_RSN is provided by mac80211 */ 2508 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 2509 2510 /* both antennas can be configured as RX or TX */ 2511 hw->wiphy->available_antennas_tx = 0x3; 2512 hw->wiphy->available_antennas_rx = 0x3; 2513 2514 hw->extra_tx_headroom = 2; 2515 hw->channel_change_time = 5000; 2516 2517 /* 2518 * Mark the device as detached to avoid processing 2519 * interrupts until setup is complete. 2520 */ 2521 __set_bit(ATH_STAT_INVALID, ah->status); 2522 2523 ah->opmode = NL80211_IFTYPE_STATION; 2524 ah->bintval = 1000; 2525 mutex_init(&ah->lock); 2526 spin_lock_init(&ah->rxbuflock); 2527 spin_lock_init(&ah->txbuflock); 2528 spin_lock_init(&ah->block); 2529 spin_lock_init(&ah->irqlock); 2530 2531 /* Setup interrupt handler */ 2532 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); 2533 if (ret) { 2534 ATH5K_ERR(ah, "request_irq failed\n"); 2535 goto err; 2536 } 2537 2538 common = ath5k_hw_common(ah); 2539 common->ops = &ath5k_common_ops; 2540 common->bus_ops = bus_ops; 2541 common->ah = ah; 2542 common->hw = hw; 2543 common->priv = ah; 2544 common->clockrate = 40; 2545 2546 /* 2547 * Cache line size is used to size and align various 2548 * structures used to communicate with the hardware. 2549 */ 2550 ath5k_read_cachesize(common, &csz); 2551 common->cachelsz = csz << 2; /* convert to bytes */ 2552 2553 spin_lock_init(&common->cc_lock); 2554 2555 /* Initialize device */ 2556 ret = ath5k_hw_init(ah); 2557 if (ret) 2558 goto err_irq; 2559 2560 /* Set up multi-rate retry capabilities */ 2561 if (ah->ah_capabilities.cap_has_mrr_support) { 2562 hw->max_rates = 4; 2563 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2564 AR5K_INIT_RETRY_LONG); 2565 } 2566 2567 hw->vif_data_size = sizeof(struct ath5k_vif); 2568 2569 /* Finish private driver data initialization */ 2570 ret = ath5k_init(hw); 2571 if (ret) 2572 goto err_ah; 2573 2574 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2575 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), 2576 ah->ah_mac_srev, 2577 ah->ah_phy_revision); 2578 2579 if (!ah->ah_single_chip) { 2580 /* Single chip radio (!RF5111) */ 2581 if (ah->ah_radio_5ghz_revision && 2582 !ah->ah_radio_2ghz_revision) { 2583 /* No 5GHz support -> report 2GHz radio */ 2584 if (!test_bit(AR5K_MODE_11A, 2585 ah->ah_capabilities.cap_mode)) { 2586 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2587 ath5k_chip_name(AR5K_VERSION_RAD, 2588 ah->ah_radio_5ghz_revision), 2589 ah->ah_radio_5ghz_revision); 2590 /* No 2GHz support (5110 and some 2591 * 5GHz only cards) -> report 5GHz radio */ 2592 } else if (!test_bit(AR5K_MODE_11B, 2593 ah->ah_capabilities.cap_mode)) { 2594 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2595 ath5k_chip_name(AR5K_VERSION_RAD, 2596 ah->ah_radio_5ghz_revision), 2597 ah->ah_radio_5ghz_revision); 2598 /* Multiband radio */ 2599 } else { 2600 ATH5K_INFO(ah, "RF%s multiband radio found" 2601 " (0x%x)\n", 2602 ath5k_chip_name(AR5K_VERSION_RAD, 2603 ah->ah_radio_5ghz_revision), 2604 ah->ah_radio_5ghz_revision); 2605 } 2606 } 2607 /* Multi chip radio (RF5111 - RF2111) -> 2608 * report both 2GHz/5GHz radios */ 2609 else if (ah->ah_radio_5ghz_revision && 2610 ah->ah_radio_2ghz_revision) { 2611 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2612 ath5k_chip_name(AR5K_VERSION_RAD, 2613 ah->ah_radio_5ghz_revision), 2614 ah->ah_radio_5ghz_revision); 2615 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2616 ath5k_chip_name(AR5K_VERSION_RAD, 2617 ah->ah_radio_2ghz_revision), 2618 ah->ah_radio_2ghz_revision); 2619 } 2620 } 2621 2622 ath5k_debug_init_device(ah); 2623 2624 /* ready to process interrupts */ 2625 __clear_bit(ATH_STAT_INVALID, ah->status); 2626 2627 return 0; 2628 err_ah: 2629 ath5k_hw_deinit(ah); 2630 err_irq: 2631 free_irq(ah->irq, ah); 2632 err: 2633 return ret; 2634 } 2635 2636 static int 2637 ath5k_stop_locked(struct ath5k_hw *ah) 2638 { 2639 2640 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", 2641 test_bit(ATH_STAT_INVALID, ah->status)); 2642 2643 /* 2644 * Shutdown the hardware and driver: 2645 * stop output from above 2646 * disable interrupts 2647 * turn off timers 2648 * turn off the radio 2649 * clear transmit machinery 2650 * clear receive machinery 2651 * drain and release tx queues 2652 * reclaim beacon resources 2653 * power down hardware 2654 * 2655 * Note that some of this work is not possible if the 2656 * hardware is gone (invalid). 2657 */ 2658 ieee80211_stop_queues(ah->hw); 2659 2660 if (!test_bit(ATH_STAT_INVALID, ah->status)) { 2661 ath5k_led_off(ah); 2662 ath5k_hw_set_imr(ah, 0); 2663 synchronize_irq(ah->irq); 2664 ath5k_rx_stop(ah); 2665 ath5k_hw_dma_stop(ah); 2666 ath5k_drain_tx_buffs(ah); 2667 ath5k_hw_phy_disable(ah); 2668 } 2669 2670 return 0; 2671 } 2672 2673 int ath5k_start(struct ieee80211_hw *hw) 2674 { 2675 struct ath5k_hw *ah = hw->priv; 2676 struct ath_common *common = ath5k_hw_common(ah); 2677 int ret, i; 2678 2679 mutex_lock(&ah->lock); 2680 2681 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); 2682 2683 /* 2684 * Stop anything previously setup. This is safe 2685 * no matter this is the first time through or not. 2686 */ 2687 ath5k_stop_locked(ah); 2688 2689 /* 2690 * The basic interface to setting the hardware in a good 2691 * state is ``reset''. On return the hardware is known to 2692 * be powered up and with interrupts disabled. This must 2693 * be followed by initialization of the appropriate bits 2694 * and then setup of the interrupt mask. 2695 */ 2696 ah->curchan = ah->hw->conf.chandef.chan; 2697 ah->imask = AR5K_INT_RXOK 2698 | AR5K_INT_RXERR 2699 | AR5K_INT_RXEOL 2700 | AR5K_INT_RXORN 2701 | AR5K_INT_TXDESC 2702 | AR5K_INT_TXEOL 2703 | AR5K_INT_FATAL 2704 | AR5K_INT_GLOBAL 2705 | AR5K_INT_MIB; 2706 2707 ret = ath5k_reset(ah, NULL, false); 2708 if (ret) 2709 goto done; 2710 2711 if (!ath5k_modparam_no_hw_rfkill_switch) 2712 ath5k_rfkill_hw_start(ah); 2713 2714 /* 2715 * Reset the key cache since some parts do not reset the 2716 * contents on initial power up or resume from suspend. 2717 */ 2718 for (i = 0; i < common->keymax; i++) 2719 ath_hw_keyreset(common, (u16) i); 2720 2721 /* Use higher rates for acks instead of base 2722 * rate */ 2723 ah->ah_ack_bitrate_high = true; 2724 2725 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) 2726 ah->bslot[i] = NULL; 2727 2728 ret = 0; 2729 done: 2730 mmiowb(); 2731 mutex_unlock(&ah->lock); 2732 2733 set_bit(ATH_STAT_STARTED, ah->status); 2734 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2735 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2736 2737 return ret; 2738 } 2739 2740 static void ath5k_stop_tasklets(struct ath5k_hw *ah) 2741 { 2742 ah->rx_pending = false; 2743 ah->tx_pending = false; 2744 tasklet_kill(&ah->rxtq); 2745 tasklet_kill(&ah->txtq); 2746 tasklet_kill(&ah->beacontq); 2747 tasklet_kill(&ah->ani_tasklet); 2748 } 2749 2750 /* 2751 * Stop the device, grabbing the top-level lock to protect 2752 * against concurrent entry through ath5k_init (which can happen 2753 * if another thread does a system call and the thread doing the 2754 * stop is preempted). 2755 */ 2756 void ath5k_stop(struct ieee80211_hw *hw) 2757 { 2758 struct ath5k_hw *ah = hw->priv; 2759 int ret; 2760 2761 mutex_lock(&ah->lock); 2762 ret = ath5k_stop_locked(ah); 2763 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { 2764 /* 2765 * Don't set the card in full sleep mode! 2766 * 2767 * a) When the device is in this state it must be carefully 2768 * woken up or references to registers in the PCI clock 2769 * domain may freeze the bus (and system). This varies 2770 * by chip and is mostly an issue with newer parts 2771 * (madwifi sources mentioned srev >= 0x78) that go to 2772 * sleep more quickly. 2773 * 2774 * b) On older chips full sleep results a weird behaviour 2775 * during wakeup. I tested various cards with srev < 0x78 2776 * and they don't wake up after module reload, a second 2777 * module reload is needed to bring the card up again. 2778 * 2779 * Until we figure out what's going on don't enable 2780 * full chip reset on any chip (this is what Legacy HAL 2781 * and Sam's HAL do anyway). Instead Perform a full reset 2782 * on the device (same as initial state after attach) and 2783 * leave it idle (keep MAC/BB on warm reset) */ 2784 ret = ath5k_hw_on_hold(ah); 2785 2786 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2787 "putting device to sleep\n"); 2788 } 2789 2790 mmiowb(); 2791 mutex_unlock(&ah->lock); 2792 2793 ath5k_stop_tasklets(ah); 2794 2795 clear_bit(ATH_STAT_STARTED, ah->status); 2796 cancel_delayed_work_sync(&ah->tx_complete_work); 2797 2798 if (!ath5k_modparam_no_hw_rfkill_switch) 2799 ath5k_rfkill_hw_stop(ah); 2800 } 2801 2802 /* 2803 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2804 * and change to the given channel. 2805 * 2806 * This should be called with ah->lock. 2807 */ 2808 static int 2809 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 2810 bool skip_pcu) 2811 { 2812 struct ath_common *common = ath5k_hw_common(ah); 2813 int ret, ani_mode; 2814 bool fast; 2815 2816 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); 2817 2818 ath5k_hw_set_imr(ah, 0); 2819 synchronize_irq(ah->irq); 2820 ath5k_stop_tasklets(ah); 2821 2822 /* Save ani mode and disable ANI during 2823 * reset. If we don't we might get false 2824 * PHY error interrupts. */ 2825 ani_mode = ah->ani_state.ani_mode; 2826 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2827 2828 /* We are going to empty hw queues 2829 * so we should also free any remaining 2830 * tx buffers */ 2831 ath5k_drain_tx_buffs(ah); 2832 if (chan) 2833 ah->curchan = chan; 2834 2835 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2836 2837 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); 2838 if (ret) { 2839 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); 2840 goto err; 2841 } 2842 2843 ret = ath5k_rx_start(ah); 2844 if (ret) { 2845 ATH5K_ERR(ah, "can't start recv logic\n"); 2846 goto err; 2847 } 2848 2849 ath5k_ani_init(ah, ani_mode); 2850 2851 /* 2852 * Set calibration intervals 2853 * 2854 * Note: We don't need to run calibration imediately 2855 * since some initial calibration is done on reset 2856 * even for fast channel switching. Also on scanning 2857 * this will get set again and again and it won't get 2858 * executed unless we connect somewhere and spend some 2859 * time on the channel (that's what calibration needs 2860 * anyway to be accurate). 2861 */ 2862 ah->ah_cal_next_full = jiffies + 2863 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2864 ah->ah_cal_next_ani = jiffies + 2865 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2866 ah->ah_cal_next_short = jiffies + 2867 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2868 2869 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2870 2871 /* clear survey data and cycle counters */ 2872 memset(&ah->survey, 0, sizeof(ah->survey)); 2873 spin_lock_bh(&common->cc_lock); 2874 ath_hw_cycle_counters_update(common); 2875 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2876 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2877 spin_unlock_bh(&common->cc_lock); 2878 2879 /* 2880 * Change channels and update the h/w rate map if we're switching; 2881 * e.g. 11a to 11b/g. 2882 * 2883 * We may be doing a reset in response to an ioctl that changes the 2884 * channel so update any state that might change as a result. 2885 * 2886 * XXX needed? 2887 */ 2888 /* ath5k_chan_change(ah, c); */ 2889 2890 ath5k_beacon_config(ah); 2891 /* intrs are enabled by ath5k_beacon_config */ 2892 2893 ieee80211_wake_queues(ah->hw); 2894 2895 return 0; 2896 err: 2897 return ret; 2898 } 2899 2900 static void ath5k_reset_work(struct work_struct *work) 2901 { 2902 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2903 reset_work); 2904 2905 mutex_lock(&ah->lock); 2906 ath5k_reset(ah, NULL, true); 2907 mutex_unlock(&ah->lock); 2908 } 2909 2910 static int 2911 ath5k_init(struct ieee80211_hw *hw) 2912 { 2913 2914 struct ath5k_hw *ah = hw->priv; 2915 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2916 struct ath5k_txq *txq; 2917 u8 mac[ETH_ALEN] = {}; 2918 int ret; 2919 2920 2921 /* 2922 * Collect the channel list. The 802.11 layer 2923 * is responsible for filtering this list based 2924 * on settings like the phy mode and regulatory 2925 * domain restrictions. 2926 */ 2927 ret = ath5k_setup_bands(hw); 2928 if (ret) { 2929 ATH5K_ERR(ah, "can't get channels\n"); 2930 goto err; 2931 } 2932 2933 /* 2934 * Allocate tx+rx descriptors and populate the lists. 2935 */ 2936 ret = ath5k_desc_alloc(ah); 2937 if (ret) { 2938 ATH5K_ERR(ah, "can't allocate descriptors\n"); 2939 goto err; 2940 } 2941 2942 /* 2943 * Allocate hardware transmit queues: one queue for 2944 * beacon frames and one data queue for each QoS 2945 * priority. Note that hw functions handle resetting 2946 * these queues at the needed time. 2947 */ 2948 ret = ath5k_beaconq_setup(ah); 2949 if (ret < 0) { 2950 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); 2951 goto err_desc; 2952 } 2953 ah->bhalq = ret; 2954 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); 2955 if (IS_ERR(ah->cabq)) { 2956 ATH5K_ERR(ah, "can't setup cab queue\n"); 2957 ret = PTR_ERR(ah->cabq); 2958 goto err_bhal; 2959 } 2960 2961 /* 5211 and 5212 usually support 10 queues but we better rely on the 2962 * capability information */ 2963 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2964 /* This order matches mac80211's queue priority, so we can 2965 * directly use the mac80211 queue number without any mapping */ 2966 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2967 if (IS_ERR(txq)) { 2968 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2969 ret = PTR_ERR(txq); 2970 goto err_queues; 2971 } 2972 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2973 if (IS_ERR(txq)) { 2974 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2975 ret = PTR_ERR(txq); 2976 goto err_queues; 2977 } 2978 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2979 if (IS_ERR(txq)) { 2980 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2981 ret = PTR_ERR(txq); 2982 goto err_queues; 2983 } 2984 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2985 if (IS_ERR(txq)) { 2986 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2987 ret = PTR_ERR(txq); 2988 goto err_queues; 2989 } 2990 hw->queues = 4; 2991 } else { 2992 /* older hardware (5210) can only support one data queue */ 2993 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2994 if (IS_ERR(txq)) { 2995 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2996 ret = PTR_ERR(txq); 2997 goto err_queues; 2998 } 2999 hw->queues = 1; 3000 } 3001 3002 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); 3003 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); 3004 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); 3005 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); 3006 3007 INIT_WORK(&ah->reset_work, ath5k_reset_work); 3008 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); 3009 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); 3010 3011 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 3012 if (ret) { 3013 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); 3014 goto err_queues; 3015 } 3016 3017 SET_IEEE80211_PERM_ADDR(hw, mac); 3018 /* All MAC address bits matter for ACKs */ 3019 ath5k_update_bssid_mask_and_opmode(ah, NULL); 3020 3021 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 3022 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 3023 if (ret) { 3024 ATH5K_ERR(ah, "can't initialize regulatory system\n"); 3025 goto err_queues; 3026 } 3027 3028 ret = ieee80211_register_hw(hw); 3029 if (ret) { 3030 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); 3031 goto err_queues; 3032 } 3033 3034 if (!ath_is_world_regd(regulatory)) 3035 regulatory_hint(hw->wiphy, regulatory->alpha2); 3036 3037 ath5k_init_leds(ah); 3038 3039 ath5k_sysfs_register(ah); 3040 3041 return 0; 3042 err_queues: 3043 ath5k_txq_release(ah); 3044 err_bhal: 3045 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3046 err_desc: 3047 ath5k_desc_free(ah); 3048 err: 3049 return ret; 3050 } 3051 3052 void 3053 ath5k_deinit_ah(struct ath5k_hw *ah) 3054 { 3055 struct ieee80211_hw *hw = ah->hw; 3056 3057 /* 3058 * NB: the order of these is important: 3059 * o call the 802.11 layer before detaching ath5k_hw to 3060 * ensure callbacks into the driver to delete global 3061 * key cache entries can be handled 3062 * o reclaim the tx queue data structures after calling 3063 * the 802.11 layer as we'll get called back to reclaim 3064 * node state and potentially want to use them 3065 * o to cleanup the tx queues the hal is called, so detach 3066 * it last 3067 * XXX: ??? detach ath5k_hw ??? 3068 * Other than that, it's straightforward... 3069 */ 3070 ieee80211_unregister_hw(hw); 3071 ath5k_desc_free(ah); 3072 ath5k_txq_release(ah); 3073 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3074 ath5k_unregister_leds(ah); 3075 3076 ath5k_sysfs_unregister(ah); 3077 /* 3078 * NB: can't reclaim these until after ieee80211_ifdetach 3079 * returns because we'll get called back to reclaim node 3080 * state and potentially want to use them. 3081 */ 3082 ath5k_hw_deinit(ah); 3083 free_irq(ah->irq, ah); 3084 } 3085 3086 bool 3087 ath5k_any_vif_assoc(struct ath5k_hw *ah) 3088 { 3089 struct ath5k_vif_iter_data iter_data; 3090 iter_data.hw_macaddr = NULL; 3091 iter_data.any_assoc = false; 3092 iter_data.need_set_hw_addr = false; 3093 iter_data.found_active = true; 3094 3095 ieee80211_iterate_active_interfaces_atomic( 3096 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 3097 ath5k_vif_iter, &iter_data); 3098 return iter_data.any_assoc; 3099 } 3100 3101 void 3102 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3103 { 3104 struct ath5k_hw *ah = hw->priv; 3105 u32 rfilt; 3106 rfilt = ath5k_hw_get_rx_filter(ah); 3107 if (enable) 3108 rfilt |= AR5K_RX_FILTER_BEACON; 3109 else 3110 rfilt &= ~AR5K_RX_FILTER_BEACON; 3111 ath5k_hw_set_rx_filter(ah, rfilt); 3112 ah->filter_flags = rfilt; 3113 } 3114 3115 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, 3116 const char *fmt, ...) 3117 { 3118 struct va_format vaf; 3119 va_list args; 3120 3121 va_start(args, fmt); 3122 3123 vaf.fmt = fmt; 3124 vaf.va = &args; 3125 3126 if (ah && ah->hw) 3127 printk("%s" pr_fmt("%s: %pV"), 3128 level, wiphy_name(ah->hw->wiphy), &vaf); 3129 else 3130 printk("%s" pr_fmt("%pV"), level, &vaf); 3131 3132 va_end(args); 3133 } 3134