1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 44 45 #include <linux/module.h> 46 #include <linux/delay.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/hardirq.h> 49 #include <linux/if.h> 50 #include <linux/io.h> 51 #include <linux/netdevice.h> 52 #include <linux/cache.h> 53 #include <linux/ethtool.h> 54 #include <linux/uaccess.h> 55 #include <linux/slab.h> 56 #include <linux/etherdevice.h> 57 #include <linux/nl80211.h> 58 59 #include <net/cfg80211.h> 60 #include <net/ieee80211_radiotap.h> 61 62 #include <asm/unaligned.h> 63 64 #include <net/mac80211.h> 65 #include "base.h" 66 #include "reg.h" 67 #include "debug.h" 68 #include "ani.h" 69 #include "ath5k.h" 70 #include "../regd.h" 71 72 #define CREATE_TRACE_POINTS 73 #include "trace.h" 74 75 bool ath5k_modparam_nohwcrypt; 76 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 77 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 78 79 static bool modparam_fastchanswitch; 80 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 81 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 82 83 static bool ath5k_modparam_no_hw_rfkill_switch; 84 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, 85 bool, S_IRUGO); 86 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); 87 88 89 /* Module info */ 90 MODULE_AUTHOR("Jiri Slaby"); 91 MODULE_AUTHOR("Nick Kossifidis"); 92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 93 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 94 MODULE_LICENSE("Dual BSD/GPL"); 95 96 static int ath5k_init(struct ieee80211_hw *hw); 97 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 98 bool skip_pcu); 99 100 /* Known SREVs */ 101 static const struct ath5k_srev_name srev_names[] = { 102 #ifdef CONFIG_ATH5K_AHB 103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 110 #else 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 #endif 130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 145 #ifdef CONFIG_ATH5K_AHB 146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 148 #endif 149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 150 }; 151 152 static const struct ieee80211_rate ath5k_rates[] = { 153 { .bitrate = 10, 154 .hw_value = ATH5K_RATE_CODE_1M, }, 155 { .bitrate = 20, 156 .hw_value = ATH5K_RATE_CODE_2M, 157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 158 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 159 { .bitrate = 55, 160 .hw_value = ATH5K_RATE_CODE_5_5M, 161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 162 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 163 { .bitrate = 110, 164 .hw_value = ATH5K_RATE_CODE_11M, 165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 166 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 167 { .bitrate = 60, 168 .hw_value = ATH5K_RATE_CODE_6M, 169 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 170 IEEE80211_RATE_SUPPORTS_10MHZ }, 171 { .bitrate = 90, 172 .hw_value = ATH5K_RATE_CODE_9M, 173 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 174 IEEE80211_RATE_SUPPORTS_10MHZ }, 175 { .bitrate = 120, 176 .hw_value = ATH5K_RATE_CODE_12M, 177 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 178 IEEE80211_RATE_SUPPORTS_10MHZ }, 179 { .bitrate = 180, 180 .hw_value = ATH5K_RATE_CODE_18M, 181 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 182 IEEE80211_RATE_SUPPORTS_10MHZ }, 183 { .bitrate = 240, 184 .hw_value = ATH5K_RATE_CODE_24M, 185 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 186 IEEE80211_RATE_SUPPORTS_10MHZ }, 187 { .bitrate = 360, 188 .hw_value = ATH5K_RATE_CODE_36M, 189 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 190 IEEE80211_RATE_SUPPORTS_10MHZ }, 191 { .bitrate = 480, 192 .hw_value = ATH5K_RATE_CODE_48M, 193 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 194 IEEE80211_RATE_SUPPORTS_10MHZ }, 195 { .bitrate = 540, 196 .hw_value = ATH5K_RATE_CODE_54M, 197 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 198 IEEE80211_RATE_SUPPORTS_10MHZ }, 199 }; 200 201 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 202 { 203 u64 tsf = ath5k_hw_get_tsf64(ah); 204 205 if ((tsf & 0x7fff) < rstamp) 206 tsf -= 0x8000; 207 208 return (tsf & ~0x7fff) | rstamp; 209 } 210 211 const char * 212 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 213 { 214 const char *name = "xxxxx"; 215 unsigned int i; 216 217 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 218 if (srev_names[i].sr_type != type) 219 continue; 220 221 if ((val & 0xf0) == srev_names[i].sr_val) 222 name = srev_names[i].sr_name; 223 224 if ((val & 0xff) == srev_names[i].sr_val) { 225 name = srev_names[i].sr_name; 226 break; 227 } 228 } 229 230 return name; 231 } 232 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 233 { 234 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 235 return ath5k_hw_reg_read(ah, reg_offset); 236 } 237 238 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 239 { 240 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 241 ath5k_hw_reg_write(ah, val, reg_offset); 242 } 243 244 static const struct ath_ops ath5k_common_ops = { 245 .read = ath5k_ioread32, 246 .write = ath5k_iowrite32, 247 }; 248 249 /***********************\ 250 * Driver Initialization * 251 \***********************/ 252 253 static void ath5k_reg_notifier(struct wiphy *wiphy, 254 struct regulatory_request *request) 255 { 256 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 257 struct ath5k_hw *ah = hw->priv; 258 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 259 260 ath_reg_notifier_apply(wiphy, request, regulatory); 261 } 262 263 /********************\ 264 * Channel/mode setup * 265 \********************/ 266 267 /* 268 * Returns true for the channel numbers used. 269 */ 270 #ifdef CONFIG_ATH5K_TEST_CHANNELS 271 static bool ath5k_is_standard_channel(short chan, enum nl80211_band band) 272 { 273 return true; 274 } 275 276 #else 277 static bool ath5k_is_standard_channel(short chan, enum nl80211_band band) 278 { 279 if (band == NL80211_BAND_2GHZ && chan <= 14) 280 return true; 281 282 return /* UNII 1,2 */ 283 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 284 /* midband */ 285 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 286 /* UNII-3 */ 287 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 288 /* 802.11j 5.030-5.080 GHz (20MHz) */ 289 (chan == 8 || chan == 12 || chan == 16) || 290 /* 802.11j 4.9GHz (20MHz) */ 291 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 292 } 293 #endif 294 295 static unsigned int 296 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 297 unsigned int mode, unsigned int max) 298 { 299 unsigned int count, size, freq, ch; 300 enum nl80211_band band; 301 302 switch (mode) { 303 case AR5K_MODE_11A: 304 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 305 size = 220; 306 band = NL80211_BAND_5GHZ; 307 break; 308 case AR5K_MODE_11B: 309 case AR5K_MODE_11G: 310 size = 26; 311 band = NL80211_BAND_2GHZ; 312 break; 313 default: 314 ATH5K_WARN(ah, "bad mode, not copying channels\n"); 315 return 0; 316 } 317 318 count = 0; 319 for (ch = 1; ch <= size && count < max; ch++) { 320 freq = ieee80211_channel_to_frequency(ch, band); 321 322 if (freq == 0) /* mapping failed - not a standard channel */ 323 continue; 324 325 /* Write channel info, needed for ath5k_channel_ok() */ 326 channels[count].center_freq = freq; 327 channels[count].band = band; 328 channels[count].hw_value = mode; 329 330 /* Check if channel is supported by the chipset */ 331 if (!ath5k_channel_ok(ah, &channels[count])) 332 continue; 333 334 if (!ath5k_is_standard_channel(ch, band)) 335 continue; 336 337 count++; 338 } 339 340 return count; 341 } 342 343 static void 344 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) 345 { 346 u8 i; 347 348 for (i = 0; i < AR5K_MAX_RATES; i++) 349 ah->rate_idx[b->band][i] = -1; 350 351 for (i = 0; i < b->n_bitrates; i++) { 352 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; 353 if (b->bitrates[i].hw_value_short) 354 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 355 } 356 } 357 358 static int 359 ath5k_setup_bands(struct ieee80211_hw *hw) 360 { 361 struct ath5k_hw *ah = hw->priv; 362 struct ieee80211_supported_band *sband; 363 int max_c, count_c = 0; 364 int i; 365 366 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS); 367 max_c = ARRAY_SIZE(ah->channels); 368 369 /* 2GHz band */ 370 sband = &ah->sbands[NL80211_BAND_2GHZ]; 371 sband->band = NL80211_BAND_2GHZ; 372 sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0]; 373 374 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { 375 /* G mode */ 376 memcpy(sband->bitrates, &ath5k_rates[0], 377 sizeof(struct ieee80211_rate) * 12); 378 sband->n_bitrates = 12; 379 380 sband->channels = ah->channels; 381 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 382 AR5K_MODE_11G, max_c); 383 384 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 385 count_c = sband->n_channels; 386 max_c -= count_c; 387 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { 388 /* B mode */ 389 memcpy(sband->bitrates, &ath5k_rates[0], 390 sizeof(struct ieee80211_rate) * 4); 391 sband->n_bitrates = 4; 392 393 /* 5211 only supports B rates and uses 4bit rate codes 394 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 395 * fix them up here: 396 */ 397 if (ah->ah_version == AR5K_AR5211) { 398 for (i = 0; i < 4; i++) { 399 sband->bitrates[i].hw_value = 400 sband->bitrates[i].hw_value & 0xF; 401 sband->bitrates[i].hw_value_short = 402 sband->bitrates[i].hw_value_short & 0xF; 403 } 404 } 405 406 sband->channels = ah->channels; 407 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 408 AR5K_MODE_11B, max_c); 409 410 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 411 count_c = sband->n_channels; 412 max_c -= count_c; 413 } 414 ath5k_setup_rate_idx(ah, sband); 415 416 /* 5GHz band, A mode */ 417 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 418 sband = &ah->sbands[NL80211_BAND_5GHZ]; 419 sband->band = NL80211_BAND_5GHZ; 420 sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0]; 421 422 memcpy(sband->bitrates, &ath5k_rates[4], 423 sizeof(struct ieee80211_rate) * 8); 424 sband->n_bitrates = 8; 425 426 sband->channels = &ah->channels[count_c]; 427 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 428 AR5K_MODE_11A, max_c); 429 430 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 431 } 432 ath5k_setup_rate_idx(ah, sband); 433 434 ath5k_debug_dump_bands(ah); 435 436 return 0; 437 } 438 439 /* 440 * Set/change channels. We always reset the chip. 441 * To accomplish this we must first cleanup any pending DMA, 442 * then restart stuff after a la ath5k_init. 443 * 444 * Called with ah->lock. 445 */ 446 int 447 ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) 448 { 449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 450 "channel set, resetting (%u -> %u MHz)\n", 451 ah->curchan->center_freq, chandef->chan->center_freq); 452 453 switch (chandef->width) { 454 case NL80211_CHAN_WIDTH_20: 455 case NL80211_CHAN_WIDTH_20_NOHT: 456 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; 457 break; 458 case NL80211_CHAN_WIDTH_5: 459 ah->ah_bwmode = AR5K_BWMODE_5MHZ; 460 break; 461 case NL80211_CHAN_WIDTH_10: 462 ah->ah_bwmode = AR5K_BWMODE_10MHZ; 463 break; 464 default: 465 WARN_ON(1); 466 return -EINVAL; 467 } 468 469 /* 470 * To switch channels clear any pending DMA operations; 471 * wait long enough for the RX fifo to drain, reset the 472 * hardware at the new frequency, and then re-enable 473 * the relevant bits of the h/w. 474 */ 475 return ath5k_reset(ah, chandef->chan, true); 476 } 477 478 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 479 { 480 struct ath5k_vif_iter_data *iter_data = data; 481 int i; 482 struct ath5k_vif *avf = (void *)vif->drv_priv; 483 484 if (iter_data->hw_macaddr) 485 for (i = 0; i < ETH_ALEN; i++) 486 iter_data->mask[i] &= 487 ~(iter_data->hw_macaddr[i] ^ mac[i]); 488 489 if (!iter_data->found_active) { 490 iter_data->found_active = true; 491 memcpy(iter_data->active_mac, mac, ETH_ALEN); 492 } 493 494 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 495 if (ether_addr_equal(iter_data->hw_macaddr, mac)) 496 iter_data->need_set_hw_addr = false; 497 498 if (!iter_data->any_assoc) { 499 if (avf->assoc) 500 iter_data->any_assoc = true; 501 } 502 503 /* Calculate combined mode - when APs are active, operate in AP mode. 504 * Otherwise use the mode of the new interface. This can currently 505 * only deal with combinations of APs and STAs. Only one ad-hoc 506 * interfaces is allowed. 507 */ 508 if (avf->opmode == NL80211_IFTYPE_AP) 509 iter_data->opmode = NL80211_IFTYPE_AP; 510 else { 511 if (avf->opmode == NL80211_IFTYPE_STATION) 512 iter_data->n_stas++; 513 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 514 iter_data->opmode = avf->opmode; 515 } 516 } 517 518 void 519 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, 520 struct ieee80211_vif *vif) 521 { 522 struct ath_common *common = ath5k_hw_common(ah); 523 struct ath5k_vif_iter_data iter_data; 524 u32 rfilt; 525 526 /* 527 * Use the hardware MAC address as reference, the hardware uses it 528 * together with the BSSID mask when matching addresses. 529 */ 530 iter_data.hw_macaddr = common->macaddr; 531 eth_broadcast_addr(iter_data.mask); 532 iter_data.found_active = false; 533 iter_data.need_set_hw_addr = true; 534 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 535 iter_data.n_stas = 0; 536 537 if (vif) 538 ath5k_vif_iter(&iter_data, vif->addr, vif); 539 540 /* Get list of all active MAC addresses */ 541 ieee80211_iterate_active_interfaces_atomic( 542 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 543 ath5k_vif_iter, &iter_data); 544 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); 545 546 ah->opmode = iter_data.opmode; 547 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) 548 /* Nothing active, default to station mode */ 549 ah->opmode = NL80211_IFTYPE_STATION; 550 551 ath5k_hw_set_opmode(ah, ah->opmode); 552 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 553 ah->opmode, ath_opmode_to_string(ah->opmode)); 554 555 if (iter_data.need_set_hw_addr && iter_data.found_active) 556 ath5k_hw_set_lladdr(ah, iter_data.active_mac); 557 558 if (ath5k_hw_hasbssidmask(ah)) 559 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); 560 561 /* Set up RX Filter */ 562 if (iter_data.n_stas > 1) { 563 /* If you have multiple STA interfaces connected to 564 * different APs, ARPs are not received (most of the time?) 565 * Enabling PROMISC appears to fix that problem. 566 */ 567 ah->filter_flags |= AR5K_RX_FILTER_PROM; 568 } 569 570 rfilt = ah->filter_flags; 571 ath5k_hw_set_rx_filter(ah, rfilt); 572 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 573 } 574 575 static inline int 576 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) 577 { 578 int rix; 579 580 /* return base rate on errors */ 581 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 582 "hw_rix out of bounds: %x\n", hw_rix)) 583 return 0; 584 585 rix = ah->rate_idx[ah->curchan->band][hw_rix]; 586 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 587 rix = 0; 588 589 return rix; 590 } 591 592 /***************\ 593 * Buffers setup * 594 \***************/ 595 596 static 597 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) 598 { 599 struct ath_common *common = ath5k_hw_common(ah); 600 struct sk_buff *skb; 601 602 /* 603 * Allocate buffer with headroom_needed space for the 604 * fake physical layer header at the start. 605 */ 606 skb = ath_rxbuf_alloc(common, 607 common->rx_bufsize, 608 GFP_ATOMIC); 609 610 if (!skb) { 611 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", 612 common->rx_bufsize); 613 return NULL; 614 } 615 616 *skb_addr = dma_map_single(ah->dev, 617 skb->data, common->rx_bufsize, 618 DMA_FROM_DEVICE); 619 620 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { 621 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); 622 dev_kfree_skb(skb); 623 return NULL; 624 } 625 return skb; 626 } 627 628 static int 629 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 630 { 631 struct sk_buff *skb = bf->skb; 632 struct ath5k_desc *ds; 633 int ret; 634 635 if (!skb) { 636 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); 637 if (!skb) 638 return -ENOMEM; 639 bf->skb = skb; 640 } 641 642 /* 643 * Setup descriptors. For receive we always terminate 644 * the descriptor list with a self-linked entry so we'll 645 * not get overrun under high load (as can happen with a 646 * 5212 when ANI processing enables PHY error frames). 647 * 648 * To ensure the last descriptor is self-linked we create 649 * each descriptor as self-linked and add it to the end. As 650 * each additional descriptor is added the previous self-linked 651 * entry is "fixed" naturally. This should be safe even 652 * if DMA is happening. When processing RX interrupts we 653 * never remove/process the last, self-linked, entry on the 654 * descriptor list. This ensures the hardware always has 655 * someplace to write a new frame. 656 */ 657 ds = bf->desc; 658 ds->ds_link = bf->daddr; /* link to self */ 659 ds->ds_data = bf->skbaddr; 660 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 661 if (ret) { 662 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); 663 return ret; 664 } 665 666 if (ah->rxlink != NULL) 667 *ah->rxlink = bf->daddr; 668 ah->rxlink = &ds->ds_link; 669 return 0; 670 } 671 672 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 673 { 674 struct ieee80211_hdr *hdr; 675 enum ath5k_pkt_type htype; 676 __le16 fc; 677 678 hdr = (struct ieee80211_hdr *)skb->data; 679 fc = hdr->frame_control; 680 681 if (ieee80211_is_beacon(fc)) 682 htype = AR5K_PKT_TYPE_BEACON; 683 else if (ieee80211_is_probe_resp(fc)) 684 htype = AR5K_PKT_TYPE_PROBE_RESP; 685 else if (ieee80211_is_atim(fc)) 686 htype = AR5K_PKT_TYPE_ATIM; 687 else if (ieee80211_is_pspoll(fc)) 688 htype = AR5K_PKT_TYPE_PSPOLL; 689 else 690 htype = AR5K_PKT_TYPE_NORMAL; 691 692 return htype; 693 } 694 695 static struct ieee80211_rate * 696 ath5k_get_rate(const struct ieee80211_hw *hw, 697 const struct ieee80211_tx_info *info, 698 struct ath5k_buf *bf, int idx) 699 { 700 /* 701 * convert a ieee80211_tx_rate RC-table entry to 702 * the respective ieee80211_rate struct 703 */ 704 if (bf->rates[idx].idx < 0) { 705 return NULL; 706 } 707 708 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ]; 709 } 710 711 static u16 712 ath5k_get_rate_hw_value(const struct ieee80211_hw *hw, 713 const struct ieee80211_tx_info *info, 714 struct ath5k_buf *bf, int idx) 715 { 716 struct ieee80211_rate *rate; 717 u16 hw_rate; 718 u8 rc_flags; 719 720 rate = ath5k_get_rate(hw, info, bf, idx); 721 if (!rate) 722 return 0; 723 724 rc_flags = bf->rates[idx].flags; 725 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 726 rate->hw_value_short : rate->hw_value; 727 728 return hw_rate; 729 } 730 731 static int 732 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, 733 struct ath5k_txq *txq, int padsize, 734 struct ieee80211_tx_control *control) 735 { 736 struct ath5k_desc *ds = bf->desc; 737 struct sk_buff *skb = bf->skb; 738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 739 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 740 struct ieee80211_rate *rate; 741 unsigned int mrr_rate[3], mrr_tries[3]; 742 int i, ret; 743 u16 hw_rate; 744 u16 cts_rate = 0; 745 u16 duration = 0; 746 u8 rc_flags; 747 748 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 749 750 /* XXX endianness */ 751 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 752 DMA_TO_DEVICE); 753 754 if (dma_mapping_error(ah->dev, bf->skbaddr)) 755 return -ENOSPC; 756 757 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates, 758 ARRAY_SIZE(bf->rates)); 759 760 rate = ath5k_get_rate(ah->hw, info, bf, 0); 761 762 if (!rate) { 763 ret = -EINVAL; 764 goto err_unmap; 765 } 766 767 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 768 flags |= AR5K_TXDESC_NOACK; 769 770 rc_flags = bf->rates[0].flags; 771 772 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); 773 774 pktlen = skb->len; 775 776 /* FIXME: If we are in g mode and rate is a CCK rate 777 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 778 * from tx power (value is in dB units already) */ 779 if (info->control.hw_key) { 780 keyidx = info->control.hw_key->hw_key_idx; 781 pktlen += info->control.hw_key->icv_len; 782 } 783 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 784 flags |= AR5K_TXDESC_RTSENA; 785 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 786 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, 787 info->control.vif, pktlen, info)); 788 } 789 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 790 flags |= AR5K_TXDESC_CTSENA; 791 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 792 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, 793 info->control.vif, pktlen, info)); 794 } 795 796 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 797 ieee80211_get_hdrlen_from_skb(skb), padsize, 798 get_hw_packet_type(skb), 799 (ah->ah_txpower.txp_requested * 2), 800 hw_rate, 801 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, 802 cts_rate, duration); 803 if (ret) 804 goto err_unmap; 805 806 /* Set up MRR descriptor */ 807 if (ah->ah_capabilities.cap_has_mrr_support) { 808 memset(mrr_rate, 0, sizeof(mrr_rate)); 809 memset(mrr_tries, 0, sizeof(mrr_tries)); 810 811 for (i = 0; i < 3; i++) { 812 813 rate = ath5k_get_rate(ah->hw, info, bf, i); 814 if (!rate) 815 break; 816 817 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); 818 mrr_tries[i] = bf->rates[i].count; 819 } 820 821 ath5k_hw_setup_mrr_tx_desc(ah, ds, 822 mrr_rate[0], mrr_tries[0], 823 mrr_rate[1], mrr_tries[1], 824 mrr_rate[2], mrr_tries[2]); 825 } 826 827 ds->ds_link = 0; 828 ds->ds_data = bf->skbaddr; 829 830 spin_lock_bh(&txq->lock); 831 list_add_tail(&bf->list, &txq->q); 832 txq->txq_len++; 833 if (txq->link == NULL) /* is this first packet? */ 834 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 835 else /* no, so only link it */ 836 *txq->link = bf->daddr; 837 838 txq->link = &ds->ds_link; 839 ath5k_hw_start_tx_dma(ah, txq->qnum); 840 mmiowb(); 841 spin_unlock_bh(&txq->lock); 842 843 return 0; 844 err_unmap: 845 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 846 return ret; 847 } 848 849 /*******************\ 850 * Descriptors setup * 851 \*******************/ 852 853 static int 854 ath5k_desc_alloc(struct ath5k_hw *ah) 855 { 856 struct ath5k_desc *ds; 857 struct ath5k_buf *bf; 858 dma_addr_t da; 859 unsigned int i; 860 int ret; 861 862 /* allocate descriptors */ 863 ah->desc_len = sizeof(struct ath5k_desc) * 864 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 865 866 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, 867 &ah->desc_daddr, GFP_KERNEL); 868 if (ah->desc == NULL) { 869 ATH5K_ERR(ah, "can't allocate descriptors\n"); 870 ret = -ENOMEM; 871 goto err; 872 } 873 ds = ah->desc; 874 da = ah->desc_daddr; 875 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 876 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); 877 878 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 879 sizeof(struct ath5k_buf), GFP_KERNEL); 880 if (bf == NULL) { 881 ATH5K_ERR(ah, "can't allocate bufptr\n"); 882 ret = -ENOMEM; 883 goto err_free; 884 } 885 ah->bufptr = bf; 886 887 INIT_LIST_HEAD(&ah->rxbuf); 888 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 889 bf->desc = ds; 890 bf->daddr = da; 891 list_add_tail(&bf->list, &ah->rxbuf); 892 } 893 894 INIT_LIST_HEAD(&ah->txbuf); 895 ah->txbuf_len = ATH_TXBUF; 896 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 897 bf->desc = ds; 898 bf->daddr = da; 899 list_add_tail(&bf->list, &ah->txbuf); 900 } 901 902 /* beacon buffers */ 903 INIT_LIST_HEAD(&ah->bcbuf); 904 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 905 bf->desc = ds; 906 bf->daddr = da; 907 list_add_tail(&bf->list, &ah->bcbuf); 908 } 909 910 return 0; 911 err_free: 912 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 913 err: 914 ah->desc = NULL; 915 return ret; 916 } 917 918 void 919 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 920 { 921 BUG_ON(!bf); 922 if (!bf->skb) 923 return; 924 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, 925 DMA_TO_DEVICE); 926 ieee80211_free_txskb(ah->hw, bf->skb); 927 bf->skb = NULL; 928 bf->skbaddr = 0; 929 bf->desc->ds_data = 0; 930 } 931 932 void 933 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 934 { 935 struct ath_common *common = ath5k_hw_common(ah); 936 937 BUG_ON(!bf); 938 if (!bf->skb) 939 return; 940 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, 941 DMA_FROM_DEVICE); 942 dev_kfree_skb_any(bf->skb); 943 bf->skb = NULL; 944 bf->skbaddr = 0; 945 bf->desc->ds_data = 0; 946 } 947 948 static void 949 ath5k_desc_free(struct ath5k_hw *ah) 950 { 951 struct ath5k_buf *bf; 952 953 list_for_each_entry(bf, &ah->txbuf, list) 954 ath5k_txbuf_free_skb(ah, bf); 955 list_for_each_entry(bf, &ah->rxbuf, list) 956 ath5k_rxbuf_free_skb(ah, bf); 957 list_for_each_entry(bf, &ah->bcbuf, list) 958 ath5k_txbuf_free_skb(ah, bf); 959 960 /* Free memory associated with all descriptors */ 961 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 962 ah->desc = NULL; 963 ah->desc_daddr = 0; 964 965 kfree(ah->bufptr); 966 ah->bufptr = NULL; 967 } 968 969 970 /**************\ 971 * Queues setup * 972 \**************/ 973 974 static struct ath5k_txq * 975 ath5k_txq_setup(struct ath5k_hw *ah, 976 int qtype, int subtype) 977 { 978 struct ath5k_txq *txq; 979 struct ath5k_txq_info qi = { 980 .tqi_subtype = subtype, 981 /* XXX: default values not correct for B and XR channels, 982 * but who cares? */ 983 .tqi_aifs = AR5K_TUNE_AIFS, 984 .tqi_cw_min = AR5K_TUNE_CWMIN, 985 .tqi_cw_max = AR5K_TUNE_CWMAX 986 }; 987 int qnum; 988 989 /* 990 * Enable interrupts only for EOL and DESC conditions. 991 * We mark tx descriptors to receive a DESC interrupt 992 * when a tx queue gets deep; otherwise we wait for the 993 * EOL to reap descriptors. Note that this is done to 994 * reduce interrupt load and this only defers reaping 995 * descriptors, never transmitting frames. Aside from 996 * reducing interrupts this also permits more concurrency. 997 * The only potential downside is if the tx queue backs 998 * up in which case the top half of the kernel may backup 999 * due to a lack of tx descriptors. 1000 */ 1001 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1002 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1003 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1004 if (qnum < 0) { 1005 /* 1006 * NB: don't print a message, this happens 1007 * normally on parts with too few tx queues 1008 */ 1009 return ERR_PTR(qnum); 1010 } 1011 txq = &ah->txqs[qnum]; 1012 if (!txq->setup) { 1013 txq->qnum = qnum; 1014 txq->link = NULL; 1015 INIT_LIST_HEAD(&txq->q); 1016 spin_lock_init(&txq->lock); 1017 txq->setup = true; 1018 txq->txq_len = 0; 1019 txq->txq_max = ATH5K_TXQ_LEN_MAX; 1020 txq->txq_poll_mark = false; 1021 txq->txq_stuck = 0; 1022 } 1023 return &ah->txqs[qnum]; 1024 } 1025 1026 static int 1027 ath5k_beaconq_setup(struct ath5k_hw *ah) 1028 { 1029 struct ath5k_txq_info qi = { 1030 /* XXX: default values not correct for B and XR channels, 1031 * but who cares? */ 1032 .tqi_aifs = AR5K_TUNE_AIFS, 1033 .tqi_cw_min = AR5K_TUNE_CWMIN, 1034 .tqi_cw_max = AR5K_TUNE_CWMAX, 1035 /* NB: for dynamic turbo, don't enable any other interrupts */ 1036 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1037 }; 1038 1039 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1040 } 1041 1042 static int 1043 ath5k_beaconq_config(struct ath5k_hw *ah) 1044 { 1045 struct ath5k_txq_info qi; 1046 int ret; 1047 1048 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); 1049 if (ret) 1050 goto err; 1051 1052 if (ah->opmode == NL80211_IFTYPE_AP || 1053 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1054 /* 1055 * Always burst out beacon and CAB traffic 1056 * (aifs = cwmin = cwmax = 0) 1057 */ 1058 qi.tqi_aifs = 0; 1059 qi.tqi_cw_min = 0; 1060 qi.tqi_cw_max = 0; 1061 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { 1062 /* 1063 * Adhoc mode; backoff between 0 and (2 * cw_min). 1064 */ 1065 qi.tqi_aifs = 0; 1066 qi.tqi_cw_min = 0; 1067 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 1068 } 1069 1070 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1071 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1072 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1073 1074 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); 1075 if (ret) { 1076 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " 1077 "hardware queue!\n", __func__); 1078 goto err; 1079 } 1080 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ 1081 if (ret) 1082 goto err; 1083 1084 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1085 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1086 if (ret) 1087 goto err; 1088 1089 qi.tqi_ready_time = (ah->bintval * 80) / 100; 1090 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1091 if (ret) 1092 goto err; 1093 1094 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1095 err: 1096 return ret; 1097 } 1098 1099 /** 1100 * ath5k_drain_tx_buffs - Empty tx buffers 1101 * 1102 * @ah The &struct ath5k_hw 1103 * 1104 * Empty tx buffers from all queues in preparation 1105 * of a reset or during shutdown. 1106 * 1107 * NB: this assumes output has been stopped and 1108 * we do not need to block ath5k_tx_tasklet 1109 */ 1110 static void 1111 ath5k_drain_tx_buffs(struct ath5k_hw *ah) 1112 { 1113 struct ath5k_txq *txq; 1114 struct ath5k_buf *bf, *bf0; 1115 int i; 1116 1117 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 1118 if (ah->txqs[i].setup) { 1119 txq = &ah->txqs[i]; 1120 spin_lock_bh(&txq->lock); 1121 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1122 ath5k_debug_printtxbuf(ah, bf); 1123 1124 ath5k_txbuf_free_skb(ah, bf); 1125 1126 spin_lock(&ah->txbuflock); 1127 list_move_tail(&bf->list, &ah->txbuf); 1128 ah->txbuf_len++; 1129 txq->txq_len--; 1130 spin_unlock(&ah->txbuflock); 1131 } 1132 txq->link = NULL; 1133 txq->txq_poll_mark = false; 1134 spin_unlock_bh(&txq->lock); 1135 } 1136 } 1137 } 1138 1139 static void 1140 ath5k_txq_release(struct ath5k_hw *ah) 1141 { 1142 struct ath5k_txq *txq = ah->txqs; 1143 unsigned int i; 1144 1145 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) 1146 if (txq->setup) { 1147 ath5k_hw_release_tx_queue(ah, txq->qnum); 1148 txq->setup = false; 1149 } 1150 } 1151 1152 1153 /*************\ 1154 * RX Handling * 1155 \*************/ 1156 1157 /* 1158 * Enable the receive h/w following a reset. 1159 */ 1160 static int 1161 ath5k_rx_start(struct ath5k_hw *ah) 1162 { 1163 struct ath_common *common = ath5k_hw_common(ah); 1164 struct ath5k_buf *bf; 1165 int ret; 1166 1167 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1168 1169 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1170 common->cachelsz, common->rx_bufsize); 1171 1172 spin_lock_bh(&ah->rxbuflock); 1173 ah->rxlink = NULL; 1174 list_for_each_entry(bf, &ah->rxbuf, list) { 1175 ret = ath5k_rxbuf_setup(ah, bf); 1176 if (ret != 0) { 1177 spin_unlock_bh(&ah->rxbuflock); 1178 goto err; 1179 } 1180 } 1181 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1182 ath5k_hw_set_rxdp(ah, bf->daddr); 1183 spin_unlock_bh(&ah->rxbuflock); 1184 1185 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1186 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ 1187 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1188 1189 return 0; 1190 err: 1191 return ret; 1192 } 1193 1194 /* 1195 * Disable the receive logic on PCU (DRU) 1196 * In preparation for a shutdown. 1197 * 1198 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1199 * does. 1200 */ 1201 static void 1202 ath5k_rx_stop(struct ath5k_hw *ah) 1203 { 1204 1205 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1206 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1207 1208 ath5k_debug_printrxbuffs(ah); 1209 } 1210 1211 static unsigned int 1212 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, 1213 struct ath5k_rx_status *rs) 1214 { 1215 struct ath_common *common = ath5k_hw_common(ah); 1216 struct ieee80211_hdr *hdr = (void *)skb->data; 1217 unsigned int keyix, hlen; 1218 1219 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1220 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1221 return RX_FLAG_DECRYPTED; 1222 1223 /* Apparently when a default key is used to decrypt the packet 1224 the hw does not set the index used to decrypt. In such cases 1225 get the index from the packet. */ 1226 hlen = ieee80211_hdrlen(hdr->frame_control); 1227 if (ieee80211_has_protected(hdr->frame_control) && 1228 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1229 skb->len >= hlen + 4) { 1230 keyix = skb->data[hlen + 3] >> 6; 1231 1232 if (test_bit(keyix, common->keymap)) 1233 return RX_FLAG_DECRYPTED; 1234 } 1235 1236 return 0; 1237 } 1238 1239 1240 static void 1241 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, 1242 struct ieee80211_rx_status *rxs) 1243 { 1244 u64 tsf, bc_tstamp; 1245 u32 hw_tu; 1246 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1247 1248 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) { 1249 /* 1250 * Received an IBSS beacon with the same BSSID. Hardware *must* 1251 * have updated the local TSF. We have to work around various 1252 * hardware bugs, though... 1253 */ 1254 tsf = ath5k_hw_get_tsf64(ah); 1255 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1256 hw_tu = TSF_TO_TU(tsf); 1257 1258 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1259 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1260 (unsigned long long)bc_tstamp, 1261 (unsigned long long)rxs->mactime, 1262 (unsigned long long)(rxs->mactime - bc_tstamp), 1263 (unsigned long long)tsf); 1264 1265 /* 1266 * Sometimes the HW will give us a wrong tstamp in the rx 1267 * status, causing the timestamp extension to go wrong. 1268 * (This seems to happen especially with beacon frames bigger 1269 * than 78 byte (incl. FCS)) 1270 * But we know that the receive timestamp must be later than the 1271 * timestamp of the beacon since HW must have synced to that. 1272 * 1273 * NOTE: here we assume mactime to be after the frame was 1274 * received, not like mac80211 which defines it at the start. 1275 */ 1276 if (bc_tstamp > rxs->mactime) { 1277 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1278 "fixing mactime from %llx to %llx\n", 1279 (unsigned long long)rxs->mactime, 1280 (unsigned long long)tsf); 1281 rxs->mactime = tsf; 1282 } 1283 1284 /* 1285 * Local TSF might have moved higher than our beacon timers, 1286 * in that case we have to update them to continue sending 1287 * beacons. This also takes care of synchronizing beacon sending 1288 * times with other stations. 1289 */ 1290 if (hw_tu >= ah->nexttbtt) 1291 ath5k_beacon_update_timers(ah, bc_tstamp); 1292 1293 /* Check if the beacon timers are still correct, because a TSF 1294 * update might have created a window between them - for a 1295 * longer description see the comment of this function: */ 1296 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { 1297 ath5k_beacon_update_timers(ah, bc_tstamp); 1298 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1299 "fixed beacon timers after beacon receive\n"); 1300 } 1301 } 1302 } 1303 1304 /* 1305 * Compute padding position. skb must contain an IEEE 802.11 frame 1306 */ 1307 static int ath5k_common_padpos(struct sk_buff *skb) 1308 { 1309 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1310 __le16 frame_control = hdr->frame_control; 1311 int padpos = 24; 1312 1313 if (ieee80211_has_a4(frame_control)) 1314 padpos += ETH_ALEN; 1315 1316 if (ieee80211_is_data_qos(frame_control)) 1317 padpos += IEEE80211_QOS_CTL_LEN; 1318 1319 return padpos; 1320 } 1321 1322 /* 1323 * This function expects an 802.11 frame and returns the number of 1324 * bytes added, or -1 if we don't have enough header room. 1325 */ 1326 static int ath5k_add_padding(struct sk_buff *skb) 1327 { 1328 int padpos = ath5k_common_padpos(skb); 1329 int padsize = padpos & 3; 1330 1331 if (padsize && skb->len > padpos) { 1332 1333 if (skb_headroom(skb) < padsize) 1334 return -1; 1335 1336 skb_push(skb, padsize); 1337 memmove(skb->data, skb->data + padsize, padpos); 1338 return padsize; 1339 } 1340 1341 return 0; 1342 } 1343 1344 /* 1345 * The MAC header is padded to have 32-bit boundary if the 1346 * packet payload is non-zero. The general calculation for 1347 * padsize would take into account odd header lengths: 1348 * padsize = 4 - (hdrlen & 3); however, since only 1349 * even-length headers are used, padding can only be 0 or 2 1350 * bytes and we can optimize this a bit. We must not try to 1351 * remove padding from short control frames that do not have a 1352 * payload. 1353 * 1354 * This function expects an 802.11 frame and returns the number of 1355 * bytes removed. 1356 */ 1357 static int ath5k_remove_padding(struct sk_buff *skb) 1358 { 1359 int padpos = ath5k_common_padpos(skb); 1360 int padsize = padpos & 3; 1361 1362 if (padsize && skb->len >= padpos + padsize) { 1363 memmove(skb->data + padsize, skb->data, padpos); 1364 skb_pull(skb, padsize); 1365 return padsize; 1366 } 1367 1368 return 0; 1369 } 1370 1371 static void 1372 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, 1373 struct ath5k_rx_status *rs) 1374 { 1375 struct ieee80211_rx_status *rxs; 1376 struct ath_common *common = ath5k_hw_common(ah); 1377 1378 ath5k_remove_padding(skb); 1379 1380 rxs = IEEE80211_SKB_RXCB(skb); 1381 1382 rxs->flag = 0; 1383 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1384 rxs->flag |= RX_FLAG_MMIC_ERROR; 1385 if (unlikely(rs->rs_status & AR5K_RXERR_CRC)) 1386 rxs->flag |= RX_FLAG_FAILED_FCS_CRC; 1387 1388 1389 /* 1390 * always extend the mac timestamp, since this information is 1391 * also needed for proper IBSS merging. 1392 * 1393 * XXX: it might be too late to do it here, since rs_tstamp is 1394 * 15bit only. that means TSF extension has to be done within 1395 * 32768usec (about 32ms). it might be necessary to move this to 1396 * the interrupt handler, like it is done in madwifi. 1397 */ 1398 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); 1399 rxs->flag |= RX_FLAG_MACTIME_END; 1400 1401 rxs->freq = ah->curchan->center_freq; 1402 rxs->band = ah->curchan->band; 1403 1404 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; 1405 1406 rxs->antenna = rs->rs_antenna; 1407 1408 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1409 ah->stats.antenna_rx[rs->rs_antenna]++; 1410 else 1411 ah->stats.antenna_rx[0]++; /* invalid */ 1412 1413 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); 1414 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); 1415 switch (ah->ah_bwmode) { 1416 case AR5K_BWMODE_5MHZ: 1417 rxs->bw = RATE_INFO_BW_5; 1418 break; 1419 case AR5K_BWMODE_10MHZ: 1420 rxs->bw = RATE_INFO_BW_10; 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 if (rs->rs_rate == 1427 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1428 rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE; 1429 1430 trace_ath5k_rx(ah, skb); 1431 1432 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) { 1433 ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); 1434 1435 /* check beacons in IBSS mode */ 1436 if (ah->opmode == NL80211_IFTYPE_ADHOC) 1437 ath5k_check_ibss_tsf(ah, skb, rxs); 1438 } 1439 1440 ieee80211_rx(ah->hw, skb); 1441 } 1442 1443 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1444 * 1445 * Check if we want to further process this frame or not. Also update 1446 * statistics. Return true if we want this frame, false if not. 1447 */ 1448 static bool 1449 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) 1450 { 1451 ah->stats.rx_all_count++; 1452 ah->stats.rx_bytes_count += rs->rs_datalen; 1453 1454 if (unlikely(rs->rs_status)) { 1455 unsigned int filters; 1456 1457 if (rs->rs_status & AR5K_RXERR_CRC) 1458 ah->stats.rxerr_crc++; 1459 if (rs->rs_status & AR5K_RXERR_FIFO) 1460 ah->stats.rxerr_fifo++; 1461 if (rs->rs_status & AR5K_RXERR_PHY) { 1462 ah->stats.rxerr_phy++; 1463 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1464 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; 1465 1466 /* 1467 * Treat packets that underwent a CCK or OFDM reset as having a bad CRC. 1468 * These restarts happen when the radio resynchronizes to a stronger frame 1469 * while receiving a weaker frame. Here we receive the prefix of the weak 1470 * frame. Since these are incomplete packets, mark their CRC as invalid. 1471 */ 1472 if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART || 1473 rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) { 1474 rs->rs_status |= AR5K_RXERR_CRC; 1475 rs->rs_status &= ~AR5K_RXERR_PHY; 1476 } else { 1477 return false; 1478 } 1479 } 1480 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1481 /* 1482 * Decrypt error. If the error occurred 1483 * because there was no hardware key, then 1484 * let the frame through so the upper layers 1485 * can process it. This is necessary for 5210 1486 * parts which have no way to setup a ``clear'' 1487 * key cache entry. 1488 * 1489 * XXX do key cache faulting 1490 */ 1491 ah->stats.rxerr_decrypt++; 1492 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1493 !(rs->rs_status & AR5K_RXERR_CRC)) 1494 return true; 1495 } 1496 if (rs->rs_status & AR5K_RXERR_MIC) { 1497 ah->stats.rxerr_mic++; 1498 return true; 1499 } 1500 1501 /* 1502 * Reject any frames with non-crypto errors, and take into account the 1503 * current FIF_* filters. 1504 */ 1505 filters = AR5K_RXERR_DECRYPT; 1506 if (ah->fif_filter_flags & FIF_FCSFAIL) 1507 filters |= AR5K_RXERR_CRC; 1508 1509 if (rs->rs_status & ~filters) 1510 return false; 1511 } 1512 1513 if (unlikely(rs->rs_more)) { 1514 ah->stats.rxerr_jumbo++; 1515 return false; 1516 } 1517 return true; 1518 } 1519 1520 static void 1521 ath5k_set_current_imask(struct ath5k_hw *ah) 1522 { 1523 enum ath5k_int imask; 1524 unsigned long flags; 1525 1526 if (test_bit(ATH_STAT_RESET, ah->status)) 1527 return; 1528 1529 spin_lock_irqsave(&ah->irqlock, flags); 1530 imask = ah->imask; 1531 if (ah->rx_pending) 1532 imask &= ~AR5K_INT_RX_ALL; 1533 if (ah->tx_pending) 1534 imask &= ~AR5K_INT_TX_ALL; 1535 ath5k_hw_set_imr(ah, imask); 1536 spin_unlock_irqrestore(&ah->irqlock, flags); 1537 } 1538 1539 static void 1540 ath5k_tasklet_rx(unsigned long data) 1541 { 1542 struct ath5k_rx_status rs = {}; 1543 struct sk_buff *skb, *next_skb; 1544 dma_addr_t next_skb_addr; 1545 struct ath5k_hw *ah = (void *)data; 1546 struct ath_common *common = ath5k_hw_common(ah); 1547 struct ath5k_buf *bf; 1548 struct ath5k_desc *ds; 1549 int ret; 1550 1551 spin_lock(&ah->rxbuflock); 1552 if (list_empty(&ah->rxbuf)) { 1553 ATH5K_WARN(ah, "empty rx buf pool\n"); 1554 goto unlock; 1555 } 1556 do { 1557 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1558 BUG_ON(bf->skb == NULL); 1559 skb = bf->skb; 1560 ds = bf->desc; 1561 1562 /* bail if HW is still using self-linked descriptor */ 1563 if (ath5k_hw_get_rxdp(ah) == bf->daddr) 1564 break; 1565 1566 ret = ah->ah_proc_rx_desc(ah, ds, &rs); 1567 if (unlikely(ret == -EINPROGRESS)) 1568 break; 1569 else if (unlikely(ret)) { 1570 ATH5K_ERR(ah, "error in processing rx descriptor\n"); 1571 ah->stats.rxerr_proc++; 1572 break; 1573 } 1574 1575 if (ath5k_receive_frame_ok(ah, &rs)) { 1576 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); 1577 1578 /* 1579 * If we can't replace bf->skb with a new skb under 1580 * memory pressure, just skip this packet 1581 */ 1582 if (!next_skb) 1583 goto next; 1584 1585 dma_unmap_single(ah->dev, bf->skbaddr, 1586 common->rx_bufsize, 1587 DMA_FROM_DEVICE); 1588 1589 skb_put(skb, rs.rs_datalen); 1590 1591 ath5k_receive_frame(ah, skb, &rs); 1592 1593 bf->skb = next_skb; 1594 bf->skbaddr = next_skb_addr; 1595 } 1596 next: 1597 list_move_tail(&bf->list, &ah->rxbuf); 1598 } while (ath5k_rxbuf_setup(ah, bf) == 0); 1599 unlock: 1600 spin_unlock(&ah->rxbuflock); 1601 ah->rx_pending = false; 1602 ath5k_set_current_imask(ah); 1603 } 1604 1605 1606 /*************\ 1607 * TX Handling * 1608 \*************/ 1609 1610 void 1611 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1612 struct ath5k_txq *txq, struct ieee80211_tx_control *control) 1613 { 1614 struct ath5k_hw *ah = hw->priv; 1615 struct ath5k_buf *bf; 1616 unsigned long flags; 1617 int padsize; 1618 1619 trace_ath5k_tx(ah, skb, txq); 1620 1621 /* 1622 * The hardware expects the header padded to 4 byte boundaries. 1623 * If this is not the case, we add the padding after the header. 1624 */ 1625 padsize = ath5k_add_padding(skb); 1626 if (padsize < 0) { 1627 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" 1628 " headroom to pad"); 1629 goto drop_packet; 1630 } 1631 1632 if (txq->txq_len >= txq->txq_max && 1633 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1634 ieee80211_stop_queue(hw, txq->qnum); 1635 1636 spin_lock_irqsave(&ah->txbuflock, flags); 1637 if (list_empty(&ah->txbuf)) { 1638 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); 1639 spin_unlock_irqrestore(&ah->txbuflock, flags); 1640 ieee80211_stop_queues(hw); 1641 goto drop_packet; 1642 } 1643 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); 1644 list_del(&bf->list); 1645 ah->txbuf_len--; 1646 if (list_empty(&ah->txbuf)) 1647 ieee80211_stop_queues(hw); 1648 spin_unlock_irqrestore(&ah->txbuflock, flags); 1649 1650 bf->skb = skb; 1651 1652 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { 1653 bf->skb = NULL; 1654 spin_lock_irqsave(&ah->txbuflock, flags); 1655 list_add_tail(&bf->list, &ah->txbuf); 1656 ah->txbuf_len++; 1657 spin_unlock_irqrestore(&ah->txbuflock, flags); 1658 goto drop_packet; 1659 } 1660 return; 1661 1662 drop_packet: 1663 ieee80211_free_txskb(hw, skb); 1664 } 1665 1666 static void 1667 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, 1668 struct ath5k_txq *txq, struct ath5k_tx_status *ts, 1669 struct ath5k_buf *bf) 1670 { 1671 struct ieee80211_tx_info *info; 1672 u8 tries[3]; 1673 int i; 1674 int size = 0; 1675 1676 ah->stats.tx_all_count++; 1677 ah->stats.tx_bytes_count += skb->len; 1678 info = IEEE80211_SKB_CB(skb); 1679 1680 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates)); 1681 memcpy(info->status.rates, bf->rates, size); 1682 1683 tries[0] = info->status.rates[0].count; 1684 tries[1] = info->status.rates[1].count; 1685 tries[2] = info->status.rates[2].count; 1686 1687 ieee80211_tx_info_clear_status(info); 1688 1689 for (i = 0; i < ts->ts_final_idx; i++) { 1690 struct ieee80211_tx_rate *r = 1691 &info->status.rates[i]; 1692 1693 r->count = tries[i]; 1694 } 1695 1696 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1697 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1698 1699 if (unlikely(ts->ts_status)) { 1700 ah->stats.ack_fail++; 1701 if (ts->ts_status & AR5K_TXERR_FILT) { 1702 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1703 ah->stats.txerr_filt++; 1704 } 1705 if (ts->ts_status & AR5K_TXERR_XRETRY) 1706 ah->stats.txerr_retry++; 1707 if (ts->ts_status & AR5K_TXERR_FIFO) 1708 ah->stats.txerr_fifo++; 1709 } else { 1710 info->flags |= IEEE80211_TX_STAT_ACK; 1711 info->status.ack_signal = ts->ts_rssi; 1712 1713 /* count the successful attempt as well */ 1714 info->status.rates[ts->ts_final_idx].count++; 1715 } 1716 1717 /* 1718 * Remove MAC header padding before giving the frame 1719 * back to mac80211. 1720 */ 1721 ath5k_remove_padding(skb); 1722 1723 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1724 ah->stats.antenna_tx[ts->ts_antenna]++; 1725 else 1726 ah->stats.antenna_tx[0]++; /* invalid */ 1727 1728 trace_ath5k_tx_complete(ah, skb, txq, ts); 1729 ieee80211_tx_status(ah->hw, skb); 1730 } 1731 1732 static void 1733 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) 1734 { 1735 struct ath5k_tx_status ts = {}; 1736 struct ath5k_buf *bf, *bf0; 1737 struct ath5k_desc *ds; 1738 struct sk_buff *skb; 1739 int ret; 1740 1741 spin_lock(&txq->lock); 1742 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1743 1744 txq->txq_poll_mark = false; 1745 1746 /* skb might already have been processed last time. */ 1747 if (bf->skb != NULL) { 1748 ds = bf->desc; 1749 1750 ret = ah->ah_proc_tx_desc(ah, ds, &ts); 1751 if (unlikely(ret == -EINPROGRESS)) 1752 break; 1753 else if (unlikely(ret)) { 1754 ATH5K_ERR(ah, 1755 "error %d while processing " 1756 "queue %u\n", ret, txq->qnum); 1757 break; 1758 } 1759 1760 skb = bf->skb; 1761 bf->skb = NULL; 1762 1763 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, 1764 DMA_TO_DEVICE); 1765 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); 1766 } 1767 1768 /* 1769 * It's possible that the hardware can say the buffer is 1770 * completed when it hasn't yet loaded the ds_link from 1771 * host memory and moved on. 1772 * Always keep the last descriptor to avoid HW races... 1773 */ 1774 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { 1775 spin_lock(&ah->txbuflock); 1776 list_move_tail(&bf->list, &ah->txbuf); 1777 ah->txbuf_len++; 1778 txq->txq_len--; 1779 spin_unlock(&ah->txbuflock); 1780 } 1781 } 1782 spin_unlock(&txq->lock); 1783 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1784 ieee80211_wake_queue(ah->hw, txq->qnum); 1785 } 1786 1787 static void 1788 ath5k_tasklet_tx(unsigned long data) 1789 { 1790 int i; 1791 struct ath5k_hw *ah = (void *)data; 1792 1793 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1794 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) 1795 ath5k_tx_processq(ah, &ah->txqs[i]); 1796 1797 ah->tx_pending = false; 1798 ath5k_set_current_imask(ah); 1799 } 1800 1801 1802 /*****************\ 1803 * Beacon handling * 1804 \*****************/ 1805 1806 /* 1807 * Setup the beacon frame for transmit. 1808 */ 1809 static int 1810 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 1811 { 1812 struct sk_buff *skb = bf->skb; 1813 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1814 struct ath5k_desc *ds; 1815 int ret = 0; 1816 u8 antenna; 1817 u32 flags; 1818 const int padsize = 0; 1819 1820 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 1821 DMA_TO_DEVICE); 1822 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1823 "skbaddr %llx\n", skb, skb->data, skb->len, 1824 (unsigned long long)bf->skbaddr); 1825 1826 if (dma_mapping_error(ah->dev, bf->skbaddr)) { 1827 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); 1828 dev_kfree_skb_any(skb); 1829 bf->skb = NULL; 1830 return -EIO; 1831 } 1832 1833 ds = bf->desc; 1834 antenna = ah->ah_tx_ant; 1835 1836 flags = AR5K_TXDESC_NOACK; 1837 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1838 ds->ds_link = bf->daddr; /* self-linked */ 1839 flags |= AR5K_TXDESC_VEOL; 1840 } else 1841 ds->ds_link = 0; 1842 1843 /* 1844 * If we use multiple antennas on AP and use 1845 * the Sectored AP scenario, switch antenna every 1846 * 4 beacons to make sure everybody hears our AP. 1847 * When a client tries to associate, hw will keep 1848 * track of the tx antenna to be used for this client 1849 * automatically, based on ACKed packets. 1850 * 1851 * Note: AP still listens and transmits RTS on the 1852 * default antenna which is supposed to be an omni. 1853 * 1854 * Note2: On sectored scenarios it's possible to have 1855 * multiple antennas (1 omni -- the default -- and 14 1856 * sectors), so if we choose to actually support this 1857 * mode, we need to allow the user to set how many antennas 1858 * we have and tweak the code below to send beacons 1859 * on all of them. 1860 */ 1861 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1862 antenna = ah->bsent & 4 ? 2 : 1; 1863 1864 1865 /* FIXME: If we are in g mode and rate is a CCK rate 1866 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1867 * from tx power (value is in dB units already) */ 1868 ds->ds_data = bf->skbaddr; 1869 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1870 ieee80211_get_hdrlen_from_skb(skb), padsize, 1871 AR5K_PKT_TYPE_BEACON, 1872 (ah->ah_txpower.txp_requested * 2), 1873 ieee80211_get_tx_rate(ah->hw, info)->hw_value, 1874 1, AR5K_TXKEYIX_INVALID, 1875 antenna, flags, 0, 0); 1876 if (ret) 1877 goto err_unmap; 1878 1879 return 0; 1880 err_unmap: 1881 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1882 return ret; 1883 } 1884 1885 /* 1886 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1887 * this is called only once at config_bss time, for AP we do it every 1888 * SWBA interrupt so that the TIM will reflect buffered frames. 1889 * 1890 * Called with the beacon lock. 1891 */ 1892 int 1893 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1894 { 1895 int ret; 1896 struct ath5k_hw *ah = hw->priv; 1897 struct ath5k_vif *avf; 1898 struct sk_buff *skb; 1899 1900 if (WARN_ON(!vif)) { 1901 ret = -EINVAL; 1902 goto out; 1903 } 1904 1905 skb = ieee80211_beacon_get(hw, vif); 1906 1907 if (!skb) { 1908 ret = -ENOMEM; 1909 goto out; 1910 } 1911 1912 avf = (void *)vif->drv_priv; 1913 ath5k_txbuf_free_skb(ah, avf->bbuf); 1914 avf->bbuf->skb = skb; 1915 ret = ath5k_beacon_setup(ah, avf->bbuf); 1916 out: 1917 return ret; 1918 } 1919 1920 /* 1921 * Transmit a beacon frame at SWBA. Dynamic updates to the 1922 * frame contents are done as needed and the slot time is 1923 * also adjusted based on current state. 1924 * 1925 * This is called from software irq context (beacontq tasklets) 1926 * or user context from ath5k_beacon_config. 1927 */ 1928 static void 1929 ath5k_beacon_send(struct ath5k_hw *ah) 1930 { 1931 struct ieee80211_vif *vif; 1932 struct ath5k_vif *avf; 1933 struct ath5k_buf *bf; 1934 struct sk_buff *skb; 1935 int err; 1936 1937 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1938 1939 /* 1940 * Check if the previous beacon has gone out. If 1941 * not, don't don't try to post another: skip this 1942 * period and wait for the next. Missed beacons 1943 * indicate a problem and should not occur. If we 1944 * miss too many consecutive beacons reset the device. 1945 */ 1946 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { 1947 ah->bmisscount++; 1948 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1949 "missed %u consecutive beacons\n", ah->bmisscount); 1950 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ 1951 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1952 "stuck beacon time (%u missed)\n", 1953 ah->bmisscount); 1954 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 1955 "stuck beacon, resetting\n"); 1956 ieee80211_queue_work(ah->hw, &ah->reset_work); 1957 } 1958 return; 1959 } 1960 if (unlikely(ah->bmisscount != 0)) { 1961 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1962 "resume beacon xmit after %u misses\n", 1963 ah->bmisscount); 1964 ah->bmisscount = 0; 1965 } 1966 1967 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + 1968 ah->num_mesh_vifs > 1) || 1969 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1970 u64 tsf = ath5k_hw_get_tsf64(ah); 1971 u32 tsftu = TSF_TO_TU(tsf); 1972 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; 1973 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; 1974 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1975 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1976 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); 1977 } else /* only one interface */ 1978 vif = ah->bslot[0]; 1979 1980 if (!vif) 1981 return; 1982 1983 avf = (void *)vif->drv_priv; 1984 bf = avf->bbuf; 1985 1986 /* 1987 * Stop any current dma and put the new frame on the queue. 1988 * This should never fail since we check above that no frames 1989 * are still pending on the queue. 1990 */ 1991 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { 1992 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); 1993 /* NB: hw still stops DMA, so proceed */ 1994 } 1995 1996 /* refresh the beacon for AP or MESH mode */ 1997 if (ah->opmode == NL80211_IFTYPE_AP || 1998 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1999 err = ath5k_beacon_update(ah->hw, vif); 2000 if (err) 2001 return; 2002 } 2003 2004 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || 2005 ah->opmode == NL80211_IFTYPE_MONITOR)) { 2006 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); 2007 return; 2008 } 2009 2010 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); 2011 2012 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); 2013 ath5k_hw_start_tx_dma(ah, ah->bhalq); 2014 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2015 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); 2016 2017 skb = ieee80211_get_buffered_bc(ah->hw, vif); 2018 while (skb) { 2019 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); 2020 2021 if (ah->cabq->txq_len >= ah->cabq->txq_max) 2022 break; 2023 2024 skb = ieee80211_get_buffered_bc(ah->hw, vif); 2025 } 2026 2027 ah->bsent++; 2028 } 2029 2030 /** 2031 * ath5k_beacon_update_timers - update beacon timers 2032 * 2033 * @ah: struct ath5k_hw pointer we are operating on 2034 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2035 * beacon timer update based on the current HW TSF. 2036 * 2037 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2038 * of a received beacon or the current local hardware TSF and write it to the 2039 * beacon timer registers. 2040 * 2041 * This is called in a variety of situations, e.g. when a beacon is received, 2042 * when a TSF update has been detected, but also when an new IBSS is created or 2043 * when we otherwise know we have to update the timers, but we keep it in this 2044 * function to have it all together in one place. 2045 */ 2046 void 2047 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) 2048 { 2049 u32 nexttbtt, intval, hw_tu, bc_tu; 2050 u64 hw_tsf; 2051 2052 intval = ah->bintval & AR5K_BEACON_PERIOD; 2053 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs 2054 + ah->num_mesh_vifs > 1) { 2055 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 2056 if (intval < 15) 2057 ATH5K_WARN(ah, "intval %u is too low, min 15\n", 2058 intval); 2059 } 2060 if (WARN_ON(!intval)) 2061 return; 2062 2063 /* beacon TSF converted to TU */ 2064 bc_tu = TSF_TO_TU(bc_tsf); 2065 2066 /* current TSF converted to TU */ 2067 hw_tsf = ath5k_hw_get_tsf64(ah); 2068 hw_tu = TSF_TO_TU(hw_tsf); 2069 2070 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 2071 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 2072 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 2073 * configuration we need to make sure it is bigger than that. */ 2074 2075 if (bc_tsf == -1) { 2076 /* 2077 * no beacons received, called internally. 2078 * just need to refresh timers based on HW TSF. 2079 */ 2080 nexttbtt = roundup(hw_tu + FUDGE, intval); 2081 } else if (bc_tsf == 0) { 2082 /* 2083 * no beacon received, probably called by ath5k_reset_tsf(). 2084 * reset TSF to start with 0. 2085 */ 2086 nexttbtt = intval; 2087 intval |= AR5K_BEACON_RESET_TSF; 2088 } else if (bc_tsf > hw_tsf) { 2089 /* 2090 * beacon received, SW merge happened but HW TSF not yet updated. 2091 * not possible to reconfigure timers yet, but next time we 2092 * receive a beacon with the same BSSID, the hardware will 2093 * automatically update the TSF and then we need to reconfigure 2094 * the timers. 2095 */ 2096 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2097 "need to wait for HW TSF sync\n"); 2098 return; 2099 } else { 2100 /* 2101 * most important case for beacon synchronization between STA. 2102 * 2103 * beacon received and HW TSF has been already updated by HW. 2104 * update next TBTT based on the TSF of the beacon, but make 2105 * sure it is ahead of our local TSF timer. 2106 */ 2107 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2108 } 2109 #undef FUDGE 2110 2111 ah->nexttbtt = nexttbtt; 2112 2113 intval |= AR5K_BEACON_ENA; 2114 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); 2115 2116 /* 2117 * debugging output last in order to preserve the time critical aspect 2118 * of this function 2119 */ 2120 if (bc_tsf == -1) 2121 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2122 "reconfigured timers based on HW TSF\n"); 2123 else if (bc_tsf == 0) 2124 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2125 "reset HW TSF and timers\n"); 2126 else 2127 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2128 "updated timers based on beacon TSF\n"); 2129 2130 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2131 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2132 (unsigned long long) bc_tsf, 2133 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2134 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2135 intval & AR5K_BEACON_PERIOD, 2136 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2137 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2138 } 2139 2140 /** 2141 * ath5k_beacon_config - Configure the beacon queues and interrupts 2142 * 2143 * @ah: struct ath5k_hw pointer we are operating on 2144 * 2145 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2146 * interrupts to detect TSF updates only. 2147 */ 2148 void 2149 ath5k_beacon_config(struct ath5k_hw *ah) 2150 { 2151 spin_lock_bh(&ah->block); 2152 ah->bmisscount = 0; 2153 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2154 2155 if (ah->enable_beacon) { 2156 /* 2157 * In IBSS mode we use a self-linked tx descriptor and let the 2158 * hardware send the beacons automatically. We have to load it 2159 * only once here. 2160 * We use the SWBA interrupt only to keep track of the beacon 2161 * timers in order to detect automatic TSF updates. 2162 */ 2163 ath5k_beaconq_config(ah); 2164 2165 ah->imask |= AR5K_INT_SWBA; 2166 2167 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2168 if (ath5k_hw_hasveol(ah)) 2169 ath5k_beacon_send(ah); 2170 } else 2171 ath5k_beacon_update_timers(ah, -1); 2172 } else { 2173 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); 2174 } 2175 2176 ath5k_hw_set_imr(ah, ah->imask); 2177 mmiowb(); 2178 spin_unlock_bh(&ah->block); 2179 } 2180 2181 static void ath5k_tasklet_beacon(unsigned long data) 2182 { 2183 struct ath5k_hw *ah = (struct ath5k_hw *) data; 2184 2185 /* 2186 * Software beacon alert--time to send a beacon. 2187 * 2188 * In IBSS mode we use this interrupt just to 2189 * keep track of the next TBTT (target beacon 2190 * transmission time) in order to detect whether 2191 * automatic TSF updates happened. 2192 */ 2193 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2194 /* XXX: only if VEOL supported */ 2195 u64 tsf = ath5k_hw_get_tsf64(ah); 2196 ah->nexttbtt += ah->bintval; 2197 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2198 "SWBA nexttbtt: %x hw_tu: %x " 2199 "TSF: %llx\n", 2200 ah->nexttbtt, 2201 TSF_TO_TU(tsf), 2202 (unsigned long long) tsf); 2203 } else { 2204 spin_lock(&ah->block); 2205 ath5k_beacon_send(ah); 2206 spin_unlock(&ah->block); 2207 } 2208 } 2209 2210 2211 /********************\ 2212 * Interrupt handling * 2213 \********************/ 2214 2215 static void 2216 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2217 { 2218 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2219 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2220 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2221 2222 /* Run ANI only when calibration is not active */ 2223 2224 ah->ah_cal_next_ani = jiffies + 2225 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2226 tasklet_schedule(&ah->ani_tasklet); 2227 2228 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && 2229 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2230 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2231 2232 /* Run calibration only when another calibration 2233 * is not running. 2234 * 2235 * Note: This is for both full/short calibration, 2236 * if it's time for a full one, ath5k_calibrate_work will deal 2237 * with it. */ 2238 2239 ah->ah_cal_next_short = jiffies + 2240 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2241 ieee80211_queue_work(ah->hw, &ah->calib_work); 2242 } 2243 /* we could use SWI to generate enough interrupts to meet our 2244 * calibration interval requirements, if necessary: 2245 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2246 } 2247 2248 static void 2249 ath5k_schedule_rx(struct ath5k_hw *ah) 2250 { 2251 ah->rx_pending = true; 2252 tasklet_schedule(&ah->rxtq); 2253 } 2254 2255 static void 2256 ath5k_schedule_tx(struct ath5k_hw *ah) 2257 { 2258 ah->tx_pending = true; 2259 tasklet_schedule(&ah->txtq); 2260 } 2261 2262 static irqreturn_t 2263 ath5k_intr(int irq, void *dev_id) 2264 { 2265 struct ath5k_hw *ah = dev_id; 2266 enum ath5k_int status; 2267 unsigned int counter = 1000; 2268 2269 2270 /* 2271 * If hw is not ready (or detached) and we get an 2272 * interrupt, or if we have no interrupts pending 2273 * (that means it's not for us) skip it. 2274 * 2275 * NOTE: Group 0/1 PCI interface registers are not 2276 * supported on WiSOCs, so we can't check for pending 2277 * interrupts (ISR belongs to another register group 2278 * so we are ok). 2279 */ 2280 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || 2281 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2282 !ath5k_hw_is_intr_pending(ah)))) 2283 return IRQ_NONE; 2284 2285 /** Main loop **/ 2286 do { 2287 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2288 2289 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2290 status, ah->imask); 2291 2292 /* 2293 * Fatal hw error -> Log and reset 2294 * 2295 * Fatal errors are unrecoverable so we have to 2296 * reset the card. These errors include bus and 2297 * dma errors. 2298 */ 2299 if (unlikely(status & AR5K_INT_FATAL)) { 2300 2301 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2302 "fatal int, resetting\n"); 2303 ieee80211_queue_work(ah->hw, &ah->reset_work); 2304 2305 /* 2306 * RX Overrun -> Count and reset if needed 2307 * 2308 * Receive buffers are full. Either the bus is busy or 2309 * the CPU is not fast enough to process all received 2310 * frames. 2311 */ 2312 } else if (unlikely(status & AR5K_INT_RXORN)) { 2313 2314 /* 2315 * Older chipsets need a reset to come out of this 2316 * condition, but we treat it as RX for newer chips. 2317 * We don't know exactly which versions need a reset 2318 * this guess is copied from the HAL. 2319 */ 2320 ah->stats.rxorn_intr++; 2321 2322 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2323 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2324 "rx overrun, resetting\n"); 2325 ieee80211_queue_work(ah->hw, &ah->reset_work); 2326 } else 2327 ath5k_schedule_rx(ah); 2328 2329 } else { 2330 2331 /* Software Beacon Alert -> Schedule beacon tasklet */ 2332 if (status & AR5K_INT_SWBA) 2333 tasklet_hi_schedule(&ah->beacontq); 2334 2335 /* 2336 * No more RX descriptors -> Just count 2337 * 2338 * NB: the hardware should re-read the link when 2339 * RXE bit is written, but it doesn't work at 2340 * least on older hardware revs. 2341 */ 2342 if (status & AR5K_INT_RXEOL) 2343 ah->stats.rxeol_intr++; 2344 2345 2346 /* TX Underrun -> Bump tx trigger level */ 2347 if (status & AR5K_INT_TXURN) 2348 ath5k_hw_update_tx_triglevel(ah, true); 2349 2350 /* RX -> Schedule rx tasklet */ 2351 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2352 ath5k_schedule_rx(ah); 2353 2354 /* TX -> Schedule tx tasklet */ 2355 if (status & (AR5K_INT_TXOK 2356 | AR5K_INT_TXDESC 2357 | AR5K_INT_TXERR 2358 | AR5K_INT_TXEOL)) 2359 ath5k_schedule_tx(ah); 2360 2361 /* Missed beacon -> TODO 2362 if (status & AR5K_INT_BMISS) 2363 */ 2364 2365 /* MIB event -> Update counters and notify ANI */ 2366 if (status & AR5K_INT_MIB) { 2367 ah->stats.mib_intr++; 2368 ath5k_hw_update_mib_counters(ah); 2369 ath5k_ani_mib_intr(ah); 2370 } 2371 2372 /* GPIO -> Notify RFKill layer */ 2373 if (status & AR5K_INT_GPIO) 2374 tasklet_schedule(&ah->rf_kill.toggleq); 2375 2376 } 2377 2378 if (ath5k_get_bus_type(ah) == ATH_AHB) 2379 break; 2380 2381 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2382 2383 /* 2384 * Until we handle rx/tx interrupts mask them on IMR 2385 * 2386 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets 2387 * and unset after we 've handled the interrupts. 2388 */ 2389 if (ah->rx_pending || ah->tx_pending) 2390 ath5k_set_current_imask(ah); 2391 2392 if (unlikely(!counter)) 2393 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); 2394 2395 /* Fire up calibration poll */ 2396 ath5k_intr_calibration_poll(ah); 2397 2398 return IRQ_HANDLED; 2399 } 2400 2401 /* 2402 * Periodically recalibrate the PHY to account 2403 * for temperature/environment changes. 2404 */ 2405 static void 2406 ath5k_calibrate_work(struct work_struct *work) 2407 { 2408 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2409 calib_work); 2410 2411 /* Should we run a full calibration ? */ 2412 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2413 2414 ah->ah_cal_next_full = jiffies + 2415 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2416 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2417 2418 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 2419 "running full calibration\n"); 2420 2421 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2422 /* 2423 * Rfgain is out of bounds, reset the chip 2424 * to load new gain values. 2425 */ 2426 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2427 "got new rfgain, resetting\n"); 2428 ieee80211_queue_work(ah->hw, &ah->reset_work); 2429 } 2430 } else 2431 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; 2432 2433 2434 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2435 ieee80211_frequency_to_channel(ah->curchan->center_freq), 2436 ah->curchan->hw_value); 2437 2438 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) 2439 ATH5K_ERR(ah, "calibration of channel %u failed\n", 2440 ieee80211_frequency_to_channel( 2441 ah->curchan->center_freq)); 2442 2443 /* Clear calibration flags */ 2444 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) 2445 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2446 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) 2447 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; 2448 } 2449 2450 2451 static void 2452 ath5k_tasklet_ani(unsigned long data) 2453 { 2454 struct ath5k_hw *ah = (void *)data; 2455 2456 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2457 ath5k_ani_calibration(ah); 2458 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2459 } 2460 2461 2462 static void 2463 ath5k_tx_complete_poll_work(struct work_struct *work) 2464 { 2465 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2466 tx_complete_work.work); 2467 struct ath5k_txq *txq; 2468 int i; 2469 bool needreset = false; 2470 2471 if (!test_bit(ATH_STAT_STARTED, ah->status)) 2472 return; 2473 2474 mutex_lock(&ah->lock); 2475 2476 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 2477 if (ah->txqs[i].setup) { 2478 txq = &ah->txqs[i]; 2479 spin_lock_bh(&txq->lock); 2480 if (txq->txq_len > 1) { 2481 if (txq->txq_poll_mark) { 2482 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, 2483 "TX queue stuck %d\n", 2484 txq->qnum); 2485 needreset = true; 2486 txq->txq_stuck++; 2487 spin_unlock_bh(&txq->lock); 2488 break; 2489 } else { 2490 txq->txq_poll_mark = true; 2491 } 2492 } 2493 spin_unlock_bh(&txq->lock); 2494 } 2495 } 2496 2497 if (needreset) { 2498 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2499 "TX queues stuck, resetting\n"); 2500 ath5k_reset(ah, NULL, true); 2501 } 2502 2503 mutex_unlock(&ah->lock); 2504 2505 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2506 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2507 } 2508 2509 2510 /*************************\ 2511 * Initialization routines * 2512 \*************************/ 2513 2514 static const struct ieee80211_iface_limit if_limits[] = { 2515 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 2516 { .max = 4, .types = 2517 #ifdef CONFIG_MAC80211_MESH 2518 BIT(NL80211_IFTYPE_MESH_POINT) | 2519 #endif 2520 BIT(NL80211_IFTYPE_AP) }, 2521 }; 2522 2523 static const struct ieee80211_iface_combination if_comb = { 2524 .limits = if_limits, 2525 .n_limits = ARRAY_SIZE(if_limits), 2526 .max_interfaces = 2048, 2527 .num_different_channels = 1, 2528 }; 2529 2530 int 2531 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) 2532 { 2533 struct ieee80211_hw *hw = ah->hw; 2534 struct ath_common *common; 2535 int ret; 2536 int csz; 2537 2538 /* Initialize driver private data */ 2539 SET_IEEE80211_DEV(hw, ah->dev); 2540 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); 2541 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2542 ieee80211_hw_set(hw, MFP_CAPABLE); 2543 ieee80211_hw_set(hw, SIGNAL_DBM); 2544 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2545 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); 2546 2547 hw->wiphy->interface_modes = 2548 BIT(NL80211_IFTYPE_AP) | 2549 BIT(NL80211_IFTYPE_STATION) | 2550 BIT(NL80211_IFTYPE_ADHOC) | 2551 BIT(NL80211_IFTYPE_MESH_POINT); 2552 2553 hw->wiphy->iface_combinations = &if_comb; 2554 hw->wiphy->n_iface_combinations = 1; 2555 2556 /* SW support for IBSS_RSN is provided by mac80211 */ 2557 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 2558 2559 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 2560 2561 /* both antennas can be configured as RX or TX */ 2562 hw->wiphy->available_antennas_tx = 0x3; 2563 hw->wiphy->available_antennas_rx = 0x3; 2564 2565 hw->extra_tx_headroom = 2; 2566 2567 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 2568 2569 /* 2570 * Mark the device as detached to avoid processing 2571 * interrupts until setup is complete. 2572 */ 2573 __set_bit(ATH_STAT_INVALID, ah->status); 2574 2575 ah->opmode = NL80211_IFTYPE_STATION; 2576 ah->bintval = 1000; 2577 mutex_init(&ah->lock); 2578 spin_lock_init(&ah->rxbuflock); 2579 spin_lock_init(&ah->txbuflock); 2580 spin_lock_init(&ah->block); 2581 spin_lock_init(&ah->irqlock); 2582 2583 /* Setup interrupt handler */ 2584 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); 2585 if (ret) { 2586 ATH5K_ERR(ah, "request_irq failed\n"); 2587 goto err; 2588 } 2589 2590 common = ath5k_hw_common(ah); 2591 common->ops = &ath5k_common_ops; 2592 common->bus_ops = bus_ops; 2593 common->ah = ah; 2594 common->hw = hw; 2595 common->priv = ah; 2596 common->clockrate = 40; 2597 2598 /* 2599 * Cache line size is used to size and align various 2600 * structures used to communicate with the hardware. 2601 */ 2602 ath5k_read_cachesize(common, &csz); 2603 common->cachelsz = csz << 2; /* convert to bytes */ 2604 2605 spin_lock_init(&common->cc_lock); 2606 2607 /* Initialize device */ 2608 ret = ath5k_hw_init(ah); 2609 if (ret) 2610 goto err_irq; 2611 2612 /* Set up multi-rate retry capabilities */ 2613 if (ah->ah_capabilities.cap_has_mrr_support) { 2614 hw->max_rates = 4; 2615 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2616 AR5K_INIT_RETRY_LONG); 2617 } 2618 2619 hw->vif_data_size = sizeof(struct ath5k_vif); 2620 2621 /* Finish private driver data initialization */ 2622 ret = ath5k_init(hw); 2623 if (ret) 2624 goto err_ah; 2625 2626 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2627 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), 2628 ah->ah_mac_srev, 2629 ah->ah_phy_revision); 2630 2631 if (!ah->ah_single_chip) { 2632 /* Single chip radio (!RF5111) */ 2633 if (ah->ah_radio_5ghz_revision && 2634 !ah->ah_radio_2ghz_revision) { 2635 /* No 5GHz support -> report 2GHz radio */ 2636 if (!test_bit(AR5K_MODE_11A, 2637 ah->ah_capabilities.cap_mode)) { 2638 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2639 ath5k_chip_name(AR5K_VERSION_RAD, 2640 ah->ah_radio_5ghz_revision), 2641 ah->ah_radio_5ghz_revision); 2642 /* No 2GHz support (5110 and some 2643 * 5GHz only cards) -> report 5GHz radio */ 2644 } else if (!test_bit(AR5K_MODE_11B, 2645 ah->ah_capabilities.cap_mode)) { 2646 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2647 ath5k_chip_name(AR5K_VERSION_RAD, 2648 ah->ah_radio_5ghz_revision), 2649 ah->ah_radio_5ghz_revision); 2650 /* Multiband radio */ 2651 } else { 2652 ATH5K_INFO(ah, "RF%s multiband radio found" 2653 " (0x%x)\n", 2654 ath5k_chip_name(AR5K_VERSION_RAD, 2655 ah->ah_radio_5ghz_revision), 2656 ah->ah_radio_5ghz_revision); 2657 } 2658 } 2659 /* Multi chip radio (RF5111 - RF2111) -> 2660 * report both 2GHz/5GHz radios */ 2661 else if (ah->ah_radio_5ghz_revision && 2662 ah->ah_radio_2ghz_revision) { 2663 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2664 ath5k_chip_name(AR5K_VERSION_RAD, 2665 ah->ah_radio_5ghz_revision), 2666 ah->ah_radio_5ghz_revision); 2667 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2668 ath5k_chip_name(AR5K_VERSION_RAD, 2669 ah->ah_radio_2ghz_revision), 2670 ah->ah_radio_2ghz_revision); 2671 } 2672 } 2673 2674 ath5k_debug_init_device(ah); 2675 2676 /* ready to process interrupts */ 2677 __clear_bit(ATH_STAT_INVALID, ah->status); 2678 2679 return 0; 2680 err_ah: 2681 ath5k_hw_deinit(ah); 2682 err_irq: 2683 free_irq(ah->irq, ah); 2684 err: 2685 return ret; 2686 } 2687 2688 static int 2689 ath5k_stop_locked(struct ath5k_hw *ah) 2690 { 2691 2692 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", 2693 test_bit(ATH_STAT_INVALID, ah->status)); 2694 2695 /* 2696 * Shutdown the hardware and driver: 2697 * stop output from above 2698 * disable interrupts 2699 * turn off timers 2700 * turn off the radio 2701 * clear transmit machinery 2702 * clear receive machinery 2703 * drain and release tx queues 2704 * reclaim beacon resources 2705 * power down hardware 2706 * 2707 * Note that some of this work is not possible if the 2708 * hardware is gone (invalid). 2709 */ 2710 ieee80211_stop_queues(ah->hw); 2711 2712 if (!test_bit(ATH_STAT_INVALID, ah->status)) { 2713 ath5k_led_off(ah); 2714 ath5k_hw_set_imr(ah, 0); 2715 synchronize_irq(ah->irq); 2716 ath5k_rx_stop(ah); 2717 ath5k_hw_dma_stop(ah); 2718 ath5k_drain_tx_buffs(ah); 2719 ath5k_hw_phy_disable(ah); 2720 } 2721 2722 return 0; 2723 } 2724 2725 int ath5k_start(struct ieee80211_hw *hw) 2726 { 2727 struct ath5k_hw *ah = hw->priv; 2728 struct ath_common *common = ath5k_hw_common(ah); 2729 int ret, i; 2730 2731 mutex_lock(&ah->lock); 2732 2733 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); 2734 2735 /* 2736 * Stop anything previously setup. This is safe 2737 * no matter this is the first time through or not. 2738 */ 2739 ath5k_stop_locked(ah); 2740 2741 /* 2742 * The basic interface to setting the hardware in a good 2743 * state is ``reset''. On return the hardware is known to 2744 * be powered up and with interrupts disabled. This must 2745 * be followed by initialization of the appropriate bits 2746 * and then setup of the interrupt mask. 2747 */ 2748 ah->curchan = ah->hw->conf.chandef.chan; 2749 ah->imask = AR5K_INT_RXOK 2750 | AR5K_INT_RXERR 2751 | AR5K_INT_RXEOL 2752 | AR5K_INT_RXORN 2753 | AR5K_INT_TXDESC 2754 | AR5K_INT_TXEOL 2755 | AR5K_INT_FATAL 2756 | AR5K_INT_GLOBAL 2757 | AR5K_INT_MIB; 2758 2759 ret = ath5k_reset(ah, NULL, false); 2760 if (ret) 2761 goto done; 2762 2763 if (!ath5k_modparam_no_hw_rfkill_switch) 2764 ath5k_rfkill_hw_start(ah); 2765 2766 /* 2767 * Reset the key cache since some parts do not reset the 2768 * contents on initial power up or resume from suspend. 2769 */ 2770 for (i = 0; i < common->keymax; i++) 2771 ath_hw_keyreset(common, (u16) i); 2772 2773 /* Use higher rates for acks instead of base 2774 * rate */ 2775 ah->ah_ack_bitrate_high = true; 2776 2777 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) 2778 ah->bslot[i] = NULL; 2779 2780 ret = 0; 2781 done: 2782 mmiowb(); 2783 mutex_unlock(&ah->lock); 2784 2785 set_bit(ATH_STAT_STARTED, ah->status); 2786 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2787 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2788 2789 return ret; 2790 } 2791 2792 static void ath5k_stop_tasklets(struct ath5k_hw *ah) 2793 { 2794 ah->rx_pending = false; 2795 ah->tx_pending = false; 2796 tasklet_kill(&ah->rxtq); 2797 tasklet_kill(&ah->txtq); 2798 tasklet_kill(&ah->beacontq); 2799 tasklet_kill(&ah->ani_tasklet); 2800 } 2801 2802 /* 2803 * Stop the device, grabbing the top-level lock to protect 2804 * against concurrent entry through ath5k_init (which can happen 2805 * if another thread does a system call and the thread doing the 2806 * stop is preempted). 2807 */ 2808 void ath5k_stop(struct ieee80211_hw *hw) 2809 { 2810 struct ath5k_hw *ah = hw->priv; 2811 int ret; 2812 2813 mutex_lock(&ah->lock); 2814 ret = ath5k_stop_locked(ah); 2815 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { 2816 /* 2817 * Don't set the card in full sleep mode! 2818 * 2819 * a) When the device is in this state it must be carefully 2820 * woken up or references to registers in the PCI clock 2821 * domain may freeze the bus (and system). This varies 2822 * by chip and is mostly an issue with newer parts 2823 * (madwifi sources mentioned srev >= 0x78) that go to 2824 * sleep more quickly. 2825 * 2826 * b) On older chips full sleep results a weird behaviour 2827 * during wakeup. I tested various cards with srev < 0x78 2828 * and they don't wake up after module reload, a second 2829 * module reload is needed to bring the card up again. 2830 * 2831 * Until we figure out what's going on don't enable 2832 * full chip reset on any chip (this is what Legacy HAL 2833 * and Sam's HAL do anyway). Instead Perform a full reset 2834 * on the device (same as initial state after attach) and 2835 * leave it idle (keep MAC/BB on warm reset) */ 2836 ret = ath5k_hw_on_hold(ah); 2837 2838 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2839 "putting device to sleep\n"); 2840 } 2841 2842 mmiowb(); 2843 mutex_unlock(&ah->lock); 2844 2845 ath5k_stop_tasklets(ah); 2846 2847 clear_bit(ATH_STAT_STARTED, ah->status); 2848 cancel_delayed_work_sync(&ah->tx_complete_work); 2849 2850 if (!ath5k_modparam_no_hw_rfkill_switch) 2851 ath5k_rfkill_hw_stop(ah); 2852 } 2853 2854 /* 2855 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2856 * and change to the given channel. 2857 * 2858 * This should be called with ah->lock. 2859 */ 2860 static int 2861 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 2862 bool skip_pcu) 2863 { 2864 struct ath_common *common = ath5k_hw_common(ah); 2865 int ret, ani_mode; 2866 bool fast = chan && modparam_fastchanswitch ? 1 : 0; 2867 2868 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); 2869 2870 __set_bit(ATH_STAT_RESET, ah->status); 2871 2872 ath5k_hw_set_imr(ah, 0); 2873 synchronize_irq(ah->irq); 2874 ath5k_stop_tasklets(ah); 2875 2876 /* Save ani mode and disable ANI during 2877 * reset. If we don't we might get false 2878 * PHY error interrupts. */ 2879 ani_mode = ah->ani_state.ani_mode; 2880 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2881 2882 /* We are going to empty hw queues 2883 * so we should also free any remaining 2884 * tx buffers */ 2885 ath5k_drain_tx_buffs(ah); 2886 2887 /* Stop PCU */ 2888 ath5k_hw_stop_rx_pcu(ah); 2889 2890 /* Stop DMA 2891 * 2892 * Note: If DMA didn't stop continue 2893 * since only a reset will fix it. 2894 */ 2895 ret = ath5k_hw_dma_stop(ah); 2896 2897 /* RF Bus grant won't work if we have pending 2898 * frames 2899 */ 2900 if (ret && fast) { 2901 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2902 "DMA didn't stop, falling back to normal reset\n"); 2903 fast = false; 2904 } 2905 2906 if (chan) 2907 ah->curchan = chan; 2908 2909 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); 2910 if (ret) { 2911 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); 2912 goto err; 2913 } 2914 2915 ret = ath5k_rx_start(ah); 2916 if (ret) { 2917 ATH5K_ERR(ah, "can't start recv logic\n"); 2918 goto err; 2919 } 2920 2921 ath5k_ani_init(ah, ani_mode); 2922 2923 /* 2924 * Set calibration intervals 2925 * 2926 * Note: We don't need to run calibration imediately 2927 * since some initial calibration is done on reset 2928 * even for fast channel switching. Also on scanning 2929 * this will get set again and again and it won't get 2930 * executed unless we connect somewhere and spend some 2931 * time on the channel (that's what calibration needs 2932 * anyway to be accurate). 2933 */ 2934 ah->ah_cal_next_full = jiffies + 2935 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2936 ah->ah_cal_next_ani = jiffies + 2937 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2938 ah->ah_cal_next_short = jiffies + 2939 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2940 2941 ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg); 2942 2943 /* clear survey data and cycle counters */ 2944 memset(&ah->survey, 0, sizeof(ah->survey)); 2945 spin_lock_bh(&common->cc_lock); 2946 ath_hw_cycle_counters_update(common); 2947 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2948 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2949 spin_unlock_bh(&common->cc_lock); 2950 2951 /* 2952 * Change channels and update the h/w rate map if we're switching; 2953 * e.g. 11a to 11b/g. 2954 * 2955 * We may be doing a reset in response to an ioctl that changes the 2956 * channel so update any state that might change as a result. 2957 * 2958 * XXX needed? 2959 */ 2960 /* ath5k_chan_change(ah, c); */ 2961 2962 __clear_bit(ATH_STAT_RESET, ah->status); 2963 2964 ath5k_beacon_config(ah); 2965 /* intrs are enabled by ath5k_beacon_config */ 2966 2967 ieee80211_wake_queues(ah->hw); 2968 2969 return 0; 2970 err: 2971 return ret; 2972 } 2973 2974 static void ath5k_reset_work(struct work_struct *work) 2975 { 2976 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2977 reset_work); 2978 2979 mutex_lock(&ah->lock); 2980 ath5k_reset(ah, NULL, true); 2981 mutex_unlock(&ah->lock); 2982 } 2983 2984 static int 2985 ath5k_init(struct ieee80211_hw *hw) 2986 { 2987 2988 struct ath5k_hw *ah = hw->priv; 2989 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2990 struct ath5k_txq *txq; 2991 u8 mac[ETH_ALEN] = {}; 2992 int ret; 2993 2994 2995 /* 2996 * Collect the channel list. The 802.11 layer 2997 * is responsible for filtering this list based 2998 * on settings like the phy mode and regulatory 2999 * domain restrictions. 3000 */ 3001 ret = ath5k_setup_bands(hw); 3002 if (ret) { 3003 ATH5K_ERR(ah, "can't get channels\n"); 3004 goto err; 3005 } 3006 3007 /* 3008 * Allocate tx+rx descriptors and populate the lists. 3009 */ 3010 ret = ath5k_desc_alloc(ah); 3011 if (ret) { 3012 ATH5K_ERR(ah, "can't allocate descriptors\n"); 3013 goto err; 3014 } 3015 3016 /* 3017 * Allocate hardware transmit queues: one queue for 3018 * beacon frames and one data queue for each QoS 3019 * priority. Note that hw functions handle resetting 3020 * these queues at the needed time. 3021 */ 3022 ret = ath5k_beaconq_setup(ah); 3023 if (ret < 0) { 3024 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); 3025 goto err_desc; 3026 } 3027 ah->bhalq = ret; 3028 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); 3029 if (IS_ERR(ah->cabq)) { 3030 ATH5K_ERR(ah, "can't setup cab queue\n"); 3031 ret = PTR_ERR(ah->cabq); 3032 goto err_bhal; 3033 } 3034 3035 /* 5211 and 5212 usually support 10 queues but we better rely on the 3036 * capability information */ 3037 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 3038 /* This order matches mac80211's queue priority, so we can 3039 * directly use the mac80211 queue number without any mapping */ 3040 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 3041 if (IS_ERR(txq)) { 3042 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3043 ret = PTR_ERR(txq); 3044 goto err_queues; 3045 } 3046 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 3047 if (IS_ERR(txq)) { 3048 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3049 ret = PTR_ERR(txq); 3050 goto err_queues; 3051 } 3052 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 3053 if (IS_ERR(txq)) { 3054 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3055 ret = PTR_ERR(txq); 3056 goto err_queues; 3057 } 3058 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 3059 if (IS_ERR(txq)) { 3060 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3061 ret = PTR_ERR(txq); 3062 goto err_queues; 3063 } 3064 hw->queues = 4; 3065 } else { 3066 /* older hardware (5210) can only support one data queue */ 3067 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 3068 if (IS_ERR(txq)) { 3069 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3070 ret = PTR_ERR(txq); 3071 goto err_queues; 3072 } 3073 hw->queues = 1; 3074 } 3075 3076 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); 3077 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); 3078 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); 3079 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); 3080 3081 INIT_WORK(&ah->reset_work, ath5k_reset_work); 3082 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); 3083 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); 3084 3085 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 3086 if (ret) { 3087 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); 3088 goto err_queues; 3089 } 3090 3091 SET_IEEE80211_PERM_ADDR(hw, mac); 3092 /* All MAC address bits matter for ACKs */ 3093 ath5k_update_bssid_mask_and_opmode(ah, NULL); 3094 3095 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 3096 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 3097 if (ret) { 3098 ATH5K_ERR(ah, "can't initialize regulatory system\n"); 3099 goto err_queues; 3100 } 3101 3102 ret = ieee80211_register_hw(hw); 3103 if (ret) { 3104 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); 3105 goto err_queues; 3106 } 3107 3108 if (!ath_is_world_regd(regulatory)) 3109 regulatory_hint(hw->wiphy, regulatory->alpha2); 3110 3111 ath5k_init_leds(ah); 3112 3113 ath5k_sysfs_register(ah); 3114 3115 return 0; 3116 err_queues: 3117 ath5k_txq_release(ah); 3118 err_bhal: 3119 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3120 err_desc: 3121 ath5k_desc_free(ah); 3122 err: 3123 return ret; 3124 } 3125 3126 void 3127 ath5k_deinit_ah(struct ath5k_hw *ah) 3128 { 3129 struct ieee80211_hw *hw = ah->hw; 3130 3131 /* 3132 * NB: the order of these is important: 3133 * o call the 802.11 layer before detaching ath5k_hw to 3134 * ensure callbacks into the driver to delete global 3135 * key cache entries can be handled 3136 * o reclaim the tx queue data structures after calling 3137 * the 802.11 layer as we'll get called back to reclaim 3138 * node state and potentially want to use them 3139 * o to cleanup the tx queues the hal is called, so detach 3140 * it last 3141 * XXX: ??? detach ath5k_hw ??? 3142 * Other than that, it's straightforward... 3143 */ 3144 ieee80211_unregister_hw(hw); 3145 ath5k_desc_free(ah); 3146 ath5k_txq_release(ah); 3147 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3148 ath5k_unregister_leds(ah); 3149 3150 ath5k_sysfs_unregister(ah); 3151 /* 3152 * NB: can't reclaim these until after ieee80211_ifdetach 3153 * returns because we'll get called back to reclaim node 3154 * state and potentially want to use them. 3155 */ 3156 ath5k_hw_deinit(ah); 3157 free_irq(ah->irq, ah); 3158 } 3159 3160 bool 3161 ath5k_any_vif_assoc(struct ath5k_hw *ah) 3162 { 3163 struct ath5k_vif_iter_data iter_data; 3164 iter_data.hw_macaddr = NULL; 3165 iter_data.any_assoc = false; 3166 iter_data.need_set_hw_addr = false; 3167 iter_data.found_active = true; 3168 3169 ieee80211_iterate_active_interfaces_atomic( 3170 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 3171 ath5k_vif_iter, &iter_data); 3172 return iter_data.any_assoc; 3173 } 3174 3175 void 3176 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3177 { 3178 struct ath5k_hw *ah = hw->priv; 3179 u32 rfilt; 3180 rfilt = ath5k_hw_get_rx_filter(ah); 3181 if (enable) 3182 rfilt |= AR5K_RX_FILTER_BEACON; 3183 else 3184 rfilt &= ~AR5K_RX_FILTER_BEACON; 3185 ath5k_hw_set_rx_filter(ah, rfilt); 3186 ah->filter_flags = rfilt; 3187 } 3188 3189 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, 3190 const char *fmt, ...) 3191 { 3192 struct va_format vaf; 3193 va_list args; 3194 3195 va_start(args, fmt); 3196 3197 vaf.fmt = fmt; 3198 vaf.va = &args; 3199 3200 if (ah && ah->hw) 3201 printk("%s" pr_fmt("%s: %pV"), 3202 level, wiphy_name(ah->hw->wiphy), &vaf); 3203 else 3204 printk("%s" pr_fmt("%pV"), level, &vaf); 3205 3206 va_end(args); 3207 } 3208