1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/pci.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 54 #include <net/ieee80211_radiotap.h> 55 56 #include <asm/unaligned.h> 57 58 #include "base.h" 59 #include "reg.h" 60 #include "debug.h" 61 62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */ 63 static int modparam_nohwcrypt; 64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 66 67 static int modparam_all_channels; 68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 70 71 72 /******************\ 73 * Internal defines * 74 \******************/ 75 76 /* Module info */ 77 MODULE_AUTHOR("Jiri Slaby"); 78 MODULE_AUTHOR("Nick Kossifidis"); 79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 81 MODULE_LICENSE("Dual BSD/GPL"); 82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)"); 83 84 85 /* Known PCI ids */ 86 static const struct pci_device_id ath5k_pci_id_table[] = { 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 105 { 0 } 106 }; 107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 108 109 /* Known SREVs */ 110 static const struct ath5k_srev_name srev_names[] = { 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 147 }; 148 149 static const struct ieee80211_rate ath5k_rates[] = { 150 { .bitrate = 10, 151 .hw_value = ATH5K_RATE_CODE_1M, }, 152 { .bitrate = 20, 153 .hw_value = ATH5K_RATE_CODE_2M, 154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 155 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 156 { .bitrate = 55, 157 .hw_value = ATH5K_RATE_CODE_5_5M, 158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 159 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 160 { .bitrate = 110, 161 .hw_value = ATH5K_RATE_CODE_11M, 162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 163 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 164 { .bitrate = 60, 165 .hw_value = ATH5K_RATE_CODE_6M, 166 .flags = 0 }, 167 { .bitrate = 90, 168 .hw_value = ATH5K_RATE_CODE_9M, 169 .flags = 0 }, 170 { .bitrate = 120, 171 .hw_value = ATH5K_RATE_CODE_12M, 172 .flags = 0 }, 173 { .bitrate = 180, 174 .hw_value = ATH5K_RATE_CODE_18M, 175 .flags = 0 }, 176 { .bitrate = 240, 177 .hw_value = ATH5K_RATE_CODE_24M, 178 .flags = 0 }, 179 { .bitrate = 360, 180 .hw_value = ATH5K_RATE_CODE_36M, 181 .flags = 0 }, 182 { .bitrate = 480, 183 .hw_value = ATH5K_RATE_CODE_48M, 184 .flags = 0 }, 185 { .bitrate = 540, 186 .hw_value = ATH5K_RATE_CODE_54M, 187 .flags = 0 }, 188 /* XR missing */ 189 }; 190 191 /* 192 * Prototypes - PCI stack related functions 193 */ 194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev, 195 const struct pci_device_id *id); 196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev); 197 #ifdef CONFIG_PM 198 static int ath5k_pci_suspend(struct device *dev); 199 static int ath5k_pci_resume(struct device *dev); 200 201 SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 202 #define ATH5K_PM_OPS (&ath5k_pm_ops) 203 #else 204 #define ATH5K_PM_OPS NULL 205 #endif /* CONFIG_PM */ 206 207 static struct pci_driver ath5k_pci_driver = { 208 .name = KBUILD_MODNAME, 209 .id_table = ath5k_pci_id_table, 210 .probe = ath5k_pci_probe, 211 .remove = __devexit_p(ath5k_pci_remove), 212 .driver.pm = ATH5K_PM_OPS, 213 }; 214 215 216 217 /* 218 * Prototypes - MAC 802.11 stack related functions 219 */ 220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 222 struct ath5k_txq *txq); 223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan); 224 static int ath5k_reset_wake(struct ath5k_softc *sc); 225 static int ath5k_start(struct ieee80211_hw *hw); 226 static void ath5k_stop(struct ieee80211_hw *hw); 227 static int ath5k_add_interface(struct ieee80211_hw *hw, 228 struct ieee80211_if_init_conf *conf); 229 static void ath5k_remove_interface(struct ieee80211_hw *hw, 230 struct ieee80211_if_init_conf *conf); 231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed); 232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 233 int mc_count, struct dev_addr_list *mc_list); 234 static void ath5k_configure_filter(struct ieee80211_hw *hw, 235 unsigned int changed_flags, 236 unsigned int *new_flags, 237 u64 multicast); 238 static int ath5k_set_key(struct ieee80211_hw *hw, 239 enum set_key_cmd cmd, 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 241 struct ieee80211_key_conf *key); 242 static int ath5k_get_stats(struct ieee80211_hw *hw, 243 struct ieee80211_low_level_stats *stats); 244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw, 245 struct ieee80211_tx_queue_stats *stats); 246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw); 247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf); 248 static void ath5k_reset_tsf(struct ieee80211_hw *hw); 249 static int ath5k_beacon_update(struct ieee80211_hw *hw, 250 struct ieee80211_vif *vif); 251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 252 struct ieee80211_vif *vif, 253 struct ieee80211_bss_conf *bss_conf, 254 u32 changes); 255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw); 256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw); 257 258 static const struct ieee80211_ops ath5k_hw_ops = { 259 .tx = ath5k_tx, 260 .start = ath5k_start, 261 .stop = ath5k_stop, 262 .add_interface = ath5k_add_interface, 263 .remove_interface = ath5k_remove_interface, 264 .config = ath5k_config, 265 .prepare_multicast = ath5k_prepare_multicast, 266 .configure_filter = ath5k_configure_filter, 267 .set_key = ath5k_set_key, 268 .get_stats = ath5k_get_stats, 269 .conf_tx = NULL, 270 .get_tx_stats = ath5k_get_tx_stats, 271 .get_tsf = ath5k_get_tsf, 272 .set_tsf = ath5k_set_tsf, 273 .reset_tsf = ath5k_reset_tsf, 274 .bss_info_changed = ath5k_bss_info_changed, 275 .sw_scan_start = ath5k_sw_scan_start, 276 .sw_scan_complete = ath5k_sw_scan_complete, 277 }; 278 279 /* 280 * Prototypes - Internal functions 281 */ 282 /* Attach detach */ 283 static int ath5k_attach(struct pci_dev *pdev, 284 struct ieee80211_hw *hw); 285 static void ath5k_detach(struct pci_dev *pdev, 286 struct ieee80211_hw *hw); 287 /* Channel/mode setup */ 288 static inline short ath5k_ieee2mhz(short chan); 289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, 290 struct ieee80211_channel *channels, 291 unsigned int mode, 292 unsigned int max); 293 static int ath5k_setup_bands(struct ieee80211_hw *hw); 294 static int ath5k_chan_set(struct ath5k_softc *sc, 295 struct ieee80211_channel *chan); 296 static void ath5k_setcurmode(struct ath5k_softc *sc, 297 unsigned int mode); 298 static void ath5k_mode_setup(struct ath5k_softc *sc); 299 300 /* Descriptor setup */ 301 static int ath5k_desc_alloc(struct ath5k_softc *sc, 302 struct pci_dev *pdev); 303 static void ath5k_desc_free(struct ath5k_softc *sc, 304 struct pci_dev *pdev); 305 /* Buffers setup */ 306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc, 307 struct ath5k_buf *bf); 308 static int ath5k_txbuf_setup(struct ath5k_softc *sc, 309 struct ath5k_buf *bf, 310 struct ath5k_txq *txq); 311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 312 struct ath5k_buf *bf) 313 { 314 BUG_ON(!bf); 315 if (!bf->skb) 316 return; 317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, 318 PCI_DMA_TODEVICE); 319 dev_kfree_skb_any(bf->skb); 320 bf->skb = NULL; 321 } 322 323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc, 324 struct ath5k_buf *bf) 325 { 326 struct ath5k_hw *ah = sc->ah; 327 struct ath_common *common = ath5k_hw_common(ah); 328 329 BUG_ON(!bf); 330 if (!bf->skb) 331 return; 332 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize, 333 PCI_DMA_FROMDEVICE); 334 dev_kfree_skb_any(bf->skb); 335 bf->skb = NULL; 336 } 337 338 339 /* Queues setup */ 340 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, 341 int qtype, int subtype); 342 static int ath5k_beaconq_setup(struct ath5k_hw *ah); 343 static int ath5k_beaconq_config(struct ath5k_softc *sc); 344 static void ath5k_txq_drainq(struct ath5k_softc *sc, 345 struct ath5k_txq *txq); 346 static void ath5k_txq_cleanup(struct ath5k_softc *sc); 347 static void ath5k_txq_release(struct ath5k_softc *sc); 348 /* Rx handling */ 349 static int ath5k_rx_start(struct ath5k_softc *sc); 350 static void ath5k_rx_stop(struct ath5k_softc *sc); 351 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, 352 struct ath5k_desc *ds, 353 struct sk_buff *skb, 354 struct ath5k_rx_status *rs); 355 static void ath5k_tasklet_rx(unsigned long data); 356 /* Tx handling */ 357 static void ath5k_tx_processq(struct ath5k_softc *sc, 358 struct ath5k_txq *txq); 359 static void ath5k_tasklet_tx(unsigned long data); 360 /* Beacon handling */ 361 static int ath5k_beacon_setup(struct ath5k_softc *sc, 362 struct ath5k_buf *bf); 363 static void ath5k_beacon_send(struct ath5k_softc *sc); 364 static void ath5k_beacon_config(struct ath5k_softc *sc); 365 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 366 static void ath5k_tasklet_beacon(unsigned long data); 367 368 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 369 { 370 u64 tsf = ath5k_hw_get_tsf64(ah); 371 372 if ((tsf & 0x7fff) < rstamp) 373 tsf -= 0x8000; 374 375 return (tsf & ~0x7fff) | rstamp; 376 } 377 378 /* Interrupt handling */ 379 static int ath5k_init(struct ath5k_softc *sc); 380 static int ath5k_stop_locked(struct ath5k_softc *sc); 381 static int ath5k_stop_hw(struct ath5k_softc *sc); 382 static irqreturn_t ath5k_intr(int irq, void *dev_id); 383 static void ath5k_tasklet_reset(unsigned long data); 384 385 static void ath5k_tasklet_calibrate(unsigned long data); 386 387 /* 388 * Module init/exit functions 389 */ 390 static int __init 391 init_ath5k_pci(void) 392 { 393 int ret; 394 395 ath5k_debug_init(); 396 397 ret = pci_register_driver(&ath5k_pci_driver); 398 if (ret) { 399 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 400 return ret; 401 } 402 403 return 0; 404 } 405 406 static void __exit 407 exit_ath5k_pci(void) 408 { 409 pci_unregister_driver(&ath5k_pci_driver); 410 411 ath5k_debug_finish(); 412 } 413 414 module_init(init_ath5k_pci); 415 module_exit(exit_ath5k_pci); 416 417 418 /********************\ 419 * PCI Initialization * 420 \********************/ 421 422 static const char * 423 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 424 { 425 const char *name = "xxxxx"; 426 unsigned int i; 427 428 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 429 if (srev_names[i].sr_type != type) 430 continue; 431 432 if ((val & 0xf0) == srev_names[i].sr_val) 433 name = srev_names[i].sr_name; 434 435 if ((val & 0xff) == srev_names[i].sr_val) { 436 name = srev_names[i].sr_name; 437 break; 438 } 439 } 440 441 return name; 442 } 443 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 444 { 445 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 446 return ath5k_hw_reg_read(ah, reg_offset); 447 } 448 449 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 450 { 451 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 452 ath5k_hw_reg_write(ah, val, reg_offset); 453 } 454 455 static const struct ath_ops ath5k_common_ops = { 456 .read = ath5k_ioread32, 457 .write = ath5k_iowrite32, 458 }; 459 460 static int __devinit 461 ath5k_pci_probe(struct pci_dev *pdev, 462 const struct pci_device_id *id) 463 { 464 void __iomem *mem; 465 struct ath5k_softc *sc; 466 struct ath_common *common; 467 struct ieee80211_hw *hw; 468 int ret; 469 u8 csz; 470 471 ret = pci_enable_device(pdev); 472 if (ret) { 473 dev_err(&pdev->dev, "can't enable device\n"); 474 goto err; 475 } 476 477 /* XXX 32-bit addressing only */ 478 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 479 if (ret) { 480 dev_err(&pdev->dev, "32-bit DMA not available\n"); 481 goto err_dis; 482 } 483 484 /* 485 * Cache line size is used to size and align various 486 * structures used to communicate with the hardware. 487 */ 488 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 489 if (csz == 0) { 490 /* 491 * Linux 2.4.18 (at least) writes the cache line size 492 * register as a 16-bit wide register which is wrong. 493 * We must have this setup properly for rx buffer 494 * DMA to work so force a reasonable value here if it 495 * comes up zero. 496 */ 497 csz = L1_CACHE_BYTES >> 2; 498 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 499 } 500 /* 501 * The default setting of latency timer yields poor results, 502 * set it to the value used by other systems. It may be worth 503 * tweaking this setting more. 504 */ 505 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 506 507 /* Enable bus mastering */ 508 pci_set_master(pdev); 509 510 /* 511 * Disable the RETRY_TIMEOUT register (0x41) to keep 512 * PCI Tx retries from interfering with C3 CPU state. 513 */ 514 pci_write_config_byte(pdev, 0x41, 0); 515 516 ret = pci_request_region(pdev, 0, "ath5k"); 517 if (ret) { 518 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 519 goto err_dis; 520 } 521 522 mem = pci_iomap(pdev, 0, 0); 523 if (!mem) { 524 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 525 ret = -EIO; 526 goto err_reg; 527 } 528 529 /* 530 * Allocate hw (mac80211 main struct) 531 * and hw->priv (driver private data) 532 */ 533 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 534 if (hw == NULL) { 535 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 536 ret = -ENOMEM; 537 goto err_map; 538 } 539 540 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 541 542 /* Initialize driver private data */ 543 SET_IEEE80211_DEV(hw, &pdev->dev); 544 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 546 IEEE80211_HW_SIGNAL_DBM | 547 IEEE80211_HW_NOISE_DBM; 548 549 hw->wiphy->interface_modes = 550 BIT(NL80211_IFTYPE_AP) | 551 BIT(NL80211_IFTYPE_STATION) | 552 BIT(NL80211_IFTYPE_ADHOC) | 553 BIT(NL80211_IFTYPE_MESH_POINT); 554 555 hw->extra_tx_headroom = 2; 556 hw->channel_change_time = 5000; 557 sc = hw->priv; 558 sc->hw = hw; 559 sc->pdev = pdev; 560 561 ath5k_debug_init_device(sc); 562 563 /* 564 * Mark the device as detached to avoid processing 565 * interrupts until setup is complete. 566 */ 567 __set_bit(ATH_STAT_INVALID, sc->status); 568 569 sc->iobase = mem; /* So we can unmap it on detach */ 570 sc->opmode = NL80211_IFTYPE_STATION; 571 sc->bintval = 1000; 572 mutex_init(&sc->lock); 573 spin_lock_init(&sc->rxbuflock); 574 spin_lock_init(&sc->txbuflock); 575 spin_lock_init(&sc->block); 576 577 /* Set private data */ 578 pci_set_drvdata(pdev, hw); 579 580 /* Setup interrupt handler */ 581 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 582 if (ret) { 583 ATH5K_ERR(sc, "request_irq failed\n"); 584 goto err_free; 585 } 586 587 /*If we passed the test malloc a ath5k_hw struct*/ 588 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); 589 if (!sc->ah) { 590 ret = -ENOMEM; 591 ATH5K_ERR(sc, "out of memory\n"); 592 goto err_irq; 593 } 594 595 sc->ah->ah_sc = sc; 596 sc->ah->ah_iobase = sc->iobase; 597 common = ath5k_hw_common(sc->ah); 598 common->ops = &ath5k_common_ops; 599 common->ah = sc->ah; 600 common->hw = hw; 601 common->cachelsz = csz << 2; /* convert to bytes */ 602 603 /* Initialize device */ 604 ret = ath5k_hw_attach(sc); 605 if (ret) { 606 goto err_free_ah; 607 } 608 609 /* set up multi-rate retry capabilities */ 610 if (sc->ah->ah_version == AR5K_AR5212) { 611 hw->max_rates = 4; 612 hw->max_rate_tries = 11; 613 } 614 615 /* Finish private driver data initialization */ 616 ret = ath5k_attach(pdev, hw); 617 if (ret) 618 goto err_ah; 619 620 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 621 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 622 sc->ah->ah_mac_srev, 623 sc->ah->ah_phy_revision); 624 625 if (!sc->ah->ah_single_chip) { 626 /* Single chip radio (!RF5111) */ 627 if (sc->ah->ah_radio_5ghz_revision && 628 !sc->ah->ah_radio_2ghz_revision) { 629 /* No 5GHz support -> report 2GHz radio */ 630 if (!test_bit(AR5K_MODE_11A, 631 sc->ah->ah_capabilities.cap_mode)) { 632 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 633 ath5k_chip_name(AR5K_VERSION_RAD, 634 sc->ah->ah_radio_5ghz_revision), 635 sc->ah->ah_radio_5ghz_revision); 636 /* No 2GHz support (5110 and some 637 * 5Ghz only cards) -> report 5Ghz radio */ 638 } else if (!test_bit(AR5K_MODE_11B, 639 sc->ah->ah_capabilities.cap_mode)) { 640 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 641 ath5k_chip_name(AR5K_VERSION_RAD, 642 sc->ah->ah_radio_5ghz_revision), 643 sc->ah->ah_radio_5ghz_revision); 644 /* Multiband radio */ 645 } else { 646 ATH5K_INFO(sc, "RF%s multiband radio found" 647 " (0x%x)\n", 648 ath5k_chip_name(AR5K_VERSION_RAD, 649 sc->ah->ah_radio_5ghz_revision), 650 sc->ah->ah_radio_5ghz_revision); 651 } 652 } 653 /* Multi chip radio (RF5111 - RF2111) -> 654 * report both 2GHz/5GHz radios */ 655 else if (sc->ah->ah_radio_5ghz_revision && 656 sc->ah->ah_radio_2ghz_revision){ 657 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 658 ath5k_chip_name(AR5K_VERSION_RAD, 659 sc->ah->ah_radio_5ghz_revision), 660 sc->ah->ah_radio_5ghz_revision); 661 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 662 ath5k_chip_name(AR5K_VERSION_RAD, 663 sc->ah->ah_radio_2ghz_revision), 664 sc->ah->ah_radio_2ghz_revision); 665 } 666 } 667 668 669 /* ready to process interrupts */ 670 __clear_bit(ATH_STAT_INVALID, sc->status); 671 672 return 0; 673 err_ah: 674 ath5k_hw_detach(sc->ah); 675 err_irq: 676 free_irq(pdev->irq, sc); 677 err_free_ah: 678 kfree(sc->ah); 679 err_free: 680 ieee80211_free_hw(hw); 681 err_map: 682 pci_iounmap(pdev, mem); 683 err_reg: 684 pci_release_region(pdev, 0); 685 err_dis: 686 pci_disable_device(pdev); 687 err: 688 return ret; 689 } 690 691 static void __devexit 692 ath5k_pci_remove(struct pci_dev *pdev) 693 { 694 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 695 struct ath5k_softc *sc = hw->priv; 696 697 ath5k_debug_finish_device(sc); 698 ath5k_detach(pdev, hw); 699 ath5k_hw_detach(sc->ah); 700 kfree(sc->ah); 701 free_irq(pdev->irq, sc); 702 pci_iounmap(pdev, sc->iobase); 703 pci_release_region(pdev, 0); 704 pci_disable_device(pdev); 705 ieee80211_free_hw(hw); 706 } 707 708 #ifdef CONFIG_PM 709 static int ath5k_pci_suspend(struct device *dev) 710 { 711 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev)); 712 struct ath5k_softc *sc = hw->priv; 713 714 ath5k_led_off(sc); 715 return 0; 716 } 717 718 static int ath5k_pci_resume(struct device *dev) 719 { 720 struct pci_dev *pdev = to_pci_dev(dev); 721 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 722 struct ath5k_softc *sc = hw->priv; 723 724 /* 725 * Suspend/Resume resets the PCI configuration space, so we have to 726 * re-disable the RETRY_TIMEOUT register (0x41) to keep 727 * PCI Tx retries from interfering with C3 CPU state 728 */ 729 pci_write_config_byte(pdev, 0x41, 0); 730 731 ath5k_led_enable(sc); 732 return 0; 733 } 734 #endif /* CONFIG_PM */ 735 736 737 /***********************\ 738 * Driver Initialization * 739 \***********************/ 740 741 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 742 { 743 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 744 struct ath5k_softc *sc = hw->priv; 745 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 746 747 return ath_reg_notifier_apply(wiphy, request, regulatory); 748 } 749 750 static int 751 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) 752 { 753 struct ath5k_softc *sc = hw->priv; 754 struct ath5k_hw *ah = sc->ah; 755 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 756 u8 mac[ETH_ALEN] = {}; 757 int ret; 758 759 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); 760 761 /* 762 * Check if the MAC has multi-rate retry support. 763 * We do this by trying to setup a fake extended 764 * descriptor. MAC's that don't have support will 765 * return false w/o doing anything. MAC's that do 766 * support it will return true w/o doing anything. 767 */ 768 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 769 if (ret < 0) 770 goto err; 771 if (ret > 0) 772 __set_bit(ATH_STAT_MRRETRY, sc->status); 773 774 /* 775 * Collect the channel list. The 802.11 layer 776 * is resposible for filtering this list based 777 * on settings like the phy mode and regulatory 778 * domain restrictions. 779 */ 780 ret = ath5k_setup_bands(hw); 781 if (ret) { 782 ATH5K_ERR(sc, "can't get channels\n"); 783 goto err; 784 } 785 786 /* NB: setup here so ath5k_rate_update is happy */ 787 if (test_bit(AR5K_MODE_11A, ah->ah_modes)) 788 ath5k_setcurmode(sc, AR5K_MODE_11A); 789 else 790 ath5k_setcurmode(sc, AR5K_MODE_11B); 791 792 /* 793 * Allocate tx+rx descriptors and populate the lists. 794 */ 795 ret = ath5k_desc_alloc(sc, pdev); 796 if (ret) { 797 ATH5K_ERR(sc, "can't allocate descriptors\n"); 798 goto err; 799 } 800 801 /* 802 * Allocate hardware transmit queues: one queue for 803 * beacon frames and one data queue for each QoS 804 * priority. Note that hw functions handle reseting 805 * these queues at the needed time. 806 */ 807 ret = ath5k_beaconq_setup(ah); 808 if (ret < 0) { 809 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 810 goto err_desc; 811 } 812 sc->bhalq = ret; 813 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 814 if (IS_ERR(sc->cabq)) { 815 ATH5K_ERR(sc, "can't setup cab queue\n"); 816 ret = PTR_ERR(sc->cabq); 817 goto err_bhal; 818 } 819 820 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 821 if (IS_ERR(sc->txq)) { 822 ATH5K_ERR(sc, "can't setup xmit queue\n"); 823 ret = PTR_ERR(sc->txq); 824 goto err_queues; 825 } 826 827 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 828 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 829 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); 830 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 831 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 832 833 ret = ath5k_eeprom_read_mac(ah, mac); 834 if (ret) { 835 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n", 836 sc->pdev->device); 837 goto err_queues; 838 } 839 840 SET_IEEE80211_PERM_ADDR(hw, mac); 841 /* All MAC address bits matter for ACKs */ 842 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); 843 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 844 845 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 846 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 847 if (ret) { 848 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 849 goto err_queues; 850 } 851 852 ret = ieee80211_register_hw(hw); 853 if (ret) { 854 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 855 goto err_queues; 856 } 857 858 if (!ath_is_world_regd(regulatory)) 859 regulatory_hint(hw->wiphy, regulatory->alpha2); 860 861 ath5k_init_leds(sc); 862 863 return 0; 864 err_queues: 865 ath5k_txq_release(sc); 866 err_bhal: 867 ath5k_hw_release_tx_queue(ah, sc->bhalq); 868 err_desc: 869 ath5k_desc_free(sc, pdev); 870 err: 871 return ret; 872 } 873 874 static void 875 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) 876 { 877 struct ath5k_softc *sc = hw->priv; 878 879 /* 880 * NB: the order of these is important: 881 * o call the 802.11 layer before detaching ath5k_hw to 882 * insure callbacks into the driver to delete global 883 * key cache entries can be handled 884 * o reclaim the tx queue data structures after calling 885 * the 802.11 layer as we'll get called back to reclaim 886 * node state and potentially want to use them 887 * o to cleanup the tx queues the hal is called, so detach 888 * it last 889 * XXX: ??? detach ath5k_hw ??? 890 * Other than that, it's straightforward... 891 */ 892 ieee80211_unregister_hw(hw); 893 ath5k_desc_free(sc, pdev); 894 ath5k_txq_release(sc); 895 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 896 ath5k_unregister_leds(sc); 897 898 /* 899 * NB: can't reclaim these until after ieee80211_ifdetach 900 * returns because we'll get called back to reclaim node 901 * state and potentially want to use them. 902 */ 903 } 904 905 906 907 908 /********************\ 909 * Channel/mode setup * 910 \********************/ 911 912 /* 913 * Convert IEEE channel number to MHz frequency. 914 */ 915 static inline short 916 ath5k_ieee2mhz(short chan) 917 { 918 if (chan <= 14 || chan >= 27) 919 return ieee80211chan2mhz(chan); 920 else 921 return 2212 + chan * 20; 922 } 923 924 /* 925 * Returns true for the channel numbers used without all_channels modparam. 926 */ 927 static bool ath5k_is_standard_channel(short chan) 928 { 929 return ((chan <= 14) || 930 /* UNII 1,2 */ 931 ((chan & 3) == 0 && chan >= 36 && chan <= 64) || 932 /* midband */ 933 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 934 /* UNII-3 */ 935 ((chan & 3) == 1 && chan >= 149 && chan <= 165)); 936 } 937 938 static unsigned int 939 ath5k_copy_channels(struct ath5k_hw *ah, 940 struct ieee80211_channel *channels, 941 unsigned int mode, 942 unsigned int max) 943 { 944 unsigned int i, count, size, chfreq, freq, ch; 945 946 if (!test_bit(mode, ah->ah_modes)) 947 return 0; 948 949 switch (mode) { 950 case AR5K_MODE_11A: 951 case AR5K_MODE_11A_TURBO: 952 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 953 size = 220 ; 954 chfreq = CHANNEL_5GHZ; 955 break; 956 case AR5K_MODE_11B: 957 case AR5K_MODE_11G: 958 case AR5K_MODE_11G_TURBO: 959 size = 26; 960 chfreq = CHANNEL_2GHZ; 961 break; 962 default: 963 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 964 return 0; 965 } 966 967 for (i = 0, count = 0; i < size && max > 0; i++) { 968 ch = i + 1 ; 969 freq = ath5k_ieee2mhz(ch); 970 971 /* Check if channel is supported by the chipset */ 972 if (!ath5k_channel_ok(ah, freq, chfreq)) 973 continue; 974 975 if (!modparam_all_channels && !ath5k_is_standard_channel(ch)) 976 continue; 977 978 /* Write channel info and increment counter */ 979 channels[count].center_freq = freq; 980 channels[count].band = (chfreq == CHANNEL_2GHZ) ? 981 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 982 switch (mode) { 983 case AR5K_MODE_11A: 984 case AR5K_MODE_11G: 985 channels[count].hw_value = chfreq | CHANNEL_OFDM; 986 break; 987 case AR5K_MODE_11A_TURBO: 988 case AR5K_MODE_11G_TURBO: 989 channels[count].hw_value = chfreq | 990 CHANNEL_OFDM | CHANNEL_TURBO; 991 break; 992 case AR5K_MODE_11B: 993 channels[count].hw_value = CHANNEL_B; 994 } 995 996 count++; 997 max--; 998 } 999 1000 return count; 1001 } 1002 1003 static void 1004 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 1005 { 1006 u8 i; 1007 1008 for (i = 0; i < AR5K_MAX_RATES; i++) 1009 sc->rate_idx[b->band][i] = -1; 1010 1011 for (i = 0; i < b->n_bitrates; i++) { 1012 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 1013 if (b->bitrates[i].hw_value_short) 1014 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 1015 } 1016 } 1017 1018 static int 1019 ath5k_setup_bands(struct ieee80211_hw *hw) 1020 { 1021 struct ath5k_softc *sc = hw->priv; 1022 struct ath5k_hw *ah = sc->ah; 1023 struct ieee80211_supported_band *sband; 1024 int max_c, count_c = 0; 1025 int i; 1026 1027 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 1028 max_c = ARRAY_SIZE(sc->channels); 1029 1030 /* 2GHz band */ 1031 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1032 sband->band = IEEE80211_BAND_2GHZ; 1033 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 1034 1035 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 1036 /* G mode */ 1037 memcpy(sband->bitrates, &ath5k_rates[0], 1038 sizeof(struct ieee80211_rate) * 12); 1039 sband->n_bitrates = 12; 1040 1041 sband->channels = sc->channels; 1042 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1043 AR5K_MODE_11G, max_c); 1044 1045 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1046 count_c = sband->n_channels; 1047 max_c -= count_c; 1048 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 1049 /* B mode */ 1050 memcpy(sband->bitrates, &ath5k_rates[0], 1051 sizeof(struct ieee80211_rate) * 4); 1052 sband->n_bitrates = 4; 1053 1054 /* 5211 only supports B rates and uses 4bit rate codes 1055 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 1056 * fix them up here: 1057 */ 1058 if (ah->ah_version == AR5K_AR5211) { 1059 for (i = 0; i < 4; i++) { 1060 sband->bitrates[i].hw_value = 1061 sband->bitrates[i].hw_value & 0xF; 1062 sband->bitrates[i].hw_value_short = 1063 sband->bitrates[i].hw_value_short & 0xF; 1064 } 1065 } 1066 1067 sband->channels = sc->channels; 1068 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1069 AR5K_MODE_11B, max_c); 1070 1071 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1072 count_c = sband->n_channels; 1073 max_c -= count_c; 1074 } 1075 ath5k_setup_rate_idx(sc, sband); 1076 1077 /* 5GHz band, A mode */ 1078 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 1079 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1080 sband->band = IEEE80211_BAND_5GHZ; 1081 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 1082 1083 memcpy(sband->bitrates, &ath5k_rates[4], 1084 sizeof(struct ieee80211_rate) * 8); 1085 sband->n_bitrates = 8; 1086 1087 sband->channels = &sc->channels[count_c]; 1088 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1089 AR5K_MODE_11A, max_c); 1090 1091 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 1092 } 1093 ath5k_setup_rate_idx(sc, sband); 1094 1095 ath5k_debug_dump_bands(sc); 1096 1097 return 0; 1098 } 1099 1100 /* 1101 * Set/change channels. We always reset the chip. 1102 * To accomplish this we must first cleanup any pending DMA, 1103 * then restart stuff after a la ath5k_init. 1104 * 1105 * Called with sc->lock. 1106 */ 1107 static int 1108 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 1109 { 1110 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", 1111 sc->curchan->center_freq, chan->center_freq); 1112 1113 /* 1114 * To switch channels clear any pending DMA operations; 1115 * wait long enough for the RX fifo to drain, reset the 1116 * hardware at the new frequency, and then re-enable 1117 * the relevant bits of the h/w. 1118 */ 1119 return ath5k_reset(sc, chan); 1120 } 1121 1122 static void 1123 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) 1124 { 1125 sc->curmode = mode; 1126 1127 if (mode == AR5K_MODE_11A) { 1128 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1129 } else { 1130 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1131 } 1132 } 1133 1134 static void 1135 ath5k_mode_setup(struct ath5k_softc *sc) 1136 { 1137 struct ath5k_hw *ah = sc->ah; 1138 u32 rfilt; 1139 1140 ah->ah_op_mode = sc->opmode; 1141 1142 /* configure rx filter */ 1143 rfilt = sc->filter_flags; 1144 ath5k_hw_set_rx_filter(ah, rfilt); 1145 1146 if (ath5k_hw_hasbssidmask(ah)) 1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask); 1148 1149 /* configure operational mode */ 1150 ath5k_hw_set_opmode(ah); 1151 1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 1153 } 1154 1155 static inline int 1156 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 1157 { 1158 int rix; 1159 1160 /* return base rate on errors */ 1161 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 1162 "hw_rix out of bounds: %x\n", hw_rix)) 1163 return 0; 1164 1165 rix = sc->rate_idx[sc->curband->band][hw_rix]; 1166 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 1167 rix = 0; 1168 1169 return rix; 1170 } 1171 1172 /***************\ 1173 * Buffers setup * 1174 \***************/ 1175 1176 static 1177 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 1178 { 1179 struct ath_common *common = ath5k_hw_common(sc->ah); 1180 struct sk_buff *skb; 1181 1182 /* 1183 * Allocate buffer with headroom_needed space for the 1184 * fake physical layer header at the start. 1185 */ 1186 skb = ath_rxbuf_alloc(common, 1187 common->rx_bufsize, 1188 GFP_ATOMIC); 1189 1190 if (!skb) { 1191 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 1192 common->rx_bufsize); 1193 return NULL; 1194 } 1195 1196 *skb_addr = pci_map_single(sc->pdev, 1197 skb->data, common->rx_bufsize, 1198 PCI_DMA_FROMDEVICE); 1199 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) { 1200 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 1201 dev_kfree_skb(skb); 1202 return NULL; 1203 } 1204 return skb; 1205 } 1206 1207 static int 1208 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1209 { 1210 struct ath5k_hw *ah = sc->ah; 1211 struct sk_buff *skb = bf->skb; 1212 struct ath5k_desc *ds; 1213 1214 if (!skb) { 1215 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 1216 if (!skb) 1217 return -ENOMEM; 1218 bf->skb = skb; 1219 } 1220 1221 /* 1222 * Setup descriptors. For receive we always terminate 1223 * the descriptor list with a self-linked entry so we'll 1224 * not get overrun under high load (as can happen with a 1225 * 5212 when ANI processing enables PHY error frames). 1226 * 1227 * To insure the last descriptor is self-linked we create 1228 * each descriptor as self-linked and add it to the end. As 1229 * each additional descriptor is added the previous self-linked 1230 * entry is ``fixed'' naturally. This should be safe even 1231 * if DMA is happening. When processing RX interrupts we 1232 * never remove/process the last, self-linked, entry on the 1233 * descriptor list. This insures the hardware always has 1234 * someplace to write a new frame. 1235 */ 1236 ds = bf->desc; 1237 ds->ds_link = bf->daddr; /* link to self */ 1238 ds->ds_data = bf->skbaddr; 1239 ah->ah_setup_rx_desc(ah, ds, 1240 skb_tailroom(skb), /* buffer size */ 1241 0); 1242 1243 if (sc->rxlink != NULL) 1244 *sc->rxlink = bf->daddr; 1245 sc->rxlink = &ds->ds_link; 1246 return 0; 1247 } 1248 1249 static int 1250 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1251 struct ath5k_txq *txq) 1252 { 1253 struct ath5k_hw *ah = sc->ah; 1254 struct ath5k_desc *ds = bf->desc; 1255 struct sk_buff *skb = bf->skb; 1256 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1257 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 1258 struct ieee80211_rate *rate; 1259 unsigned int mrr_rate[3], mrr_tries[3]; 1260 int i, ret; 1261 u16 hw_rate; 1262 u16 cts_rate = 0; 1263 u16 duration = 0; 1264 u8 rc_flags; 1265 1266 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 1267 1268 /* XXX endianness */ 1269 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 1270 PCI_DMA_TODEVICE); 1271 1272 rate = ieee80211_get_tx_rate(sc->hw, info); 1273 1274 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1275 flags |= AR5K_TXDESC_NOACK; 1276 1277 rc_flags = info->control.rates[0].flags; 1278 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 1279 rate->hw_value_short : rate->hw_value; 1280 1281 pktlen = skb->len; 1282 1283 /* FIXME: If we are in g mode and rate is a CCK rate 1284 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1285 * from tx power (value is in dB units already) */ 1286 if (info->control.hw_key) { 1287 keyidx = info->control.hw_key->hw_key_idx; 1288 pktlen += info->control.hw_key->icv_len; 1289 } 1290 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1291 flags |= AR5K_TXDESC_RTSENA; 1292 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1293 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 1294 sc->vif, pktlen, info)); 1295 } 1296 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1297 flags |= AR5K_TXDESC_CTSENA; 1298 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1299 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 1300 sc->vif, pktlen, info)); 1301 } 1302 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1303 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, 1304 (sc->power_level * 2), 1305 hw_rate, 1306 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 1307 cts_rate, duration); 1308 if (ret) 1309 goto err_unmap; 1310 1311 memset(mrr_rate, 0, sizeof(mrr_rate)); 1312 memset(mrr_tries, 0, sizeof(mrr_tries)); 1313 for (i = 0; i < 3; i++) { 1314 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 1315 if (!rate) 1316 break; 1317 1318 mrr_rate[i] = rate->hw_value; 1319 mrr_tries[i] = info->control.rates[i + 1].count; 1320 } 1321 1322 ah->ah_setup_mrr_tx_desc(ah, ds, 1323 mrr_rate[0], mrr_tries[0], 1324 mrr_rate[1], mrr_tries[1], 1325 mrr_rate[2], mrr_tries[2]); 1326 1327 ds->ds_link = 0; 1328 ds->ds_data = bf->skbaddr; 1329 1330 spin_lock_bh(&txq->lock); 1331 list_add_tail(&bf->list, &txq->q); 1332 sc->tx_stats[txq->qnum].len++; 1333 if (txq->link == NULL) /* is this first packet? */ 1334 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 1335 else /* no, so only link it */ 1336 *txq->link = bf->daddr; 1337 1338 txq->link = &ds->ds_link; 1339 ath5k_hw_start_tx_dma(ah, txq->qnum); 1340 mmiowb(); 1341 spin_unlock_bh(&txq->lock); 1342 1343 return 0; 1344 err_unmap: 1345 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 1346 return ret; 1347 } 1348 1349 /*******************\ 1350 * Descriptors setup * 1351 \*******************/ 1352 1353 static int 1354 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) 1355 { 1356 struct ath5k_desc *ds; 1357 struct ath5k_buf *bf; 1358 dma_addr_t da; 1359 unsigned int i; 1360 int ret; 1361 1362 /* allocate descriptors */ 1363 sc->desc_len = sizeof(struct ath5k_desc) * 1364 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 1365 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); 1366 if (sc->desc == NULL) { 1367 ATH5K_ERR(sc, "can't allocate descriptors\n"); 1368 ret = -ENOMEM; 1369 goto err; 1370 } 1371 ds = sc->desc; 1372 da = sc->desc_daddr; 1373 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 1374 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 1375 1376 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 1377 sizeof(struct ath5k_buf), GFP_KERNEL); 1378 if (bf == NULL) { 1379 ATH5K_ERR(sc, "can't allocate bufptr\n"); 1380 ret = -ENOMEM; 1381 goto err_free; 1382 } 1383 sc->bufptr = bf; 1384 1385 INIT_LIST_HEAD(&sc->rxbuf); 1386 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 1387 bf->desc = ds; 1388 bf->daddr = da; 1389 list_add_tail(&bf->list, &sc->rxbuf); 1390 } 1391 1392 INIT_LIST_HEAD(&sc->txbuf); 1393 sc->txbuf_len = ATH_TXBUF; 1394 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 1395 da += sizeof(*ds)) { 1396 bf->desc = ds; 1397 bf->daddr = da; 1398 list_add_tail(&bf->list, &sc->txbuf); 1399 } 1400 1401 /* beacon buffer */ 1402 bf->desc = ds; 1403 bf->daddr = da; 1404 sc->bbuf = bf; 1405 1406 return 0; 1407 err_free: 1408 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1409 err: 1410 sc->desc = NULL; 1411 return ret; 1412 } 1413 1414 static void 1415 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) 1416 { 1417 struct ath5k_buf *bf; 1418 1419 ath5k_txbuf_free(sc, sc->bbuf); 1420 list_for_each_entry(bf, &sc->txbuf, list) 1421 ath5k_txbuf_free(sc, bf); 1422 list_for_each_entry(bf, &sc->rxbuf, list) 1423 ath5k_rxbuf_free(sc, bf); 1424 1425 /* Free memory associated with all descriptors */ 1426 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1427 1428 kfree(sc->bufptr); 1429 sc->bufptr = NULL; 1430 } 1431 1432 1433 1434 1435 1436 /**************\ 1437 * Queues setup * 1438 \**************/ 1439 1440 static struct ath5k_txq * 1441 ath5k_txq_setup(struct ath5k_softc *sc, 1442 int qtype, int subtype) 1443 { 1444 struct ath5k_hw *ah = sc->ah; 1445 struct ath5k_txq *txq; 1446 struct ath5k_txq_info qi = { 1447 .tqi_subtype = subtype, 1448 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1449 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1450 .tqi_cw_max = AR5K_TXQ_USEDEFAULT 1451 }; 1452 int qnum; 1453 1454 /* 1455 * Enable interrupts only for EOL and DESC conditions. 1456 * We mark tx descriptors to receive a DESC interrupt 1457 * when a tx queue gets deep; otherwise waiting for the 1458 * EOL to reap descriptors. Note that this is done to 1459 * reduce interrupt load and this only defers reaping 1460 * descriptors, never transmitting frames. Aside from 1461 * reducing interrupts this also permits more concurrency. 1462 * The only potential downside is if the tx queue backs 1463 * up in which case the top half of the kernel may backup 1464 * due to a lack of tx descriptors. 1465 */ 1466 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1467 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1468 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1469 if (qnum < 0) { 1470 /* 1471 * NB: don't print a message, this happens 1472 * normally on parts with too few tx queues 1473 */ 1474 return ERR_PTR(qnum); 1475 } 1476 if (qnum >= ARRAY_SIZE(sc->txqs)) { 1477 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 1478 qnum, ARRAY_SIZE(sc->txqs)); 1479 ath5k_hw_release_tx_queue(ah, qnum); 1480 return ERR_PTR(-EINVAL); 1481 } 1482 txq = &sc->txqs[qnum]; 1483 if (!txq->setup) { 1484 txq->qnum = qnum; 1485 txq->link = NULL; 1486 INIT_LIST_HEAD(&txq->q); 1487 spin_lock_init(&txq->lock); 1488 txq->setup = true; 1489 } 1490 return &sc->txqs[qnum]; 1491 } 1492 1493 static int 1494 ath5k_beaconq_setup(struct ath5k_hw *ah) 1495 { 1496 struct ath5k_txq_info qi = { 1497 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1498 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1499 .tqi_cw_max = AR5K_TXQ_USEDEFAULT, 1500 /* NB: for dynamic turbo, don't enable any other interrupts */ 1501 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1502 }; 1503 1504 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1505 } 1506 1507 static int 1508 ath5k_beaconq_config(struct ath5k_softc *sc) 1509 { 1510 struct ath5k_hw *ah = sc->ah; 1511 struct ath5k_txq_info qi; 1512 int ret; 1513 1514 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 1515 if (ret) 1516 return ret; 1517 if (sc->opmode == NL80211_IFTYPE_AP || 1518 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1519 /* 1520 * Always burst out beacon and CAB traffic 1521 * (aifs = cwmin = cwmax = 0) 1522 */ 1523 qi.tqi_aifs = 0; 1524 qi.tqi_cw_min = 0; 1525 qi.tqi_cw_max = 0; 1526 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 1527 /* 1528 * Adhoc mode; backoff between 0 and (2 * cw_min). 1529 */ 1530 qi.tqi_aifs = 0; 1531 qi.tqi_cw_min = 0; 1532 qi.tqi_cw_max = 2 * ah->ah_cw_min; 1533 } 1534 1535 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1536 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1537 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1538 1539 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1540 if (ret) { 1541 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1542 "hardware queue!\n", __func__); 1543 return ret; 1544 } 1545 1546 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; 1547 } 1548 1549 static void 1550 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1551 { 1552 struct ath5k_buf *bf, *bf0; 1553 1554 /* 1555 * NB: this assumes output has been stopped and 1556 * we do not need to block ath5k_tx_tasklet 1557 */ 1558 spin_lock_bh(&txq->lock); 1559 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1560 ath5k_debug_printtxbuf(sc, bf); 1561 1562 ath5k_txbuf_free(sc, bf); 1563 1564 spin_lock_bh(&sc->txbuflock); 1565 sc->tx_stats[txq->qnum].len--; 1566 list_move_tail(&bf->list, &sc->txbuf); 1567 sc->txbuf_len++; 1568 spin_unlock_bh(&sc->txbuflock); 1569 } 1570 txq->link = NULL; 1571 spin_unlock_bh(&txq->lock); 1572 } 1573 1574 /* 1575 * Drain the transmit queues and reclaim resources. 1576 */ 1577 static void 1578 ath5k_txq_cleanup(struct ath5k_softc *sc) 1579 { 1580 struct ath5k_hw *ah = sc->ah; 1581 unsigned int i; 1582 1583 /* XXX return value */ 1584 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { 1585 /* don't touch the hardware if marked invalid */ 1586 ath5k_hw_stop_tx_dma(ah, sc->bhalq); 1587 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", 1588 ath5k_hw_get_txdp(ah, sc->bhalq)); 1589 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1590 if (sc->txqs[i].setup) { 1591 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); 1592 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " 1593 "link %p\n", 1594 sc->txqs[i].qnum, 1595 ath5k_hw_get_txdp(ah, 1596 sc->txqs[i].qnum), 1597 sc->txqs[i].link); 1598 } 1599 } 1600 ieee80211_wake_queues(sc->hw); /* XXX move to callers */ 1601 1602 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1603 if (sc->txqs[i].setup) 1604 ath5k_txq_drainq(sc, &sc->txqs[i]); 1605 } 1606 1607 static void 1608 ath5k_txq_release(struct ath5k_softc *sc) 1609 { 1610 struct ath5k_txq *txq = sc->txqs; 1611 unsigned int i; 1612 1613 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1614 if (txq->setup) { 1615 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1616 txq->setup = false; 1617 } 1618 } 1619 1620 1621 1622 1623 /*************\ 1624 * RX Handling * 1625 \*************/ 1626 1627 /* 1628 * Enable the receive h/w following a reset. 1629 */ 1630 static int 1631 ath5k_rx_start(struct ath5k_softc *sc) 1632 { 1633 struct ath5k_hw *ah = sc->ah; 1634 struct ath_common *common = ath5k_hw_common(ah); 1635 struct ath5k_buf *bf; 1636 int ret; 1637 1638 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz); 1639 1640 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1641 common->cachelsz, common->rx_bufsize); 1642 1643 spin_lock_bh(&sc->rxbuflock); 1644 sc->rxlink = NULL; 1645 list_for_each_entry(bf, &sc->rxbuf, list) { 1646 ret = ath5k_rxbuf_setup(sc, bf); 1647 if (ret != 0) { 1648 spin_unlock_bh(&sc->rxbuflock); 1649 goto err; 1650 } 1651 } 1652 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1653 ath5k_hw_set_rxdp(ah, bf->daddr); 1654 spin_unlock_bh(&sc->rxbuflock); 1655 1656 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1657 ath5k_mode_setup(sc); /* set filters, etc. */ 1658 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1659 1660 return 0; 1661 err: 1662 return ret; 1663 } 1664 1665 /* 1666 * Disable the receive h/w in preparation for a reset. 1667 */ 1668 static void 1669 ath5k_rx_stop(struct ath5k_softc *sc) 1670 { 1671 struct ath5k_hw *ah = sc->ah; 1672 1673 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1674 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1675 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ 1676 1677 ath5k_debug_printrxbuffs(sc, ah); 1678 1679 sc->rxlink = NULL; /* just in case */ 1680 } 1681 1682 static unsigned int 1683 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, 1684 struct sk_buff *skb, struct ath5k_rx_status *rs) 1685 { 1686 struct ath5k_hw *ah = sc->ah; 1687 struct ath_common *common = ath5k_hw_common(ah); 1688 struct ieee80211_hdr *hdr = (void *)skb->data; 1689 unsigned int keyix, hlen; 1690 1691 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1692 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1693 return RX_FLAG_DECRYPTED; 1694 1695 /* Apparently when a default key is used to decrypt the packet 1696 the hw does not set the index used to decrypt. In such cases 1697 get the index from the packet. */ 1698 hlen = ieee80211_hdrlen(hdr->frame_control); 1699 if (ieee80211_has_protected(hdr->frame_control) && 1700 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1701 skb->len >= hlen + 4) { 1702 keyix = skb->data[hlen + 3] >> 6; 1703 1704 if (test_bit(keyix, common->keymap)) 1705 return RX_FLAG_DECRYPTED; 1706 } 1707 1708 return 0; 1709 } 1710 1711 1712 static void 1713 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1714 struct ieee80211_rx_status *rxs) 1715 { 1716 struct ath_common *common = ath5k_hw_common(sc->ah); 1717 u64 tsf, bc_tstamp; 1718 u32 hw_tu; 1719 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1720 1721 if (ieee80211_is_beacon(mgmt->frame_control) && 1722 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1723 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1724 /* 1725 * Received an IBSS beacon with the same BSSID. Hardware *must* 1726 * have updated the local TSF. We have to work around various 1727 * hardware bugs, though... 1728 */ 1729 tsf = ath5k_hw_get_tsf64(sc->ah); 1730 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1731 hw_tu = TSF_TO_TU(tsf); 1732 1733 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1734 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1735 (unsigned long long)bc_tstamp, 1736 (unsigned long long)rxs->mactime, 1737 (unsigned long long)(rxs->mactime - bc_tstamp), 1738 (unsigned long long)tsf); 1739 1740 /* 1741 * Sometimes the HW will give us a wrong tstamp in the rx 1742 * status, causing the timestamp extension to go wrong. 1743 * (This seems to happen especially with beacon frames bigger 1744 * than 78 byte (incl. FCS)) 1745 * But we know that the receive timestamp must be later than the 1746 * timestamp of the beacon since HW must have synced to that. 1747 * 1748 * NOTE: here we assume mactime to be after the frame was 1749 * received, not like mac80211 which defines it at the start. 1750 */ 1751 if (bc_tstamp > rxs->mactime) { 1752 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1753 "fixing mactime from %llx to %llx\n", 1754 (unsigned long long)rxs->mactime, 1755 (unsigned long long)tsf); 1756 rxs->mactime = tsf; 1757 } 1758 1759 /* 1760 * Local TSF might have moved higher than our beacon timers, 1761 * in that case we have to update them to continue sending 1762 * beacons. This also takes care of synchronizing beacon sending 1763 * times with other stations. 1764 */ 1765 if (hw_tu >= sc->nexttbtt) 1766 ath5k_beacon_update_timers(sc, bc_tstamp); 1767 } 1768 } 1769 1770 static void 1771 ath5k_tasklet_rx(unsigned long data) 1772 { 1773 struct ieee80211_rx_status *rxs; 1774 struct ath5k_rx_status rs = {}; 1775 struct sk_buff *skb, *next_skb; 1776 dma_addr_t next_skb_addr; 1777 struct ath5k_softc *sc = (void *)data; 1778 struct ath5k_hw *ah = sc->ah; 1779 struct ath_common *common = ath5k_hw_common(ah); 1780 struct ath5k_buf *bf; 1781 struct ath5k_desc *ds; 1782 int ret; 1783 int hdrlen; 1784 int padsize; 1785 int rx_flag; 1786 1787 spin_lock(&sc->rxbuflock); 1788 if (list_empty(&sc->rxbuf)) { 1789 ATH5K_WARN(sc, "empty rx buf pool\n"); 1790 goto unlock; 1791 } 1792 do { 1793 rx_flag = 0; 1794 1795 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1796 BUG_ON(bf->skb == NULL); 1797 skb = bf->skb; 1798 ds = bf->desc; 1799 1800 /* bail if HW is still using self-linked descriptor */ 1801 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1802 break; 1803 1804 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1805 if (unlikely(ret == -EINPROGRESS)) 1806 break; 1807 else if (unlikely(ret)) { 1808 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1809 spin_unlock(&sc->rxbuflock); 1810 return; 1811 } 1812 1813 if (unlikely(rs.rs_more)) { 1814 ATH5K_WARN(sc, "unsupported jumbo\n"); 1815 goto next; 1816 } 1817 1818 if (unlikely(rs.rs_status)) { 1819 if (rs.rs_status & AR5K_RXERR_PHY) 1820 goto next; 1821 if (rs.rs_status & AR5K_RXERR_DECRYPT) { 1822 /* 1823 * Decrypt error. If the error occurred 1824 * because there was no hardware key, then 1825 * let the frame through so the upper layers 1826 * can process it. This is necessary for 5210 1827 * parts which have no way to setup a ``clear'' 1828 * key cache entry. 1829 * 1830 * XXX do key cache faulting 1831 */ 1832 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && 1833 !(rs.rs_status & AR5K_RXERR_CRC)) 1834 goto accept; 1835 } 1836 if (rs.rs_status & AR5K_RXERR_MIC) { 1837 rx_flag |= RX_FLAG_MMIC_ERROR; 1838 goto accept; 1839 } 1840 1841 /* let crypto-error packets fall through in MNTR */ 1842 if ((rs.rs_status & 1843 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || 1844 sc->opmode != NL80211_IFTYPE_MONITOR) 1845 goto next; 1846 } 1847 accept: 1848 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1849 1850 /* 1851 * If we can't replace bf->skb with a new skb under memory 1852 * pressure, just skip this packet 1853 */ 1854 if (!next_skb) 1855 goto next; 1856 1857 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize, 1858 PCI_DMA_FROMDEVICE); 1859 skb_put(skb, rs.rs_datalen); 1860 1861 /* The MAC header is padded to have 32-bit boundary if the 1862 * packet payload is non-zero. The general calculation for 1863 * padsize would take into account odd header lengths: 1864 * padsize = (4 - hdrlen % 4) % 4; However, since only 1865 * even-length headers are used, padding can only be 0 or 2 1866 * bytes and we can optimize this a bit. In addition, we must 1867 * not try to remove padding from short control frames that do 1868 * not have payload. */ 1869 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1870 padsize = ath5k_pad_size(hdrlen); 1871 if (padsize) { 1872 memmove(skb->data + padsize, skb->data, hdrlen); 1873 skb_pull(skb, padsize); 1874 } 1875 rxs = IEEE80211_SKB_RXCB(skb); 1876 1877 /* 1878 * always extend the mac timestamp, since this information is 1879 * also needed for proper IBSS merging. 1880 * 1881 * XXX: it might be too late to do it here, since rs_tstamp is 1882 * 15bit only. that means TSF extension has to be done within 1883 * 32768usec (about 32ms). it might be necessary to move this to 1884 * the interrupt handler, like it is done in madwifi. 1885 * 1886 * Unfortunately we don't know when the hardware takes the rx 1887 * timestamp (beginning of phy frame, data frame, end of rx?). 1888 * The only thing we know is that it is hardware specific... 1889 * On AR5213 it seems the rx timestamp is at the end of the 1890 * frame, but i'm not sure. 1891 * 1892 * NOTE: mac80211 defines mactime at the beginning of the first 1893 * data symbol. Since we don't have any time references it's 1894 * impossible to comply to that. This affects IBSS merge only 1895 * right now, so it's not too bad... 1896 */ 1897 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp); 1898 rxs->flag = rx_flag | RX_FLAG_TSFT; 1899 1900 rxs->freq = sc->curchan->center_freq; 1901 rxs->band = sc->curband->band; 1902 1903 rxs->noise = sc->ah->ah_noise_floor; 1904 rxs->signal = rxs->noise + rs.rs_rssi; 1905 1906 rxs->antenna = rs.rs_antenna; 1907 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 1908 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); 1909 1910 if (rxs->rate_idx >= 0 && rs.rs_rate == 1911 sc->curband->bitrates[rxs->rate_idx].hw_value_short) 1912 rxs->flag |= RX_FLAG_SHORTPRE; 1913 1914 ath5k_debug_dump_skb(sc, skb, "RX ", 0); 1915 1916 /* check beacons in IBSS mode */ 1917 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1918 ath5k_check_ibss_tsf(sc, skb, rxs); 1919 1920 ieee80211_rx(sc->hw, skb); 1921 1922 bf->skb = next_skb; 1923 bf->skbaddr = next_skb_addr; 1924 next: 1925 list_move_tail(&bf->list, &sc->rxbuf); 1926 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1927 unlock: 1928 spin_unlock(&sc->rxbuflock); 1929 } 1930 1931 1932 1933 1934 /*************\ 1935 * TX Handling * 1936 \*************/ 1937 1938 static void 1939 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1940 { 1941 struct ath5k_tx_status ts = {}; 1942 struct ath5k_buf *bf, *bf0; 1943 struct ath5k_desc *ds; 1944 struct sk_buff *skb; 1945 struct ieee80211_tx_info *info; 1946 int i, ret; 1947 1948 spin_lock(&txq->lock); 1949 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1950 ds = bf->desc; 1951 1952 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1953 if (unlikely(ret == -EINPROGRESS)) 1954 break; 1955 else if (unlikely(ret)) { 1956 ATH5K_ERR(sc, "error %d while processing queue %u\n", 1957 ret, txq->qnum); 1958 break; 1959 } 1960 1961 skb = bf->skb; 1962 info = IEEE80211_SKB_CB(skb); 1963 bf->skb = NULL; 1964 1965 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, 1966 PCI_DMA_TODEVICE); 1967 1968 ieee80211_tx_info_clear_status(info); 1969 for (i = 0; i < 4; i++) { 1970 struct ieee80211_tx_rate *r = 1971 &info->status.rates[i]; 1972 1973 if (ts.ts_rate[i]) { 1974 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]); 1975 r->count = ts.ts_retry[i]; 1976 } else { 1977 r->idx = -1; 1978 r->count = 0; 1979 } 1980 } 1981 1982 /* count the successful attempt as well */ 1983 info->status.rates[ts.ts_final_idx].count++; 1984 1985 if (unlikely(ts.ts_status)) { 1986 sc->ll_stats.dot11ACKFailureCount++; 1987 if (ts.ts_status & AR5K_TXERR_FILT) 1988 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1989 } else { 1990 info->flags |= IEEE80211_TX_STAT_ACK; 1991 info->status.ack_signal = ts.ts_rssi; 1992 } 1993 1994 ieee80211_tx_status(sc->hw, skb); 1995 sc->tx_stats[txq->qnum].count++; 1996 1997 spin_lock(&sc->txbuflock); 1998 sc->tx_stats[txq->qnum].len--; 1999 list_move_tail(&bf->list, &sc->txbuf); 2000 sc->txbuf_len++; 2001 spin_unlock(&sc->txbuflock); 2002 } 2003 if (likely(list_empty(&txq->q))) 2004 txq->link = NULL; 2005 spin_unlock(&txq->lock); 2006 if (sc->txbuf_len > ATH_TXBUF / 5) 2007 ieee80211_wake_queues(sc->hw); 2008 } 2009 2010 static void 2011 ath5k_tasklet_tx(unsigned long data) 2012 { 2013 int i; 2014 struct ath5k_softc *sc = (void *)data; 2015 2016 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 2017 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 2018 ath5k_tx_processq(sc, &sc->txqs[i]); 2019 } 2020 2021 2022 /*****************\ 2023 * Beacon handling * 2024 \*****************/ 2025 2026 /* 2027 * Setup the beacon frame for transmit. 2028 */ 2029 static int 2030 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 2031 { 2032 struct sk_buff *skb = bf->skb; 2033 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2034 struct ath5k_hw *ah = sc->ah; 2035 struct ath5k_desc *ds; 2036 int ret = 0; 2037 u8 antenna; 2038 u32 flags; 2039 2040 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 2041 PCI_DMA_TODEVICE); 2042 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 2043 "skbaddr %llx\n", skb, skb->data, skb->len, 2044 (unsigned long long)bf->skbaddr); 2045 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) { 2046 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 2047 return -EIO; 2048 } 2049 2050 ds = bf->desc; 2051 antenna = ah->ah_tx_ant; 2052 2053 flags = AR5K_TXDESC_NOACK; 2054 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 2055 ds->ds_link = bf->daddr; /* self-linked */ 2056 flags |= AR5K_TXDESC_VEOL; 2057 } else 2058 ds->ds_link = 0; 2059 2060 /* 2061 * If we use multiple antennas on AP and use 2062 * the Sectored AP scenario, switch antenna every 2063 * 4 beacons to make sure everybody hears our AP. 2064 * When a client tries to associate, hw will keep 2065 * track of the tx antenna to be used for this client 2066 * automaticaly, based on ACKed packets. 2067 * 2068 * Note: AP still listens and transmits RTS on the 2069 * default antenna which is supposed to be an omni. 2070 * 2071 * Note2: On sectored scenarios it's possible to have 2072 * multiple antennas (1omni -the default- and 14 sectors) 2073 * so if we choose to actually support this mode we need 2074 * to allow user to set how many antennas we have and tweak 2075 * the code below to send beacons on all of them. 2076 */ 2077 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 2078 antenna = sc->bsent & 4 ? 2 : 1; 2079 2080 2081 /* FIXME: If we are in g mode and rate is a CCK rate 2082 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 2083 * from tx power (value is in dB units already) */ 2084 ds->ds_data = bf->skbaddr; 2085 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 2086 ieee80211_get_hdrlen_from_skb(skb), 2087 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 2088 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 2089 1, AR5K_TXKEYIX_INVALID, 2090 antenna, flags, 0, 0); 2091 if (ret) 2092 goto err_unmap; 2093 2094 return 0; 2095 err_unmap: 2096 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 2097 return ret; 2098 } 2099 2100 /* 2101 * Transmit a beacon frame at SWBA. Dynamic updates to the 2102 * frame contents are done as needed and the slot time is 2103 * also adjusted based on current state. 2104 * 2105 * This is called from software irq context (beacontq or restq 2106 * tasklets) or user context from ath5k_beacon_config. 2107 */ 2108 static void 2109 ath5k_beacon_send(struct ath5k_softc *sc) 2110 { 2111 struct ath5k_buf *bf = sc->bbuf; 2112 struct ath5k_hw *ah = sc->ah; 2113 struct sk_buff *skb; 2114 2115 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 2116 2117 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 2118 sc->opmode == NL80211_IFTYPE_MONITOR)) { 2119 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 2120 return; 2121 } 2122 /* 2123 * Check if the previous beacon has gone out. If 2124 * not don't don't try to post another, skip this 2125 * period and wait for the next. Missed beacons 2126 * indicate a problem and should not occur. If we 2127 * miss too many consecutive beacons reset the device. 2128 */ 2129 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 2130 sc->bmisscount++; 2131 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2132 "missed %u consecutive beacons\n", sc->bmisscount); 2133 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 2134 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2135 "stuck beacon time (%u missed)\n", 2136 sc->bmisscount); 2137 tasklet_schedule(&sc->restq); 2138 } 2139 return; 2140 } 2141 if (unlikely(sc->bmisscount != 0)) { 2142 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2143 "resume beacon xmit after %u misses\n", 2144 sc->bmisscount); 2145 sc->bmisscount = 0; 2146 } 2147 2148 /* 2149 * Stop any current dma and put the new frame on the queue. 2150 * This should never fail since we check above that no frames 2151 * are still pending on the queue. 2152 */ 2153 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { 2154 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 2155 /* NB: hw still stops DMA, so proceed */ 2156 } 2157 2158 /* refresh the beacon for AP mode */ 2159 if (sc->opmode == NL80211_IFTYPE_AP) 2160 ath5k_beacon_update(sc->hw, sc->vif); 2161 2162 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 2163 ath5k_hw_start_tx_dma(ah, sc->bhalq); 2164 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2165 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 2166 2167 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2168 while (skb) { 2169 ath5k_tx_queue(sc->hw, skb, sc->cabq); 2170 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2171 } 2172 2173 sc->bsent++; 2174 } 2175 2176 2177 /** 2178 * ath5k_beacon_update_timers - update beacon timers 2179 * 2180 * @sc: struct ath5k_softc pointer we are operating on 2181 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2182 * beacon timer update based on the current HW TSF. 2183 * 2184 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2185 * of a received beacon or the current local hardware TSF and write it to the 2186 * beacon timer registers. 2187 * 2188 * This is called in a variety of situations, e.g. when a beacon is received, 2189 * when a TSF update has been detected, but also when an new IBSS is created or 2190 * when we otherwise know we have to update the timers, but we keep it in this 2191 * function to have it all together in one place. 2192 */ 2193 static void 2194 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 2195 { 2196 struct ath5k_hw *ah = sc->ah; 2197 u32 nexttbtt, intval, hw_tu, bc_tu; 2198 u64 hw_tsf; 2199 2200 intval = sc->bintval & AR5K_BEACON_PERIOD; 2201 if (WARN_ON(!intval)) 2202 return; 2203 2204 /* beacon TSF converted to TU */ 2205 bc_tu = TSF_TO_TU(bc_tsf); 2206 2207 /* current TSF converted to TU */ 2208 hw_tsf = ath5k_hw_get_tsf64(ah); 2209 hw_tu = TSF_TO_TU(hw_tsf); 2210 2211 #define FUDGE 3 2212 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */ 2213 if (bc_tsf == -1) { 2214 /* 2215 * no beacons received, called internally. 2216 * just need to refresh timers based on HW TSF. 2217 */ 2218 nexttbtt = roundup(hw_tu + FUDGE, intval); 2219 } else if (bc_tsf == 0) { 2220 /* 2221 * no beacon received, probably called by ath5k_reset_tsf(). 2222 * reset TSF to start with 0. 2223 */ 2224 nexttbtt = intval; 2225 intval |= AR5K_BEACON_RESET_TSF; 2226 } else if (bc_tsf > hw_tsf) { 2227 /* 2228 * beacon received, SW merge happend but HW TSF not yet updated. 2229 * not possible to reconfigure timers yet, but next time we 2230 * receive a beacon with the same BSSID, the hardware will 2231 * automatically update the TSF and then we need to reconfigure 2232 * the timers. 2233 */ 2234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2235 "need to wait for HW TSF sync\n"); 2236 return; 2237 } else { 2238 /* 2239 * most important case for beacon synchronization between STA. 2240 * 2241 * beacon received and HW TSF has been already updated by HW. 2242 * update next TBTT based on the TSF of the beacon, but make 2243 * sure it is ahead of our local TSF timer. 2244 */ 2245 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2246 } 2247 #undef FUDGE 2248 2249 sc->nexttbtt = nexttbtt; 2250 2251 intval |= AR5K_BEACON_ENA; 2252 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2253 2254 /* 2255 * debugging output last in order to preserve the time critical aspect 2256 * of this function 2257 */ 2258 if (bc_tsf == -1) 2259 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2260 "reconfigured timers based on HW TSF\n"); 2261 else if (bc_tsf == 0) 2262 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2263 "reset HW TSF and timers\n"); 2264 else 2265 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2266 "updated timers based on beacon TSF\n"); 2267 2268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2269 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2270 (unsigned long long) bc_tsf, 2271 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2272 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2273 intval & AR5K_BEACON_PERIOD, 2274 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2275 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2276 } 2277 2278 2279 /** 2280 * ath5k_beacon_config - Configure the beacon queues and interrupts 2281 * 2282 * @sc: struct ath5k_softc pointer we are operating on 2283 * 2284 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2285 * interrupts to detect TSF updates only. 2286 */ 2287 static void 2288 ath5k_beacon_config(struct ath5k_softc *sc) 2289 { 2290 struct ath5k_hw *ah = sc->ah; 2291 unsigned long flags; 2292 2293 spin_lock_irqsave(&sc->block, flags); 2294 sc->bmisscount = 0; 2295 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2296 2297 if (sc->enable_beacon) { 2298 /* 2299 * In IBSS mode we use a self-linked tx descriptor and let the 2300 * hardware send the beacons automatically. We have to load it 2301 * only once here. 2302 * We use the SWBA interrupt only to keep track of the beacon 2303 * timers in order to detect automatic TSF updates. 2304 */ 2305 ath5k_beaconq_config(sc); 2306 2307 sc->imask |= AR5K_INT_SWBA; 2308 2309 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2310 if (ath5k_hw_hasveol(ah)) 2311 ath5k_beacon_send(sc); 2312 } else 2313 ath5k_beacon_update_timers(sc, -1); 2314 } else { 2315 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq); 2316 } 2317 2318 ath5k_hw_set_imr(ah, sc->imask); 2319 mmiowb(); 2320 spin_unlock_irqrestore(&sc->block, flags); 2321 } 2322 2323 static void ath5k_tasklet_beacon(unsigned long data) 2324 { 2325 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2326 2327 /* 2328 * Software beacon alert--time to send a beacon. 2329 * 2330 * In IBSS mode we use this interrupt just to 2331 * keep track of the next TBTT (target beacon 2332 * transmission time) in order to detect wether 2333 * automatic TSF updates happened. 2334 */ 2335 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2336 /* XXX: only if VEOL suppported */ 2337 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2338 sc->nexttbtt += sc->bintval; 2339 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2340 "SWBA nexttbtt: %x hw_tu: %x " 2341 "TSF: %llx\n", 2342 sc->nexttbtt, 2343 TSF_TO_TU(tsf), 2344 (unsigned long long) tsf); 2345 } else { 2346 spin_lock(&sc->block); 2347 ath5k_beacon_send(sc); 2348 spin_unlock(&sc->block); 2349 } 2350 } 2351 2352 2353 /********************\ 2354 * Interrupt handling * 2355 \********************/ 2356 2357 static int 2358 ath5k_init(struct ath5k_softc *sc) 2359 { 2360 struct ath5k_hw *ah = sc->ah; 2361 int ret, i; 2362 2363 mutex_lock(&sc->lock); 2364 2365 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2366 2367 /* 2368 * Stop anything previously setup. This is safe 2369 * no matter this is the first time through or not. 2370 */ 2371 ath5k_stop_locked(sc); 2372 2373 /* Set PHY calibration interval */ 2374 ah->ah_cal_intval = ath5k_calinterval; 2375 2376 /* 2377 * The basic interface to setting the hardware in a good 2378 * state is ``reset''. On return the hardware is known to 2379 * be powered up and with interrupts disabled. This must 2380 * be followed by initialization of the appropriate bits 2381 * and then setup of the interrupt mask. 2382 */ 2383 sc->curchan = sc->hw->conf.channel; 2384 sc->curband = &sc->sbands[sc->curchan->band]; 2385 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2386 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2387 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI; 2388 ret = ath5k_reset(sc, NULL); 2389 if (ret) 2390 goto done; 2391 2392 ath5k_rfkill_hw_start(ah); 2393 2394 /* 2395 * Reset the key cache since some parts do not reset the 2396 * contents on initial power up or resume from suspend. 2397 */ 2398 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) 2399 ath5k_hw_reset_key(ah, i); 2400 2401 /* Set ack to be sent at low bit-rates */ 2402 ath5k_hw_set_ack_bitrate_high(ah, false); 2403 ret = 0; 2404 done: 2405 mmiowb(); 2406 mutex_unlock(&sc->lock); 2407 return ret; 2408 } 2409 2410 static int 2411 ath5k_stop_locked(struct ath5k_softc *sc) 2412 { 2413 struct ath5k_hw *ah = sc->ah; 2414 2415 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2416 test_bit(ATH_STAT_INVALID, sc->status)); 2417 2418 /* 2419 * Shutdown the hardware and driver: 2420 * stop output from above 2421 * disable interrupts 2422 * turn off timers 2423 * turn off the radio 2424 * clear transmit machinery 2425 * clear receive machinery 2426 * drain and release tx queues 2427 * reclaim beacon resources 2428 * power down hardware 2429 * 2430 * Note that some of this work is not possible if the 2431 * hardware is gone (invalid). 2432 */ 2433 ieee80211_stop_queues(sc->hw); 2434 2435 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2436 ath5k_led_off(sc); 2437 ath5k_hw_set_imr(ah, 0); 2438 synchronize_irq(sc->pdev->irq); 2439 } 2440 ath5k_txq_cleanup(sc); 2441 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2442 ath5k_rx_stop(sc); 2443 ath5k_hw_phy_disable(ah); 2444 } else 2445 sc->rxlink = NULL; 2446 2447 return 0; 2448 } 2449 2450 /* 2451 * Stop the device, grabbing the top-level lock to protect 2452 * against concurrent entry through ath5k_init (which can happen 2453 * if another thread does a system call and the thread doing the 2454 * stop is preempted). 2455 */ 2456 static int 2457 ath5k_stop_hw(struct ath5k_softc *sc) 2458 { 2459 int ret; 2460 2461 mutex_lock(&sc->lock); 2462 ret = ath5k_stop_locked(sc); 2463 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2464 /* 2465 * Don't set the card in full sleep mode! 2466 * 2467 * a) When the device is in this state it must be carefully 2468 * woken up or references to registers in the PCI clock 2469 * domain may freeze the bus (and system). This varies 2470 * by chip and is mostly an issue with newer parts 2471 * (madwifi sources mentioned srev >= 0x78) that go to 2472 * sleep more quickly. 2473 * 2474 * b) On older chips full sleep results a weird behaviour 2475 * during wakeup. I tested various cards with srev < 0x78 2476 * and they don't wake up after module reload, a second 2477 * module reload is needed to bring the card up again. 2478 * 2479 * Until we figure out what's going on don't enable 2480 * full chip reset on any chip (this is what Legacy HAL 2481 * and Sam's HAL do anyway). Instead Perform a full reset 2482 * on the device (same as initial state after attach) and 2483 * leave it idle (keep MAC/BB on warm reset) */ 2484 ret = ath5k_hw_on_hold(sc->ah); 2485 2486 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2487 "putting device to sleep\n"); 2488 } 2489 ath5k_txbuf_free(sc, sc->bbuf); 2490 2491 mmiowb(); 2492 mutex_unlock(&sc->lock); 2493 2494 tasklet_kill(&sc->rxtq); 2495 tasklet_kill(&sc->txtq); 2496 tasklet_kill(&sc->restq); 2497 tasklet_kill(&sc->calib); 2498 tasklet_kill(&sc->beacontq); 2499 2500 ath5k_rfkill_hw_stop(sc->ah); 2501 2502 return ret; 2503 } 2504 2505 static irqreturn_t 2506 ath5k_intr(int irq, void *dev_id) 2507 { 2508 struct ath5k_softc *sc = dev_id; 2509 struct ath5k_hw *ah = sc->ah; 2510 enum ath5k_int status; 2511 unsigned int counter = 1000; 2512 2513 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2514 !ath5k_hw_is_intr_pending(ah))) 2515 return IRQ_NONE; 2516 2517 do { 2518 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2519 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2520 status, sc->imask); 2521 if (unlikely(status & AR5K_INT_FATAL)) { 2522 /* 2523 * Fatal errors are unrecoverable. 2524 * Typically these are caused by DMA errors. 2525 */ 2526 tasklet_schedule(&sc->restq); 2527 } else if (unlikely(status & AR5K_INT_RXORN)) { 2528 tasklet_schedule(&sc->restq); 2529 } else { 2530 if (status & AR5K_INT_SWBA) { 2531 tasklet_hi_schedule(&sc->beacontq); 2532 } 2533 if (status & AR5K_INT_RXEOL) { 2534 /* 2535 * NB: the hardware should re-read the link when 2536 * RXE bit is written, but it doesn't work at 2537 * least on older hardware revs. 2538 */ 2539 sc->rxlink = NULL; 2540 } 2541 if (status & AR5K_INT_TXURN) { 2542 /* bump tx trigger level */ 2543 ath5k_hw_update_tx_triglevel(ah, true); 2544 } 2545 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2546 tasklet_schedule(&sc->rxtq); 2547 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2548 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2549 tasklet_schedule(&sc->txtq); 2550 if (status & AR5K_INT_BMISS) { 2551 /* TODO */ 2552 } 2553 if (status & AR5K_INT_SWI) { 2554 tasklet_schedule(&sc->calib); 2555 } 2556 if (status & AR5K_INT_MIB) { 2557 /* 2558 * These stats are also used for ANI i think 2559 * so how about updating them more often ? 2560 */ 2561 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 2562 } 2563 if (status & AR5K_INT_GPIO) 2564 tasklet_schedule(&sc->rf_kill.toggleq); 2565 2566 } 2567 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2568 2569 if (unlikely(!counter)) 2570 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2571 2572 ath5k_hw_calibration_poll(ah); 2573 2574 return IRQ_HANDLED; 2575 } 2576 2577 static void 2578 ath5k_tasklet_reset(unsigned long data) 2579 { 2580 struct ath5k_softc *sc = (void *)data; 2581 2582 ath5k_reset_wake(sc); 2583 } 2584 2585 /* 2586 * Periodically recalibrate the PHY to account 2587 * for temperature/environment changes. 2588 */ 2589 static void 2590 ath5k_tasklet_calibrate(unsigned long data) 2591 { 2592 struct ath5k_softc *sc = (void *)data; 2593 struct ath5k_hw *ah = sc->ah; 2594 2595 /* Only full calibration for now */ 2596 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION) 2597 return; 2598 2599 /* Stop queues so that calibration 2600 * doesn't interfere with tx */ 2601 ieee80211_stop_queues(sc->hw); 2602 2603 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2604 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2605 sc->curchan->hw_value); 2606 2607 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2608 /* 2609 * Rfgain is out of bounds, reset the chip 2610 * to load new gain values. 2611 */ 2612 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2613 ath5k_reset_wake(sc); 2614 } 2615 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2616 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2617 ieee80211_frequency_to_channel( 2618 sc->curchan->center_freq)); 2619 2620 ah->ah_swi_mask = 0; 2621 2622 /* Wake queues */ 2623 ieee80211_wake_queues(sc->hw); 2624 2625 } 2626 2627 2628 /********************\ 2629 * Mac80211 functions * 2630 \********************/ 2631 2632 static int 2633 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2634 { 2635 struct ath5k_softc *sc = hw->priv; 2636 2637 return ath5k_tx_queue(hw, skb, sc->txq); 2638 } 2639 2640 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 2641 struct ath5k_txq *txq) 2642 { 2643 struct ath5k_softc *sc = hw->priv; 2644 struct ath5k_buf *bf; 2645 unsigned long flags; 2646 int hdrlen; 2647 int padsize; 2648 2649 ath5k_debug_dump_skb(sc, skb, "TX ", 1); 2650 2651 if (sc->opmode == NL80211_IFTYPE_MONITOR) 2652 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n"); 2653 2654 /* 2655 * the hardware expects the header padded to 4 byte boundaries 2656 * if this is not the case we add the padding after the header 2657 */ 2658 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 2659 padsize = ath5k_pad_size(hdrlen); 2660 if (padsize) { 2661 2662 if (skb_headroom(skb) < padsize) { 2663 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough" 2664 " headroom to pad %d\n", hdrlen, padsize); 2665 goto drop_packet; 2666 } 2667 skb_push(skb, padsize); 2668 memmove(skb->data, skb->data+padsize, hdrlen); 2669 } 2670 2671 spin_lock_irqsave(&sc->txbuflock, flags); 2672 if (list_empty(&sc->txbuf)) { 2673 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 2674 spin_unlock_irqrestore(&sc->txbuflock, flags); 2675 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 2676 goto drop_packet; 2677 } 2678 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 2679 list_del(&bf->list); 2680 sc->txbuf_len--; 2681 if (list_empty(&sc->txbuf)) 2682 ieee80211_stop_queues(hw); 2683 spin_unlock_irqrestore(&sc->txbuflock, flags); 2684 2685 bf->skb = skb; 2686 2687 if (ath5k_txbuf_setup(sc, bf, txq)) { 2688 bf->skb = NULL; 2689 spin_lock_irqsave(&sc->txbuflock, flags); 2690 list_add_tail(&bf->list, &sc->txbuf); 2691 sc->txbuf_len++; 2692 spin_unlock_irqrestore(&sc->txbuflock, flags); 2693 goto drop_packet; 2694 } 2695 return NETDEV_TX_OK; 2696 2697 drop_packet: 2698 dev_kfree_skb_any(skb); 2699 return NETDEV_TX_OK; 2700 } 2701 2702 /* 2703 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2704 * and change to the given channel. 2705 */ 2706 static int 2707 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan) 2708 { 2709 struct ath5k_hw *ah = sc->ah; 2710 int ret; 2711 2712 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2713 2714 if (chan) { 2715 ath5k_hw_set_imr(ah, 0); 2716 ath5k_txq_cleanup(sc); 2717 ath5k_rx_stop(sc); 2718 2719 sc->curchan = chan; 2720 sc->curband = &sc->sbands[chan->band]; 2721 } 2722 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL); 2723 if (ret) { 2724 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2725 goto err; 2726 } 2727 2728 ret = ath5k_rx_start(sc); 2729 if (ret) { 2730 ATH5K_ERR(sc, "can't start recv logic\n"); 2731 goto err; 2732 } 2733 2734 /* 2735 * Change channels and update the h/w rate map if we're switching; 2736 * e.g. 11a to 11b/g. 2737 * 2738 * We may be doing a reset in response to an ioctl that changes the 2739 * channel so update any state that might change as a result. 2740 * 2741 * XXX needed? 2742 */ 2743 /* ath5k_chan_change(sc, c); */ 2744 2745 ath5k_beacon_config(sc); 2746 /* intrs are enabled by ath5k_beacon_config */ 2747 2748 return 0; 2749 err: 2750 return ret; 2751 } 2752 2753 static int 2754 ath5k_reset_wake(struct ath5k_softc *sc) 2755 { 2756 int ret; 2757 2758 ret = ath5k_reset(sc, sc->curchan); 2759 if (!ret) 2760 ieee80211_wake_queues(sc->hw); 2761 2762 return ret; 2763 } 2764 2765 static int ath5k_start(struct ieee80211_hw *hw) 2766 { 2767 return ath5k_init(hw->priv); 2768 } 2769 2770 static void ath5k_stop(struct ieee80211_hw *hw) 2771 { 2772 ath5k_stop_hw(hw->priv); 2773 } 2774 2775 static int ath5k_add_interface(struct ieee80211_hw *hw, 2776 struct ieee80211_if_init_conf *conf) 2777 { 2778 struct ath5k_softc *sc = hw->priv; 2779 int ret; 2780 2781 mutex_lock(&sc->lock); 2782 if (sc->vif) { 2783 ret = 0; 2784 goto end; 2785 } 2786 2787 sc->vif = conf->vif; 2788 2789 switch (conf->type) { 2790 case NL80211_IFTYPE_AP: 2791 case NL80211_IFTYPE_STATION: 2792 case NL80211_IFTYPE_ADHOC: 2793 case NL80211_IFTYPE_MESH_POINT: 2794 case NL80211_IFTYPE_MONITOR: 2795 sc->opmode = conf->type; 2796 break; 2797 default: 2798 ret = -EOPNOTSUPP; 2799 goto end; 2800 } 2801 2802 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr); 2803 ath5k_mode_setup(sc); 2804 2805 ret = 0; 2806 end: 2807 mutex_unlock(&sc->lock); 2808 return ret; 2809 } 2810 2811 static void 2812 ath5k_remove_interface(struct ieee80211_hw *hw, 2813 struct ieee80211_if_init_conf *conf) 2814 { 2815 struct ath5k_softc *sc = hw->priv; 2816 u8 mac[ETH_ALEN] = {}; 2817 2818 mutex_lock(&sc->lock); 2819 if (sc->vif != conf->vif) 2820 goto end; 2821 2822 ath5k_hw_set_lladdr(sc->ah, mac); 2823 sc->vif = NULL; 2824 end: 2825 mutex_unlock(&sc->lock); 2826 } 2827 2828 /* 2829 * TODO: Phy disable/diversity etc 2830 */ 2831 static int 2832 ath5k_config(struct ieee80211_hw *hw, u32 changed) 2833 { 2834 struct ath5k_softc *sc = hw->priv; 2835 struct ath5k_hw *ah = sc->ah; 2836 struct ieee80211_conf *conf = &hw->conf; 2837 int ret = 0; 2838 2839 mutex_lock(&sc->lock); 2840 2841 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 2842 ret = ath5k_chan_set(sc, conf->channel); 2843 if (ret < 0) 2844 goto unlock; 2845 } 2846 2847 if ((changed & IEEE80211_CONF_CHANGE_POWER) && 2848 (sc->power_level != conf->power_level)) { 2849 sc->power_level = conf->power_level; 2850 2851 /* Half dB steps */ 2852 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); 2853 } 2854 2855 /* TODO: 2856 * 1) Move this on config_interface and handle each case 2857 * separately eg. when we have only one STA vif, use 2858 * AR5K_ANTMODE_SINGLE_AP 2859 * 2860 * 2) Allow the user to change antenna mode eg. when only 2861 * one antenna is present 2862 * 2863 * 3) Allow the user to set default/tx antenna when possible 2864 * 2865 * 4) Default mode should handle 90% of the cases, together 2866 * with fixed a/b and single AP modes we should be able to 2867 * handle 99%. Sectored modes are extreme cases and i still 2868 * haven't found a usage for them. If we decide to support them, 2869 * then we must allow the user to set how many tx antennas we 2870 * have available 2871 */ 2872 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT); 2873 2874 unlock: 2875 mutex_unlock(&sc->lock); 2876 return ret; 2877 } 2878 2879 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 2880 int mc_count, struct dev_addr_list *mclist) 2881 { 2882 u32 mfilt[2], val; 2883 int i; 2884 u8 pos; 2885 2886 mfilt[0] = 0; 2887 mfilt[1] = 1; 2888 2889 for (i = 0; i < mc_count; i++) { 2890 if (!mclist) 2891 break; 2892 /* calculate XOR of eight 6-bit values */ 2893 val = get_unaligned_le32(mclist->dmi_addr + 0); 2894 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2895 val = get_unaligned_le32(mclist->dmi_addr + 3); 2896 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2897 pos &= 0x3f; 2898 mfilt[pos / 32] |= (1 << (pos % 32)); 2899 /* XXX: we might be able to just do this instead, 2900 * but not sure, needs testing, if we do use this we'd 2901 * neet to inform below to not reset the mcast */ 2902 /* ath5k_hw_set_mcast_filterindex(ah, 2903 * mclist->dmi_addr[5]); */ 2904 mclist = mclist->next; 2905 } 2906 2907 return ((u64)(mfilt[1]) << 32) | mfilt[0]; 2908 } 2909 2910 #define SUPPORTED_FIF_FLAGS \ 2911 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ 2912 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ 2913 FIF_BCN_PRBRESP_PROMISC 2914 /* 2915 * o always accept unicast, broadcast, and multicast traffic 2916 * o multicast traffic for all BSSIDs will be enabled if mac80211 2917 * says it should be 2918 * o maintain current state of phy ofdm or phy cck error reception. 2919 * If the hardware detects any of these type of errors then 2920 * ath5k_hw_get_rx_filter() will pass to us the respective 2921 * hardware filters to be able to receive these type of frames. 2922 * o probe request frames are accepted only when operating in 2923 * hostap, adhoc, or monitor modes 2924 * o enable promiscuous mode according to the interface state 2925 * o accept beacons: 2926 * - when operating in adhoc mode so the 802.11 layer creates 2927 * node table entries for peers, 2928 * - when operating in station mode for collecting rssi data when 2929 * the station is otherwise quiet, or 2930 * - when scanning 2931 */ 2932 static void ath5k_configure_filter(struct ieee80211_hw *hw, 2933 unsigned int changed_flags, 2934 unsigned int *new_flags, 2935 u64 multicast) 2936 { 2937 struct ath5k_softc *sc = hw->priv; 2938 struct ath5k_hw *ah = sc->ah; 2939 u32 mfilt[2], rfilt; 2940 2941 mutex_lock(&sc->lock); 2942 2943 mfilt[0] = multicast; 2944 mfilt[1] = multicast >> 32; 2945 2946 /* Only deal with supported flags */ 2947 changed_flags &= SUPPORTED_FIF_FLAGS; 2948 *new_flags &= SUPPORTED_FIF_FLAGS; 2949 2950 /* If HW detects any phy or radar errors, leave those filters on. 2951 * Also, always enable Unicast, Broadcasts and Multicast 2952 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ 2953 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | 2954 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | 2955 AR5K_RX_FILTER_MCAST); 2956 2957 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { 2958 if (*new_flags & FIF_PROMISC_IN_BSS) { 2959 rfilt |= AR5K_RX_FILTER_PROM; 2960 __set_bit(ATH_STAT_PROMISC, sc->status); 2961 } else { 2962 __clear_bit(ATH_STAT_PROMISC, sc->status); 2963 } 2964 } 2965 2966 /* Note, AR5K_RX_FILTER_MCAST is already enabled */ 2967 if (*new_flags & FIF_ALLMULTI) { 2968 mfilt[0] = ~0; 2969 mfilt[1] = ~0; 2970 } 2971 2972 /* This is the best we can do */ 2973 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) 2974 rfilt |= AR5K_RX_FILTER_PHYERR; 2975 2976 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons 2977 * and probes for any BSSID, this needs testing */ 2978 if (*new_flags & FIF_BCN_PRBRESP_PROMISC) 2979 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ; 2980 2981 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not 2982 * set we should only pass on control frames for this 2983 * station. This needs testing. I believe right now this 2984 * enables *all* control frames, which is OK.. but 2985 * but we should see if we can improve on granularity */ 2986 if (*new_flags & FIF_CONTROL) 2987 rfilt |= AR5K_RX_FILTER_CONTROL; 2988 2989 /* Additional settings per mode -- this is per ath5k */ 2990 2991 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ 2992 2993 switch (sc->opmode) { 2994 case NL80211_IFTYPE_MESH_POINT: 2995 case NL80211_IFTYPE_MONITOR: 2996 rfilt |= AR5K_RX_FILTER_CONTROL | 2997 AR5K_RX_FILTER_BEACON | 2998 AR5K_RX_FILTER_PROBEREQ | 2999 AR5K_RX_FILTER_PROM; 3000 break; 3001 case NL80211_IFTYPE_AP: 3002 case NL80211_IFTYPE_ADHOC: 3003 rfilt |= AR5K_RX_FILTER_PROBEREQ | 3004 AR5K_RX_FILTER_BEACON; 3005 break; 3006 case NL80211_IFTYPE_STATION: 3007 if (sc->assoc) 3008 rfilt |= AR5K_RX_FILTER_BEACON; 3009 default: 3010 break; 3011 } 3012 3013 /* Set filters */ 3014 ath5k_hw_set_rx_filter(ah, rfilt); 3015 3016 /* Set multicast bits */ 3017 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); 3018 /* Set the cached hw filter flags, this will alter actually 3019 * be set in HW */ 3020 sc->filter_flags = rfilt; 3021 3022 mutex_unlock(&sc->lock); 3023 } 3024 3025 static int 3026 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3027 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3028 struct ieee80211_key_conf *key) 3029 { 3030 struct ath5k_softc *sc = hw->priv; 3031 struct ath5k_hw *ah = sc->ah; 3032 struct ath_common *common = ath5k_hw_common(ah); 3033 int ret = 0; 3034 3035 if (modparam_nohwcrypt) 3036 return -EOPNOTSUPP; 3037 3038 if (sc->opmode == NL80211_IFTYPE_AP) 3039 return -EOPNOTSUPP; 3040 3041 switch (key->alg) { 3042 case ALG_WEP: 3043 case ALG_TKIP: 3044 break; 3045 case ALG_CCMP: 3046 if (sc->ah->ah_aes_support) 3047 break; 3048 3049 return -EOPNOTSUPP; 3050 default: 3051 WARN_ON(1); 3052 return -EINVAL; 3053 } 3054 3055 mutex_lock(&sc->lock); 3056 3057 switch (cmd) { 3058 case SET_KEY: 3059 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, 3060 sta ? sta->addr : NULL); 3061 if (ret) { 3062 ATH5K_ERR(sc, "can't set the key\n"); 3063 goto unlock; 3064 } 3065 __set_bit(key->keyidx, common->keymap); 3066 key->hw_key_idx = key->keyidx; 3067 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV | 3068 IEEE80211_KEY_FLAG_GENERATE_MMIC); 3069 break; 3070 case DISABLE_KEY: 3071 ath5k_hw_reset_key(sc->ah, key->keyidx); 3072 __clear_bit(key->keyidx, common->keymap); 3073 break; 3074 default: 3075 ret = -EINVAL; 3076 goto unlock; 3077 } 3078 3079 unlock: 3080 mmiowb(); 3081 mutex_unlock(&sc->lock); 3082 return ret; 3083 } 3084 3085 static int 3086 ath5k_get_stats(struct ieee80211_hw *hw, 3087 struct ieee80211_low_level_stats *stats) 3088 { 3089 struct ath5k_softc *sc = hw->priv; 3090 struct ath5k_hw *ah = sc->ah; 3091 3092 /* Force update */ 3093 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 3094 3095 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); 3096 3097 return 0; 3098 } 3099 3100 static int 3101 ath5k_get_tx_stats(struct ieee80211_hw *hw, 3102 struct ieee80211_tx_queue_stats *stats) 3103 { 3104 struct ath5k_softc *sc = hw->priv; 3105 3106 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); 3107 3108 return 0; 3109 } 3110 3111 static u64 3112 ath5k_get_tsf(struct ieee80211_hw *hw) 3113 { 3114 struct ath5k_softc *sc = hw->priv; 3115 3116 return ath5k_hw_get_tsf64(sc->ah); 3117 } 3118 3119 static void 3120 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3121 { 3122 struct ath5k_softc *sc = hw->priv; 3123 3124 ath5k_hw_set_tsf64(sc->ah, tsf); 3125 } 3126 3127 static void 3128 ath5k_reset_tsf(struct ieee80211_hw *hw) 3129 { 3130 struct ath5k_softc *sc = hw->priv; 3131 3132 /* 3133 * in IBSS mode we need to update the beacon timers too. 3134 * this will also reset the TSF if we call it with 0 3135 */ 3136 if (sc->opmode == NL80211_IFTYPE_ADHOC) 3137 ath5k_beacon_update_timers(sc, 0); 3138 else 3139 ath5k_hw_reset_tsf(sc->ah); 3140 } 3141 3142 /* 3143 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 3144 * this is called only once at config_bss time, for AP we do it every 3145 * SWBA interrupt so that the TIM will reflect buffered frames. 3146 * 3147 * Called with the beacon lock. 3148 */ 3149 static int 3150 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3151 { 3152 int ret; 3153 struct ath5k_softc *sc = hw->priv; 3154 struct sk_buff *skb; 3155 3156 if (WARN_ON(!vif)) { 3157 ret = -EINVAL; 3158 goto out; 3159 } 3160 3161 skb = ieee80211_beacon_get(hw, vif); 3162 3163 if (!skb) { 3164 ret = -ENOMEM; 3165 goto out; 3166 } 3167 3168 ath5k_debug_dump_skb(sc, skb, "BC ", 1); 3169 3170 ath5k_txbuf_free(sc, sc->bbuf); 3171 sc->bbuf->skb = skb; 3172 ret = ath5k_beacon_setup(sc, sc->bbuf); 3173 if (ret) 3174 sc->bbuf->skb = NULL; 3175 out: 3176 return ret; 3177 } 3178 3179 static void 3180 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3181 { 3182 struct ath5k_softc *sc = hw->priv; 3183 struct ath5k_hw *ah = sc->ah; 3184 u32 rfilt; 3185 rfilt = ath5k_hw_get_rx_filter(ah); 3186 if (enable) 3187 rfilt |= AR5K_RX_FILTER_BEACON; 3188 else 3189 rfilt &= ~AR5K_RX_FILTER_BEACON; 3190 ath5k_hw_set_rx_filter(ah, rfilt); 3191 sc->filter_flags = rfilt; 3192 } 3193 3194 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 3195 struct ieee80211_vif *vif, 3196 struct ieee80211_bss_conf *bss_conf, 3197 u32 changes) 3198 { 3199 struct ath5k_softc *sc = hw->priv; 3200 struct ath5k_hw *ah = sc->ah; 3201 struct ath_common *common = ath5k_hw_common(ah); 3202 unsigned long flags; 3203 3204 mutex_lock(&sc->lock); 3205 if (WARN_ON(sc->vif != vif)) 3206 goto unlock; 3207 3208 if (changes & BSS_CHANGED_BSSID) { 3209 /* Cache for later use during resets */ 3210 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 3211 common->curaid = 0; 3212 ath5k_hw_set_associd(ah); 3213 mmiowb(); 3214 } 3215 3216 if (changes & BSS_CHANGED_BEACON_INT) 3217 sc->bintval = bss_conf->beacon_int; 3218 3219 if (changes & BSS_CHANGED_ASSOC) { 3220 sc->assoc = bss_conf->assoc; 3221 if (sc->opmode == NL80211_IFTYPE_STATION) 3222 set_beacon_filter(hw, sc->assoc); 3223 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3224 AR5K_LED_ASSOC : AR5K_LED_INIT); 3225 if (bss_conf->assoc) { 3226 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, 3227 "Bss Info ASSOC %d, bssid: %pM\n", 3228 bss_conf->aid, common->curbssid); 3229 common->curaid = bss_conf->aid; 3230 ath5k_hw_set_associd(ah); 3231 /* Once ANI is available you would start it here */ 3232 } 3233 } 3234 3235 if (changes & BSS_CHANGED_BEACON) { 3236 spin_lock_irqsave(&sc->block, flags); 3237 ath5k_beacon_update(hw, vif); 3238 spin_unlock_irqrestore(&sc->block, flags); 3239 } 3240 3241 if (changes & BSS_CHANGED_BEACON_ENABLED) 3242 sc->enable_beacon = bss_conf->enable_beacon; 3243 3244 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | 3245 BSS_CHANGED_BEACON_INT)) 3246 ath5k_beacon_config(sc); 3247 3248 unlock: 3249 mutex_unlock(&sc->lock); 3250 } 3251 3252 static void ath5k_sw_scan_start(struct ieee80211_hw *hw) 3253 { 3254 struct ath5k_softc *sc = hw->priv; 3255 if (!sc->assoc) 3256 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); 3257 } 3258 3259 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw) 3260 { 3261 struct ath5k_softc *sc = hw->priv; 3262 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3263 AR5K_LED_ASSOC : AR5K_LED_INIT); 3264 } 3265